drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 /*(DEBLOBBED)*/
  53
  54
  55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  56 {
  57         SDMA0_REGISTER_OFFSET,
  58         SDMA1_REGISTER_OFFSET
  59 };
  60
  61 static const u32 golden_settings_tonga_a11[] =
  62 {
  63         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  64         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  65         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  66         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  67         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  68         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  69         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  70         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  71         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  72         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  73 };
  74
  75 static const u32 tonga_mgcg_cgcg_init[] =
  76 {
  77         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  78         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  79 };
  80
  81 static const u32 golden_settings_fiji_a10[] =
  82 {
  83         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  84         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  85         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  86         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  87         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  88         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  89         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  90         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  91 };
  92
  93 static const u32 fiji_mgcg_cgcg_init[] =
  94 {
  95         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  96         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  97 };
  98
  99 static const u32 golden_settings_polaris11_a11[] =
 100 {
 101         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 102         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 103         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 104         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 105         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 106         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 108         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 109         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 110         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 111 };
 112
 113 static const u32 golden_settings_polaris10_a11[] =
 114 {
 115         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 116         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 117         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 118         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 119         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 120         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 121         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 122         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 123         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 124         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 125 };
 126
 127 static const u32 cz_golden_settings_a11[] =
 128 {
 129         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 130         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 131         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 132         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 133         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 134         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 135         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 136         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 137         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 138         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 139         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 140         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 141 };
 142
 143 static const u32 cz_mgcg_cgcg_init[] =
 144 {
 145         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 146         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 147 };
 148
 149 static const u32 stoney_golden_settings_a11[] =
 150 {
 151         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 152         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 153         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 154         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 155 };
 156
 157 static const u32 stoney_mgcg_cgcg_init[] =
 158 {
 159         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 160 };
 161
 162 /*
 163  * sDMA - System DMA
 164  * Starting with CIK, the GPU has new asynchronous
 165  * DMA engines.  These engines are used for compute
 166  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 167  * and each one supports 1 ring buffer used for gfx
 168  * and 2 queues used for compute.
 169  *
 170  * The programming model is very similar to the CP
 171  * (ring buffer, IBs, etc.), but sDMA has it's own
 172  * packet format that is different from the PM4 format
 173  * used by the CP. sDMA supports copying data, writing
 174  * embedded data, solid fills, and a number of other
 175  * things.  It also has support for tiling/detiling of
 176  * buffers.
 177  */
 178
 179 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 180 {
 181         switch (adev->asic_type) {
 182         case CHIP_FIJI:
 183                 amdgpu_program_register_sequence(adev,
 184                                                  fiji_mgcg_cgcg_init,
 185                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 186                 amdgpu_program_register_sequence(adev,
 187                                                  golden_settings_fiji_a10,
 188                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 189                 break;
 190         case CHIP_TONGA:
 191                 amdgpu_program_register_sequence(adev,
 192                                                  tonga_mgcg_cgcg_init,
 193                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 194                 amdgpu_program_register_sequence(adev,
 195                                                  golden_settings_tonga_a11,
 196                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 197                 break;
 198         case CHIP_POLARIS11:
 199                 amdgpu_program_register_sequence(adev,
 200                                                  golden_settings_polaris11_a11,
 201                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 202                 break;
 203         case CHIP_POLARIS10:
 204                 amdgpu_program_register_sequence(adev,
 205                                                  golden_settings_polaris10_a11,
 206                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 207                 break;
 208         case CHIP_CARRIZO:
 209                 amdgpu_program_register_sequence(adev,
 210                                                  cz_mgcg_cgcg_init,
 211                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 212                 amdgpu_program_register_sequence(adev,
 213                                                  cz_golden_settings_a11,
 214                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 215                 break;
 216         case CHIP_STONEY:
 217                 amdgpu_program_register_sequence(adev,
 218                                                  stoney_mgcg_cgcg_init,
 219                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 220                 amdgpu_program_register_sequence(adev,
 221                                                  stoney_golden_settings_a11,
 222                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 223                 break;
 224         default:
 225                 break;
 226         }
 227 }
 228
 229 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 230 {
 231         int i;
 232         for (i = 0; i < adev->sdma.num_instances; i++) {
 233                 release_firmware(adev->sdma.instance[i].fw);
 234                 adev->sdma.instance[i].fw = NULL;
 235         }
 236 }
 237
 238 /**
 239  * sdma_v3_0_init_microcode - load ucode images from disk
 240  *
 241  * @adev: amdgpu_device pointer
 242  *
 243  * Use the firmware interface to load the ucode images into
 244  * the driver (not loaded into hw).
 245  * Returns 0 on success, error on failure.
 246  */
 247 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 248 {
 249         const char *chip_name;
 250         char fw_name[30];
 251         int err = 0, i;
 252         struct amdgpu_firmware_info *info = NULL;
 253         const struct common_firmware_header *header = NULL;
 254         const struct sdma_firmware_header_v1_0 *hdr;
 255
 256         DRM_DEBUG("\n");
 257
 258         switch (adev->asic_type) {
 259         case CHIP_TONGA:
 260                 chip_name = "tonga";
 261                 break;
 262         case CHIP_FIJI:
 263                 chip_name = "fiji";
 264                 break;
 265         case CHIP_POLARIS11:
 266                 chip_name = "polaris11";
 267                 break;
 268         case CHIP_POLARIS10:
 269                 chip_name = "polaris10";
 270                 break;
 271         case CHIP_CARRIZO:
 272                 chip_name = "carrizo";
 273                 break;
 274         case CHIP_STONEY:
 275                 chip_name = "stoney";
 276                 break;
 277         default: BUG();
 278         }
 279
 280         for (i = 0; i < adev->sdma.num_instances; i++) {
 281                 if (i == 0)
 282                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 283                 else
 284                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 285                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 286                 if (err)
 287                         goto out;
 288                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 289                 if (err)
 290                         goto out;
 291                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 292                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 293                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 294                 if (adev->sdma.instance[i].feature_version >= 20)
 295                         adev->sdma.instance[i].burst_nop = true;
 296
 297                 if (adev->firmware.smu_load) {
 298                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 299                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 300                         info->fw = adev->sdma.instance[i].fw;
 301                         header = (const struct common_firmware_header *)info->fw->data;
 302                         adev->firmware.fw_size +=
 303                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 304                 }
 305         }
 306 out:
 307         if (err) {
 308                 printk(KERN_ERR
 309                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
 310                        fw_name);
 311                 for (i = 0; i < adev->sdma.num_instances; i++) {
 312                         release_firmware(adev->sdma.instance[i].fw);
 313                         adev->sdma.instance[i].fw = NULL;
 314                 }
 315         }
 316         return err;
 317 }
 318
 319 /**
 320  * sdma_v3_0_ring_get_rptr - get the current read pointer
 321  *
 322  * @ring: amdgpu ring pointer
 323  *
 324  * Get the current rptr from the hardware (VI+).
 325  */
 326 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 327 {
 328         /* XXX check if swapping is necessary on BE */
 329         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 330 }
 331
 332 /**
 333  * sdma_v3_0_ring_get_wptr - get the current write pointer
 334  *
 335  * @ring: amdgpu ring pointer
 336  *
 337  * Get the current wptr from the hardware (VI+).
 338  */
 339 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 340 {
 341         struct amdgpu_device *adev = ring->adev;
 342         u32 wptr;
 343
 344         if (ring->use_doorbell) {
 345                 /* XXX check if swapping is necessary on BE */
 346                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 347         } else {
 348                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 349
 350                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 351         }
 352
 353         return wptr;
 354 }
 355
 356 /**
 357  * sdma_v3_0_ring_set_wptr - commit the write pointer
 358  *
 359  * @ring: amdgpu ring pointer
 360  *
 361  * Write the wptr back to the hardware (VI+).
 362  */
 363 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366
 367         if (ring->use_doorbell) {
 368                 /* XXX check if swapping is necessary on BE */
 369                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
 370                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 371         } else {
 372                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 373
 374                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 375         }
 376 }
 377
 378 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 379 {
 380         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 381         int i;
 382
 383         for (i = 0; i < count; i++)
 384                 if (sdma && sdma->burst_nop && (i == 0))
 385                         amdgpu_ring_write(ring, ring->nop |
 386                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 387                 else
 388                         amdgpu_ring_write(ring, ring->nop);
 389 }
 390
 391 /**
 392  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 393  *
 394  * @ring: amdgpu ring pointer
 395  * @ib: IB object to schedule
 396  *
 397  * Schedule an IB in the DMA ring (VI).
 398  */
 399 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 400                                    struct amdgpu_ib *ib,
 401                                    unsigned vm_id, bool ctx_switch)
 402 {
 403         u32 vmid = vm_id & 0xf;
 404
 405         /* IB packet must end on a 8 DW boundary */
 406         sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 407
 408         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 409                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 410         /* base must be 32 byte aligned */
 411         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 412         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 413         amdgpu_ring_write(ring, ib->length_dw);
 414         amdgpu_ring_write(ring, 0);
 415         amdgpu_ring_write(ring, 0);
 416
 417 }
 418
 419 /**
 420  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 421  *
 422  * @ring: amdgpu ring pointer
 423  *
 424  * Emit an hdp flush packet on the requested DMA ring.
 425  */
 426 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 427 {
 428         u32 ref_and_mask = 0;
 429
 430         if (ring == &ring->adev->sdma.instance[0].ring)
 431                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 432         else
 433                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 434
 435         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 436                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 437                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 438         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 439         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 440         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 441         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 442         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 443                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 444 }
 445
 446 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 447 {
 448         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 449                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 450         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 451         amdgpu_ring_write(ring, 1);
 452 }
 453
 454 /**
 455  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 456  *
 457  * @ring: amdgpu ring pointer
 458  * @fence: amdgpu fence object
 459  *
 460  * Add a DMA fence packet to the ring to write
 461  * the fence seq number and DMA trap packet to generate
 462  * an interrupt if needed (VI).
 463  */
 464 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 465                                       unsigned flags)
 466 {
 467         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 468         /* write the fence */
 469         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 470         amdgpu_ring_write(ring, lower_32_bits(addr));
 471         amdgpu_ring_write(ring, upper_32_bits(addr));
 472         amdgpu_ring_write(ring, lower_32_bits(seq));
 473
 474         /* optionally write high bits as well */
 475         if (write64bit) {
 476                 addr += 4;
 477                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 478                 amdgpu_ring_write(ring, lower_32_bits(addr));
 479                 amdgpu_ring_write(ring, upper_32_bits(addr));
 480                 amdgpu_ring_write(ring, upper_32_bits(seq));
 481         }
 482
 483         /* generate an interrupt */
 484         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 485         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 486 }
 487
 488 /**
 489  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 490  *
 491  * @adev: amdgpu_device pointer
 492  *
 493  * Stop the gfx async dma ring buffers (VI).
 494  */
 495 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 496 {
 497         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 498         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 499         u32 rb_cntl, ib_cntl;
 500         int i;
 501
 502         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 503             (adev->mman.buffer_funcs_ring == sdma1))
 504                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 505
 506         for (i = 0; i < adev->sdma.num_instances; i++) {
 507                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 508                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 509                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 510                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 511                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 512                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 513         }
 514         sdma0->ready = false;
 515         sdma1->ready = false;
 516 }
 517
 518 /**
 519  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 520  *
 521  * @adev: amdgpu_device pointer
 522  *
 523  * Stop the compute async dma queues (VI).
 524  */
 525 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 526 {
 527         /* XXX todo */
 528 }
 529
 530 /**
 531  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 532  *
 533  * @adev: amdgpu_device pointer
 534  * @enable: enable/disable the DMA MEs context switch.
 535  *
 536  * Halt or unhalt the async dma engines context switch (VI).
 537  */
 538 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 539 {
 540         u32 f32_cntl;
 541         int i;
 542
 543         for (i = 0; i < adev->sdma.num_instances; i++) {
 544                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 545                 if (enable)
 546                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 547                                         AUTO_CTXSW_ENABLE, 1);
 548                 else
 549                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 550                                         AUTO_CTXSW_ENABLE, 0);
 551                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 552         }
 553 }
 554
 555 /**
 556  * sdma_v3_0_enable - stop the async dma engines
 557  *
 558  * @adev: amdgpu_device pointer
 559  * @enable: enable/disable the DMA MEs.
 560  *
 561  * Halt or unhalt the async dma engines (VI).
 562  */
 563 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 564 {
 565         u32 f32_cntl;
 566         int i;
 567
 568         if (!enable) {
 569                 sdma_v3_0_gfx_stop(adev);
 570                 sdma_v3_0_rlc_stop(adev);
 571         }
 572
 573         for (i = 0; i < adev->sdma.num_instances; i++) {
 574                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 575                 if (enable)
 576                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 577                 else
 578                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 579                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 580         }
 581 }
 582
 583 /**
 584  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 585  *
 586  * @adev: amdgpu_device pointer
 587  *
 588  * Set up the gfx DMA ring buffers and enable them (VI).
 589  * Returns 0 for success, error for failure.
 590  */
 591 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 592 {
 593         struct amdgpu_ring *ring;
 594         u32 rb_cntl, ib_cntl;
 595         u32 rb_bufsz;
 596         u32 wb_offset;
 597         u32 doorbell;
 598         int i, j, r;
 599
 600         for (i = 0; i < adev->sdma.num_instances; i++) {
 601                 ring = &adev->sdma.instance[i].ring;
 602                 wb_offset = (ring->rptr_offs * 4);
 603
 604                 mutex_lock(&adev->srbm_mutex);
 605                 for (j = 0; j < 16; j++) {
 606                         vi_srbm_select(adev, 0, 0, 0, j);
 607                         /* SDMA GFX */
 608                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 609                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 610                 }
 611                 vi_srbm_select(adev, 0, 0, 0, 0);
 612                 mutex_unlock(&adev->srbm_mutex);
 613
 614                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 615                        adev->gfx.config.gb_addr_config & 0x70);
 616
 617                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 618
 619                 /* Set ring buffer size in dwords */
 620                 rb_bufsz = order_base_2(ring->ring_size / 4);
 621                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 622                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 623 #ifdef __BIG_ENDIAN
 624                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 625                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 626                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 627 #endif
 628                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 629
 630                 /* Initialize the ring buffer's read and write pointers */
 631                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 632                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 633                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 634                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 635
 636                 /* set the wb address whether it's enabled or not */
 637                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 638                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 639                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 640                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 641
 642                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 643
 644                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 645                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 646
 647                 ring->wptr = 0;
 648                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 649
 650                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 651
 652                 if (ring->use_doorbell) {
 653                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 654                                                  OFFSET, ring->doorbell_index);
 655                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 656                 } else {
 657                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 658                 }
 659                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 660
 661                 /* enable DMA RB */
 662                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 663                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 664
 665                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 666                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 667 #ifdef __BIG_ENDIAN
 668                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 669 #endif
 670                 /* enable DMA IBs */
 671                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 672
 673                 ring->ready = true;
 674         }
 675
 676         /* unhalt the MEs */
 677         sdma_v3_0_enable(adev, true);
 678         /* enable sdma ring preemption */
 679         sdma_v3_0_ctx_switch_enable(adev, true);
 680
 681         for (i = 0; i < adev->sdma.num_instances; i++) {
 682                 ring = &adev->sdma.instance[i].ring;
 683                 r = amdgpu_ring_test_ring(ring);
 684                 if (r) {
 685                         ring->ready = false;
 686                         return r;
 687                 }
 688
 689                 if (adev->mman.buffer_funcs_ring == ring)
 690                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 691         }
 692
 693         return 0;
 694 }
 695
 696 /**
 697  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 698  *
 699  * @adev: amdgpu_device pointer
 700  *
 701  * Set up the compute DMA queues and enable them (VI).
 702  * Returns 0 for success, error for failure.
 703  */
 704 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 705 {
 706         /* XXX todo */
 707         return 0;
 708 }
 709
 710 /**
 711  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 712  *
 713  * @adev: amdgpu_device pointer
 714  *
 715  * Loads the sDMA0/1 ucode.
 716  * Returns 0 for success, -EINVAL if the ucode is not available.
 717  */
 718 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 719 {
 720         const struct sdma_firmware_header_v1_0 *hdr;
 721         const __le32 *fw_data;
 722         u32 fw_size;
 723         int i, j;
 724
 725         /* halt the MEs */
 726         sdma_v3_0_enable(adev, false);
 727
 728         for (i = 0; i < adev->sdma.num_instances; i++) {
 729                 if (!adev->sdma.instance[i].fw)
 730                         return -EINVAL;
 731                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 732                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 733                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 734                 fw_data = (const __le32 *)
 735                         (adev->sdma.instance[i].fw->data +
 736                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 737                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 738                 for (j = 0; j < fw_size; j++)
 739                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 740                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 741         }
 742
 743         return 0;
 744 }
 745
 746 /**
 747  * sdma_v3_0_start - setup and start the async dma engines
 748  *
 749  * @adev: amdgpu_device pointer
 750  *
 751  * Set up the DMA engines and enable them (VI).
 752  * Returns 0 for success, error for failure.
 753  */
 754 static int sdma_v3_0_start(struct amdgpu_device *adev)
 755 {
 756         int r, i;
 757
 758         if (!adev->pp_enabled) {
 759                 if (!adev->firmware.smu_load) {
 760                         r = sdma_v3_0_load_microcode(adev);
 761                         if (r)
 762                                 return r;
 763                 } else {
 764                         for (i = 0; i < adev->sdma.num_instances; i++) {
 765                                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 766                                                                                  (i == 0) ?
 767                                                                                  AMDGPU_UCODE_ID_SDMA0 :
 768                                                                                  AMDGPU_UCODE_ID_SDMA1);
 769                                 if (r)
 770                                         return -EINVAL;
 771                         }
 772                 }
 773         }
 774
 775         /* disble sdma engine before programing it */
 776         sdma_v3_0_ctx_switch_enable(adev, false);
 777         sdma_v3_0_enable(adev, false);
 778
 779         /* start the gfx rings and rlc compute queues */
 780         r = sdma_v3_0_gfx_resume(adev);
 781         if (r)
 782                 return r;
 783         r = sdma_v3_0_rlc_resume(adev);
 784         if (r)
 785                 return r;
 786
 787         return 0;
 788 }
 789
 790 /**
 791  * sdma_v3_0_ring_test_ring - simple async dma engine test
 792  *
 793  * @ring: amdgpu_ring structure holding ring information
 794  *
 795  * Test the DMA engine by writing using it to write an
 796  * value to memory. (VI).
 797  * Returns 0 for success, error for failure.
 798  */
 799 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 800 {
 801         struct amdgpu_device *adev = ring->adev;
 802         unsigned i;
 803         unsigned index;
 804         int r;
 805         u32 tmp;
 806         u64 gpu_addr;
 807
 808         r = amdgpu_wb_get(adev, &index);
 809         if (r) {
 810                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 811                 return r;
 812         }
 813
 814         gpu_addr = adev->wb.gpu_addr + (index * 4);
 815         tmp = 0xCAFEDEAD;
 816         adev->wb.wb[index] = cpu_to_le32(tmp);
 817
 818         r = amdgpu_ring_alloc(ring, 5);
 819         if (r) {
 820                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 821                 amdgpu_wb_free(adev, index);
 822                 return r;
 823         }
 824
 825         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 826                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 827         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 828         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 829         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 830         amdgpu_ring_write(ring, 0xDEADBEEF);
 831         amdgpu_ring_commit(ring);
 832
 833         for (i = 0; i < adev->usec_timeout; i++) {
 834                 tmp = le32_to_cpu(adev->wb.wb[index]);
 835                 if (tmp == 0xDEADBEEF)
 836                         break;
 837                 DRM_UDELAY(1);
 838         }
 839
 840         if (i < adev->usec_timeout) {
 841                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 842         } else {
 843                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 844                           ring->idx, tmp);
 845                 r = -EINVAL;
 846         }
 847         amdgpu_wb_free(adev, index);
 848
 849         return r;
 850 }
 851
 852 /**
 853  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 854  *
 855  * @ring: amdgpu_ring structure holding ring information
 856  *
 857  * Test a simple IB in the DMA ring (VI).
 858  * Returns 0 on success, error on failure.
 859  */
 860 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 861 {
 862         struct amdgpu_device *adev = ring->adev;
 863         struct amdgpu_ib ib;
 864         struct fence *f = NULL;
 865         unsigned index;
 866         u32 tmp = 0;
 867         u64 gpu_addr;
 868         long r;
 869
 870         r = amdgpu_wb_get(adev, &index);
 871         if (r) {
 872                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 873                 return r;
 874         }
 875
 876         gpu_addr = adev->wb.gpu_addr + (index * 4);
 877         tmp = 0xCAFEDEAD;
 878         adev->wb.wb[index] = cpu_to_le32(tmp);
 879         memset(&ib, 0, sizeof(ib));
 880         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 881         if (r) {
 882                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 883                 goto err0;
 884         }
 885
 886         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 887                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 888         ib.ptr[1] = lower_32_bits(gpu_addr);
 889         ib.ptr[2] = upper_32_bits(gpu_addr);
 890         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 891         ib.ptr[4] = 0xDEADBEEF;
 892         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 893         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 894         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 895         ib.length_dw = 8;
 896
 897         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 898         if (r)
 899                 goto err1;
 900
 901         r = fence_wait_timeout(f, false, timeout);
 902         if (r == 0) {
 903                 DRM_ERROR("amdgpu: IB test timed out\n");
 904                 r = -ETIMEDOUT;
 905                 goto err1;
 906         } else if (r < 0) {
 907                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 908                 goto err1;
 909         }
 910         tmp = le32_to_cpu(adev->wb.wb[index]);
 911         if (tmp == 0xDEADBEEF) {
 912                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 913                 r = 0;
 914         } else {
 915                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 916                 r = -EINVAL;
 917         }
 918 err1:
 919         amdgpu_ib_free(adev, &ib, NULL);
 920         fence_put(f);
 921 err0:
 922         amdgpu_wb_free(adev, index);
 923         return r;
 924 }
 925
 926 /**
 927  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 928  *
 929  * @ib: indirect buffer to fill with commands
 930  * @pe: addr of the page entry
 931  * @src: src addr to copy from
 932  * @count: number of page entries to update
 933  *
 934  * Update PTEs by copying them from the GART using sDMA (CIK).
 935  */
 936 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 937                                   uint64_t pe, uint64_t src,
 938                                   unsigned count)
 939 {
 940         unsigned bytes = count * 8;
 941
 942         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 943                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 944         ib->ptr[ib->length_dw++] = bytes;
 945         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 946         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 947         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 948         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 949         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 950 }
 951
 952 /**
 953  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 954  *
 955  * @ib: indirect buffer to fill with commands
 956  * @pe: addr of the page entry
 957  * @value: dst addr to write into pe
 958  * @count: number of page entries to update
 959  * @incr: increase next addr by incr bytes
 960  *
 961  * Update PTEs by writing them manually using sDMA (CIK).
 962  */
 963 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 964                                    uint64_t value, unsigned count,
 965                                    uint32_t incr)
 966 {
 967         unsigned ndw = count * 2;
 968
 969         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 970                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 971         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 972         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 973         ib->ptr[ib->length_dw++] = ndw;
 974         for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 975                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 976                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 977                 value += incr;
 978         }
 979 }
 980
 981 /**
 982  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 983  *
 984  * @ib: indirect buffer to fill with commands
 985  * @pe: addr of the page entry
 986  * @addr: dst addr to write into pe
 987  * @count: number of page entries to update
 988  * @incr: increase next addr by incr bytes
 989  * @flags: access flags
 990  *
 991  * Update the page tables using sDMA (CIK).
 992  */
 993 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 994                                      uint64_t addr, unsigned count,
 995                                      uint32_t incr, uint32_t flags)
 996 {
 997         /* for physically contiguous pages (vram) */
 998         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 999         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1000         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1001         ib->ptr[ib->length_dw++] = flags; /* mask */
1002         ib->ptr[ib->length_dw++] = 0;
1003         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1004         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1005         ib->ptr[ib->length_dw++] = incr; /* increment size */
1006         ib->ptr[ib->length_dw++] = 0;
1007         ib->ptr[ib->length_dw++] = count; /* number of entries */
1008 }
1009
1010 /**
1011  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1012  *
1013  * @ib: indirect buffer to fill with padding
1014  *
1015  */
1016 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1017 {
1018         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1019         u32 pad_count;
1020         int i;
1021
1022         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1023         for (i = 0; i < pad_count; i++)
1024                 if (sdma && sdma->burst_nop && (i == 0))
1025                         ib->ptr[ib->length_dw++] =
1026                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1027                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1028                 else
1029                         ib->ptr[ib->length_dw++] =
1030                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1031 }
1032
1033 /**
1034  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1035  *
1036  * @ring: amdgpu_ring pointer
1037  *
1038  * Make sure all previous operations are completed (CIK).
1039  */
1040 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1041 {
1042         uint32_t seq = ring->fence_drv.sync_seq;
1043         uint64_t addr = ring->fence_drv.gpu_addr;
1044
1045         /* wait for idle */
1046         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1047                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1048                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1049                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1050         amdgpu_ring_write(ring, addr & 0xfffffffc);
1051         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1052         amdgpu_ring_write(ring, seq); /* reference */
1053         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1054         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1055                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1056 }
1057
1058 /**
1059  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1060  *
1061  * @ring: amdgpu_ring pointer
1062  * @vm: amdgpu_vm pointer
1063  *
1064  * Update the page table base and flush the VM TLB
1065  * using sDMA (VI).
1066  */
1067 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1068                                          unsigned vm_id, uint64_t pd_addr)
1069 {
1070         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1071                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1072         if (vm_id < 8) {
1073                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1074         } else {
1075                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1076         }
1077         amdgpu_ring_write(ring, pd_addr >> 12);
1078
1079         /* flush TLB */
1080         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1081                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1082         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1083         amdgpu_ring_write(ring, 1 << vm_id);
1084
1085         /* wait for flush */
1086         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1087                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1088                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1089         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1090         amdgpu_ring_write(ring, 0);
1091         amdgpu_ring_write(ring, 0); /* reference */
1092         amdgpu_ring_write(ring, 0); /* mask */
1093         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1094                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1095 }
1096
1097 static unsigned sdma_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
1098 {
1099         return
1100                 7 + 6; /* sdma_v3_0_ring_emit_ib */
1101 }
1102
1103 static unsigned sdma_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring)
1104 {
1105         return
1106                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1107                 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
1108                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1109                 12 + /* sdma_v3_0_ring_emit_vm_flush */
1110                 10 + 10 + 10; /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1111 }
1112
1113 static int sdma_v3_0_early_init(void *handle)
1114 {
1115         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1116
1117         switch (adev->asic_type) {
1118         case CHIP_STONEY:
1119                 adev->sdma.num_instances = 1;
1120                 break;
1121         default:
1122                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1123                 break;
1124         }
1125
1126         sdma_v3_0_set_ring_funcs(adev);
1127         sdma_v3_0_set_buffer_funcs(adev);
1128         sdma_v3_0_set_vm_pte_funcs(adev);
1129         sdma_v3_0_set_irq_funcs(adev);
1130
1131         return 0;
1132 }
1133
1134 static int sdma_v3_0_sw_init(void *handle)
1135 {
1136         struct amdgpu_ring *ring;
1137         int r, i;
1138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139
1140         /* SDMA trap event */
1141         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1142         if (r)
1143                 return r;
1144
1145         /* SDMA Privileged inst */
1146         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1147         if (r)
1148                 return r;
1149
1150         /* SDMA Privileged inst */
1151         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1152         if (r)
1153                 return r;
1154
1155         r = sdma_v3_0_init_microcode(adev);
1156         if (r) {
1157                 DRM_ERROR("Failed to load sdma firmware!\n");
1158                 return r;
1159         }
1160
1161         for (i = 0; i < adev->sdma.num_instances; i++) {
1162                 ring = &adev->sdma.instance[i].ring;
1163                 ring->ring_obj = NULL;
1164                 ring->use_doorbell = true;
1165                 ring->doorbell_index = (i == 0) ?
1166                         AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1167
1168                 sprintf(ring->name, "sdma%d", i);
1169                 r = amdgpu_ring_init(adev, ring, 1024,
1170                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1171                                      &adev->sdma.trap_irq,
1172                                      (i == 0) ?
1173                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1174                                      AMDGPU_RING_TYPE_SDMA);
1175                 if (r)
1176                         return r;
1177         }
1178
1179         return r;
1180 }
1181
1182 static int sdma_v3_0_sw_fini(void *handle)
1183 {
1184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185         int i;
1186
1187         for (i = 0; i < adev->sdma.num_instances; i++)
1188                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1189
1190         sdma_v3_0_free_microcode(adev);
1191         return 0;
1192 }
1193
1194 static int sdma_v3_0_hw_init(void *handle)
1195 {
1196         int r;
1197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1198
1199         sdma_v3_0_init_golden_registers(adev);
1200
1201         r = sdma_v3_0_start(adev);
1202         if (r)
1203                 return r;
1204
1205         return r;
1206 }
1207
1208 static int sdma_v3_0_hw_fini(void *handle)
1209 {
1210         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1211
1212         sdma_v3_0_ctx_switch_enable(adev, false);
1213         sdma_v3_0_enable(adev, false);
1214
1215         return 0;
1216 }
1217
1218 static int sdma_v3_0_suspend(void *handle)
1219 {
1220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221
1222         return sdma_v3_0_hw_fini(adev);
1223 }
1224
1225 static int sdma_v3_0_resume(void *handle)
1226 {
1227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228
1229         return sdma_v3_0_hw_init(adev);
1230 }
1231
1232 static bool sdma_v3_0_is_idle(void *handle)
1233 {
1234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235         u32 tmp = RREG32(mmSRBM_STATUS2);
1236
1237         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1238                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1239             return false;
1240
1241         return true;
1242 }
1243
1244 static int sdma_v3_0_wait_for_idle(void *handle)
1245 {
1246         unsigned i;
1247         u32 tmp;
1248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249
1250         for (i = 0; i < adev->usec_timeout; i++) {
1251                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1252                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1253
1254                 if (!tmp)
1255                         return 0;
1256                 udelay(1);
1257         }
1258         return -ETIMEDOUT;
1259 }
1260
1261 static bool sdma_v3_0_check_soft_reset(void *handle)
1262 {
1263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264         u32 srbm_soft_reset = 0;
1265         u32 tmp = RREG32(mmSRBM_STATUS2);
1266
1267         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1268             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1269                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1270                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1271         }
1272
1273         if (srbm_soft_reset) {
1274                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1275                 return true;
1276         } else {
1277                 adev->sdma.srbm_soft_reset = 0;
1278                 return false;
1279         }
1280 }
1281
1282 static int sdma_v3_0_pre_soft_reset(void *handle)
1283 {
1284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285         u32 srbm_soft_reset = 0;
1286
1287         if (!adev->sdma.srbm_soft_reset)
1288                 return 0;
1289
1290         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1291
1292         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1293             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1294                 sdma_v3_0_ctx_switch_enable(adev, false);
1295                 sdma_v3_0_enable(adev, false);
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int sdma_v3_0_post_soft_reset(void *handle)
1302 {
1303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304         u32 srbm_soft_reset = 0;
1305
1306         if (!adev->sdma.srbm_soft_reset)
1307                 return 0;
1308
1309         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1310
1311         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1312             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1313                 sdma_v3_0_gfx_resume(adev);
1314                 sdma_v3_0_rlc_resume(adev);
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int sdma_v3_0_soft_reset(void *handle)
1321 {
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323         u32 srbm_soft_reset = 0;
1324         u32 tmp;
1325
1326         if (!adev->sdma.srbm_soft_reset)
1327                 return 0;
1328
1329         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1330
1331         if (srbm_soft_reset) {
1332                 tmp = RREG32(mmSRBM_SOFT_RESET);
1333                 tmp |= srbm_soft_reset;
1334                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1335                 WREG32(mmSRBM_SOFT_RESET, tmp);
1336                 tmp = RREG32(mmSRBM_SOFT_RESET);
1337
1338                 udelay(50);
1339
1340                 tmp &= ~srbm_soft_reset;
1341                 WREG32(mmSRBM_SOFT_RESET, tmp);
1342                 tmp = RREG32(mmSRBM_SOFT_RESET);
1343
1344                 /* Wait a little for things to settle down */
1345                 udelay(50);
1346         }
1347
1348         return 0;
1349 }
1350
1351 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1352                                         struct amdgpu_irq_src *source,
1353                                         unsigned type,
1354                                         enum amdgpu_interrupt_state state)
1355 {
1356         u32 sdma_cntl;
1357
1358         switch (type) {
1359         case AMDGPU_SDMA_IRQ_TRAP0:
1360                 switch (state) {
1361                 case AMDGPU_IRQ_STATE_DISABLE:
1362                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1363                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1364                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1365                         break;
1366                 case AMDGPU_IRQ_STATE_ENABLE:
1367                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1368                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1369                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1370                         break;
1371                 default:
1372                         break;
1373                 }
1374                 break;
1375         case AMDGPU_SDMA_IRQ_TRAP1:
1376                 switch (state) {
1377                 case AMDGPU_IRQ_STATE_DISABLE:
1378                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1379                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1380                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1381                         break;
1382                 case AMDGPU_IRQ_STATE_ENABLE:
1383                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1384                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1385                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1386                         break;
1387                 default:
1388                         break;
1389                 }
1390                 break;
1391         default:
1392                 break;
1393         }
1394         return 0;
1395 }
1396
1397 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1398                                       struct amdgpu_irq_src *source,
1399                                       struct amdgpu_iv_entry *entry)
1400 {
1401         u8 instance_id, queue_id;
1402
1403         instance_id = (entry->ring_id & 0x3) >> 0;
1404         queue_id = (entry->ring_id & 0xc) >> 2;
1405         DRM_DEBUG("IH: SDMA trap\n");
1406         switch (instance_id) {
1407         case 0:
1408                 switch (queue_id) {
1409                 case 0:
1410                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1411                         break;
1412                 case 1:
1413                         /* XXX compute */
1414                         break;
1415                 case 2:
1416                         /* XXX compute */
1417                         break;
1418                 }
1419                 break;
1420         case 1:
1421                 switch (queue_id) {
1422                 case 0:
1423                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1424                         break;
1425                 case 1:
1426                         /* XXX compute */
1427                         break;
1428                 case 2:
1429                         /* XXX compute */
1430                         break;
1431                 }
1432                 break;
1433         }
1434         return 0;
1435 }
1436
1437 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1438                                               struct amdgpu_irq_src *source,
1439                                               struct amdgpu_iv_entry *entry)
1440 {
1441         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1442         schedule_work(&adev->reset_work);
1443         return 0;
1444 }
1445
1446 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1447                 struct amdgpu_device *adev,
1448                 bool enable)
1449 {
1450         uint32_t temp, data;
1451         int i;
1452
1453         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1454                 for (i = 0; i < adev->sdma.num_instances; i++) {
1455                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1456                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1457                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1458                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1459                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1460                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1461                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1462                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1463                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1464                         if (data != temp)
1465                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1466                 }
1467         } else {
1468                 for (i = 0; i < adev->sdma.num_instances; i++) {
1469                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1470                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1471                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1472                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1473                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1474                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1475                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1476                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1477                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1478
1479                         if (data != temp)
1480                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1481                 }
1482         }
1483 }
1484
1485 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1486                 struct amdgpu_device *adev,
1487                 bool enable)
1488 {
1489         uint32_t temp, data;
1490         int i;
1491
1492         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1493                 for (i = 0; i < adev->sdma.num_instances; i++) {
1494                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1495                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1496
1497                         if (temp != data)
1498                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1499                 }
1500         } else {
1501                 for (i = 0; i < adev->sdma.num_instances; i++) {
1502                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1503                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1504
1505                         if (temp != data)
1506                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1507                 }
1508         }
1509 }
1510
1511 static int sdma_v3_0_set_clockgating_state(void *handle,
1512                                           enum amd_clockgating_state state)
1513 {
1514         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1515
1516         switch (adev->asic_type) {
1517         case CHIP_FIJI:
1518         case CHIP_CARRIZO:
1519         case CHIP_STONEY:
1520                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1521                                 state == AMD_CG_STATE_GATE ? true : false);
1522                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1523                                 state == AMD_CG_STATE_GATE ? true : false);
1524                 break;
1525         default:
1526                 break;
1527         }
1528         return 0;
1529 }
1530
1531 static int sdma_v3_0_set_powergating_state(void *handle,
1532                                           enum amd_powergating_state state)
1533 {
1534         return 0;
1535 }
1536
1537 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1538         .name = "sdma_v3_0",
1539         .early_init = sdma_v3_0_early_init,
1540         .late_init = NULL,
1541         .sw_init = sdma_v3_0_sw_init,
1542         .sw_fini = sdma_v3_0_sw_fini,
1543         .hw_init = sdma_v3_0_hw_init,
1544         .hw_fini = sdma_v3_0_hw_fini,
1545         .suspend = sdma_v3_0_suspend,
1546         .resume = sdma_v3_0_resume,
1547         .is_idle = sdma_v3_0_is_idle,
1548         .wait_for_idle = sdma_v3_0_wait_for_idle,
1549         .check_soft_reset = sdma_v3_0_check_soft_reset,
1550         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1551         .post_soft_reset = sdma_v3_0_post_soft_reset,
1552         .soft_reset = sdma_v3_0_soft_reset,
1553         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1554         .set_powergating_state = sdma_v3_0_set_powergating_state,
1555 };
1556
1557 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1558         .get_rptr = sdma_v3_0_ring_get_rptr,
1559         .get_wptr = sdma_v3_0_ring_get_wptr,
1560         .set_wptr = sdma_v3_0_ring_set_wptr,
1561         .parse_cs = NULL,
1562         .emit_ib = sdma_v3_0_ring_emit_ib,
1563         .emit_fence = sdma_v3_0_ring_emit_fence,
1564         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1565         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1566         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1567         .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1568         .test_ring = sdma_v3_0_ring_test_ring,
1569         .test_ib = sdma_v3_0_ring_test_ib,
1570         .insert_nop = sdma_v3_0_ring_insert_nop,
1571         .pad_ib = sdma_v3_0_ring_pad_ib,
1572         .get_emit_ib_size = sdma_v3_0_ring_get_emit_ib_size,
1573         .get_dma_frame_size = sdma_v3_0_ring_get_dma_frame_size,
1574 };
1575
1576 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1577 {
1578         int i;
1579
1580         for (i = 0; i < adev->sdma.num_instances; i++)
1581                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1582 }
1583
1584 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1585         .set = sdma_v3_0_set_trap_irq_state,
1586         .process = sdma_v3_0_process_trap_irq,
1587 };
1588
1589 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1590         .process = sdma_v3_0_process_illegal_inst_irq,
1591 };
1592
1593 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1594 {
1595         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1596         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1597         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1598 }
1599
1600 /**
1601  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1602  *
1603  * @ring: amdgpu_ring structure holding ring information
1604  * @src_offset: src GPU address
1605  * @dst_offset: dst GPU address
1606  * @byte_count: number of bytes to xfer
1607  *
1608  * Copy GPU buffers using the DMA engine (VI).
1609  * Used by the amdgpu ttm implementation to move pages if
1610  * registered as the asic copy callback.
1611  */
1612 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1613                                        uint64_t src_offset,
1614                                        uint64_t dst_offset,
1615                                        uint32_t byte_count)
1616 {
1617         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1618                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1619         ib->ptr[ib->length_dw++] = byte_count;
1620         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1621         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1622         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1623         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1624         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1625 }
1626
1627 /**
1628  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1629  *
1630  * @ring: amdgpu_ring structure holding ring information
1631  * @src_data: value to write to buffer
1632  * @dst_offset: dst GPU address
1633  * @byte_count: number of bytes to xfer
1634  *
1635  * Fill GPU buffers using the DMA engine (VI).
1636  */
1637 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1638                                        uint32_t src_data,
1639                                        uint64_t dst_offset,
1640                                        uint32_t byte_count)
1641 {
1642         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1643         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1644         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1645         ib->ptr[ib->length_dw++] = src_data;
1646         ib->ptr[ib->length_dw++] = byte_count;
1647 }
1648
1649 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1650         .copy_max_bytes = 0x1fffff,
1651         .copy_num_dw = 7,
1652         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1653
1654         .fill_max_bytes = 0x1fffff,
1655         .fill_num_dw = 5,
1656         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1657 };
1658
1659 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1660 {
1661         if (adev->mman.buffer_funcs == NULL) {
1662                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1663                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1664         }
1665 }
1666
1667 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1668         .copy_pte = sdma_v3_0_vm_copy_pte,
1669         .write_pte = sdma_v3_0_vm_write_pte,
1670         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1671 };
1672
1673 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1674 {
1675         unsigned i;
1676
1677         if (adev->vm_manager.vm_pte_funcs == NULL) {
1678                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1679                 for (i = 0; i < adev->sdma.num_instances; i++)
1680                         adev->vm_manager.vm_pte_rings[i] =
1681                                 &adev->sdma.instance[i].ring;
1682
1683                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1684         }
1685 }