drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 #include "ivsrcid/ivsrcid_vislands30.h"
  48
  49 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 /*(DEBLOBBED)*/
  55
  56 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  57 {
  58         SDMA0_REGISTER_OFFSET,
  59         SDMA1_REGISTER_OFFSET
  60 };
  61
  62 static const u32 golden_settings_iceland_a11[] =
  63 {
  64         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  65         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  66         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  67         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  68 };
  69
  70 static const u32 iceland_mgcg_cgcg_init[] =
  71 {
  72         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  73         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  74 };
  75
  76 /*
  77  * sDMA - System DMA
  78  * Starting with CIK, the GPU has new asynchronous
  79  * DMA engines.  These engines are used for compute
  80  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  81  * and each one supports 1 ring buffer used for gfx
  82  * and 2 queues used for compute.
  83  *
  84  * The programming model is very similar to the CP
  85  * (ring buffer, IBs, etc.), but sDMA has it's own
  86  * packet format that is different from the PM4 format
  87  * used by the CP. sDMA supports copying data, writing
  88  * embedded data, solid fills, and a number of other
  89  * things.  It also has support for tiling/detiling of
  90  * buffers.
  91  */
  92
  93 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  94 {
  95         switch (adev->asic_type) {
  96         case CHIP_TOPAZ:
  97                 amdgpu_device_program_register_sequence(adev,
  98                                                         iceland_mgcg_cgcg_init,
  99                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 100                 amdgpu_device_program_register_sequence(adev,
 101                                                         golden_settings_iceland_a11,
 102                                                         ARRAY_SIZE(golden_settings_iceland_a11));
 103                 break;
 104         default:
 105                 break;
 106         }
 107 }
 108
 109 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 110 {
 111         int i;
 112         for (i = 0; i < adev->sdma.num_instances; i++) {
 113                 release_firmware(adev->sdma.instance[i].fw);
 114                 adev->sdma.instance[i].fw = NULL;
 115         }
 116 }
 117
 118 /**
 119  * sdma_v2_4_init_microcode - load ucode images from disk
 120  *
 121  * @adev: amdgpu_device pointer
 122  *
 123  * Use the firmware interface to load the ucode images into
 124  * the driver (not loaded into hw).
 125  * Returns 0 on success, error on failure.
 126  */
 127 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 128 {
 129         const char *chip_name;
 130         char fw_name[30];
 131         int err = 0, i;
 132         struct amdgpu_firmware_info *info = NULL;
 133         const struct common_firmware_header *header = NULL;
 134         const struct sdma_firmware_header_v1_0 *hdr;
 135
 136         DRM_DEBUG("\n");
 137
 138         switch (adev->asic_type) {
 139         case CHIP_TOPAZ:
 140                 chip_name = "topaz";
 141                 break;
 142         default: BUG();
 143         }
 144
 145         for (i = 0; i < adev->sdma.num_instances; i++) {
 146                 if (i == 0)
 147                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 148                 else
 149                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 150                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 151                 if (err)
 152                         goto out;
 153                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 154                 if (err)
 155                         goto out;
 156                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 157                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 158                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 159                 if (adev->sdma.instance[i].feature_version >= 20)
 160                         adev->sdma.instance[i].burst_nop = true;
 161
 162                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
 163                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 164                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 165                         info->fw = adev->sdma.instance[i].fw;
 166                         header = (const struct common_firmware_header *)info->fw->data;
 167                         adev->firmware.fw_size +=
 168                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 169                 }
 170         }
 171
 172 out:
 173         if (err) {
 174                 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
 175                 for (i = 0; i < adev->sdma.num_instances; i++) {
 176                         release_firmware(adev->sdma.instance[i].fw);
 177                         adev->sdma.instance[i].fw = NULL;
 178                 }
 179         }
 180         return err;
 181 }
 182
 183 /**
 184  * sdma_v2_4_ring_get_rptr - get the current read pointer
 185  *
 186  * @ring: amdgpu ring pointer
 187  *
 188  * Get the current rptr from the hardware (VI+).
 189  */
 190 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 191 {
 192         /* XXX check if swapping is necessary on BE */
 193         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 194 }
 195
 196 /**
 197  * sdma_v2_4_ring_get_wptr - get the current write pointer
 198  *
 199  * @ring: amdgpu ring pointer
 200  *
 201  * Get the current wptr from the hardware (VI+).
 202  */
 203 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 204 {
 205         struct amdgpu_device *adev = ring->adev;
 206         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 207
 208         return wptr;
 209 }
 210
 211 /**
 212  * sdma_v2_4_ring_set_wptr - commit the write pointer
 213  *
 214  * @ring: amdgpu ring pointer
 215  *
 216  * Write the wptr back to the hardware (VI+).
 217  */
 218 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 219 {
 220         struct amdgpu_device *adev = ring->adev;
 221
 222         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
 223 }
 224
 225 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 226 {
 227         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 228         int i;
 229
 230         for (i = 0; i < count; i++)
 231                 if (sdma && sdma->burst_nop && (i == 0))
 232                         amdgpu_ring_write(ring, ring->funcs->nop |
 233                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 234                 else
 235                         amdgpu_ring_write(ring, ring->funcs->nop);
 236 }
 237
 238 /**
 239  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 240  *
 241  * @ring: amdgpu ring pointer
 242  * @ib: IB object to schedule
 243  *
 244  * Schedule an IB in the DMA ring (VI).
 245  */
 246 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 247                                    struct amdgpu_ib *ib,
 248                                    unsigned vmid, bool ctx_switch)
 249 {
 250         /* IB packet must end on a 8 DW boundary */
 251         sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 252
 253         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 254                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 255         /* base must be 32 byte aligned */
 256         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 257         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 258         amdgpu_ring_write(ring, ib->length_dw);
 259         amdgpu_ring_write(ring, 0);
 260         amdgpu_ring_write(ring, 0);
 261
 262 }
 263
 264 /**
 265  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 266  *
 267  * @ring: amdgpu ring pointer
 268  *
 269  * Emit an hdp flush packet on the requested DMA ring.
 270  */
 271 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 272 {
 273         u32 ref_and_mask = 0;
 274
 275         if (ring->me == 0)
 276                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 277         else
 278                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 279
 280         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 281                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 282                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 283         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 284         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 285         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 286         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 287         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 288                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 289 }
 290
 291 /**
 292  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 293  *
 294  * @ring: amdgpu ring pointer
 295  * @fence: amdgpu fence object
 296  *
 297  * Add a DMA fence packet to the ring to write
 298  * the fence seq number and DMA trap packet to generate
 299  * an interrupt if needed (VI).
 300  */
 301 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 302                                       unsigned flags)
 303 {
 304         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 305         /* write the fence */
 306         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 307         amdgpu_ring_write(ring, lower_32_bits(addr));
 308         amdgpu_ring_write(ring, upper_32_bits(addr));
 309         amdgpu_ring_write(ring, lower_32_bits(seq));
 310
 311         /* optionally write high bits as well */
 312         if (write64bit) {
 313                 addr += 4;
 314                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 315                 amdgpu_ring_write(ring, lower_32_bits(addr));
 316                 amdgpu_ring_write(ring, upper_32_bits(addr));
 317                 amdgpu_ring_write(ring, upper_32_bits(seq));
 318         }
 319
 320         /* generate an interrupt */
 321         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 322         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 323 }
 324
 325 /**
 326  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 327  *
 328  * @adev: amdgpu_device pointer
 329  *
 330  * Stop the gfx async dma ring buffers (VI).
 331  */
 332 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 333 {
 334         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 335         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 336         u32 rb_cntl, ib_cntl;
 337         int i;
 338
 339         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 340             (adev->mman.buffer_funcs_ring == sdma1))
 341                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 342
 343         for (i = 0; i < adev->sdma.num_instances; i++) {
 344                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 345                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 346                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 347                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 348                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 349                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 350         }
 351         sdma0->ready = false;
 352         sdma1->ready = false;
 353 }
 354
 355 /**
 356  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 357  *
 358  * @adev: amdgpu_device pointer
 359  *
 360  * Stop the compute async dma queues (VI).
 361  */
 362 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 363 {
 364         /* XXX todo */
 365 }
 366
 367 /**
 368  * sdma_v2_4_enable - stop the async dma engines
 369  *
 370  * @adev: amdgpu_device pointer
 371  * @enable: enable/disable the DMA MEs.
 372  *
 373  * Halt or unhalt the async dma engines (VI).
 374  */
 375 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 376 {
 377         u32 f32_cntl;
 378         int i;
 379
 380         if (!enable) {
 381                 sdma_v2_4_gfx_stop(adev);
 382                 sdma_v2_4_rlc_stop(adev);
 383         }
 384
 385         for (i = 0; i < adev->sdma.num_instances; i++) {
 386                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 387                 if (enable)
 388                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 389                 else
 390                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 391                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 392         }
 393 }
 394
 395 /**
 396  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 397  *
 398  * @adev: amdgpu_device pointer
 399  *
 400  * Set up the gfx DMA ring buffers and enable them (VI).
 401  * Returns 0 for success, error for failure.
 402  */
 403 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 404 {
 405         struct amdgpu_ring *ring;
 406         u32 rb_cntl, ib_cntl;
 407         u32 rb_bufsz;
 408         u32 wb_offset;
 409         int i, j, r;
 410
 411         for (i = 0; i < adev->sdma.num_instances; i++) {
 412                 ring = &adev->sdma.instance[i].ring;
 413                 wb_offset = (ring->rptr_offs * 4);
 414
 415                 mutex_lock(&adev->srbm_mutex);
 416                 for (j = 0; j < 16; j++) {
 417                         vi_srbm_select(adev, 0, 0, 0, j);
 418                         /* SDMA GFX */
 419                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 420                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 421                 }
 422                 vi_srbm_select(adev, 0, 0, 0, 0);
 423                 mutex_unlock(&adev->srbm_mutex);
 424
 425                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 426                        adev->gfx.config.gb_addr_config & 0x70);
 427
 428                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 429
 430                 /* Set ring buffer size in dwords */
 431                 rb_bufsz = order_base_2(ring->ring_size / 4);
 432                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 433                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 434 #ifdef __BIG_ENDIAN
 435                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 436                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 437                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 438 #endif
 439                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 440
 441                 /* Initialize the ring buffer's read and write pointers */
 442                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 443                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 444                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 445                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 446
 447                 /* set the wb address whether it's enabled or not */
 448                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 449                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 450                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 451                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 452
 453                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 454
 455                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 456                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 457
 458                 ring->wptr = 0;
 459                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 460
 461                 /* enable DMA RB */
 462                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 463                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 464
 465                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 466                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 467 #ifdef __BIG_ENDIAN
 468                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 469 #endif
 470                 /* enable DMA IBs */
 471                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 472
 473                 ring->ready = true;
 474         }
 475
 476         sdma_v2_4_enable(adev, true);
 477         for (i = 0; i < adev->sdma.num_instances; i++) {
 478                 ring = &adev->sdma.instance[i].ring;
 479                 r = amdgpu_ring_test_ring(ring);
 480                 if (r) {
 481                         ring->ready = false;
 482                         return r;
 483                 }
 484
 485                 if (adev->mman.buffer_funcs_ring == ring)
 486                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 487         }
 488
 489         return 0;
 490 }
 491
 492 /**
 493  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 494  *
 495  * @adev: amdgpu_device pointer
 496  *
 497  * Set up the compute DMA queues and enable them (VI).
 498  * Returns 0 for success, error for failure.
 499  */
 500 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 501 {
 502         /* XXX todo */
 503         return 0;
 504 }
 505
 506 /**
 507  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 508  *
 509  * @adev: amdgpu_device pointer
 510  *
 511  * Loads the sDMA0/1 ucode.
 512  * Returns 0 for success, -EINVAL if the ucode is not available.
 513  */
 514 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 515 {
 516         const struct sdma_firmware_header_v1_0 *hdr;
 517         const __le32 *fw_data;
 518         u32 fw_size;
 519         int i, j;
 520
 521         /* halt the MEs */
 522         sdma_v2_4_enable(adev, false);
 523
 524         for (i = 0; i < adev->sdma.num_instances; i++) {
 525                 if (!adev->sdma.instance[i].fw)
 526                         return -EINVAL;
 527                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 528                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 529                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 530                 fw_data = (const __le32 *)
 531                         (adev->sdma.instance[i].fw->data +
 532                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 533                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 534                 for (j = 0; j < fw_size; j++)
 535                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 536                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 537         }
 538
 539         return 0;
 540 }
 541
 542 /**
 543  * sdma_v2_4_start - setup and start the async dma engines
 544  *
 545  * @adev: amdgpu_device pointer
 546  *
 547  * Set up the DMA engines and enable them (VI).
 548  * Returns 0 for success, error for failure.
 549  */
 550 static int sdma_v2_4_start(struct amdgpu_device *adev)
 551 {
 552         int r;
 553
 554
 555         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 556                 r = sdma_v2_4_load_microcode(adev);
 557                 if (r)
 558                         return r;
 559         }
 560
 561         /* halt the engine before programing */
 562         sdma_v2_4_enable(adev, false);
 563
 564         /* start the gfx rings and rlc compute queues */
 565         r = sdma_v2_4_gfx_resume(adev);
 566         if (r)
 567                 return r;
 568         r = sdma_v2_4_rlc_resume(adev);
 569         if (r)
 570                 return r;
 571
 572         return 0;
 573 }
 574
 575 /**
 576  * sdma_v2_4_ring_test_ring - simple async dma engine test
 577  *
 578  * @ring: amdgpu_ring structure holding ring information
 579  *
 580  * Test the DMA engine by writing using it to write an
 581  * value to memory. (VI).
 582  * Returns 0 for success, error for failure.
 583  */
 584 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 585 {
 586         struct amdgpu_device *adev = ring->adev;
 587         unsigned i;
 588         unsigned index;
 589         int r;
 590         u32 tmp;
 591         u64 gpu_addr;
 592
 593         r = amdgpu_device_wb_get(adev, &index);
 594         if (r) {
 595                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 596                 return r;
 597         }
 598
 599         gpu_addr = adev->wb.gpu_addr + (index * 4);
 600         tmp = 0xCAFEDEAD;
 601         adev->wb.wb[index] = cpu_to_le32(tmp);
 602
 603         r = amdgpu_ring_alloc(ring, 5);
 604         if (r) {
 605                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 606                 amdgpu_device_wb_free(adev, index);
 607                 return r;
 608         }
 609
 610         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 611                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 612         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 613         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 614         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 615         amdgpu_ring_write(ring, 0xDEADBEEF);
 616         amdgpu_ring_commit(ring);
 617
 618         for (i = 0; i < adev->usec_timeout; i++) {
 619                 tmp = le32_to_cpu(adev->wb.wb[index]);
 620                 if (tmp == 0xDEADBEEF)
 621                         break;
 622                 DRM_UDELAY(1);
 623         }
 624
 625         if (i < adev->usec_timeout) {
 626                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 627         } else {
 628                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 629                           ring->idx, tmp);
 630                 r = -EINVAL;
 631         }
 632         amdgpu_device_wb_free(adev, index);
 633
 634         return r;
 635 }
 636
 637 /**
 638  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 639  *
 640  * @ring: amdgpu_ring structure holding ring information
 641  *
 642  * Test a simple IB in the DMA ring (VI).
 643  * Returns 0 on success, error on failure.
 644  */
 645 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 646 {
 647         struct amdgpu_device *adev = ring->adev;
 648         struct amdgpu_ib ib;
 649         struct dma_fence *f = NULL;
 650         unsigned index;
 651         u32 tmp = 0;
 652         u64 gpu_addr;
 653         long r;
 654
 655         r = amdgpu_device_wb_get(adev, &index);
 656         if (r) {
 657                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 658                 return r;
 659         }
 660
 661         gpu_addr = adev->wb.gpu_addr + (index * 4);
 662         tmp = 0xCAFEDEAD;
 663         adev->wb.wb[index] = cpu_to_le32(tmp);
 664         memset(&ib, 0, sizeof(ib));
 665         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 666         if (r) {
 667                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 668                 goto err0;
 669         }
 670
 671         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 672                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 673         ib.ptr[1] = lower_32_bits(gpu_addr);
 674         ib.ptr[2] = upper_32_bits(gpu_addr);
 675         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 676         ib.ptr[4] = 0xDEADBEEF;
 677         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 678         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 679         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 680         ib.length_dw = 8;
 681
 682         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 683         if (r)
 684                 goto err1;
 685
 686         r = dma_fence_wait_timeout(f, false, timeout);
 687         if (r == 0) {
 688                 DRM_ERROR("amdgpu: IB test timed out\n");
 689                 r = -ETIMEDOUT;
 690                 goto err1;
 691         } else if (r < 0) {
 692                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 693                 goto err1;
 694         }
 695         tmp = le32_to_cpu(adev->wb.wb[index]);
 696         if (tmp == 0xDEADBEEF) {
 697                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 698                 r = 0;
 699         } else {
 700                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 701                 r = -EINVAL;
 702         }
 703
 704 err1:
 705         amdgpu_ib_free(adev, &ib, NULL);
 706         dma_fence_put(f);
 707 err0:
 708         amdgpu_device_wb_free(adev, index);
 709         return r;
 710 }
 711
 712 /**
 713  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 714  *
 715  * @ib: indirect buffer to fill with commands
 716  * @pe: addr of the page entry
 717  * @src: src addr to copy from
 718  * @count: number of page entries to update
 719  *
 720  * Update PTEs by copying them from the GART using sDMA (CIK).
 721  */
 722 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 723                                   uint64_t pe, uint64_t src,
 724                                   unsigned count)
 725 {
 726         unsigned bytes = count * 8;
 727
 728         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 729                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 730         ib->ptr[ib->length_dw++] = bytes;
 731         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 732         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 733         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 734         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 735         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 736 }
 737
 738 /**
 739  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 740  *
 741  * @ib: indirect buffer to fill with commands
 742  * @pe: addr of the page entry
 743  * @value: dst addr to write into pe
 744  * @count: number of page entries to update
 745  * @incr: increase next addr by incr bytes
 746  *
 747  * Update PTEs by writing them manually using sDMA (CIK).
 748  */
 749 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 750                                    uint64_t value, unsigned count,
 751                                    uint32_t incr)
 752 {
 753         unsigned ndw = count * 2;
 754
 755         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 756                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 757         ib->ptr[ib->length_dw++] = pe;
 758         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 759         ib->ptr[ib->length_dw++] = ndw;
 760         for (; ndw > 0; ndw -= 2) {
 761                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 762                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 763                 value += incr;
 764         }
 765 }
 766
 767 /**
 768  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 769  *
 770  * @ib: indirect buffer to fill with commands
 771  * @pe: addr of the page entry
 772  * @addr: dst addr to write into pe
 773  * @count: number of page entries to update
 774  * @incr: increase next addr by incr bytes
 775  * @flags: access flags
 776  *
 777  * Update the page tables using sDMA (CIK).
 778  */
 779 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 780                                      uint64_t addr, unsigned count,
 781                                      uint32_t incr, uint64_t flags)
 782 {
 783         /* for physically contiguous pages (vram) */
 784         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 785         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 786         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 787         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 788         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 789         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 790         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 791         ib->ptr[ib->length_dw++] = incr; /* increment size */
 792         ib->ptr[ib->length_dw++] = 0;
 793         ib->ptr[ib->length_dw++] = count; /* number of entries */
 794 }
 795
 796 /**
 797  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 798  *
 799  * @ib: indirect buffer to fill with padding
 800  *
 801  */
 802 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 803 {
 804         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 805         u32 pad_count;
 806         int i;
 807
 808         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 809         for (i = 0; i < pad_count; i++)
 810                 if (sdma && sdma->burst_nop && (i == 0))
 811                         ib->ptr[ib->length_dw++] =
 812                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 813                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 814                 else
 815                         ib->ptr[ib->length_dw++] =
 816                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 817 }
 818
 819 /**
 820  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 821  *
 822  * @ring: amdgpu_ring pointer
 823  *
 824  * Make sure all previous operations are completed (CIK).
 825  */
 826 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 827 {
 828         uint32_t seq = ring->fence_drv.sync_seq;
 829         uint64_t addr = ring->fence_drv.gpu_addr;
 830
 831         /* wait for idle */
 832         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 833                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 834                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 835                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 836         amdgpu_ring_write(ring, addr & 0xfffffffc);
 837         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 838         amdgpu_ring_write(ring, seq); /* reference */
 839         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 840         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 841                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 842 }
 843
 844 /**
 845  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 846  *
 847  * @ring: amdgpu_ring pointer
 848  * @vm: amdgpu_vm pointer
 849  *
 850  * Update the page table base and flush the VM TLB
 851  * using sDMA (VI).
 852  */
 853 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 854                                          unsigned vmid, uint64_t pd_addr)
 855 {
 856         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 857
 858         /* wait for flush */
 859         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 860                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 861                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 862         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 863         amdgpu_ring_write(ring, 0);
 864         amdgpu_ring_write(ring, 0); /* reference */
 865         amdgpu_ring_write(ring, 0); /* mask */
 866         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 867                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 868 }
 869
 870 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
 871                                      uint32_t reg, uint32_t val)
 872 {
 873         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 874                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 875         amdgpu_ring_write(ring, reg);
 876         amdgpu_ring_write(ring, val);
 877 }
 878
 879 static int sdma_v2_4_early_init(void *handle)
 880 {
 881         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 882
 883         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 884
 885         sdma_v2_4_set_ring_funcs(adev);
 886         sdma_v2_4_set_buffer_funcs(adev);
 887         sdma_v2_4_set_vm_pte_funcs(adev);
 888         sdma_v2_4_set_irq_funcs(adev);
 889
 890         return 0;
 891 }
 892
 893 static int sdma_v2_4_sw_init(void *handle)
 894 {
 895         struct amdgpu_ring *ring;
 896         int r, i;
 897         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 898
 899         /* SDMA trap event */
 900         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
 901                               &adev->sdma.trap_irq);
 902         if (r)
 903                 return r;
 904
 905         /* SDMA Privileged inst */
 906         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
 907                               &adev->sdma.illegal_inst_irq);
 908         if (r)
 909                 return r;
 910
 911         /* SDMA Privileged inst */
 912         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
 913                               &adev->sdma.illegal_inst_irq);
 914         if (r)
 915                 return r;
 916
 917         r = sdma_v2_4_init_microcode(adev);
 918         if (r) {
 919                 DRM_ERROR("Failed to load sdma firmware!\n");
 920                 return r;
 921         }
 922
 923         for (i = 0; i < adev->sdma.num_instances; i++) {
 924                 ring = &adev->sdma.instance[i].ring;
 925                 ring->ring_obj = NULL;
 926                 ring->use_doorbell = false;
 927                 sprintf(ring->name, "sdma%d", i);
 928                 r = amdgpu_ring_init(adev, ring, 1024,
 929                                      &adev->sdma.trap_irq,
 930                                      (i == 0) ?
 931                                      AMDGPU_SDMA_IRQ_TRAP0 :
 932                                      AMDGPU_SDMA_IRQ_TRAP1);
 933                 if (r)
 934                         return r;
 935         }
 936
 937         return r;
 938 }
 939
 940 static int sdma_v2_4_sw_fini(void *handle)
 941 {
 942         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 943         int i;
 944
 945         for (i = 0; i < adev->sdma.num_instances; i++)
 946                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 947
 948         sdma_v2_4_free_microcode(adev);
 949         return 0;
 950 }
 951
 952 static int sdma_v2_4_hw_init(void *handle)
 953 {
 954         int r;
 955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 956
 957         sdma_v2_4_init_golden_registers(adev);
 958
 959         r = sdma_v2_4_start(adev);
 960         if (r)
 961                 return r;
 962
 963         return r;
 964 }
 965
 966 static int sdma_v2_4_hw_fini(void *handle)
 967 {
 968         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 969
 970         sdma_v2_4_enable(adev, false);
 971
 972         return 0;
 973 }
 974
 975 static int sdma_v2_4_suspend(void *handle)
 976 {
 977         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 978
 979         return sdma_v2_4_hw_fini(adev);
 980 }
 981
 982 static int sdma_v2_4_resume(void *handle)
 983 {
 984         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 985
 986         return sdma_v2_4_hw_init(adev);
 987 }
 988
 989 static bool sdma_v2_4_is_idle(void *handle)
 990 {
 991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 992         u32 tmp = RREG32(mmSRBM_STATUS2);
 993
 994         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
 995                    SRBM_STATUS2__SDMA1_BUSY_MASK))
 996             return false;
 997
 998         return true;
 999 }
1000
1001 static int sdma_v2_4_wait_for_idle(void *handle)
1002 {
1003         unsigned i;
1004         u32 tmp;
1005         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006
1007         for (i = 0; i < adev->usec_timeout; i++) {
1008                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1009                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1010
1011                 if (!tmp)
1012                         return 0;
1013                 udelay(1);
1014         }
1015         return -ETIMEDOUT;
1016 }
1017
1018 static int sdma_v2_4_soft_reset(void *handle)
1019 {
1020         u32 srbm_soft_reset = 0;
1021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022         u32 tmp = RREG32(mmSRBM_STATUS2);
1023
1024         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1025                 /* sdma0 */
1026                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1027                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1028                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1029                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1030         }
1031         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1032                 /* sdma1 */
1033                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1034                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1035                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1036                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1037         }
1038
1039         if (srbm_soft_reset) {
1040                 tmp = RREG32(mmSRBM_SOFT_RESET);
1041                 tmp |= srbm_soft_reset;
1042                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1043                 WREG32(mmSRBM_SOFT_RESET, tmp);
1044                 tmp = RREG32(mmSRBM_SOFT_RESET);
1045
1046                 udelay(50);
1047
1048                 tmp &= ~srbm_soft_reset;
1049                 WREG32(mmSRBM_SOFT_RESET, tmp);
1050                 tmp = RREG32(mmSRBM_SOFT_RESET);
1051
1052                 /* Wait a little for things to settle down */
1053                 udelay(50);
1054         }
1055
1056         return 0;
1057 }
1058
1059 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1060                                         struct amdgpu_irq_src *src,
1061                                         unsigned type,
1062                                         enum amdgpu_interrupt_state state)
1063 {
1064         u32 sdma_cntl;
1065
1066         switch (type) {
1067         case AMDGPU_SDMA_IRQ_TRAP0:
1068                 switch (state) {
1069                 case AMDGPU_IRQ_STATE_DISABLE:
1070                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1071                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1072                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1073                         break;
1074                 case AMDGPU_IRQ_STATE_ENABLE:
1075                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1076                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1077                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1078                         break;
1079                 default:
1080                         break;
1081                 }
1082                 break;
1083         case AMDGPU_SDMA_IRQ_TRAP1:
1084                 switch (state) {
1085                 case AMDGPU_IRQ_STATE_DISABLE:
1086                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1087                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1088                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1089                         break;
1090                 case AMDGPU_IRQ_STATE_ENABLE:
1091                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1092                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1093                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1094                         break;
1095                 default:
1096                         break;
1097                 }
1098                 break;
1099         default:
1100                 break;
1101         }
1102         return 0;
1103 }
1104
1105 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1106                                       struct amdgpu_irq_src *source,
1107                                       struct amdgpu_iv_entry *entry)
1108 {
1109         u8 instance_id, queue_id;
1110
1111         instance_id = (entry->ring_id & 0x3) >> 0;
1112         queue_id = (entry->ring_id & 0xc) >> 2;
1113         DRM_DEBUG("IH: SDMA trap\n");
1114         switch (instance_id) {
1115         case 0:
1116                 switch (queue_id) {
1117                 case 0:
1118                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1119                         break;
1120                 case 1:
1121                         /* XXX compute */
1122                         break;
1123                 case 2:
1124                         /* XXX compute */
1125                         break;
1126                 }
1127                 break;
1128         case 1:
1129                 switch (queue_id) {
1130                 case 0:
1131                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1132                         break;
1133                 case 1:
1134                         /* XXX compute */
1135                         break;
1136                 case 2:
1137                         /* XXX compute */
1138                         break;
1139                 }
1140                 break;
1141         }
1142         return 0;
1143 }
1144
1145 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1146                                               struct amdgpu_irq_src *source,
1147                                               struct amdgpu_iv_entry *entry)
1148 {
1149         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1150         schedule_work(&adev->reset_work);
1151         return 0;
1152 }
1153
1154 static int sdma_v2_4_set_clockgating_state(void *handle,
1155                                           enum amd_clockgating_state state)
1156 {
1157         /* XXX handled via the smc on VI */
1158         return 0;
1159 }
1160
1161 static int sdma_v2_4_set_powergating_state(void *handle,
1162                                           enum amd_powergating_state state)
1163 {
1164         return 0;
1165 }
1166
1167 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1168         .name = "sdma_v2_4",
1169         .early_init = sdma_v2_4_early_init,
1170         .late_init = NULL,
1171         .sw_init = sdma_v2_4_sw_init,
1172         .sw_fini = sdma_v2_4_sw_fini,
1173         .hw_init = sdma_v2_4_hw_init,
1174         .hw_fini = sdma_v2_4_hw_fini,
1175         .suspend = sdma_v2_4_suspend,
1176         .resume = sdma_v2_4_resume,
1177         .is_idle = sdma_v2_4_is_idle,
1178         .wait_for_idle = sdma_v2_4_wait_for_idle,
1179         .soft_reset = sdma_v2_4_soft_reset,
1180         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1181         .set_powergating_state = sdma_v2_4_set_powergating_state,
1182 };
1183
1184 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1185         .type = AMDGPU_RING_TYPE_SDMA,
1186         .align_mask = 0xf,
1187         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1188         .support_64bit_ptrs = false,
1189         .get_rptr = sdma_v2_4_ring_get_rptr,
1190         .get_wptr = sdma_v2_4_ring_get_wptr,
1191         .set_wptr = sdma_v2_4_ring_set_wptr,
1192         .emit_frame_size =
1193                 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1194                 3 + /* hdp invalidate */
1195                 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1196                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1197                 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1198         .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1199         .emit_ib = sdma_v2_4_ring_emit_ib,
1200         .emit_fence = sdma_v2_4_ring_emit_fence,
1201         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1202         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1203         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1204         .test_ring = sdma_v2_4_ring_test_ring,
1205         .test_ib = sdma_v2_4_ring_test_ib,
1206         .insert_nop = sdma_v2_4_ring_insert_nop,
1207         .pad_ib = sdma_v2_4_ring_pad_ib,
1208         .emit_wreg = sdma_v2_4_ring_emit_wreg,
1209 };
1210
1211 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1212 {
1213         int i;
1214
1215         for (i = 0; i < adev->sdma.num_instances; i++) {
1216                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1217                 adev->sdma.instance[i].ring.me = i;
1218         }
1219 }
1220
1221 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1222         .set = sdma_v2_4_set_trap_irq_state,
1223         .process = sdma_v2_4_process_trap_irq,
1224 };
1225
1226 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1227         .process = sdma_v2_4_process_illegal_inst_irq,
1228 };
1229
1230 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1231 {
1232         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1233         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1234         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1235 }
1236
1237 /**
1238  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1239  *
1240  * @ring: amdgpu_ring structure holding ring information
1241  * @src_offset: src GPU address
1242  * @dst_offset: dst GPU address
1243  * @byte_count: number of bytes to xfer
1244  *
1245  * Copy GPU buffers using the DMA engine (VI).
1246  * Used by the amdgpu ttm implementation to move pages if
1247  * registered as the asic copy callback.
1248  */
1249 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1250                                        uint64_t src_offset,
1251                                        uint64_t dst_offset,
1252                                        uint32_t byte_count)
1253 {
1254         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1255                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1256         ib->ptr[ib->length_dw++] = byte_count;
1257         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1258         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1259         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1260         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1261         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1262 }
1263
1264 /**
1265  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1266  *
1267  * @ring: amdgpu_ring structure holding ring information
1268  * @src_data: value to write to buffer
1269  * @dst_offset: dst GPU address
1270  * @byte_count: number of bytes to xfer
1271  *
1272  * Fill GPU buffers using the DMA engine (VI).
1273  */
1274 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1275                                        uint32_t src_data,
1276                                        uint64_t dst_offset,
1277                                        uint32_t byte_count)
1278 {
1279         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1280         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1281         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1282         ib->ptr[ib->length_dw++] = src_data;
1283         ib->ptr[ib->length_dw++] = byte_count;
1284 }
1285
1286 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1287         .copy_max_bytes = 0x1fffff,
1288         .copy_num_dw = 7,
1289         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1290
1291         .fill_max_bytes = 0x1fffff,
1292         .fill_num_dw = 7,
1293         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1294 };
1295
1296 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1297 {
1298         if (adev->mman.buffer_funcs == NULL) {
1299                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1300                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1301         }
1302 }
1303
1304 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1305         .copy_pte_num_dw = 7,
1306         .copy_pte = sdma_v2_4_vm_copy_pte,
1307
1308         .write_pte = sdma_v2_4_vm_write_pte,
1309         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1310 };
1311
1312 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1313 {
1314         unsigned i;
1315
1316         if (adev->vm_manager.vm_pte_funcs == NULL) {
1317                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1318                 for (i = 0; i < adev->sdma.num_instances; i++)
1319                         adev->vm_manager.vm_pte_rings[i] =
1320                                 &adev->sdma.instance[i].ring;
1321
1322                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1323         }
1324 }
1325
1326 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1327 {
1328         .type = AMD_IP_BLOCK_TYPE_SDMA,
1329         .major = 2,
1330         .minor = 4,
1331         .rev = 0,
1332         .funcs = &sdma_v2_4_ip_funcs,
1333 };