2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
35 #include "gmc/gmc_7_1_d.h"
36 #include "gmc/gmc_7_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "iceland_sdma_pkt_open.h"
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
54 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
56 SDMA0_REGISTER_OFFSET,
60 static const u32 golden_settings_iceland_a11[] =
62 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
63 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
64 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
65 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
68 static const u32 iceland_mgcg_cgcg_init[] =
70 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
71 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
76 * Starting with CIK, the GPU has new asynchronous
77 * DMA engines. These engines are used for compute
78 * and gfx. There are two DMA engines (SDMA0, SDMA1)
79 * and each one supports 1 ring buffer used for gfx
80 * and 2 queues used for compute.
82 * The programming model is very similar to the CP
83 * (ring buffer, IBs, etc.), but sDMA has it's own
84 * packet format that is different from the PM4 format
85 * used by the CP. sDMA supports copying data, writing
86 * embedded data, solid fills, and a number of other
87 * things. It also has support for tiling/detiling of
91 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
93 switch (adev->asic_type) {
95 amdgpu_program_register_sequence(adev,
96 iceland_mgcg_cgcg_init,
97 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
98 amdgpu_program_register_sequence(adev,
99 golden_settings_iceland_a11,
100 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
108 * sdma_v2_4_init_microcode - load ucode images from disk
110 * @adev: amdgpu_device pointer
112 * Use the firmware interface to load the ucode images into
113 * the driver (not loaded into hw).
114 * Returns 0 on success, error on failure.
116 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
118 const char *chip_name;
121 struct amdgpu_firmware_info *info = NULL;
122 const struct common_firmware_header *header = NULL;
123 const struct sdma_firmware_header_v1_0 *hdr;
127 switch (adev->asic_type) {
134 for (i = 0; i < adev->sdma.num_instances; i++) {
136 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
138 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
139 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
142 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
145 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
146 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
147 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
148 if (adev->sdma.instance[i].feature_version >= 20)
149 adev->sdma.instance[i].burst_nop = true;
151 if (adev->firmware.smu_load) {
152 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
153 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
154 info->fw = adev->sdma.instance[i].fw;
155 header = (const struct common_firmware_header *)info->fw->data;
156 adev->firmware.fw_size +=
157 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
164 "sdma_v2_4: Failed to load firmware \"%s\"\n",
166 for (i = 0; i < adev->sdma.num_instances; i++) {
167 release_firmware(adev->sdma.instance[i].fw);
168 adev->sdma.instance[i].fw = NULL;
175 * sdma_v2_4_ring_get_rptr - get the current read pointer
177 * @ring: amdgpu ring pointer
179 * Get the current rptr from the hardware (VI+).
181 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
185 /* XXX check if swapping is necessary on BE */
186 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
192 * sdma_v2_4_ring_get_wptr - get the current write pointer
194 * @ring: amdgpu ring pointer
196 * Get the current wptr from the hardware (VI+).
198 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
200 struct amdgpu_device *adev = ring->adev;
201 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
202 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
208 * sdma_v2_4_ring_set_wptr - commit the write pointer
210 * @ring: amdgpu ring pointer
212 * Write the wptr back to the hardware (VI+).
214 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
216 struct amdgpu_device *adev = ring->adev;
217 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
219 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
222 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
224 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
227 for (i = 0; i < count; i++)
228 if (sdma && sdma->burst_nop && (i == 0))
229 amdgpu_ring_write(ring, ring->nop |
230 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
232 amdgpu_ring_write(ring, ring->nop);
236 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
238 * @ring: amdgpu ring pointer
239 * @ib: IB object to schedule
241 * Schedule an IB in the DMA ring (VI).
243 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
244 struct amdgpu_ib *ib)
246 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
247 u32 next_rptr = ring->wptr + 5;
249 while ((next_rptr & 7) != 2)
254 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
255 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
256 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
257 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
258 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
259 amdgpu_ring_write(ring, next_rptr);
261 /* IB packet must end on a 8 DW boundary */
262 sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
264 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
265 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
266 /* base must be 32 byte aligned */
267 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
268 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
269 amdgpu_ring_write(ring, ib->length_dw);
270 amdgpu_ring_write(ring, 0);
271 amdgpu_ring_write(ring, 0);
276 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
278 * @ring: amdgpu ring pointer
280 * Emit an hdp flush packet on the requested DMA ring.
282 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
284 u32 ref_and_mask = 0;
286 if (ring == &ring->adev->sdma.instance[0].ring)
287 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
291 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
292 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
293 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
294 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
295 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
296 amdgpu_ring_write(ring, ref_and_mask); /* reference */
297 amdgpu_ring_write(ring, ref_and_mask); /* mask */
298 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
299 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
303 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
305 * @ring: amdgpu ring pointer
306 * @fence: amdgpu fence object
308 * Add a DMA fence packet to the ring to write
309 * the fence seq number and DMA trap packet to generate
310 * an interrupt if needed (VI).
312 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
315 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
316 /* write the fence */
317 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
318 amdgpu_ring_write(ring, lower_32_bits(addr));
319 amdgpu_ring_write(ring, upper_32_bits(addr));
320 amdgpu_ring_write(ring, lower_32_bits(seq));
322 /* optionally write high bits as well */
325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
326 amdgpu_ring_write(ring, lower_32_bits(addr));
327 amdgpu_ring_write(ring, upper_32_bits(addr));
328 amdgpu_ring_write(ring, upper_32_bits(seq));
331 /* generate an interrupt */
332 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
333 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
337 * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
339 * @ring: amdgpu_ring structure holding ring information
340 * @semaphore: amdgpu semaphore object
341 * @emit_wait: wait or signal semaphore
343 * Add a DMA semaphore packet to the ring wait on or signal
346 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
347 struct amdgpu_semaphore *semaphore,
350 u64 addr = semaphore->gpu_addr;
351 u32 sig = emit_wait ? 0 : 1;
353 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
354 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
355 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
356 amdgpu_ring_write(ring, upper_32_bits(addr));
362 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
364 * @adev: amdgpu_device pointer
366 * Stop the gfx async dma ring buffers (VI).
368 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
370 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
371 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
372 u32 rb_cntl, ib_cntl;
375 if ((adev->mman.buffer_funcs_ring == sdma0) ||
376 (adev->mman.buffer_funcs_ring == sdma1))
377 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
379 for (i = 0; i < adev->sdma.num_instances; i++) {
380 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
381 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
382 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
383 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
384 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
385 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
387 sdma0->ready = false;
388 sdma1->ready = false;
392 * sdma_v2_4_rlc_stop - stop the compute async dma engines
394 * @adev: amdgpu_device pointer
396 * Stop the compute async dma queues (VI).
398 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
404 * sdma_v2_4_enable - stop the async dma engines
406 * @adev: amdgpu_device pointer
407 * @enable: enable/disable the DMA MEs.
409 * Halt or unhalt the async dma engines (VI).
411 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
416 if (enable == false) {
417 sdma_v2_4_gfx_stop(adev);
418 sdma_v2_4_rlc_stop(adev);
421 for (i = 0; i < adev->sdma.num_instances; i++) {
422 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
424 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
426 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
427 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
432 * sdma_v2_4_gfx_resume - setup and start the async dma engines
434 * @adev: amdgpu_device pointer
436 * Set up the gfx DMA ring buffers and enable them (VI).
437 * Returns 0 for success, error for failure.
439 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
441 struct amdgpu_ring *ring;
442 u32 rb_cntl, ib_cntl;
447 for (i = 0; i < adev->sdma.num_instances; i++) {
448 ring = &adev->sdma.instance[i].ring;
449 wb_offset = (ring->rptr_offs * 4);
451 mutex_lock(&adev->srbm_mutex);
452 for (j = 0; j < 16; j++) {
453 vi_srbm_select(adev, 0, 0, 0, j);
455 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
456 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
458 vi_srbm_select(adev, 0, 0, 0, 0);
459 mutex_unlock(&adev->srbm_mutex);
461 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
463 /* Set ring buffer size in dwords */
464 rb_bufsz = order_base_2(ring->ring_size / 4);
465 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
466 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
468 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
469 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
470 RPTR_WRITEBACK_SWAP_ENABLE, 1);
472 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
474 /* Initialize the ring buffer's read and write pointers */
475 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
476 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
478 /* set the wb address whether it's enabled or not */
479 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
480 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
481 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
482 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
484 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
486 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
487 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
490 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
493 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
494 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
496 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
497 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
499 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
502 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
506 r = amdgpu_ring_test_ring(ring);
512 if (adev->mman.buffer_funcs_ring == ring)
513 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
520 * sdma_v2_4_rlc_resume - setup and start the async dma engines
522 * @adev: amdgpu_device pointer
524 * Set up the compute DMA queues and enable them (VI).
525 * Returns 0 for success, error for failure.
527 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
534 * sdma_v2_4_load_microcode - load the sDMA ME ucode
536 * @adev: amdgpu_device pointer
538 * Loads the sDMA0/1 ucode.
539 * Returns 0 for success, -EINVAL if the ucode is not available.
541 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
543 const struct sdma_firmware_header_v1_0 *hdr;
544 const __le32 *fw_data;
549 sdma_v2_4_enable(adev, false);
551 for (i = 0; i < adev->sdma.num_instances; i++) {
552 if (!adev->sdma.instance[i].fw)
554 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
555 amdgpu_ucode_print_sdma_hdr(&hdr->header);
556 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
557 fw_data = (const __le32 *)
558 (adev->sdma.instance[i].fw->data +
559 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
560 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
561 for (j = 0; j < fw_size; j++)
562 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
563 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
570 * sdma_v2_4_start - setup and start the async dma engines
572 * @adev: amdgpu_device pointer
574 * Set up the DMA engines and enable them (VI).
575 * Returns 0 for success, error for failure.
577 static int sdma_v2_4_start(struct amdgpu_device *adev)
581 if (!adev->firmware.smu_load) {
582 r = sdma_v2_4_load_microcode(adev);
586 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
587 AMDGPU_UCODE_ID_SDMA0);
590 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
591 AMDGPU_UCODE_ID_SDMA1);
597 sdma_v2_4_enable(adev, true);
599 /* start the gfx rings and rlc compute queues */
600 r = sdma_v2_4_gfx_resume(adev);
603 r = sdma_v2_4_rlc_resume(adev);
611 * sdma_v2_4_ring_test_ring - simple async dma engine test
613 * @ring: amdgpu_ring structure holding ring information
615 * Test the DMA engine by writing using it to write an
616 * value to memory. (VI).
617 * Returns 0 for success, error for failure.
619 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
621 struct amdgpu_device *adev = ring->adev;
628 r = amdgpu_wb_get(adev, &index);
630 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
634 gpu_addr = adev->wb.gpu_addr + (index * 4);
636 adev->wb.wb[index] = cpu_to_le32(tmp);
638 r = amdgpu_ring_lock(ring, 5);
640 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
641 amdgpu_wb_free(adev, index);
645 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
646 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
647 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
648 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
649 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
650 amdgpu_ring_write(ring, 0xDEADBEEF);
651 amdgpu_ring_unlock_commit(ring);
653 for (i = 0; i < adev->usec_timeout; i++) {
654 tmp = le32_to_cpu(adev->wb.wb[index]);
655 if (tmp == 0xDEADBEEF)
660 if (i < adev->usec_timeout) {
661 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
663 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
667 amdgpu_wb_free(adev, index);
673 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
675 * @ring: amdgpu_ring structure holding ring information
677 * Test a simple IB in the DMA ring (VI).
678 * Returns 0 on success, error on failure.
680 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
682 struct amdgpu_device *adev = ring->adev;
684 struct fence *f = NULL;
691 r = amdgpu_wb_get(adev, &index);
693 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
697 gpu_addr = adev->wb.gpu_addr + (index * 4);
699 adev->wb.wb[index] = cpu_to_le32(tmp);
700 memset(&ib, 0, sizeof(ib));
701 r = amdgpu_ib_get(ring, NULL, 256, &ib);
703 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
707 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
708 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
709 ib.ptr[1] = lower_32_bits(gpu_addr);
710 ib.ptr[2] = upper_32_bits(gpu_addr);
711 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
712 ib.ptr[4] = 0xDEADBEEF;
713 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
714 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
715 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
718 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
719 AMDGPU_FENCE_OWNER_UNDEFINED,
724 r = fence_wait(f, false);
726 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
729 for (i = 0; i < adev->usec_timeout; i++) {
730 tmp = le32_to_cpu(adev->wb.wb[index]);
731 if (tmp == 0xDEADBEEF)
735 if (i < adev->usec_timeout) {
736 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
740 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
746 amdgpu_ib_free(adev, &ib);
748 amdgpu_wb_free(adev, index);
753 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
755 * @ib: indirect buffer to fill with commands
756 * @pe: addr of the page entry
757 * @src: src addr to copy from
758 * @count: number of page entries to update
760 * Update PTEs by copying them from the GART using sDMA (CIK).
762 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
763 uint64_t pe, uint64_t src,
767 unsigned bytes = count * 8;
768 if (bytes > 0x1FFFF8)
771 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
772 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
773 ib->ptr[ib->length_dw++] = bytes;
774 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
775 ib->ptr[ib->length_dw++] = lower_32_bits(src);
776 ib->ptr[ib->length_dw++] = upper_32_bits(src);
777 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
778 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
787 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
789 * @ib: indirect buffer to fill with commands
790 * @pe: addr of the page entry
791 * @addr: dst addr to write into pe
792 * @count: number of page entries to update
793 * @incr: increase next addr by incr bytes
794 * @flags: access flags
796 * Update PTEs by writing them manually using sDMA (CIK).
798 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
800 uint64_t addr, unsigned count,
801 uint32_t incr, uint32_t flags)
811 /* for non-physically contiguous pages (system) */
812 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
813 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
814 ib->ptr[ib->length_dw++] = pe;
815 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
816 ib->ptr[ib->length_dw++] = ndw;
817 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
818 if (flags & AMDGPU_PTE_SYSTEM) {
819 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
820 value &= 0xFFFFFFFFFFFFF000ULL;
821 } else if (flags & AMDGPU_PTE_VALID) {
828 ib->ptr[ib->length_dw++] = value;
829 ib->ptr[ib->length_dw++] = upper_32_bits(value);
835 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
837 * @ib: indirect buffer to fill with commands
838 * @pe: addr of the page entry
839 * @addr: dst addr to write into pe
840 * @count: number of page entries to update
841 * @incr: increase next addr by incr bytes
842 * @flags: access flags
844 * Update the page tables using sDMA (CIK).
846 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
848 uint64_t addr, unsigned count,
849 uint32_t incr, uint32_t flags)
859 if (flags & AMDGPU_PTE_VALID)
864 /* for physically contiguous pages (vram) */
865 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
866 ib->ptr[ib->length_dw++] = pe; /* dst addr */
867 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
868 ib->ptr[ib->length_dw++] = flags; /* mask */
869 ib->ptr[ib->length_dw++] = 0;
870 ib->ptr[ib->length_dw++] = value; /* value */
871 ib->ptr[ib->length_dw++] = upper_32_bits(value);
872 ib->ptr[ib->length_dw++] = incr; /* increment size */
873 ib->ptr[ib->length_dw++] = 0;
874 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
883 * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
885 * @ib: indirect buffer to fill with padding
888 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
890 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
894 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
895 for (i = 0; i < pad_count; i++)
896 if (sdma && sdma->burst_nop && (i == 0))
897 ib->ptr[ib->length_dw++] =
898 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
899 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
901 ib->ptr[ib->length_dw++] =
902 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
906 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
908 * @ring: amdgpu_ring pointer
909 * @vm: amdgpu_vm pointer
911 * Update the page table base and flush the VM TLB
914 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
915 unsigned vm_id, uint64_t pd_addr)
917 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
918 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
920 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
922 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
924 amdgpu_ring_write(ring, pd_addr >> 12);
927 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
928 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
929 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
930 amdgpu_ring_write(ring, 1 << vm_id);
933 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
934 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
935 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
936 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
937 amdgpu_ring_write(ring, 0);
938 amdgpu_ring_write(ring, 0); /* reference */
939 amdgpu_ring_write(ring, 0); /* mask */
940 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
941 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
944 static int sdma_v2_4_early_init(void *handle)
946 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
948 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
950 sdma_v2_4_set_ring_funcs(adev);
951 sdma_v2_4_set_buffer_funcs(adev);
952 sdma_v2_4_set_vm_pte_funcs(adev);
953 sdma_v2_4_set_irq_funcs(adev);
958 static int sdma_v2_4_sw_init(void *handle)
960 struct amdgpu_ring *ring;
962 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
964 /* SDMA trap event */
965 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
969 /* SDMA Privileged inst */
970 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
974 /* SDMA Privileged inst */
975 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
979 r = sdma_v2_4_init_microcode(adev);
981 DRM_ERROR("Failed to load sdma firmware!\n");
985 for (i = 0; i < adev->sdma.num_instances; i++) {
986 ring = &adev->sdma.instance[i].ring;
987 ring->ring_obj = NULL;
988 ring->use_doorbell = false;
989 sprintf(ring->name, "sdma%d", i);
990 r = amdgpu_ring_init(adev, ring, 256 * 1024,
991 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
992 &adev->sdma.trap_irq,
994 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
995 AMDGPU_RING_TYPE_SDMA);
1003 static int sdma_v2_4_sw_fini(void *handle)
1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008 for (i = 0; i < adev->sdma.num_instances; i++)
1009 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1014 static int sdma_v2_4_hw_init(void *handle)
1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019 sdma_v2_4_init_golden_registers(adev);
1021 r = sdma_v2_4_start(adev);
1028 static int sdma_v2_4_hw_fini(void *handle)
1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032 sdma_v2_4_enable(adev, false);
1037 static int sdma_v2_4_suspend(void *handle)
1039 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041 return sdma_v2_4_hw_fini(adev);
1044 static int sdma_v2_4_resume(void *handle)
1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1048 return sdma_v2_4_hw_init(adev);
1051 static bool sdma_v2_4_is_idle(void *handle)
1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054 u32 tmp = RREG32(mmSRBM_STATUS2);
1056 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1057 SRBM_STATUS2__SDMA1_BUSY_MASK))
1063 static int sdma_v2_4_wait_for_idle(void *handle)
1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069 for (i = 0; i < adev->usec_timeout; i++) {
1070 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1071 SRBM_STATUS2__SDMA1_BUSY_MASK);
1080 static void sdma_v2_4_print_status(void *handle)
1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085 dev_info(adev->dev, "VI SDMA registers\n");
1086 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1087 RREG32(mmSRBM_STATUS2));
1088 for (i = 0; i < adev->sdma.num_instances; i++) {
1089 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1090 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1091 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1092 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1093 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1094 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1095 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1096 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1097 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1098 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1099 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1100 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1101 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1102 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1103 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1104 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1105 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1106 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1107 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1108 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1109 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1110 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1111 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1112 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1113 mutex_lock(&adev->srbm_mutex);
1114 for (j = 0; j < 16; j++) {
1115 vi_srbm_select(adev, 0, 0, 0, j);
1116 dev_info(adev->dev, " VM %d:\n", j);
1117 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1118 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1119 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1120 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1122 vi_srbm_select(adev, 0, 0, 0, 0);
1123 mutex_unlock(&adev->srbm_mutex);
1127 static int sdma_v2_4_soft_reset(void *handle)
1129 u32 srbm_soft_reset = 0;
1130 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1131 u32 tmp = RREG32(mmSRBM_STATUS2);
1133 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1135 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1136 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1137 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1138 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1140 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1142 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1143 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1144 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1145 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1148 if (srbm_soft_reset) {
1149 sdma_v2_4_print_status((void *)adev);
1151 tmp = RREG32(mmSRBM_SOFT_RESET);
1152 tmp |= srbm_soft_reset;
1153 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1154 WREG32(mmSRBM_SOFT_RESET, tmp);
1155 tmp = RREG32(mmSRBM_SOFT_RESET);
1159 tmp &= ~srbm_soft_reset;
1160 WREG32(mmSRBM_SOFT_RESET, tmp);
1161 tmp = RREG32(mmSRBM_SOFT_RESET);
1163 /* Wait a little for things to settle down */
1166 sdma_v2_4_print_status((void *)adev);
1172 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1173 struct amdgpu_irq_src *src,
1175 enum amdgpu_interrupt_state state)
1180 case AMDGPU_SDMA_IRQ_TRAP0:
1182 case AMDGPU_IRQ_STATE_DISABLE:
1183 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1184 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1185 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1187 case AMDGPU_IRQ_STATE_ENABLE:
1188 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1189 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1190 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1196 case AMDGPU_SDMA_IRQ_TRAP1:
1198 case AMDGPU_IRQ_STATE_DISABLE:
1199 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1200 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1201 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1203 case AMDGPU_IRQ_STATE_ENABLE:
1204 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1205 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1206 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1218 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1219 struct amdgpu_irq_src *source,
1220 struct amdgpu_iv_entry *entry)
1222 u8 instance_id, queue_id;
1224 instance_id = (entry->ring_id & 0x3) >> 0;
1225 queue_id = (entry->ring_id & 0xc) >> 2;
1226 DRM_DEBUG("IH: SDMA trap\n");
1227 switch (instance_id) {
1231 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1244 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1258 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1259 struct amdgpu_irq_src *source,
1260 struct amdgpu_iv_entry *entry)
1262 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1263 schedule_work(&adev->reset_work);
1267 static int sdma_v2_4_set_clockgating_state(void *handle,
1268 enum amd_clockgating_state state)
1270 /* XXX handled via the smc on VI */
1274 static int sdma_v2_4_set_powergating_state(void *handle,
1275 enum amd_powergating_state state)
1280 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1281 .early_init = sdma_v2_4_early_init,
1283 .sw_init = sdma_v2_4_sw_init,
1284 .sw_fini = sdma_v2_4_sw_fini,
1285 .hw_init = sdma_v2_4_hw_init,
1286 .hw_fini = sdma_v2_4_hw_fini,
1287 .suspend = sdma_v2_4_suspend,
1288 .resume = sdma_v2_4_resume,
1289 .is_idle = sdma_v2_4_is_idle,
1290 .wait_for_idle = sdma_v2_4_wait_for_idle,
1291 .soft_reset = sdma_v2_4_soft_reset,
1292 .print_status = sdma_v2_4_print_status,
1293 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1294 .set_powergating_state = sdma_v2_4_set_powergating_state,
1297 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1298 .get_rptr = sdma_v2_4_ring_get_rptr,
1299 .get_wptr = sdma_v2_4_ring_get_wptr,
1300 .set_wptr = sdma_v2_4_ring_set_wptr,
1302 .emit_ib = sdma_v2_4_ring_emit_ib,
1303 .emit_fence = sdma_v2_4_ring_emit_fence,
1304 .emit_semaphore = sdma_v2_4_ring_emit_semaphore,
1305 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1306 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1307 .test_ring = sdma_v2_4_ring_test_ring,
1308 .test_ib = sdma_v2_4_ring_test_ib,
1309 .insert_nop = sdma_v2_4_ring_insert_nop,
1312 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1316 for (i = 0; i < adev->sdma.num_instances; i++)
1317 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1320 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1321 .set = sdma_v2_4_set_trap_irq_state,
1322 .process = sdma_v2_4_process_trap_irq,
1325 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1326 .process = sdma_v2_4_process_illegal_inst_irq,
1329 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1331 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1332 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1333 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1337 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1339 * @ring: amdgpu_ring structure holding ring information
1340 * @src_offset: src GPU address
1341 * @dst_offset: dst GPU address
1342 * @byte_count: number of bytes to xfer
1344 * Copy GPU buffers using the DMA engine (VI).
1345 * Used by the amdgpu ttm implementation to move pages if
1346 * registered as the asic copy callback.
1348 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1349 uint64_t src_offset,
1350 uint64_t dst_offset,
1351 uint32_t byte_count)
1353 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1354 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1355 ib->ptr[ib->length_dw++] = byte_count;
1356 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1357 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1358 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1359 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1360 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1364 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1366 * @ring: amdgpu_ring structure holding ring information
1367 * @src_data: value to write to buffer
1368 * @dst_offset: dst GPU address
1369 * @byte_count: number of bytes to xfer
1371 * Fill GPU buffers using the DMA engine (VI).
1373 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1375 uint64_t dst_offset,
1376 uint32_t byte_count)
1378 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1379 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1380 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1381 ib->ptr[ib->length_dw++] = src_data;
1382 ib->ptr[ib->length_dw++] = byte_count;
1385 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1386 .copy_max_bytes = 0x1fffff,
1388 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1390 .fill_max_bytes = 0x1fffff,
1392 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1395 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1397 if (adev->mman.buffer_funcs == NULL) {
1398 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1399 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1403 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1404 .copy_pte = sdma_v2_4_vm_copy_pte,
1405 .write_pte = sdma_v2_4_vm_write_pte,
1406 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1407 .pad_ib = sdma_v2_4_vm_pad_ib,
1410 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1412 if (adev->vm_manager.vm_pte_funcs == NULL) {
1413 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1414 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1415 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;