drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 /*(DEBLOBBED)*/
  53
  54 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  55 {
  56         SDMA0_REGISTER_OFFSET,
  57         SDMA1_REGISTER_OFFSET
  58 };
  59
  60 static const u32 golden_settings_iceland_a11[] =
  61 {
  62         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  63         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  64         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  65         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  66 };
  67
  68 static const u32 iceland_mgcg_cgcg_init[] =
  69 {
  70         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  71         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  72 };
  73
  74 /*
  75  * sDMA - System DMA
  76  * Starting with CIK, the GPU has new asynchronous
  77  * DMA engines.  These engines are used for compute
  78  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  79  * and each one supports 1 ring buffer used for gfx
  80  * and 2 queues used for compute.
  81  *
  82  * The programming model is very similar to the CP
  83  * (ring buffer, IBs, etc.), but sDMA has it's own
  84  * packet format that is different from the PM4 format
  85  * used by the CP. sDMA supports copying data, writing
  86  * embedded data, solid fills, and a number of other
  87  * things.  It also has support for tiling/detiling of
  88  * buffers.
  89  */
  90
  91 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  92 {
  93         switch (adev->asic_type) {
  94         case CHIP_TOPAZ:
  95                 amdgpu_program_register_sequence(adev,
  96                                                  iceland_mgcg_cgcg_init,
  97                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  98                 amdgpu_program_register_sequence(adev,
  99                                                  golden_settings_iceland_a11,
 100                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 101                 break;
 102         default:
 103                 break;
 104         }
 105 }
 106
 107 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 108 {
 109         int i;
 110         for (i = 0; i < adev->sdma.num_instances; i++) {
 111                 release_firmware(adev->sdma.instance[i].fw);
 112                 adev->sdma.instance[i].fw = NULL;
 113         }
 114 }
 115
 116 /**
 117  * sdma_v2_4_init_microcode - load ucode images from disk
 118  *
 119  * @adev: amdgpu_device pointer
 120  *
 121  * Use the firmware interface to load the ucode images into
 122  * the driver (not loaded into hw).
 123  * Returns 0 on success, error on failure.
 124  */
 125 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 126 {
 127         const char *chip_name;
 128         char fw_name[30];
 129         int err = 0, i;
 130         struct amdgpu_firmware_info *info = NULL;
 131         const struct common_firmware_header *header = NULL;
 132         const struct sdma_firmware_header_v1_0 *hdr;
 133
 134         DRM_DEBUG("\n");
 135
 136         switch (adev->asic_type) {
 137         case CHIP_TOPAZ:
 138                 chip_name = "topaz";
 139                 break;
 140         default: BUG();
 141         }
 142
 143         for (i = 0; i < adev->sdma.num_instances; i++) {
 144                 if (i == 0)
 145                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 146                 else
 147                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 148                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 149                 if (err)
 150                         goto out;
 151                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 152                 if (err)
 153                         goto out;
 154                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 155                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 156                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 157                 if (adev->sdma.instance[i].feature_version >= 20)
 158                         adev->sdma.instance[i].burst_nop = true;
 159
 160                 if (adev->firmware.smu_load) {
 161                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 162                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 163                         info->fw = adev->sdma.instance[i].fw;
 164                         header = (const struct common_firmware_header *)info->fw->data;
 165                         adev->firmware.fw_size +=
 166                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 167                 }
 168         }
 169
 170 out:
 171         if (err) {
 172                 printk(KERN_ERR
 173                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 174                        fw_name);
 175                 for (i = 0; i < adev->sdma.num_instances; i++) {
 176                         release_firmware(adev->sdma.instance[i].fw);
 177                         adev->sdma.instance[i].fw = NULL;
 178                 }
 179         }
 180         return err;
 181 }
 182
 183 /**
 184  * sdma_v2_4_ring_get_rptr - get the current read pointer
 185  *
 186  * @ring: amdgpu ring pointer
 187  *
 188  * Get the current rptr from the hardware (VI+).
 189  */
 190 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 191 {
 192         /* XXX check if swapping is necessary on BE */
 193         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 194 }
 195
 196 /**
 197  * sdma_v2_4_ring_get_wptr - get the current write pointer
 198  *
 199  * @ring: amdgpu ring pointer
 200  *
 201  * Get the current wptr from the hardware (VI+).
 202  */
 203 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 204 {
 205         struct amdgpu_device *adev = ring->adev;
 206         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 207         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 208
 209         return wptr;
 210 }
 211
 212 /**
 213  * sdma_v2_4_ring_set_wptr - commit the write pointer
 214  *
 215  * @ring: amdgpu ring pointer
 216  *
 217  * Write the wptr back to the hardware (VI+).
 218  */
 219 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 220 {
 221         struct amdgpu_device *adev = ring->adev;
 222         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 223
 224         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 225 }
 226
 227 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 228 {
 229         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 230         int i;
 231
 232         for (i = 0; i < count; i++)
 233                 if (sdma && sdma->burst_nop && (i == 0))
 234                         amdgpu_ring_write(ring, ring->nop |
 235                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 236                 else
 237                         amdgpu_ring_write(ring, ring->nop);
 238 }
 239
 240 /**
 241  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 242  *
 243  * @ring: amdgpu ring pointer
 244  * @ib: IB object to schedule
 245  *
 246  * Schedule an IB in the DMA ring (VI).
 247  */
 248 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 249                                    struct amdgpu_ib *ib,
 250                                    unsigned vm_id, bool ctx_switch)
 251 {
 252         u32 vmid = vm_id & 0xf;
 253
 254         /* IB packet must end on a 8 DW boundary */
 255         sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 256
 257         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 258                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 259         /* base must be 32 byte aligned */
 260         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 261         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 262         amdgpu_ring_write(ring, ib->length_dw);
 263         amdgpu_ring_write(ring, 0);
 264         amdgpu_ring_write(ring, 0);
 265
 266 }
 267
 268 /**
 269  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 270  *
 271  * @ring: amdgpu ring pointer
 272  *
 273  * Emit an hdp flush packet on the requested DMA ring.
 274  */
 275 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 276 {
 277         u32 ref_and_mask = 0;
 278
 279         if (ring == &ring->adev->sdma.instance[0].ring)
 280                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 281         else
 282                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 283
 284         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 285                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 286                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 287         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 288         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 289         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 290         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 291         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 292                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 293 }
 294
 295 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 296 {
 297         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 298                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 299         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 300         amdgpu_ring_write(ring, 1);
 301 }
 302 /**
 303  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 304  *
 305  * @ring: amdgpu ring pointer
 306  * @fence: amdgpu fence object
 307  *
 308  * Add a DMA fence packet to the ring to write
 309  * the fence seq number and DMA trap packet to generate
 310  * an interrupt if needed (VI).
 311  */
 312 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 313                                       unsigned flags)
 314 {
 315         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 316         /* write the fence */
 317         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 318         amdgpu_ring_write(ring, lower_32_bits(addr));
 319         amdgpu_ring_write(ring, upper_32_bits(addr));
 320         amdgpu_ring_write(ring, lower_32_bits(seq));
 321
 322         /* optionally write high bits as well */
 323         if (write64bit) {
 324                 addr += 4;
 325                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 326                 amdgpu_ring_write(ring, lower_32_bits(addr));
 327                 amdgpu_ring_write(ring, upper_32_bits(addr));
 328                 amdgpu_ring_write(ring, upper_32_bits(seq));
 329         }
 330
 331         /* generate an interrupt */
 332         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 333         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 334 }
 335
 336 /**
 337  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 338  *
 339  * @adev: amdgpu_device pointer
 340  *
 341  * Stop the gfx async dma ring buffers (VI).
 342  */
 343 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 344 {
 345         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 346         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 347         u32 rb_cntl, ib_cntl;
 348         int i;
 349
 350         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 351             (adev->mman.buffer_funcs_ring == sdma1))
 352                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 353
 354         for (i = 0; i < adev->sdma.num_instances; i++) {
 355                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 356                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 357                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 358                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 359                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 360                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 361         }
 362         sdma0->ready = false;
 363         sdma1->ready = false;
 364 }
 365
 366 /**
 367  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 368  *
 369  * @adev: amdgpu_device pointer
 370  *
 371  * Stop the compute async dma queues (VI).
 372  */
 373 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 374 {
 375         /* XXX todo */
 376 }
 377
 378 /**
 379  * sdma_v2_4_enable - stop the async dma engines
 380  *
 381  * @adev: amdgpu_device pointer
 382  * @enable: enable/disable the DMA MEs.
 383  *
 384  * Halt or unhalt the async dma engines (VI).
 385  */
 386 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 387 {
 388         u32 f32_cntl;
 389         int i;
 390
 391         if (!enable) {
 392                 sdma_v2_4_gfx_stop(adev);
 393                 sdma_v2_4_rlc_stop(adev);
 394         }
 395
 396         for (i = 0; i < adev->sdma.num_instances; i++) {
 397                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 398                 if (enable)
 399                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 400                 else
 401                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 402                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 403         }
 404 }
 405
 406 /**
 407  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 408  *
 409  * @adev: amdgpu_device pointer
 410  *
 411  * Set up the gfx DMA ring buffers and enable them (VI).
 412  * Returns 0 for success, error for failure.
 413  */
 414 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 415 {
 416         struct amdgpu_ring *ring;
 417         u32 rb_cntl, ib_cntl;
 418         u32 rb_bufsz;
 419         u32 wb_offset;
 420         int i, j, r;
 421
 422         for (i = 0; i < adev->sdma.num_instances; i++) {
 423                 ring = &adev->sdma.instance[i].ring;
 424                 wb_offset = (ring->rptr_offs * 4);
 425
 426                 mutex_lock(&adev->srbm_mutex);
 427                 for (j = 0; j < 16; j++) {
 428                         vi_srbm_select(adev, 0, 0, 0, j);
 429                         /* SDMA GFX */
 430                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 431                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 432                 }
 433                 vi_srbm_select(adev, 0, 0, 0, 0);
 434                 mutex_unlock(&adev->srbm_mutex);
 435
 436                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 437                        adev->gfx.config.gb_addr_config & 0x70);
 438
 439                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 440
 441                 /* Set ring buffer size in dwords */
 442                 rb_bufsz = order_base_2(ring->ring_size / 4);
 443                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 444                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 445 #ifdef __BIG_ENDIAN
 446                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 447                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 448                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 449 #endif
 450                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 451
 452                 /* Initialize the ring buffer's read and write pointers */
 453                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 454                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 455                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 456                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 457
 458                 /* set the wb address whether it's enabled or not */
 459                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 460                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 461                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 462                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 463
 464                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 465
 466                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 467                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 468
 469                 ring->wptr = 0;
 470                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 471
 472                 /* enable DMA RB */
 473                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 474                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 475
 476                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 477                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 478 #ifdef __BIG_ENDIAN
 479                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 480 #endif
 481                 /* enable DMA IBs */
 482                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 483
 484                 ring->ready = true;
 485         }
 486
 487         sdma_v2_4_enable(adev, true);
 488         for (i = 0; i < adev->sdma.num_instances; i++) {
 489                 ring = &adev->sdma.instance[i].ring;
 490                 r = amdgpu_ring_test_ring(ring);
 491                 if (r) {
 492                         ring->ready = false;
 493                         return r;
 494                 }
 495
 496                 if (adev->mman.buffer_funcs_ring == ring)
 497                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 498         }
 499
 500         return 0;
 501 }
 502
 503 /**
 504  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 505  *
 506  * @adev: amdgpu_device pointer
 507  *
 508  * Set up the compute DMA queues and enable them (VI).
 509  * Returns 0 for success, error for failure.
 510  */
 511 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 512 {
 513         /* XXX todo */
 514         return 0;
 515 }
 516
 517 /**
 518  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 519  *
 520  * @adev: amdgpu_device pointer
 521  *
 522  * Loads the sDMA0/1 ucode.
 523  * Returns 0 for success, -EINVAL if the ucode is not available.
 524  */
 525 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 526 {
 527         const struct sdma_firmware_header_v1_0 *hdr;
 528         const __le32 *fw_data;
 529         u32 fw_size;
 530         int i, j;
 531
 532         /* halt the MEs */
 533         sdma_v2_4_enable(adev, false);
 534
 535         for (i = 0; i < adev->sdma.num_instances; i++) {
 536                 if (!adev->sdma.instance[i].fw)
 537                         return -EINVAL;
 538                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 539                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 540                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 541                 fw_data = (const __le32 *)
 542                         (adev->sdma.instance[i].fw->data +
 543                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 544                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 545                 for (j = 0; j < fw_size; j++)
 546                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 547                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 548         }
 549
 550         return 0;
 551 }
 552
 553 /**
 554  * sdma_v2_4_start - setup and start the async dma engines
 555  *
 556  * @adev: amdgpu_device pointer
 557  *
 558  * Set up the DMA engines and enable them (VI).
 559  * Returns 0 for success, error for failure.
 560  */
 561 static int sdma_v2_4_start(struct amdgpu_device *adev)
 562 {
 563         int r;
 564
 565         if (!adev->pp_enabled) {
 566                 if (!adev->firmware.smu_load) {
 567                         r = sdma_v2_4_load_microcode(adev);
 568                         if (r)
 569                                 return r;
 570                 } else {
 571                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 572                                                         AMDGPU_UCODE_ID_SDMA0);
 573                         if (r)
 574                                 return -EINVAL;
 575                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 576                                                         AMDGPU_UCODE_ID_SDMA1);
 577                         if (r)
 578                                 return -EINVAL;
 579                 }
 580         }
 581
 582         /* halt the engine before programing */
 583         sdma_v2_4_enable(adev, false);
 584
 585         /* start the gfx rings and rlc compute queues */
 586         r = sdma_v2_4_gfx_resume(adev);
 587         if (r)
 588                 return r;
 589         r = sdma_v2_4_rlc_resume(adev);
 590         if (r)
 591                 return r;
 592
 593         return 0;
 594 }
 595
 596 /**
 597  * sdma_v2_4_ring_test_ring - simple async dma engine test
 598  *
 599  * @ring: amdgpu_ring structure holding ring information
 600  *
 601  * Test the DMA engine by writing using it to write an
 602  * value to memory. (VI).
 603  * Returns 0 for success, error for failure.
 604  */
 605 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 606 {
 607         struct amdgpu_device *adev = ring->adev;
 608         unsigned i;
 609         unsigned index;
 610         int r;
 611         u32 tmp;
 612         u64 gpu_addr;
 613
 614         r = amdgpu_wb_get(adev, &index);
 615         if (r) {
 616                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 617                 return r;
 618         }
 619
 620         gpu_addr = adev->wb.gpu_addr + (index * 4);
 621         tmp = 0xCAFEDEAD;
 622         adev->wb.wb[index] = cpu_to_le32(tmp);
 623
 624         r = amdgpu_ring_alloc(ring, 5);
 625         if (r) {
 626                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 627                 amdgpu_wb_free(adev, index);
 628                 return r;
 629         }
 630
 631         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 632                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 633         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 634         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 635         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 636         amdgpu_ring_write(ring, 0xDEADBEEF);
 637         amdgpu_ring_commit(ring);
 638
 639         for (i = 0; i < adev->usec_timeout; i++) {
 640                 tmp = le32_to_cpu(adev->wb.wb[index]);
 641                 if (tmp == 0xDEADBEEF)
 642                         break;
 643                 DRM_UDELAY(1);
 644         }
 645
 646         if (i < adev->usec_timeout) {
 647                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 648         } else {
 649                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 650                           ring->idx, tmp);
 651                 r = -EINVAL;
 652         }
 653         amdgpu_wb_free(adev, index);
 654
 655         return r;
 656 }
 657
 658 /**
 659  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 660  *
 661  * @ring: amdgpu_ring structure holding ring information
 662  *
 663  * Test a simple IB in the DMA ring (VI).
 664  * Returns 0 on success, error on failure.
 665  */
 666 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 667 {
 668         struct amdgpu_device *adev = ring->adev;
 669         struct amdgpu_ib ib;
 670         struct fence *f = NULL;
 671         unsigned index;
 672         u32 tmp = 0;
 673         u64 gpu_addr;
 674         long r;
 675
 676         r = amdgpu_wb_get(adev, &index);
 677         if (r) {
 678                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 679                 return r;
 680         }
 681
 682         gpu_addr = adev->wb.gpu_addr + (index * 4);
 683         tmp = 0xCAFEDEAD;
 684         adev->wb.wb[index] = cpu_to_le32(tmp);
 685         memset(&ib, 0, sizeof(ib));
 686         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 687         if (r) {
 688                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 689                 goto err0;
 690         }
 691
 692         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 693                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 694         ib.ptr[1] = lower_32_bits(gpu_addr);
 695         ib.ptr[2] = upper_32_bits(gpu_addr);
 696         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 697         ib.ptr[4] = 0xDEADBEEF;
 698         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 699         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 700         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 701         ib.length_dw = 8;
 702
 703         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 704         if (r)
 705                 goto err1;
 706
 707         r = fence_wait_timeout(f, false, timeout);
 708         if (r == 0) {
 709                 DRM_ERROR("amdgpu: IB test timed out\n");
 710                 r = -ETIMEDOUT;
 711                 goto err1;
 712         } else if (r < 0) {
 713                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 714                 goto err1;
 715         }
 716         tmp = le32_to_cpu(adev->wb.wb[index]);
 717         if (tmp == 0xDEADBEEF) {
 718                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 719                 r = 0;
 720         } else {
 721                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 722                 r = -EINVAL;
 723         }
 724
 725 err1:
 726         amdgpu_ib_free(adev, &ib, NULL);
 727         fence_put(f);
 728 err0:
 729         amdgpu_wb_free(adev, index);
 730         return r;
 731 }
 732
 733 /**
 734  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 735  *
 736  * @ib: indirect buffer to fill with commands
 737  * @pe: addr of the page entry
 738  * @src: src addr to copy from
 739  * @count: number of page entries to update
 740  *
 741  * Update PTEs by copying them from the GART using sDMA (CIK).
 742  */
 743 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 744                                   uint64_t pe, uint64_t src,
 745                                   unsigned count)
 746 {
 747         unsigned bytes = count * 8;
 748
 749         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 750                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 751         ib->ptr[ib->length_dw++] = bytes;
 752         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 753         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 754         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 755         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 756         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 757 }
 758
 759 /**
 760  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 761  *
 762  * @ib: indirect buffer to fill with commands
 763  * @pe: addr of the page entry
 764  * @value: dst addr to write into pe
 765  * @count: number of page entries to update
 766  * @incr: increase next addr by incr bytes
 767  *
 768  * Update PTEs by writing them manually using sDMA (CIK).
 769  */
 770 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 771                                    uint64_t value, unsigned count,
 772                                    uint32_t incr)
 773 {
 774         unsigned ndw = count * 2;
 775
 776         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 777                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 778         ib->ptr[ib->length_dw++] = pe;
 779         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 780         ib->ptr[ib->length_dw++] = ndw;
 781         for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 782                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 783                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 784                 value += incr;
 785         }
 786 }
 787
 788 /**
 789  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 790  *
 791  * @ib: indirect buffer to fill with commands
 792  * @pe: addr of the page entry
 793  * @addr: dst addr to write into pe
 794  * @count: number of page entries to update
 795  * @incr: increase next addr by incr bytes
 796  * @flags: access flags
 797  *
 798  * Update the page tables using sDMA (CIK).
 799  */
 800 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 801                                      uint64_t addr, unsigned count,
 802                                      uint32_t incr, uint32_t flags)
 803 {
 804         /* for physically contiguous pages (vram) */
 805         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 806         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 807         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 808         ib->ptr[ib->length_dw++] = flags; /* mask */
 809         ib->ptr[ib->length_dw++] = 0;
 810         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 811         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 812         ib->ptr[ib->length_dw++] = incr; /* increment size */
 813         ib->ptr[ib->length_dw++] = 0;
 814         ib->ptr[ib->length_dw++] = count; /* number of entries */
 815 }
 816
 817 /**
 818  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 819  *
 820  * @ib: indirect buffer to fill with padding
 821  *
 822  */
 823 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 824 {
 825         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 826         u32 pad_count;
 827         int i;
 828
 829         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 830         for (i = 0; i < pad_count; i++)
 831                 if (sdma && sdma->burst_nop && (i == 0))
 832                         ib->ptr[ib->length_dw++] =
 833                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 834                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 835                 else
 836                         ib->ptr[ib->length_dw++] =
 837                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 838 }
 839
 840 /**
 841  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 842  *
 843  * @ring: amdgpu_ring pointer
 844  *
 845  * Make sure all previous operations are completed (CIK).
 846  */
 847 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 848 {
 849         uint32_t seq = ring->fence_drv.sync_seq;
 850         uint64_t addr = ring->fence_drv.gpu_addr;
 851
 852         /* wait for idle */
 853         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 854                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 855                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 856                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 857         amdgpu_ring_write(ring, addr & 0xfffffffc);
 858         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 859         amdgpu_ring_write(ring, seq); /* reference */
 860         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 861         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 862                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 863 }
 864
 865 /**
 866  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 867  *
 868  * @ring: amdgpu_ring pointer
 869  * @vm: amdgpu_vm pointer
 870  *
 871  * Update the page table base and flush the VM TLB
 872  * using sDMA (VI).
 873  */
 874 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 875                                          unsigned vm_id, uint64_t pd_addr)
 876 {
 877         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 878                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 879         if (vm_id < 8) {
 880                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 881         } else {
 882                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 883         }
 884         amdgpu_ring_write(ring, pd_addr >> 12);
 885
 886         /* flush TLB */
 887         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 888                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 889         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 890         amdgpu_ring_write(ring, 1 << vm_id);
 891
 892         /* wait for flush */
 893         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 894                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 895                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 896         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 897         amdgpu_ring_write(ring, 0);
 898         amdgpu_ring_write(ring, 0); /* reference */
 899         amdgpu_ring_write(ring, 0); /* mask */
 900         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 901                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 902 }
 903
 904 static unsigned sdma_v2_4_ring_get_emit_ib_size(struct amdgpu_ring *ring)
 905 {
 906         return
 907                 7 + 6; /* sdma_v2_4_ring_emit_ib */
 908 }
 909
 910 static unsigned sdma_v2_4_ring_get_dma_frame_size(struct amdgpu_ring *ring)
 911 {
 912         return
 913                 6 + /* sdma_v2_4_ring_emit_hdp_flush */
 914                 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
 915                 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
 916                 12 + /* sdma_v2_4_ring_emit_vm_flush */
 917                 10 + 10 + 10; /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
 918 }
 919
 920 static int sdma_v2_4_early_init(void *handle)
 921 {
 922         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 923
 924         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 925
 926         sdma_v2_4_set_ring_funcs(adev);
 927         sdma_v2_4_set_buffer_funcs(adev);
 928         sdma_v2_4_set_vm_pte_funcs(adev);
 929         sdma_v2_4_set_irq_funcs(adev);
 930
 931         return 0;
 932 }
 933
 934 static int sdma_v2_4_sw_init(void *handle)
 935 {
 936         struct amdgpu_ring *ring;
 937         int r, i;
 938         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 939
 940         /* SDMA trap event */
 941         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 942         if (r)
 943                 return r;
 944
 945         /* SDMA Privileged inst */
 946         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 947         if (r)
 948                 return r;
 949
 950         /* SDMA Privileged inst */
 951         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 952         if (r)
 953                 return r;
 954
 955         r = sdma_v2_4_init_microcode(adev);
 956         if (r) {
 957                 DRM_ERROR("Failed to load sdma firmware!\n");
 958                 return r;
 959         }
 960
 961         for (i = 0; i < adev->sdma.num_instances; i++) {
 962                 ring = &adev->sdma.instance[i].ring;
 963                 ring->ring_obj = NULL;
 964                 ring->use_doorbell = false;
 965                 sprintf(ring->name, "sdma%d", i);
 966                 r = amdgpu_ring_init(adev, ring, 1024,
 967                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
 968                                      &adev->sdma.trap_irq,
 969                                      (i == 0) ?
 970                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 971                                      AMDGPU_RING_TYPE_SDMA);
 972                 if (r)
 973                         return r;
 974         }
 975
 976         return r;
 977 }
 978
 979 static int sdma_v2_4_sw_fini(void *handle)
 980 {
 981         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 982         int i;
 983
 984         for (i = 0; i < adev->sdma.num_instances; i++)
 985                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 986
 987         sdma_v2_4_free_microcode(adev);
 988         return 0;
 989 }
 990
 991 static int sdma_v2_4_hw_init(void *handle)
 992 {
 993         int r;
 994         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 995
 996         sdma_v2_4_init_golden_registers(adev);
 997
 998         r = sdma_v2_4_start(adev);
 999         if (r)
1000                 return r;
1001
1002         return r;
1003 }
1004
1005 static int sdma_v2_4_hw_fini(void *handle)
1006 {
1007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008
1009         sdma_v2_4_enable(adev, false);
1010
1011         return 0;
1012 }
1013
1014 static int sdma_v2_4_suspend(void *handle)
1015 {
1016         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
1018         return sdma_v2_4_hw_fini(adev);
1019 }
1020
1021 static int sdma_v2_4_resume(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         return sdma_v2_4_hw_init(adev);
1026 }
1027
1028 static bool sdma_v2_4_is_idle(void *handle)
1029 {
1030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031         u32 tmp = RREG32(mmSRBM_STATUS2);
1032
1033         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1034                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1035             return false;
1036
1037         return true;
1038 }
1039
1040 static int sdma_v2_4_wait_for_idle(void *handle)
1041 {
1042         unsigned i;
1043         u32 tmp;
1044         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045
1046         for (i = 0; i < adev->usec_timeout; i++) {
1047                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1048                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1049
1050                 if (!tmp)
1051                         return 0;
1052                 udelay(1);
1053         }
1054         return -ETIMEDOUT;
1055 }
1056
1057 static int sdma_v2_4_soft_reset(void *handle)
1058 {
1059         u32 srbm_soft_reset = 0;
1060         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1061         u32 tmp = RREG32(mmSRBM_STATUS2);
1062
1063         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1064                 /* sdma0 */
1065                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1066                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1067                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1068                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1069         }
1070         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1071                 /* sdma1 */
1072                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1073                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1074                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1075                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1076         }
1077
1078         if (srbm_soft_reset) {
1079                 tmp = RREG32(mmSRBM_SOFT_RESET);
1080                 tmp |= srbm_soft_reset;
1081                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1082                 WREG32(mmSRBM_SOFT_RESET, tmp);
1083                 tmp = RREG32(mmSRBM_SOFT_RESET);
1084
1085                 udelay(50);
1086
1087                 tmp &= ~srbm_soft_reset;
1088                 WREG32(mmSRBM_SOFT_RESET, tmp);
1089                 tmp = RREG32(mmSRBM_SOFT_RESET);
1090
1091                 /* Wait a little for things to settle down */
1092                 udelay(50);
1093         }
1094
1095         return 0;
1096 }
1097
1098 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1099                                         struct amdgpu_irq_src *src,
1100                                         unsigned type,
1101                                         enum amdgpu_interrupt_state state)
1102 {
1103         u32 sdma_cntl;
1104
1105         switch (type) {
1106         case AMDGPU_SDMA_IRQ_TRAP0:
1107                 switch (state) {
1108                 case AMDGPU_IRQ_STATE_DISABLE:
1109                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1110                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1111                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1112                         break;
1113                 case AMDGPU_IRQ_STATE_ENABLE:
1114                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1115                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1116                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1117                         break;
1118                 default:
1119                         break;
1120                 }
1121                 break;
1122         case AMDGPU_SDMA_IRQ_TRAP1:
1123                 switch (state) {
1124                 case AMDGPU_IRQ_STATE_DISABLE:
1125                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1126                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1127                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1128                         break;
1129                 case AMDGPU_IRQ_STATE_ENABLE:
1130                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1131                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1132                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1133                         break;
1134                 default:
1135                         break;
1136                 }
1137                 break;
1138         default:
1139                 break;
1140         }
1141         return 0;
1142 }
1143
1144 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1145                                       struct amdgpu_irq_src *source,
1146                                       struct amdgpu_iv_entry *entry)
1147 {
1148         u8 instance_id, queue_id;
1149
1150         instance_id = (entry->ring_id & 0x3) >> 0;
1151         queue_id = (entry->ring_id & 0xc) >> 2;
1152         DRM_DEBUG("IH: SDMA trap\n");
1153         switch (instance_id) {
1154         case 0:
1155                 switch (queue_id) {
1156                 case 0:
1157                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1158                         break;
1159                 case 1:
1160                         /* XXX compute */
1161                         break;
1162                 case 2:
1163                         /* XXX compute */
1164                         break;
1165                 }
1166                 break;
1167         case 1:
1168                 switch (queue_id) {
1169                 case 0:
1170                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1171                         break;
1172                 case 1:
1173                         /* XXX compute */
1174                         break;
1175                 case 2:
1176                         /* XXX compute */
1177                         break;
1178                 }
1179                 break;
1180         }
1181         return 0;
1182 }
1183
1184 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1185                                               struct amdgpu_irq_src *source,
1186                                               struct amdgpu_iv_entry *entry)
1187 {
1188         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1189         schedule_work(&adev->reset_work);
1190         return 0;
1191 }
1192
1193 static int sdma_v2_4_set_clockgating_state(void *handle,
1194                                           enum amd_clockgating_state state)
1195 {
1196         /* XXX handled via the smc on VI */
1197         return 0;
1198 }
1199
1200 static int sdma_v2_4_set_powergating_state(void *handle,
1201                                           enum amd_powergating_state state)
1202 {
1203         return 0;
1204 }
1205
1206 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1207         .name = "sdma_v2_4",
1208         .early_init = sdma_v2_4_early_init,
1209         .late_init = NULL,
1210         .sw_init = sdma_v2_4_sw_init,
1211         .sw_fini = sdma_v2_4_sw_fini,
1212         .hw_init = sdma_v2_4_hw_init,
1213         .hw_fini = sdma_v2_4_hw_fini,
1214         .suspend = sdma_v2_4_suspend,
1215         .resume = sdma_v2_4_resume,
1216         .is_idle = sdma_v2_4_is_idle,
1217         .wait_for_idle = sdma_v2_4_wait_for_idle,
1218         .soft_reset = sdma_v2_4_soft_reset,
1219         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1220         .set_powergating_state = sdma_v2_4_set_powergating_state,
1221 };
1222
1223 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1224         .get_rptr = sdma_v2_4_ring_get_rptr,
1225         .get_wptr = sdma_v2_4_ring_get_wptr,
1226         .set_wptr = sdma_v2_4_ring_set_wptr,
1227         .parse_cs = NULL,
1228         .emit_ib = sdma_v2_4_ring_emit_ib,
1229         .emit_fence = sdma_v2_4_ring_emit_fence,
1230         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1231         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1232         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1233         .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1234         .test_ring = sdma_v2_4_ring_test_ring,
1235         .test_ib = sdma_v2_4_ring_test_ib,
1236         .insert_nop = sdma_v2_4_ring_insert_nop,
1237         .pad_ib = sdma_v2_4_ring_pad_ib,
1238         .get_emit_ib_size = sdma_v2_4_ring_get_emit_ib_size,
1239         .get_dma_frame_size = sdma_v2_4_ring_get_dma_frame_size,
1240 };
1241
1242 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1243 {
1244         int i;
1245
1246         for (i = 0; i < adev->sdma.num_instances; i++)
1247                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1248 }
1249
1250 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1251         .set = sdma_v2_4_set_trap_irq_state,
1252         .process = sdma_v2_4_process_trap_irq,
1253 };
1254
1255 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1256         .process = sdma_v2_4_process_illegal_inst_irq,
1257 };
1258
1259 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1260 {
1261         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1262         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1263         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1264 }
1265
1266 /**
1267  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1268  *
1269  * @ring: amdgpu_ring structure holding ring information
1270  * @src_offset: src GPU address
1271  * @dst_offset: dst GPU address
1272  * @byte_count: number of bytes to xfer
1273  *
1274  * Copy GPU buffers using the DMA engine (VI).
1275  * Used by the amdgpu ttm implementation to move pages if
1276  * registered as the asic copy callback.
1277  */
1278 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1279                                        uint64_t src_offset,
1280                                        uint64_t dst_offset,
1281                                        uint32_t byte_count)
1282 {
1283         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1284                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1285         ib->ptr[ib->length_dw++] = byte_count;
1286         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1287         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1288         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1289         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1290         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1291 }
1292
1293 /**
1294  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1295  *
1296  * @ring: amdgpu_ring structure holding ring information
1297  * @src_data: value to write to buffer
1298  * @dst_offset: dst GPU address
1299  * @byte_count: number of bytes to xfer
1300  *
1301  * Fill GPU buffers using the DMA engine (VI).
1302  */
1303 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1304                                        uint32_t src_data,
1305                                        uint64_t dst_offset,
1306                                        uint32_t byte_count)
1307 {
1308         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1309         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1310         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1311         ib->ptr[ib->length_dw++] = src_data;
1312         ib->ptr[ib->length_dw++] = byte_count;
1313 }
1314
1315 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1316         .copy_max_bytes = 0x1fffff,
1317         .copy_num_dw = 7,
1318         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1319
1320         .fill_max_bytes = 0x1fffff,
1321         .fill_num_dw = 7,
1322         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1323 };
1324
1325 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1326 {
1327         if (adev->mman.buffer_funcs == NULL) {
1328                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1329                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1330         }
1331 }
1332
1333 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1334         .copy_pte = sdma_v2_4_vm_copy_pte,
1335         .write_pte = sdma_v2_4_vm_write_pte,
1336         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1337 };
1338
1339 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1340 {
1341         unsigned i;
1342
1343         if (adev->vm_manager.vm_pte_funcs == NULL) {
1344                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1345                 for (i = 0; i < adev->sdma.num_instances; i++)
1346                         adev->vm_manager.vm_pte_rings[i] =
1347                                 &adev->sdma.instance[i].ring;
1348
1349                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1350         }
1351 }