drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_psp.h"
  29 #include "amdgpu_ucode.h"
  30 #include "soc15_common.h"
  31 #include "psp_v10_0.h"
  32
  33 #include "vega10/soc15ip.h"
  34 #include "raven1/MP/mp_10_0_offset.h"
  35 #include "raven1/GC/gc_9_1_offset.h"
  36 #include "raven1/SDMA0/sdma0_4_1_offset.h"
  37
  38 static int
  39 psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
  40 {
  41         switch(ucode->ucode_id) {
  42         case AMDGPU_UCODE_ID_SDMA0:
  43                 *type = GFX_FW_TYPE_SDMA0;
  44                 break;
  45         case AMDGPU_UCODE_ID_SDMA1:
  46                 *type = GFX_FW_TYPE_SDMA1;
  47                 break;
  48         case AMDGPU_UCODE_ID_CP_CE:
  49                 *type = GFX_FW_TYPE_CP_CE;
  50                 break;
  51         case AMDGPU_UCODE_ID_CP_PFP:
  52                 *type = GFX_FW_TYPE_CP_PFP;
  53                 break;
  54         case AMDGPU_UCODE_ID_CP_ME:
  55                 *type = GFX_FW_TYPE_CP_ME;
  56                 break;
  57         case AMDGPU_UCODE_ID_CP_MEC1:
  58                 *type = GFX_FW_TYPE_CP_MEC;
  59                 break;
  60         case AMDGPU_UCODE_ID_CP_MEC1_JT:
  61                 *type = GFX_FW_TYPE_CP_MEC_ME1;
  62                 break;
  63         case AMDGPU_UCODE_ID_CP_MEC2:
  64                 *type = GFX_FW_TYPE_CP_MEC;
  65                 break;
  66         case AMDGPU_UCODE_ID_CP_MEC2_JT:
  67                 *type = GFX_FW_TYPE_CP_MEC_ME2;
  68                 break;
  69         case AMDGPU_UCODE_ID_RLC_G:
  70                 *type = GFX_FW_TYPE_RLC_G;
  71                 break;
  72         case AMDGPU_UCODE_ID_SMC:
  73                 *type = GFX_FW_TYPE_SMU;
  74                 break;
  75         case AMDGPU_UCODE_ID_UVD:
  76                 *type = GFX_FW_TYPE_UVD;
  77                 break;
  78         case AMDGPU_UCODE_ID_VCE:
  79                 *type = GFX_FW_TYPE_VCE;
  80                 break;
  81         case AMDGPU_UCODE_ID_VCN:
  82                 *type = GFX_FW_TYPE_VCN;
  83                 break;
  84         case AMDGPU_UCODE_ID_MAXIMUM:
  85         default:
  86                 return -EINVAL;
  87         }
  88
  89         return 0;
  90 }
  91
  92 int psp_v10_0_init_microcode(struct psp_context *psp)
  93 {
  94         struct amdgpu_device *adev = psp->adev;
  95         const char *chip_name;
  96         char fw_name[30];
  97         int err = 0;
  98         const struct psp_firmware_header_v1_0 *hdr;
  99
 100         DRM_DEBUG("\n");
 101
 102         switch (adev->asic_type) {
 103         case CHIP_RAVEN:
 104                 chip_name = "raven";
 105                 break;
 106         default: BUG();
 107         }
 108
 109         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 110         err = reject_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 111         if (err)
 112                 goto out;
 113
 114         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 115         if (err)
 116                 goto out;
 117
 118         hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 119         adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
 120         adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
 121         adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 122         adev->psp.asd_start_addr = (uint8_t *)hdr +
 123                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
 124
 125         return 0;
 126 out:
 127         if (err) {
 128                 dev_err(adev->dev,
 129                         "psp v10.0: Failed to load firmware \"%s\"\n",
 130                         fw_name);
 131                 release_firmware(adev->psp.asd_fw);
 132                 adev->psp.asd_fw = NULL;
 133         }
 134
 135         return err;
 136 }
 137
 138 int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
 139 {
 140         int ret;
 141         uint64_t fw_mem_mc_addr = ucode->mc_addr;
 142         struct  common_firmware_header *header;
 143
 144         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 145         header = (struct common_firmware_header *)ucode->fw;
 146
 147         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 148         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 149         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 150         cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
 151
 152         ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 153         if (ret)
 154                 DRM_ERROR("Unknown firmware type\n");
 155
 156         return ret;
 157 }
 158
 159 int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
 160 {
 161         int ret = 0;
 162         struct psp_ring *ring;
 163         struct amdgpu_device *adev = psp->adev;
 164
 165         ring = &psp->km_ring;
 166
 167         ring->ring_type = ring_type;
 168
 169         /* allocate 4k Page of Local Frame Buffer memory for ring */
 170         ring->ring_size = 0x1000;
 171         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 172                                       AMDGPU_GEM_DOMAIN_VRAM,
 173                                       &adev->firmware.rbuf,
 174                                       &ring->ring_mem_mc_addr,
 175                                       (void **)&ring->ring_mem);
 176         if (ret) {
 177                 ring->ring_size = 0;
 178                 return ret;
 179         }
 180
 181         return 0;
 182 }
 183
 184 int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
 185 {
 186         int ret = 0;
 187         unsigned int psp_ring_reg = 0;
 188         struct psp_ring *ring = &psp->km_ring;
 189         struct amdgpu_device *adev = psp->adev;
 190
 191         /* Write low address of the ring to C2PMSG_69 */
 192         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 193         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 194         /* Write high address of the ring to C2PMSG_70 */
 195         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 196         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 197         /* Write size of ring to C2PMSG_71 */
 198         psp_ring_reg = ring->ring_size;
 199         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 200         /* Write the ring initialization command to C2PMSG_64 */
 201         psp_ring_reg = ring_type;
 202         psp_ring_reg = psp_ring_reg << 16;
 203         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 204
 205         /* There might be handshake issue with hardware which needs delay */
 206         mdelay(20);
 207
 208         /* Wait for response flag (bit 31) in C2PMSG_64 */
 209         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 210                            0x80000000, 0x8000FFFF, false);
 211
 212         return ret;
 213 }
 214
 215 int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
 216 {
 217         int ret = 0;
 218         struct psp_ring *ring;
 219         unsigned int psp_ring_reg = 0;
 220         struct amdgpu_device *adev = psp->adev;
 221
 222         ring = &psp->km_ring;
 223
 224         /* Write the ring destroy command to C2PMSG_64 */
 225         psp_ring_reg = 3 << 16;
 226         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 227
 228         /* There might be handshake issue with hardware which needs delay */
 229         mdelay(20);
 230
 231         /* Wait for response flag (bit 31) in C2PMSG_64 */
 232         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 233                            0x80000000, 0x80000000, false);
 234
 235         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 236                               &ring->ring_mem_mc_addr,
 237                               (void **)&ring->ring_mem);
 238
 239         return ret;
 240 }
 241
 242 int psp_v10_0_cmd_submit(struct psp_context *psp,
 243                         struct amdgpu_firmware_info *ucode,
 244                         uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 245                         int index)
 246 {
 247         unsigned int psp_write_ptr_reg = 0;
 248         struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 249         struct psp_ring *ring = &psp->km_ring;
 250         struct amdgpu_device *adev = psp->adev;
 251
 252         /* KM (GPCOM) prepare write pointer */
 253         psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 254
 255         /* Update KM RB frame pointer to new frame */
 256         if ((psp_write_ptr_reg % ring->ring_size) == 0)
 257                 write_frame = ring->ring_mem;
 258         else
 259                 write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
 260
 261         /* Update KM RB frame */
 262         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 263         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 264         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 265         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 266         write_frame->fence_value = index;
 267
 268         /* Update the write Pointer in DWORDs */
 269         psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
 270         psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
 271         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 272
 273         return 0;
 274 }
 275
 276 static int
 277 psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 278                   unsigned int *sram_data_reg_offset,
 279                   enum AMDGPU_UCODE_ID ucode_id)
 280 {
 281         int ret = 0;
 282
 283         switch(ucode_id) {
 284 /* TODO: needs to confirm */
 285 #if 0
 286         case AMDGPU_UCODE_ID_SMC:
 287                 *sram_offset = 0;
 288                 *sram_addr_reg_offset = 0;
 289                 *sram_data_reg_offset = 0;
 290                 break;
 291 #endif
 292
 293         case AMDGPU_UCODE_ID_CP_CE:
 294                 *sram_offset = 0x0;
 295                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 296                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 297                 break;
 298
 299         case AMDGPU_UCODE_ID_CP_PFP:
 300                 *sram_offset = 0x0;
 301                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 302                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 303                 break;
 304
 305         case AMDGPU_UCODE_ID_CP_ME:
 306                 *sram_offset = 0x0;
 307                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 308                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 309                 break;
 310
 311         case AMDGPU_UCODE_ID_CP_MEC1:
 312                 *sram_offset = 0x10000;
 313                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 314                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 315                 break;
 316
 317         case AMDGPU_UCODE_ID_CP_MEC2:
 318                 *sram_offset = 0x10000;
 319                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 320                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 321                 break;
 322
 323         case AMDGPU_UCODE_ID_RLC_G:
 324                 *sram_offset = 0x2000;
 325                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 326                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 327                 break;
 328
 329         case AMDGPU_UCODE_ID_SDMA0:
 330                 *sram_offset = 0x0;
 331                 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 332                 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 333                 break;
 334
 335 /* TODO: needs to confirm */
 336 #if 0
 337         case AMDGPU_UCODE_ID_SDMA1:
 338                 *sram_offset = ;
 339                 *sram_addr_reg_offset = ;
 340                 break;
 341
 342         case AMDGPU_UCODE_ID_UVD:
 343                 *sram_offset = ;
 344                 *sram_addr_reg_offset = ;
 345                 break;
 346
 347         case AMDGPU_UCODE_ID_VCE:
 348                 *sram_offset = ;
 349                 *sram_addr_reg_offset = ;
 350                 break;
 351 #endif
 352
 353         case AMDGPU_UCODE_ID_MAXIMUM:
 354         default:
 355                 ret = -EINVAL;
 356                 break;
 357         }
 358
 359         return ret;
 360 }
 361
 362 bool psp_v10_0_compare_sram_data(struct psp_context *psp,
 363                                 struct amdgpu_firmware_info *ucode,
 364                                 enum AMDGPU_UCODE_ID ucode_type)
 365 {
 366         int err = 0;
 367         unsigned int fw_sram_reg_val = 0;
 368         unsigned int fw_sram_addr_reg_offset = 0;
 369         unsigned int fw_sram_data_reg_offset = 0;
 370         unsigned int ucode_size;
 371         uint32_t *ucode_mem = NULL;
 372         struct amdgpu_device *adev = psp->adev;
 373
 374         err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
 375                                 &fw_sram_data_reg_offset, ucode_type);
 376         if (err)
 377                 return false;
 378
 379         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 380
 381         ucode_size = ucode->ucode_size;
 382         ucode_mem = (uint32_t *)ucode->kaddr;
 383         while (!ucode_size) {
 384                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 385
 386                 if (*ucode_mem != fw_sram_reg_val)
 387                         return false;
 388
 389                 ucode_mem++;
 390                 /* 4 bytes */
 391                 ucode_size -= 4;
 392         }
 393
 394         return true;
 395 }