drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "mmhub_v1_0.h"
  25
  26 #include "vega10/soc15ip.h"
  27 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  28 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  29 #include "vega10/MMHUB/mmhub_1_0_default.h"
  30 #include "vega10/ATHUB/athub_1_0_offset.h"
  31 #include "vega10/ATHUB/athub_1_0_sh_mask.h"
  32 #include "vega10/ATHUB/athub_1_0_default.h"
  33 #include "vega10/vega10_enum.h"
  34
  35 #include "soc15_common.h"
  36
  37 #define mmDAGB0_CNTL_MISC2_RV 0x008f
  38 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
  39
  40 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
  41 {
  42         u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
  43
  44         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  45         base <<= 24;
  46
  47         return base;
  48 }
  49
  50 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
  51 {
  52         uint64_t value;
  53
  54         BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
  55         value = adev->gart.table_addr - adev->mc.vram_start +
  56                 adev->vm_manager.vram_base_offset;
  57         value &= 0x0000FFFFFFFFF000ULL;
  58         value |= 0x1; /* valid bit */
  59
  60         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  61                      lower_32_bits(value));
  62
  63         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  64                      upper_32_bits(value));
  65 }
  66
  67 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  68 {
  69         mmhub_v1_0_init_gart_pt_regs(adev);
  70
  71         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  72                      (u32)(adev->mc.gart_start >> 12));
  73         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  74                      (u32)(adev->mc.gart_start >> 44));
  75
  76         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  77                      (u32)(adev->mc.gart_end >> 12));
  78         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  79                      (u32)(adev->mc.gart_end >> 44));
  80 }
  81
  82 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  83 {
  84         uint64_t value;
  85         uint32_t tmp;
  86
  87         /* Disable AGP. */
  88         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
  89         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
  90         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
  91
  92         /* Program the system aperture low logical page number. */
  93         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  94                      adev->mc.vram_start >> 18);
  95         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  96                      adev->mc.vram_end >> 18);
  97
  98         /* Set default page address. */
  99         value = adev->vram_scratch.gpu_addr - adev->mc.vram_start +
 100                 adev->vm_manager.vram_base_offset;
 101         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 102                      (u32)(value >> 12));
 103         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 104                      (u32)(value >> 44));
 105
 106         /* Program "protection fault". */
 107         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 108                      (u32)(adev->dummy_page.addr >> 12));
 109         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 110                      (u32)((u64)adev->dummy_page.addr >> 44));
 111
 112         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
 113         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 114                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 115         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 116 }
 117
 118 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 119 {
 120         uint32_t tmp;
 121
 122         /* Setup TLB control */
 123         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 124
 125         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 126         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 127         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 128                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 129         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 130                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 131         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 132         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 133                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 134         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 135
 136         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 137 }
 138
 139 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 140 {
 141         uint32_t tmp;
 142
 143         /* Setup L2 cache */
 144         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 145         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 146         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 147         /* XXX for emulation, Refer to closed source code.*/
 148         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 149                             0);
 150         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
 151         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 152         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 153         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 154
 155         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
 156         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 157         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 158         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 159
 160         tmp = mmVM_L2_CNTL3_DEFAULT;
 161         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 162         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 163         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 164
 165         tmp = mmVM_L2_CNTL4_DEFAULT;
 166         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 167         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 168         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
 169 }
 170
 171 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 172 {
 173         uint32_t tmp;
 174
 175         tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 176         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 177         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 178         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
 179 }
 180
 181 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 182 {
 183         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 184                      0XFFFFFFFF);
 185         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 186                      0x0000000F);
 187
 188         WREG32_SOC15(MMHUB, 0,
 189                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 190         WREG32_SOC15(MMHUB, 0,
 191                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 192
 193         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 194                      0);
 195         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 196                      0);
 197 }
 198
 199 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 200 {
 201         int i;
 202         uint32_t tmp;
 203
 204         for (i = 0; i <= 14; i++) {
 205                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
 206                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 207                                 ENABLE_CONTEXT, 1);
 208                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 209                                 PAGE_TABLE_DEPTH, adev->vm_manager.num_level);
 210                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 211                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 212                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 213                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 214                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 215                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 216                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 217                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 218                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 219                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 220                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 221                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 222                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 223                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 224                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 225                                 PAGE_TABLE_BLOCK_SIZE,
 226                                 adev->vm_manager.block_size - 9);
 227                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 228                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 229                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 230                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 231                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 232                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 233                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
 234                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 235                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 236                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 237         }
 238 }
 239
 240 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 241 {
 242         unsigned i;
 243
 244         for (i = 0; i < 18; ++i) {
 245                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 246                                     2 * i, 0xffffffff);
 247                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 248                                     2 * i, 0x1f);
 249         }
 250 }
 251
 252 struct pctl_data {
 253         uint32_t index;
 254         uint32_t data;
 255 };
 256
 257 static const struct pctl_data pctl0_data[] = {
 258         {0x0, 0x7a640},
 259         {0x9, 0x2a64a},
 260         {0xd, 0x2a680},
 261         {0x11, 0x6a684},
 262         {0x19, 0xea68e},
 263         {0x29, 0xa69e},
 264         {0x2b, 0x34a6c0},
 265         {0x61, 0x83a707},
 266         {0xe6, 0x8a7a4},
 267         {0xf0, 0x1a7b8},
 268         {0xf3, 0xfa7cc},
 269         {0x104, 0x17a7dd},
 270         {0x11d, 0xa7dc},
 271         {0x11f, 0x12a7f5},
 272         {0x133, 0xa808},
 273         {0x135, 0x12a810},
 274         {0x149, 0x7a82c}
 275 };
 276 #define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0]))
 277
 278 #define PCTL0_RENG_EXEC_END_PTR 0x151
 279 #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE  0xa640
 280 #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
 281
 282 static const struct pctl_data pctl1_data[] = {
 283         {0x0, 0x39a000},
 284         {0x3b, 0x44a040},
 285         {0x81, 0x2a08d},
 286         {0x85, 0x6ba094},
 287         {0xf2, 0x18a100},
 288         {0x10c, 0x4a132},
 289         {0x112, 0xca141},
 290         {0x120, 0x2fa158},
 291         {0x151, 0x17a1d0},
 292         {0x16a, 0x1a1e9},
 293         {0x16d, 0x13a1ec},
 294         {0x182, 0x7a201},
 295         {0x18b, 0x3a20a},
 296         {0x190, 0x7a580},
 297         {0x199, 0xa590},
 298         {0x19b, 0x4a594},
 299         {0x1a1, 0x1a59c},
 300         {0x1a4, 0x7a82c},
 301         {0x1ad, 0xfa7cc},
 302         {0x1be, 0x17a7dd},
 303         {0x1d7, 0x12a810},
 304         {0x1eb, 0x4000a7e1},
 305         {0x1ec, 0x5000a7f5},
 306         {0x1ed, 0x4000a7e2},
 307         {0x1ee, 0x5000a7dc},
 308         {0x1ef, 0x4000a7e3},
 309         {0x1f0, 0x5000a7f6},
 310         {0x1f1, 0x5000a7e4}
 311 };
 312 #define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0]))
 313
 314 #define PCTL1_RENG_EXEC_END_PTR 0x1f1
 315 #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE  0xa000
 316 #define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d
 317 #define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE  0xa580
 318 #define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d
 319 #define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE  0xa82c
 320 #define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833
 321
 322 static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev)
 323 {
 324         uint32_t tmp = 0;
 325
 326         /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */
 327         tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
 328                         STCTRL_REGISTER_SAVE_BASE,
 329                         PCTL0_STCTRL_REG_SAVE_RANGE0_BASE);
 330         tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
 331                         STCTRL_REGISTER_SAVE_LIMIT,
 332                         PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT);
 333         WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp);
 334
 335         /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */
 336         tmp = 0;
 337         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
 338                         STCTRL_REGISTER_SAVE_BASE,
 339                         PCTL1_STCTRL_REG_SAVE_RANGE0_BASE);
 340         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
 341                         STCTRL_REGISTER_SAVE_LIMIT,
 342                         PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT);
 343         WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp);
 344
 345         /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */
 346         tmp = 0;
 347         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
 348                         STCTRL_REGISTER_SAVE_BASE,
 349                         PCTL1_STCTRL_REG_SAVE_RANGE1_BASE);
 350         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
 351                         STCTRL_REGISTER_SAVE_LIMIT,
 352                         PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT);
 353         WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp);
 354
 355         /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */
 356         tmp = 0;
 357         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
 358                         STCTRL_REGISTER_SAVE_BASE,
 359                         PCTL1_STCTRL_REG_SAVE_RANGE2_BASE);
 360         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
 361                         STCTRL_REGISTER_SAVE_LIMIT,
 362                         PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT);
 363         WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp);
 364 }
 365
 366 void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev)
 367 {
 368         uint32_t pctl0_misc = 0;
 369         uint32_t pctl0_reng_execute = 0;
 370         uint32_t pctl1_misc = 0;
 371         uint32_t pctl1_reng_execute = 0;
 372         int i = 0;
 373
 374         if (amdgpu_sriov_vf(adev))
 375                 return;
 376
 377         pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC);
 378         pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
 379         pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
 380         pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
 381
 382         /* Light sleep must be disabled before writing to pctl0 registers */
 383         pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
 384         WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
 385
 386         /* Write data used to access ram of register engine */
 387         for (i = 0; i < PCTL0_DATA_LEN; i++) {
 388                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX,
 389                         pctl0_data[i].index);
 390                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA,
 391                         pctl0_data[i].data);
 392         }
 393
 394         /* Set the reng execute end ptr for pctl0 */
 395         pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 396                                         PCTL0_RENG_EXECUTE,
 397                                         RENG_EXECUTE_END_PTR,
 398                                         PCTL0_RENG_EXEC_END_PTR);
 399         WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
 400
 401         /* Light sleep must be disabled before writing to pctl1 registers */
 402         pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
 403         WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
 404
 405         /* Write data used to access ram of register engine */
 406         for (i = 0; i < PCTL1_DATA_LEN; i++) {
 407                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX,
 408                         pctl1_data[i].index);
 409                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA,
 410                         pctl1_data[i].data);
 411         }
 412
 413         /* Set the reng execute end ptr for pctl1 */
 414         pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 415                                         PCTL1_RENG_EXECUTE,
 416                                         RENG_EXECUTE_END_PTR,
 417                                         PCTL1_RENG_EXEC_END_PTR);
 418         WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 419
 420         mmhub_v1_0_power_gating_write_save_ranges(adev);
 421
 422         /* Re-enable light sleep */
 423         pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
 424         WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
 425         pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
 426         WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
 427 }
 428
 429 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 430                                 bool enable)
 431 {
 432         uint32_t pctl0_reng_execute = 0;
 433         uint32_t pctl1_reng_execute = 0;
 434
 435         if (amdgpu_sriov_vf(adev))
 436                 return;
 437
 438         pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
 439         pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
 440
 441         if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
 442                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 443                                                 PCTL0_RENG_EXECUTE,
 444                                                 RENG_EXECUTE_ON_PWR_UP, 1);
 445                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 446                                                 PCTL0_RENG_EXECUTE,
 447                                                 RENG_EXECUTE_ON_REG_UPDATE, 1);
 448                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
 449
 450                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 451                                                 PCTL1_RENG_EXECUTE,
 452                                                 RENG_EXECUTE_ON_PWR_UP, 1);
 453                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 454                                                 PCTL1_RENG_EXECUTE,
 455                                                 RENG_EXECUTE_ON_REG_UPDATE, 1);
 456                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 457
 458         } else {
 459                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 460                                                 PCTL0_RENG_EXECUTE,
 461                                                 RENG_EXECUTE_ON_PWR_UP, 0);
 462                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 463                                                 PCTL0_RENG_EXECUTE,
 464                                                 RENG_EXECUTE_ON_REG_UPDATE, 0);
 465                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
 466
 467                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 468                                                 PCTL1_RENG_EXECUTE,
 469                                                 RENG_EXECUTE_ON_PWR_UP, 0);
 470                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 471                                                 PCTL1_RENG_EXECUTE,
 472                                                 RENG_EXECUTE_ON_REG_UPDATE, 0);
 473                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 474         }
 475 }
 476
 477 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 478 {
 479         if (amdgpu_sriov_vf(adev)) {
 480                 /*
 481                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 482                  * VF copy registers so vbios post doesn't program them, for
 483                  * SRIOV driver need to program them
 484                  */
 485                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
 486                              adev->mc.vram_start >> 24);
 487                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
 488                              adev->mc.vram_end >> 24);
 489         }
 490
 491         /* GART Enable. */
 492         mmhub_v1_0_init_gart_aperture_regs(adev);
 493         mmhub_v1_0_init_system_aperture_regs(adev);
 494         mmhub_v1_0_init_tlb_regs(adev);
 495         mmhub_v1_0_init_cache_regs(adev);
 496
 497         mmhub_v1_0_enable_system_domain(adev);
 498         mmhub_v1_0_disable_identity_aperture(adev);
 499         mmhub_v1_0_setup_vmid_config(adev);
 500         mmhub_v1_0_program_invalidation(adev);
 501
 502         return 0;
 503 }
 504
 505 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
 506 {
 507         u32 tmp;
 508         u32 i;
 509
 510         /* Disable all tables */
 511         for (i = 0; i < 16; i++)
 512                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
 513
 514         /* Setup TLB control */
 515         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 516         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 517         tmp = REG_SET_FIELD(tmp,
 518                                 MC_VM_MX_L1_TLB_CNTL,
 519                                 ENABLE_ADVANCED_DRIVER_MODEL,
 520                                 0);
 521         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 522
 523         /* Setup L2 cache */
 524         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 525         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 526         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 527         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
 528 }
 529
 530 /**
 531  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 532  *
 533  * @adev: amdgpu_device pointer
 534  * @value: true redirects VM faults to the default page
 535  */
 536 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 537 {
 538         u32 tmp;
 539         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 540         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 541                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 542         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 543                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 544         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 545                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 546         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 547                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 548         tmp = REG_SET_FIELD(tmp,
 549                         VM_L2_PROTECTION_FAULT_CNTL,
 550                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 551                         value);
 552         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 553                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 554         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 555                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 556         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 557                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 558         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 559                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 560         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 561                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 562         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 563                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 564         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 565 }
 566
 567 void mmhub_v1_0_init(struct amdgpu_device *adev)
 568 {
 569         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
 570
 571         hub->ctx0_ptb_addr_lo32 =
 572                 SOC15_REG_OFFSET(MMHUB, 0,
 573                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 574         hub->ctx0_ptb_addr_hi32 =
 575                 SOC15_REG_OFFSET(MMHUB, 0,
 576                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 577         hub->vm_inv_eng0_req =
 578                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
 579         hub->vm_inv_eng0_ack =
 580                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
 581         hub->vm_context0_cntl =
 582                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 583         hub->vm_l2_pro_fault_status =
 584                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 585         hub->vm_l2_pro_fault_cntl =
 586                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 587
 588 }
 589
 590 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 591                                                         bool enable)
 592 {
 593         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 594
 595         def  = data  = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 596
 597         if (adev->asic_type != CHIP_RAVEN) {
 598                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 599                 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
 600         } else
 601                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
 602
 603         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 604                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 605
 606                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 607                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 608                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 609                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 610                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 611                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 612
 613                 if (adev->asic_type != CHIP_RAVEN)
 614                         data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 615                                    DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 616                                    DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 617                                    DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 618                                    DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 619                                    DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 620         } else {
 621                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 622
 623                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 624                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 625                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 626                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 627                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 628                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 629
 630                 if (adev->asic_type != CHIP_RAVEN)
 631                         data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 632                                   DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 633                                   DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 634                                   DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 635                                   DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 636                                   DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 637         }
 638
 639         if (def != data)
 640                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 641
 642         if (def1 != data1) {
 643                 if (adev->asic_type != CHIP_RAVEN)
 644                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 645                 else
 646                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
 647         }
 648
 649         if (adev->asic_type != CHIP_RAVEN && def2 != data2)
 650                 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
 651 }
 652
 653 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 654                                                    bool enable)
 655 {
 656         uint32_t def, data;
 657
 658         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 659
 660         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 661                 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 662         else
 663                 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 664
 665         if (def != data)
 666                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
 667 }
 668
 669 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 670                                                        bool enable)
 671 {
 672         uint32_t def, data;
 673
 674         def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 675
 676         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 677                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 678         else
 679                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 680
 681         if (def != data)
 682                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 683 }
 684
 685 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 686                                                   bool enable)
 687 {
 688         uint32_t def, data;
 689
 690         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 691
 692         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
 693             (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 694                 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 695         else
 696                 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 697
 698         if(def != data)
 699                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
 700 }
 701
 702 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 703                                enum amd_clockgating_state state)
 704 {
 705         if (amdgpu_sriov_vf(adev))
 706                 return 0;
 707
 708         switch (adev->asic_type) {
 709         case CHIP_VEGA10:
 710         case CHIP_RAVEN:
 711                 mmhub_v1_0_update_medium_grain_clock_gating(adev,
 712                                 state == AMD_CG_STATE_GATE ? true : false);
 713                 athub_update_medium_grain_clock_gating(adev,
 714                                 state == AMD_CG_STATE_GATE ? true : false);
 715                 mmhub_v1_0_update_medium_grain_light_sleep(adev,
 716                                 state == AMD_CG_STATE_GATE ? true : false);
 717                 athub_update_medium_grain_light_sleep(adev,
 718                                 state == AMD_CG_STATE_GATE ? true : false);
 719                 break;
 720         default:
 721                 break;
 722         }
 723
 724         return 0;
 725 }
 726
 727 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 728 {
 729         int data;
 730
 731         if (amdgpu_sriov_vf(adev))
 732                 *flags = 0;
 733
 734         /* AMD_CG_SUPPORT_MC_MGCG */
 735         data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 736         if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
 737                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 738
 739         /* AMD_CG_SUPPORT_MC_LS */
 740         data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 741         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 742                 *flags |= AMD_CG_SUPPORT_MC_LS;
 743 }