2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "amdgpu_pm.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_dpm.h"
33 #include <linux/seq_file.h>
35 #include "smu/smu_7_0_0_d.h"
36 #include "smu/smu_7_0_0_sh_mask.h"
38 #include "gca/gfx_7_2_d.h"
39 #include "gca/gfx_7_2_sh_mask.h"
41 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
42 #define KV_MINIMUM_ENGINE_CLOCK 800
43 #define SMC_RAM_END 0x40000
45 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
55 struct amdgpu_ps *new_rps);
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
58 static int kv_force_dpm_highest(struct amdgpu_device *adev);
59 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
60 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
61 struct amdgpu_ps *new_rps,
62 struct amdgpu_ps *old_rps);
63 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
64 int min_temp, int max_temp);
65 static int kv_init_fps_limits(struct amdgpu_device *adev);
67 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
68 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
69 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
70 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
73 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
74 struct sumo_vid_mapping_table *vid_mapping_table,
77 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
78 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
81 if (vddc_sclk_table && vddc_sclk_table->count) {
82 if (vid_2bit < vddc_sclk_table->count)
83 return vddc_sclk_table->entries[vid_2bit].v;
85 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
87 for (i = 0; i < vid_mapping_table->num_entries; i++) {
88 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
89 return vid_mapping_table->entries[i].vid_7bit;
91 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
95 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
96 struct sumo_vid_mapping_table *vid_mapping_table,
99 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
100 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
103 if (vddc_sclk_table && vddc_sclk_table->count) {
104 for (i = 0; i < vddc_sclk_table->count; i++) {
105 if (vddc_sclk_table->entries[i].v == vid_7bit)
108 return vddc_sclk_table->count - 1;
110 for (i = 0; i < vid_mapping_table->num_entries; i++) {
111 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
112 return vid_mapping_table->entries[i].vid_2bit;
115 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
119 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
121 /* This bit selects who handles display phy powergating.
122 * Clear the bit to let atom handle it.
123 * Set it to let the driver handle it.
124 * For now we just let atom handle it.
127 u32 v = RREG32(mmDOUT_SCRATCH3);
134 WREG32(mmDOUT_SCRATCH3, v);
138 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
139 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
140 ATOM_AVAILABLE_SCLK_LIST *table)
146 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
147 if (table[i].ulSupportedSCLK > prev_sclk) {
148 sclk_voltage_mapping_table->entries[n].sclk_frequency =
149 table[i].ulSupportedSCLK;
150 sclk_voltage_mapping_table->entries[n].vid_2bit =
151 table[i].usVoltageIndex;
152 prev_sclk = table[i].ulSupportedSCLK;
157 sclk_voltage_mapping_table->num_max_dpm_entries = n;
160 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
161 struct sumo_vid_mapping_table *vid_mapping_table,
162 ATOM_AVAILABLE_SCLK_LIST *table)
166 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
167 if (table[i].ulSupportedSCLK != 0) {
168 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
169 table[i].usVoltageID;
170 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
171 table[i].usVoltageIndex;
175 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
176 if (vid_mapping_table->entries[i].vid_7bit == 0) {
177 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
178 if (vid_mapping_table->entries[j].vid_7bit != 0) {
179 vid_mapping_table->entries[i] =
180 vid_mapping_table->entries[j];
181 vid_mapping_table->entries[j].vid_7bit = 0;
186 if (j == SUMO_MAX_NUMBER_VOLTAGES)
191 vid_mapping_table->num_entries = i;
195 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
208 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
214 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
220 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
226 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
232 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
264 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
266 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
269 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
271 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
274 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
276 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
279 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
281 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
284 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
286 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
289 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
291 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
295 static const struct kv_pt_config_reg didt_config_kv[] =
297 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
298 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
299 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
300 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
301 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
302 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
303 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
304 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
305 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
306 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
307 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
308 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
309 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
310 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
311 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
312 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
313 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
314 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
315 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
316 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
317 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
318 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
319 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
320 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
321 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
322 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
323 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
324 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
325 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
326 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
327 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
328 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
329 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
330 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
331 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
332 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
333 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
334 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
335 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
336 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
337 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
338 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
339 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
340 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
341 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
342 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
343 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
344 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
345 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
346 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
347 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
348 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
349 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
350 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
351 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
352 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
353 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
354 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
355 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
356 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
357 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
358 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
359 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
360 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
361 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
362 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
363 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
364 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
365 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
366 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
367 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
368 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
372 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
374 struct kv_ps *ps = rps->ps_priv;
379 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
381 struct kv_power_info *pi = adev->pm.dpm.priv;
387 static void kv_program_local_cac_table(struct amdgpu_device *adev,
388 const struct kv_lcac_config_values *local_cac_table,
389 const struct kv_lcac_config_reg *local_cac_reg)
392 const struct kv_lcac_config_values *values = local_cac_table;
394 while (values->block_id != 0xffffffff) {
395 count = values->signal_id;
396 for (i = 0; i < count; i++) {
397 data = ((values->block_id << local_cac_reg->block_shift) &
398 local_cac_reg->block_mask);
399 data |= ((i << local_cac_reg->signal_shift) &
400 local_cac_reg->signal_mask);
401 data |= ((values->t << local_cac_reg->t_shift) &
402 local_cac_reg->t_mask);
403 data |= ((1 << local_cac_reg->enable_shift) &
404 local_cac_reg->enable_mask);
405 WREG32_SMC(local_cac_reg->cntl, data);
412 static int kv_program_pt_config_registers(struct amdgpu_device *adev,
413 const struct kv_pt_config_reg *cac_config_regs)
415 const struct kv_pt_config_reg *config_regs = cac_config_regs;
419 if (config_regs == NULL)
422 while (config_regs->offset != 0xFFFFFFFF) {
423 if (config_regs->type == KV_CONFIGREG_CACHE) {
424 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
426 switch (config_regs->type) {
427 case KV_CONFIGREG_SMC_IND:
428 data = RREG32_SMC(config_regs->offset);
430 case KV_CONFIGREG_DIDT_IND:
431 data = RREG32_DIDT(config_regs->offset);
434 data = RREG32(config_regs->offset);
438 data &= ~config_regs->mask;
439 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
443 switch (config_regs->type) {
444 case KV_CONFIGREG_SMC_IND:
445 WREG32_SMC(config_regs->offset, data);
447 case KV_CONFIGREG_DIDT_IND:
448 WREG32_DIDT(config_regs->offset, data);
451 WREG32(config_regs->offset, data);
461 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
463 struct kv_power_info *pi = kv_get_pi(adev);
466 if (pi->caps_sq_ramping) {
467 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
469 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
471 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
472 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
475 if (pi->caps_db_ramping) {
476 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
478 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
480 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
481 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
484 if (pi->caps_td_ramping) {
485 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
487 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
489 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
490 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
493 if (pi->caps_tcp_ramping) {
494 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
496 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
498 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
499 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
503 static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
505 struct kv_power_info *pi = kv_get_pi(adev);
508 if (pi->caps_sq_ramping ||
509 pi->caps_db_ramping ||
510 pi->caps_td_ramping ||
511 pi->caps_tcp_ramping) {
512 adev->gfx.rlc.funcs->enter_safe_mode(adev);
515 ret = kv_program_pt_config_registers(adev, didt_config_kv);
517 adev->gfx.rlc.funcs->exit_safe_mode(adev);
522 kv_do_enable_didt(adev, enable);
524 adev->gfx.rlc.funcs->exit_safe_mode(adev);
531 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
533 struct kv_power_info *pi = kv_get_pi(adev);
536 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
537 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
538 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
540 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
541 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
542 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
544 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
545 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
546 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
548 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
549 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
550 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
552 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
553 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
554 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
556 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
557 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
558 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
563 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
565 struct kv_power_info *pi = kv_get_pi(adev);
570 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
572 pi->cac_enabled = false;
574 pi->cac_enabled = true;
575 } else if (pi->cac_enabled) {
576 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
577 pi->cac_enabled = false;
584 static int kv_process_firmware_header(struct amdgpu_device *adev)
586 struct kv_power_info *pi = kv_get_pi(adev);
590 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
591 offsetof(SMU7_Firmware_Header, DpmTable),
595 pi->dpm_table_start = tmp;
597 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
598 offsetof(SMU7_Firmware_Header, SoftRegisters),
602 pi->soft_regs_start = tmp;
607 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
609 struct kv_power_info *pi = kv_get_pi(adev);
612 pi->graphics_voltage_change_enable = 1;
614 ret = amdgpu_kv_copy_bytes_to_smc(adev,
615 pi->dpm_table_start +
616 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
617 &pi->graphics_voltage_change_enable,
618 sizeof(u8), pi->sram_end);
623 static int kv_set_dpm_interval(struct amdgpu_device *adev)
625 struct kv_power_info *pi = kv_get_pi(adev);
628 pi->graphics_interval = 1;
630 ret = amdgpu_kv_copy_bytes_to_smc(adev,
631 pi->dpm_table_start +
632 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
633 &pi->graphics_interval,
634 sizeof(u8), pi->sram_end);
639 static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
641 struct kv_power_info *pi = kv_get_pi(adev);
644 ret = amdgpu_kv_copy_bytes_to_smc(adev,
645 pi->dpm_table_start +
646 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
647 &pi->graphics_boot_level,
648 sizeof(u8), pi->sram_end);
653 static void kv_program_vc(struct amdgpu_device *adev)
655 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
658 static void kv_clear_vc(struct amdgpu_device *adev)
660 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
663 static int kv_set_divider_value(struct amdgpu_device *adev,
666 struct kv_power_info *pi = kv_get_pi(adev);
667 struct atom_clock_dividers dividers;
670 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
671 sclk, false, ÷rs);
675 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
676 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
681 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
684 return 6200 - (voltage * 25);
687 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
690 struct kv_power_info *pi = kv_get_pi(adev);
691 u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
692 &pi->sys_info.vid_mapping_table,
695 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
699 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
701 struct kv_power_info *pi = kv_get_pi(adev);
703 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
704 pi->graphics_level[index].MinVddNb =
705 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
710 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
712 struct kv_power_info *pi = kv_get_pi(adev);
714 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
719 static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
720 u32 index, bool enable)
722 struct kv_power_info *pi = kv_get_pi(adev);
724 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
727 static void kv_start_dpm(struct amdgpu_device *adev)
729 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
731 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
732 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
734 amdgpu_kv_smc_dpm_enable(adev, true);
737 static void kv_stop_dpm(struct amdgpu_device *adev)
739 amdgpu_kv_smc_dpm_enable(adev, false);
742 static void kv_start_am(struct amdgpu_device *adev)
744 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
746 sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
747 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
748 sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
750 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
753 static void kv_reset_am(struct amdgpu_device *adev)
755 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
757 sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
758 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
760 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
763 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
765 return amdgpu_kv_notify_message_to_smu(adev, freeze ?
766 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
769 static int kv_force_lowest_valid(struct amdgpu_device *adev)
771 return kv_force_dpm_lowest(adev);
774 static int kv_unforce_levels(struct amdgpu_device *adev)
776 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
777 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
779 return kv_set_enabled_levels(adev);
782 static int kv_update_sclk_t(struct amdgpu_device *adev)
784 struct kv_power_info *pi = kv_get_pi(adev);
785 u32 low_sclk_interrupt_t = 0;
788 if (pi->caps_sclk_throttle_low_notification) {
789 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
791 ret = amdgpu_kv_copy_bytes_to_smc(adev,
792 pi->dpm_table_start +
793 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
794 (u8 *)&low_sclk_interrupt_t,
795 sizeof(u32), pi->sram_end);
800 static int kv_program_bootup_state(struct amdgpu_device *adev)
802 struct kv_power_info *pi = kv_get_pi(adev);
804 struct amdgpu_clock_voltage_dependency_table *table =
805 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
807 if (table && table->count) {
808 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
809 if (table->entries[i].clk == pi->boot_pl.sclk)
813 pi->graphics_boot_level = (u8)i;
814 kv_dpm_power_level_enable(adev, i, true);
816 struct sumo_sclk_voltage_mapping_table *table =
817 &pi->sys_info.sclk_voltage_mapping_table;
819 if (table->num_max_dpm_entries == 0)
822 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
823 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
827 pi->graphics_boot_level = (u8)i;
828 kv_dpm_power_level_enable(adev, i, true);
833 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
835 struct kv_power_info *pi = kv_get_pi(adev);
838 pi->graphics_therm_throttle_enable = 1;
840 ret = amdgpu_kv_copy_bytes_to_smc(adev,
841 pi->dpm_table_start +
842 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
843 &pi->graphics_therm_throttle_enable,
844 sizeof(u8), pi->sram_end);
849 static int kv_upload_dpm_settings(struct amdgpu_device *adev)
851 struct kv_power_info *pi = kv_get_pi(adev);
854 ret = amdgpu_kv_copy_bytes_to_smc(adev,
855 pi->dpm_table_start +
856 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
857 (u8 *)&pi->graphics_level,
858 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
864 ret = amdgpu_kv_copy_bytes_to_smc(adev,
865 pi->dpm_table_start +
866 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
867 &pi->graphics_dpm_level_count,
868 sizeof(u8), pi->sram_end);
873 static u32 kv_get_clock_difference(u32 a, u32 b)
875 return (a >= b) ? a - b : b - a;
878 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
880 struct kv_power_info *pi = kv_get_pi(adev);
883 if (pi->caps_enable_dfs_bypass) {
884 if (kv_get_clock_difference(clk, 40000) < 200)
886 else if (kv_get_clock_difference(clk, 30000) < 200)
888 else if (kv_get_clock_difference(clk, 20000) < 200)
890 else if (kv_get_clock_difference(clk, 15000) < 200)
892 else if (kv_get_clock_difference(clk, 10000) < 200)
903 static int kv_populate_uvd_table(struct amdgpu_device *adev)
905 struct kv_power_info *pi = kv_get_pi(adev);
906 struct amdgpu_uvd_clock_voltage_dependency_table *table =
907 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
908 struct atom_clock_dividers dividers;
912 if (table == NULL || table->count == 0)
915 pi->uvd_level_count = 0;
916 for (i = 0; i < table->count; i++) {
917 if (pi->high_voltage_t &&
918 (pi->high_voltage_t < table->entries[i].v))
921 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
922 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
923 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
925 pi->uvd_level[i].VClkBypassCntl =
926 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
927 pi->uvd_level[i].DClkBypassCntl =
928 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
930 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
931 table->entries[i].vclk, false, ÷rs);
934 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
936 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
937 table->entries[i].dclk, false, ÷rs);
940 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
942 pi->uvd_level_count++;
945 ret = amdgpu_kv_copy_bytes_to_smc(adev,
946 pi->dpm_table_start +
947 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
948 (u8 *)&pi->uvd_level_count,
949 sizeof(u8), pi->sram_end);
953 pi->uvd_interval = 1;
955 ret = amdgpu_kv_copy_bytes_to_smc(adev,
956 pi->dpm_table_start +
957 offsetof(SMU7_Fusion_DpmTable, UVDInterval),
959 sizeof(u8), pi->sram_end);
963 ret = amdgpu_kv_copy_bytes_to_smc(adev,
964 pi->dpm_table_start +
965 offsetof(SMU7_Fusion_DpmTable, UvdLevel),
966 (u8 *)&pi->uvd_level,
967 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
974 static int kv_populate_vce_table(struct amdgpu_device *adev)
976 struct kv_power_info *pi = kv_get_pi(adev);
979 struct amdgpu_vce_clock_voltage_dependency_table *table =
980 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
981 struct atom_clock_dividers dividers;
983 if (table == NULL || table->count == 0)
986 pi->vce_level_count = 0;
987 for (i = 0; i < table->count; i++) {
988 if (pi->high_voltage_t &&
989 pi->high_voltage_t < table->entries[i].v)
992 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
993 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
995 pi->vce_level[i].ClkBypassCntl =
996 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
998 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
999 table->entries[i].evclk, false, ÷rs);
1002 pi->vce_level[i].Divider = (u8)dividers.post_div;
1004 pi->vce_level_count++;
1007 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1008 pi->dpm_table_start +
1009 offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
1010 (u8 *)&pi->vce_level_count,
1016 pi->vce_interval = 1;
1018 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1019 pi->dpm_table_start +
1020 offsetof(SMU7_Fusion_DpmTable, VCEInterval),
1021 (u8 *)&pi->vce_interval,
1027 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1028 pi->dpm_table_start +
1029 offsetof(SMU7_Fusion_DpmTable, VceLevel),
1030 (u8 *)&pi->vce_level,
1031 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
1037 static int kv_populate_samu_table(struct amdgpu_device *adev)
1039 struct kv_power_info *pi = kv_get_pi(adev);
1040 struct amdgpu_clock_voltage_dependency_table *table =
1041 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1042 struct atom_clock_dividers dividers;
1046 if (table == NULL || table->count == 0)
1049 pi->samu_level_count = 0;
1050 for (i = 0; i < table->count; i++) {
1051 if (pi->high_voltage_t &&
1052 pi->high_voltage_t < table->entries[i].v)
1055 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1056 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1058 pi->samu_level[i].ClkBypassCntl =
1059 (u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1061 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1062 table->entries[i].clk, false, ÷rs);
1065 pi->samu_level[i].Divider = (u8)dividers.post_div;
1067 pi->samu_level_count++;
1070 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1071 pi->dpm_table_start +
1072 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
1073 (u8 *)&pi->samu_level_count,
1079 pi->samu_interval = 1;
1081 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1082 pi->dpm_table_start +
1083 offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
1084 (u8 *)&pi->samu_interval,
1090 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1091 pi->dpm_table_start +
1092 offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1093 (u8 *)&pi->samu_level,
1094 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1103 static int kv_populate_acp_table(struct amdgpu_device *adev)
1105 struct kv_power_info *pi = kv_get_pi(adev);
1106 struct amdgpu_clock_voltage_dependency_table *table =
1107 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1108 struct atom_clock_dividers dividers;
1112 if (table == NULL || table->count == 0)
1115 pi->acp_level_count = 0;
1116 for (i = 0; i < table->count; i++) {
1117 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1118 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1120 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1121 table->entries[i].clk, false, ÷rs);
1124 pi->acp_level[i].Divider = (u8)dividers.post_div;
1126 pi->acp_level_count++;
1129 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1130 pi->dpm_table_start +
1131 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1132 (u8 *)&pi->acp_level_count,
1138 pi->acp_interval = 1;
1140 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1141 pi->dpm_table_start +
1142 offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1143 (u8 *)&pi->acp_interval,
1149 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1150 pi->dpm_table_start +
1151 offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1152 (u8 *)&pi->acp_level,
1153 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1161 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
1163 struct kv_power_info *pi = kv_get_pi(adev);
1165 struct amdgpu_clock_voltage_dependency_table *table =
1166 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1168 if (table && table->count) {
1169 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1170 if (pi->caps_enable_dfs_bypass) {
1171 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1172 pi->graphics_level[i].ClkBypassCntl = 3;
1173 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1174 pi->graphics_level[i].ClkBypassCntl = 2;
1175 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1176 pi->graphics_level[i].ClkBypassCntl = 7;
1177 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1178 pi->graphics_level[i].ClkBypassCntl = 6;
1179 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1180 pi->graphics_level[i].ClkBypassCntl = 8;
1182 pi->graphics_level[i].ClkBypassCntl = 0;
1184 pi->graphics_level[i].ClkBypassCntl = 0;
1188 struct sumo_sclk_voltage_mapping_table *table =
1189 &pi->sys_info.sclk_voltage_mapping_table;
1190 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1191 if (pi->caps_enable_dfs_bypass) {
1192 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1193 pi->graphics_level[i].ClkBypassCntl = 3;
1194 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1195 pi->graphics_level[i].ClkBypassCntl = 2;
1196 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1197 pi->graphics_level[i].ClkBypassCntl = 7;
1198 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1199 pi->graphics_level[i].ClkBypassCntl = 6;
1200 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1201 pi->graphics_level[i].ClkBypassCntl = 8;
1203 pi->graphics_level[i].ClkBypassCntl = 0;
1205 pi->graphics_level[i].ClkBypassCntl = 0;
1211 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
1213 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1214 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1217 static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
1219 struct kv_power_info *pi = kv_get_pi(adev);
1221 pi->acp_boot_level = 0xff;
1224 static void kv_update_current_ps(struct amdgpu_device *adev,
1225 struct amdgpu_ps *rps)
1227 struct kv_ps *new_ps = kv_get_ps(rps);
1228 struct kv_power_info *pi = kv_get_pi(adev);
1230 pi->current_rps = *rps;
1231 pi->current_ps = *new_ps;
1232 pi->current_rps.ps_priv = &pi->current_ps;
1233 adev->pm.dpm.current_ps = &pi->current_rps;
1236 static void kv_update_requested_ps(struct amdgpu_device *adev,
1237 struct amdgpu_ps *rps)
1239 struct kv_ps *new_ps = kv_get_ps(rps);
1240 struct kv_power_info *pi = kv_get_pi(adev);
1242 pi->requested_rps = *rps;
1243 pi->requested_ps = *new_ps;
1244 pi->requested_rps.ps_priv = &pi->requested_ps;
1245 adev->pm.dpm.requested_ps = &pi->requested_rps;
1248 static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
1250 struct kv_power_info *pi = kv_get_pi(adev);
1253 if (pi->bapm_enable) {
1254 ret = amdgpu_kv_smc_bapm_enable(adev, enable);
1256 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1260 static int kv_dpm_enable(struct amdgpu_device *adev)
1262 struct kv_power_info *pi = kv_get_pi(adev);
1265 ret = kv_process_firmware_header(adev);
1267 DRM_ERROR("kv_process_firmware_header failed\n");
1270 kv_init_fps_limits(adev);
1271 kv_init_graphics_levels(adev);
1272 ret = kv_program_bootup_state(adev);
1274 DRM_ERROR("kv_program_bootup_state failed\n");
1277 kv_calculate_dfs_bypass_settings(adev);
1278 ret = kv_upload_dpm_settings(adev);
1280 DRM_ERROR("kv_upload_dpm_settings failed\n");
1283 ret = kv_populate_uvd_table(adev);
1285 DRM_ERROR("kv_populate_uvd_table failed\n");
1288 ret = kv_populate_vce_table(adev);
1290 DRM_ERROR("kv_populate_vce_table failed\n");
1293 ret = kv_populate_samu_table(adev);
1295 DRM_ERROR("kv_populate_samu_table failed\n");
1298 ret = kv_populate_acp_table(adev);
1300 DRM_ERROR("kv_populate_acp_table failed\n");
1303 kv_program_vc(adev);
1305 kv_initialize_hardware_cac_manager(adev);
1308 if (pi->enable_auto_thermal_throttling) {
1309 ret = kv_enable_auto_thermal_throttling(adev);
1311 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1315 ret = kv_enable_dpm_voltage_scaling(adev);
1317 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1320 ret = kv_set_dpm_interval(adev);
1322 DRM_ERROR("kv_set_dpm_interval failed\n");
1325 ret = kv_set_dpm_boot_state(adev);
1327 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1330 ret = kv_enable_ulv(adev, true);
1332 DRM_ERROR("kv_enable_ulv failed\n");
1336 ret = kv_enable_didt(adev, true);
1338 DRM_ERROR("kv_enable_didt failed\n");
1341 ret = kv_enable_smc_cac(adev, true);
1343 DRM_ERROR("kv_enable_smc_cac failed\n");
1347 kv_reset_acp_boot_level(adev);
1349 ret = amdgpu_kv_smc_bapm_enable(adev, false);
1351 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1355 if (adev->irq.installed &&
1356 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
1357 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
1359 DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1362 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1363 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1364 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1365 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1371 static void kv_dpm_disable(struct amdgpu_device *adev)
1373 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1374 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1375 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1376 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1378 amdgpu_kv_smc_bapm_enable(adev, false);
1380 if (adev->asic_type == CHIP_MULLINS)
1381 kv_enable_nb_dpm(adev, false);
1383 /* powerup blocks */
1384 kv_dpm_powergate_acp(adev, false);
1385 kv_dpm_powergate_samu(adev, false);
1386 kv_dpm_powergate_vce(adev, false);
1387 kv_dpm_powergate_uvd(adev, false);
1389 kv_enable_smc_cac(adev, false);
1390 kv_enable_didt(adev, false);
1393 kv_enable_ulv(adev, false);
1396 kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1400 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1401 u16 reg_offset, u32 value)
1403 struct kv_power_info *pi = kv_get_pi(adev);
1405 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1406 (u8 *)&value, sizeof(u16), pi->sram_end);
1409 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1410 u16 reg_offset, u32 *value)
1412 struct kv_power_info *pi = kv_get_pi(adev);
1414 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1415 value, pi->sram_end);
1419 static void kv_init_sclk_t(struct amdgpu_device *adev)
1421 struct kv_power_info *pi = kv_get_pi(adev);
1423 pi->low_sclk_interrupt_t = 0;
1426 static int kv_init_fps_limits(struct amdgpu_device *adev)
1428 struct kv_power_info *pi = kv_get_pi(adev);
1435 pi->fps_high_t = cpu_to_be16(tmp);
1436 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1437 pi->dpm_table_start +
1438 offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1439 (u8 *)&pi->fps_high_t,
1440 sizeof(u16), pi->sram_end);
1443 pi->fps_low_t = cpu_to_be16(tmp);
1445 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1446 pi->dpm_table_start +
1447 offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1448 (u8 *)&pi->fps_low_t,
1449 sizeof(u16), pi->sram_end);
1455 static void kv_init_powergate_state(struct amdgpu_device *adev)
1457 struct kv_power_info *pi = kv_get_pi(adev);
1459 pi->uvd_power_gated = false;
1460 pi->vce_power_gated = false;
1461 pi->samu_power_gated = false;
1462 pi->acp_power_gated = false;
1466 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1468 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1469 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1472 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1474 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1475 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1478 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
1480 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1481 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1484 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
1486 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1487 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1490 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1492 struct kv_power_info *pi = kv_get_pi(adev);
1493 struct amdgpu_uvd_clock_voltage_dependency_table *table =
1494 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1500 pi->uvd_boot_level = table->count - 1;
1502 pi->uvd_boot_level = 0;
1504 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1505 mask = 1 << pi->uvd_boot_level;
1510 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1511 pi->dpm_table_start +
1512 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1513 (uint8_t *)&pi->uvd_boot_level,
1514 sizeof(u8), pi->sram_end);
1518 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1519 PPSMC_MSG_UVDDPM_SetEnabledMask,
1523 return kv_enable_uvd_dpm(adev, !gate);
1526 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
1529 struct amdgpu_vce_clock_voltage_dependency_table *table =
1530 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1532 for (i = 0; i < table->count; i++) {
1533 if (table->entries[i].evclk >= evclk)
1540 static int kv_update_vce_dpm(struct amdgpu_device *adev,
1541 struct amdgpu_ps *amdgpu_new_state,
1542 struct amdgpu_ps *amdgpu_current_state)
1544 struct kv_power_info *pi = kv_get_pi(adev);
1545 struct amdgpu_vce_clock_voltage_dependency_table *table =
1546 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1549 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1550 kv_dpm_powergate_vce(adev, false);
1551 if (pi->caps_stable_p_state)
1552 pi->vce_boot_level = table->count - 1;
1554 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
1556 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1557 pi->dpm_table_start +
1558 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1559 (u8 *)&pi->vce_boot_level,
1565 if (pi->caps_stable_p_state)
1566 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1567 PPSMC_MSG_VCEDPM_SetEnabledMask,
1568 (1 << pi->vce_boot_level));
1569 kv_enable_vce_dpm(adev, true);
1570 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1571 kv_enable_vce_dpm(adev, false);
1572 kv_dpm_powergate_vce(adev, true);
1578 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
1580 struct kv_power_info *pi = kv_get_pi(adev);
1581 struct amdgpu_clock_voltage_dependency_table *table =
1582 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1586 if (pi->caps_stable_p_state)
1587 pi->samu_boot_level = table->count - 1;
1589 pi->samu_boot_level = 0;
1591 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1592 pi->dpm_table_start +
1593 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1594 (u8 *)&pi->samu_boot_level,
1600 if (pi->caps_stable_p_state)
1601 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1602 PPSMC_MSG_SAMUDPM_SetEnabledMask,
1603 (1 << pi->samu_boot_level));
1606 return kv_enable_samu_dpm(adev, !gate);
1609 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
1612 struct amdgpu_clock_voltage_dependency_table *table =
1613 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1615 for (i = 0; i < table->count; i++) {
1616 if (table->entries[i].clk >= 0) /* XXX */
1620 if (i >= table->count)
1621 i = table->count - 1;
1626 static void kv_update_acp_boot_level(struct amdgpu_device *adev)
1628 struct kv_power_info *pi = kv_get_pi(adev);
1631 if (!pi->caps_stable_p_state) {
1632 acp_boot_level = kv_get_acp_boot_level(adev);
1633 if (acp_boot_level != pi->acp_boot_level) {
1634 pi->acp_boot_level = acp_boot_level;
1635 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1636 PPSMC_MSG_ACPDPM_SetEnabledMask,
1637 (1 << pi->acp_boot_level));
1642 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
1644 struct kv_power_info *pi = kv_get_pi(adev);
1645 struct amdgpu_clock_voltage_dependency_table *table =
1646 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1650 if (pi->caps_stable_p_state)
1651 pi->acp_boot_level = table->count - 1;
1653 pi->acp_boot_level = kv_get_acp_boot_level(adev);
1655 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1656 pi->dpm_table_start +
1657 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1658 (u8 *)&pi->acp_boot_level,
1664 if (pi->caps_stable_p_state)
1665 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1666 PPSMC_MSG_ACPDPM_SetEnabledMask,
1667 (1 << pi->acp_boot_level));
1670 return kv_enable_acp_dpm(adev, !gate);
1673 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1675 struct kv_power_info *pi = kv_get_pi(adev);
1678 pi->uvd_power_gated = gate;
1681 /* stop the UVD block */
1682 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1684 kv_update_uvd_dpm(adev, gate);
1685 if (pi->caps_uvd_pg)
1686 /* power off the UVD block */
1687 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1689 if (pi->caps_uvd_pg)
1690 /* power on the UVD block */
1691 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1692 /* re-init the UVD block */
1693 kv_update_uvd_dpm(adev, gate);
1695 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1696 AMD_PG_STATE_UNGATE);
1700 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1702 struct kv_power_info *pi = kv_get_pi(adev);
1704 if (pi->vce_power_gated == gate)
1707 pi->vce_power_gated = gate;
1709 if (!pi->caps_vce_pg)
1713 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1715 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1718 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
1720 struct kv_power_info *pi = kv_get_pi(adev);
1722 if (pi->samu_power_gated == gate)
1725 pi->samu_power_gated = gate;
1728 kv_update_samu_dpm(adev, true);
1729 if (pi->caps_samu_pg)
1730 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
1732 if (pi->caps_samu_pg)
1733 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
1734 kv_update_samu_dpm(adev, false);
1738 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
1740 struct kv_power_info *pi = kv_get_pi(adev);
1742 if (pi->acp_power_gated == gate)
1745 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
1748 pi->acp_power_gated = gate;
1751 kv_update_acp_dpm(adev, true);
1752 if (pi->caps_acp_pg)
1753 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
1755 if (pi->caps_acp_pg)
1756 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
1757 kv_update_acp_dpm(adev, false);
1761 static void kv_set_valid_clock_range(struct amdgpu_device *adev,
1762 struct amdgpu_ps *new_rps)
1764 struct kv_ps *new_ps = kv_get_ps(new_rps);
1765 struct kv_power_info *pi = kv_get_pi(adev);
1767 struct amdgpu_clock_voltage_dependency_table *table =
1768 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1770 if (table && table->count) {
1771 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1772 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1773 (i == (pi->graphics_dpm_level_count - 1))) {
1774 pi->lowest_valid = i;
1779 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1780 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1783 pi->highest_valid = i;
1785 if (pi->lowest_valid > pi->highest_valid) {
1786 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1787 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1788 pi->highest_valid = pi->lowest_valid;
1790 pi->lowest_valid = pi->highest_valid;
1793 struct sumo_sclk_voltage_mapping_table *table =
1794 &pi->sys_info.sclk_voltage_mapping_table;
1796 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1797 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1798 i == (int)(pi->graphics_dpm_level_count - 1)) {
1799 pi->lowest_valid = i;
1804 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1805 if (table->entries[i].sclk_frequency <=
1806 new_ps->levels[new_ps->num_levels - 1].sclk)
1809 pi->highest_valid = i;
1811 if (pi->lowest_valid > pi->highest_valid) {
1812 if ((new_ps->levels[0].sclk -
1813 table->entries[pi->highest_valid].sclk_frequency) >
1814 (table->entries[pi->lowest_valid].sclk_frequency -
1815 new_ps->levels[new_ps->num_levels -1].sclk))
1816 pi->highest_valid = pi->lowest_valid;
1818 pi->lowest_valid = pi->highest_valid;
1823 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
1824 struct amdgpu_ps *new_rps)
1826 struct kv_ps *new_ps = kv_get_ps(new_rps);
1827 struct kv_power_info *pi = kv_get_pi(adev);
1831 if (pi->caps_enable_dfs_bypass) {
1832 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1833 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1834 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1835 (pi->dpm_table_start +
1836 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1837 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1838 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1840 sizeof(u8), pi->sram_end);
1846 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
1849 struct kv_power_info *pi = kv_get_pi(adev);
1853 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1854 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
1856 pi->nb_dpm_enabled = true;
1859 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1860 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
1862 pi->nb_dpm_enabled = false;
1869 static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
1870 enum amd_dpm_forced_level level)
1874 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
1875 ret = kv_force_dpm_highest(adev);
1878 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
1879 ret = kv_force_dpm_lowest(adev);
1882 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
1883 ret = kv_unforce_levels(adev);
1888 adev->pm.dpm.forced_level = level;
1893 static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
1895 struct kv_power_info *pi = kv_get_pi(adev);
1896 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1897 struct amdgpu_ps *new_ps = &requested_ps;
1899 kv_update_requested_ps(adev, new_ps);
1901 kv_apply_state_adjust_rules(adev,
1908 static int kv_dpm_set_power_state(struct amdgpu_device *adev)
1910 struct kv_power_info *pi = kv_get_pi(adev);
1911 struct amdgpu_ps *new_ps = &pi->requested_rps;
1912 struct amdgpu_ps *old_ps = &pi->current_rps;
1915 if (pi->bapm_enable) {
1916 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power);
1918 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1923 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
1924 if (pi->enable_dpm) {
1925 kv_set_valid_clock_range(adev, new_ps);
1926 kv_update_dfs_bypass_settings(adev, new_ps);
1927 ret = kv_calculate_ds_divider(adev);
1929 DRM_ERROR("kv_calculate_ds_divider failed\n");
1932 kv_calculate_nbps_level_settings(adev);
1933 kv_calculate_dpm_settings(adev);
1934 kv_force_lowest_valid(adev);
1935 kv_enable_new_levels(adev);
1936 kv_upload_dpm_settings(adev);
1937 kv_program_nbps_index_settings(adev, new_ps);
1938 kv_unforce_levels(adev);
1939 kv_set_enabled_levels(adev);
1940 kv_force_lowest_valid(adev);
1941 kv_unforce_levels(adev);
1943 ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1945 DRM_ERROR("kv_update_vce_dpm failed\n");
1948 kv_update_sclk_t(adev);
1949 if (adev->asic_type == CHIP_MULLINS)
1950 kv_enable_nb_dpm(adev, true);
1953 if (pi->enable_dpm) {
1954 kv_set_valid_clock_range(adev, new_ps);
1955 kv_update_dfs_bypass_settings(adev, new_ps);
1956 ret = kv_calculate_ds_divider(adev);
1958 DRM_ERROR("kv_calculate_ds_divider failed\n");
1961 kv_calculate_nbps_level_settings(adev);
1962 kv_calculate_dpm_settings(adev);
1963 kv_freeze_sclk_dpm(adev, true);
1964 kv_upload_dpm_settings(adev);
1965 kv_program_nbps_index_settings(adev, new_ps);
1966 kv_freeze_sclk_dpm(adev, false);
1967 kv_set_enabled_levels(adev);
1968 ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1970 DRM_ERROR("kv_update_vce_dpm failed\n");
1973 kv_update_acp_boot_level(adev);
1974 kv_update_sclk_t(adev);
1975 kv_enable_nb_dpm(adev, true);
1982 static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)
1984 struct kv_power_info *pi = kv_get_pi(adev);
1985 struct amdgpu_ps *new_ps = &pi->requested_rps;
1987 kv_update_current_ps(adev, new_ps);
1990 static void kv_dpm_setup_asic(struct amdgpu_device *adev)
1992 sumo_take_smu_control(adev, true);
1993 kv_init_powergate_state(adev);
1994 kv_init_sclk_t(adev);
1998 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2000 struct kv_power_info *pi = kv_get_pi(adev);
2002 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2003 kv_force_lowest_valid(adev);
2004 kv_init_graphics_levels(adev);
2005 kv_program_bootup_state(adev);
2006 kv_upload_dpm_settings(adev);
2007 kv_force_lowest_valid(adev);
2008 kv_unforce_levels(adev);
2010 kv_init_graphics_levels(adev);
2011 kv_program_bootup_state(adev);
2012 kv_freeze_sclk_dpm(adev, true);
2013 kv_upload_dpm_settings(adev);
2014 kv_freeze_sclk_dpm(adev, false);
2015 kv_set_enabled_level(adev, pi->graphics_boot_level);
2020 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
2021 struct amdgpu_clock_and_voltage_limits *table)
2023 struct kv_power_info *pi = kv_get_pi(adev);
2025 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
2026 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
2028 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
2030 kv_convert_2bit_index_to_voltage(adev,
2031 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
2034 table->mclk = pi->sys_info.nbp_memory_clock[0];
2037 static void kv_patch_voltage_values(struct amdgpu_device *adev)
2040 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
2041 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
2042 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
2043 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2044 struct amdgpu_clock_voltage_dependency_table *samu_table =
2045 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
2046 struct amdgpu_clock_voltage_dependency_table *acp_table =
2047 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
2049 if (uvd_table->count) {
2050 for (i = 0; i < uvd_table->count; i++)
2051 uvd_table->entries[i].v =
2052 kv_convert_8bit_index_to_voltage(adev,
2053 uvd_table->entries[i].v);
2056 if (vce_table->count) {
2057 for (i = 0; i < vce_table->count; i++)
2058 vce_table->entries[i].v =
2059 kv_convert_8bit_index_to_voltage(adev,
2060 vce_table->entries[i].v);
2063 if (samu_table->count) {
2064 for (i = 0; i < samu_table->count; i++)
2065 samu_table->entries[i].v =
2066 kv_convert_8bit_index_to_voltage(adev,
2067 samu_table->entries[i].v);
2070 if (acp_table->count) {
2071 for (i = 0; i < acp_table->count; i++)
2072 acp_table->entries[i].v =
2073 kv_convert_8bit_index_to_voltage(adev,
2074 acp_table->entries[i].v);
2079 static void kv_construct_boot_state(struct amdgpu_device *adev)
2081 struct kv_power_info *pi = kv_get_pi(adev);
2083 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2084 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2085 pi->boot_pl.ds_divider_index = 0;
2086 pi->boot_pl.ss_divider_index = 0;
2087 pi->boot_pl.allow_gnb_slow = 1;
2088 pi->boot_pl.force_nbp_state = 0;
2089 pi->boot_pl.display_wm = 0;
2090 pi->boot_pl.vce_wm = 0;
2093 static int kv_force_dpm_highest(struct amdgpu_device *adev)
2098 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2102 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
2103 if (enable_mask & (1 << i))
2107 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2108 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2110 return kv_set_enabled_level(adev, i);
2113 static int kv_force_dpm_lowest(struct amdgpu_device *adev)
2118 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2122 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2123 if (enable_mask & (1 << i))
2127 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2128 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2130 return kv_set_enabled_level(adev, i);
2133 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2134 u32 sclk, u32 min_sclk_in_sr)
2136 struct kv_power_info *pi = kv_get_pi(adev);
2139 u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);
2144 if (!pi->caps_sclk_ds)
2147 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2156 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
2158 struct kv_power_info *pi = kv_get_pi(adev);
2159 struct amdgpu_clock_voltage_dependency_table *table =
2160 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2163 if (table && table->count) {
2164 for (i = table->count - 1; i >= 0; i--) {
2165 if (pi->high_voltage_t &&
2166 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
2167 pi->high_voltage_t)) {
2173 struct sumo_sclk_voltage_mapping_table *table =
2174 &pi->sys_info.sclk_voltage_mapping_table;
2176 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2177 if (pi->high_voltage_t &&
2178 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
2179 pi->high_voltage_t)) {
2190 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
2191 struct amdgpu_ps *new_rps,
2192 struct amdgpu_ps *old_rps)
2194 struct kv_ps *ps = kv_get_ps(new_rps);
2195 struct kv_power_info *pi = kv_get_pi(adev);
2196 u32 min_sclk = 10000; /* ??? */
2200 struct amdgpu_clock_voltage_dependency_table *table =
2201 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2202 u32 stable_p_state_sclk = 0;
2203 struct amdgpu_clock_and_voltage_limits *max_limits =
2204 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2206 if (new_rps->vce_active) {
2207 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
2208 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
2214 mclk = max_limits->mclk;
2217 if (pi->caps_stable_p_state) {
2218 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2220 for (i = table->count - 1; i >= 0; i--) {
2221 if (stable_p_state_sclk >= table->entries[i].clk) {
2222 stable_p_state_sclk = table->entries[i].clk;
2228 stable_p_state_sclk = table->entries[0].clk;
2230 sclk = stable_p_state_sclk;
2233 if (new_rps->vce_active) {
2234 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
2235 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
2238 ps->need_dfs_bypass = true;
2240 for (i = 0; i < ps->num_levels; i++) {
2241 if (ps->levels[i].sclk < sclk)
2242 ps->levels[i].sclk = sclk;
2245 if (table && table->count) {
2246 for (i = 0; i < ps->num_levels; i++) {
2247 if (pi->high_voltage_t &&
2248 (pi->high_voltage_t <
2249 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2250 kv_get_high_voltage_limit(adev, &limit);
2251 ps->levels[i].sclk = table->entries[limit].clk;
2255 struct sumo_sclk_voltage_mapping_table *table =
2256 &pi->sys_info.sclk_voltage_mapping_table;
2258 for (i = 0; i < ps->num_levels; i++) {
2259 if (pi->high_voltage_t &&
2260 (pi->high_voltage_t <
2261 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2262 kv_get_high_voltage_limit(adev, &limit);
2263 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2268 if (pi->caps_stable_p_state) {
2269 for (i = 0; i < ps->num_levels; i++) {
2270 ps->levels[i].sclk = stable_p_state_sclk;
2274 pi->video_start = new_rps->dclk || new_rps->vclk ||
2275 new_rps->evclk || new_rps->ecclk;
2277 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2278 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2279 pi->battery_state = true;
2281 pi->battery_state = false;
2283 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2284 ps->dpm0_pg_nb_ps_lo = 0x1;
2285 ps->dpm0_pg_nb_ps_hi = 0x0;
2286 ps->dpmx_nb_ps_lo = 0x1;
2287 ps->dpmx_nb_ps_hi = 0x0;
2289 ps->dpm0_pg_nb_ps_lo = 0x3;
2290 ps->dpm0_pg_nb_ps_hi = 0x0;
2291 ps->dpmx_nb_ps_lo = 0x3;
2292 ps->dpmx_nb_ps_hi = 0x0;
2294 if (pi->sys_info.nb_dpm_enable) {
2295 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2296 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
2297 pi->disable_nb_ps3_in_battery;
2298 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2299 ps->dpm0_pg_nb_ps_hi = 0x2;
2300 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2301 ps->dpmx_nb_ps_hi = 0x2;
2306 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
2307 u32 index, bool enable)
2309 struct kv_power_info *pi = kv_get_pi(adev);
2311 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2314 static int kv_calculate_ds_divider(struct amdgpu_device *adev)
2316 struct kv_power_info *pi = kv_get_pi(adev);
2317 u32 sclk_in_sr = 10000; /* ??? */
2320 if (pi->lowest_valid > pi->highest_valid)
2323 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2324 pi->graphics_level[i].DeepSleepDivId =
2325 kv_get_sleep_divider_id_from_clock(adev,
2326 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2332 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
2334 struct kv_power_info *pi = kv_get_pi(adev);
2337 struct amdgpu_clock_and_voltage_limits *max_limits =
2338 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2339 u32 mclk = max_limits->mclk;
2341 if (pi->lowest_valid > pi->highest_valid)
2344 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2345 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2346 pi->graphics_level[i].GnbSlow = 1;
2347 pi->graphics_level[i].ForceNbPs1 = 0;
2348 pi->graphics_level[i].UpH = 0;
2351 if (!pi->sys_info.nb_dpm_enable)
2354 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2355 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2358 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2359 pi->graphics_level[i].GnbSlow = 0;
2361 if (pi->battery_state)
2362 pi->graphics_level[0].ForceNbPs1 = 1;
2364 pi->graphics_level[1].GnbSlow = 0;
2365 pi->graphics_level[2].GnbSlow = 0;
2366 pi->graphics_level[3].GnbSlow = 0;
2367 pi->graphics_level[4].GnbSlow = 0;
2370 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2371 pi->graphics_level[i].GnbSlow = 1;
2372 pi->graphics_level[i].ForceNbPs1 = 0;
2373 pi->graphics_level[i].UpH = 0;
2376 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2377 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2378 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2379 if (pi->lowest_valid != pi->highest_valid)
2380 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2386 static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
2388 struct kv_power_info *pi = kv_get_pi(adev);
2391 if (pi->lowest_valid > pi->highest_valid)
2394 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2395 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2400 static void kv_init_graphics_levels(struct amdgpu_device *adev)
2402 struct kv_power_info *pi = kv_get_pi(adev);
2404 struct amdgpu_clock_voltage_dependency_table *table =
2405 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2407 if (table && table->count) {
2410 pi->graphics_dpm_level_count = 0;
2411 for (i = 0; i < table->count; i++) {
2412 if (pi->high_voltage_t &&
2413 (pi->high_voltage_t <
2414 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
2417 kv_set_divider_value(adev, i, table->entries[i].clk);
2418 vid_2bit = kv_convert_vid7_to_vid2(adev,
2419 &pi->sys_info.vid_mapping_table,
2420 table->entries[i].v);
2421 kv_set_vid(adev, i, vid_2bit);
2422 kv_set_at(adev, i, pi->at[i]);
2423 kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2424 pi->graphics_dpm_level_count++;
2427 struct sumo_sclk_voltage_mapping_table *table =
2428 &pi->sys_info.sclk_voltage_mapping_table;
2430 pi->graphics_dpm_level_count = 0;
2431 for (i = 0; i < table->num_max_dpm_entries; i++) {
2432 if (pi->high_voltage_t &&
2433 pi->high_voltage_t <
2434 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
2437 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
2438 kv_set_vid(adev, i, table->entries[i].vid_2bit);
2439 kv_set_at(adev, i, pi->at[i]);
2440 kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2441 pi->graphics_dpm_level_count++;
2445 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2446 kv_dpm_power_level_enable(adev, i, false);
2449 static void kv_enable_new_levels(struct amdgpu_device *adev)
2451 struct kv_power_info *pi = kv_get_pi(adev);
2454 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2455 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2456 kv_dpm_power_level_enable(adev, i, true);
2460 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
2462 u32 new_mask = (1 << level);
2464 return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2465 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2469 static int kv_set_enabled_levels(struct amdgpu_device *adev)
2471 struct kv_power_info *pi = kv_get_pi(adev);
2472 u32 i, new_mask = 0;
2474 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2475 new_mask |= (1 << i);
2477 return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2478 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2482 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
2483 struct amdgpu_ps *new_rps)
2485 struct kv_ps *new_ps = kv_get_ps(new_rps);
2486 struct kv_power_info *pi = kv_get_pi(adev);
2489 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2492 if (pi->sys_info.nb_dpm_enable) {
2493 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2494 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
2495 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
2496 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
2497 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
2498 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
2499 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
2500 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
2501 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
2502 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
2506 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
2507 int min_temp, int max_temp)
2509 int low_temp = 0 * 1000;
2510 int high_temp = 255 * 1000;
2513 if (low_temp < min_temp)
2514 low_temp = min_temp;
2515 if (high_temp > max_temp)
2516 high_temp = max_temp;
2517 if (high_temp < low_temp) {
2518 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2522 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2523 tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
2524 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
2525 tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
2526 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
2527 WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
2529 adev->pm.dpm.thermal.min_temp = low_temp;
2530 adev->pm.dpm.thermal.max_temp = high_temp;
2536 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2537 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2538 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2539 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2540 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2541 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2544 static int kv_parse_sys_info_table(struct amdgpu_device *adev)
2546 struct kv_power_info *pi = kv_get_pi(adev);
2547 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2548 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2549 union igp_info *igp_info;
2554 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2555 &frev, &crev, &data_offset)) {
2556 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2560 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2563 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2564 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2565 pi->sys_info.bootup_nb_voltage_index =
2566 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2567 if (igp_info->info_8.ucHtcTmpLmt == 0)
2568 pi->sys_info.htc_tmp_lmt = 203;
2570 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2571 if (igp_info->info_8.ucHtcHystLmt == 0)
2572 pi->sys_info.htc_hyst_lmt = 5;
2574 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2575 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2576 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2579 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2580 pi->sys_info.nb_dpm_enable = true;
2582 pi->sys_info.nb_dpm_enable = false;
2584 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2585 pi->sys_info.nbp_memory_clock[i] =
2586 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2587 pi->sys_info.nbp_n_clock[i] =
2588 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2590 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2591 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2592 pi->caps_enable_dfs_bypass = true;
2594 sumo_construct_sclk_voltage_mapping_table(adev,
2595 &pi->sys_info.sclk_voltage_mapping_table,
2596 igp_info->info_8.sAvail_SCLK);
2598 sumo_construct_vid_mapping_table(adev,
2599 &pi->sys_info.vid_mapping_table,
2600 igp_info->info_8.sAvail_SCLK);
2602 kv_construct_max_power_limits_table(adev,
2603 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2609 struct _ATOM_POWERPLAY_INFO info;
2610 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2611 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2612 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2613 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2614 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2617 union pplib_clock_info {
2618 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2619 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2620 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2621 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2624 union pplib_power_state {
2625 struct _ATOM_PPLIB_STATE v1;
2626 struct _ATOM_PPLIB_STATE_V2 v2;
2629 static void kv_patch_boot_state(struct amdgpu_device *adev,
2632 struct kv_power_info *pi = kv_get_pi(adev);
2635 ps->levels[0] = pi->boot_pl;
2638 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
2639 struct amdgpu_ps *rps,
2640 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2643 struct kv_ps *ps = kv_get_ps(rps);
2645 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2646 rps->class = le16_to_cpu(non_clock_info->usClassification);
2647 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2649 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2650 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2651 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2657 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2658 adev->pm.dpm.boot_ps = rps;
2659 kv_patch_boot_state(adev, ps);
2661 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2662 adev->pm.dpm.uvd_ps = rps;
2665 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
2666 struct amdgpu_ps *rps, int index,
2667 union pplib_clock_info *clock_info)
2669 struct kv_power_info *pi = kv_get_pi(adev);
2670 struct kv_ps *ps = kv_get_ps(rps);
2671 struct kv_pl *pl = &ps->levels[index];
2674 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2675 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2677 pl->vddc_index = clock_info->sumo.vddcIndex;
2679 ps->num_levels = index + 1;
2681 if (pi->caps_sclk_ds) {
2682 pl->ds_divider_index = 5;
2683 pl->ss_divider_index = 5;
2687 static int kv_parse_power_table(struct amdgpu_device *adev)
2689 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2690 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2691 union pplib_power_state *power_state;
2692 int i, j, k, non_clock_array_index, clock_array_index;
2693 union pplib_clock_info *clock_info;
2694 struct _StateArray *state_array;
2695 struct _ClockInfoArray *clock_info_array;
2696 struct _NonClockInfoArray *non_clock_info_array;
2697 union power_info *power_info;
2698 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2701 u8 *power_state_offset;
2704 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2705 &frev, &crev, &data_offset))
2707 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2709 amdgpu_add_thermal_controller(adev);
2711 state_array = (struct _StateArray *)
2712 (mode_info->atom_context->bios + data_offset +
2713 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2714 clock_info_array = (struct _ClockInfoArray *)
2715 (mode_info->atom_context->bios + data_offset +
2716 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2717 non_clock_info_array = (struct _NonClockInfoArray *)
2718 (mode_info->atom_context->bios + data_offset +
2719 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2721 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
2722 state_array->ucNumEntries, GFP_KERNEL);
2723 if (!adev->pm.dpm.ps)
2725 power_state_offset = (u8 *)state_array->states;
2726 for (i = 0; i < state_array->ucNumEntries; i++) {
2728 power_state = (union pplib_power_state *)power_state_offset;
2729 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2730 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2731 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2732 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2734 kfree(adev->pm.dpm.ps);
2737 adev->pm.dpm.ps[i].ps_priv = ps;
2739 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2740 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2741 clock_array_index = idx[j];
2742 if (clock_array_index >= clock_info_array->ucNumEntries)
2744 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2746 clock_info = (union pplib_clock_info *)
2747 ((u8 *)&clock_info_array->clockInfo[0] +
2748 (clock_array_index * clock_info_array->ucEntrySize));
2749 kv_parse_pplib_clock_info(adev,
2750 &adev->pm.dpm.ps[i], k,
2754 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
2756 non_clock_info_array->ucEntrySize);
2757 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2759 adev->pm.dpm.num_ps = state_array->ucNumEntries;
2761 /* fill in the vce power states */
2762 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
2764 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
2765 clock_info = (union pplib_clock_info *)
2766 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2767 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2768 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2769 adev->pm.dpm.vce_states[i].sclk = sclk;
2770 adev->pm.dpm.vce_states[i].mclk = 0;
2776 static int kv_dpm_init(struct amdgpu_device *adev)
2778 struct kv_power_info *pi;
2781 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2784 adev->pm.dpm.priv = pi;
2786 ret = amdgpu_get_platform_caps(adev);
2790 ret = amdgpu_parse_extended_power_table(adev);
2794 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2795 pi->at[i] = TRINITY_AT_DFLT;
2797 pi->sram_end = SMC_RAM_END;
2799 pi->enable_nb_dpm = true;
2801 pi->caps_power_containment = true;
2802 pi->caps_cac = true;
2803 pi->enable_didt = false;
2804 if (pi->enable_didt) {
2805 pi->caps_sq_ramping = true;
2806 pi->caps_db_ramping = true;
2807 pi->caps_td_ramping = true;
2808 pi->caps_tcp_ramping = true;
2811 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
2812 pi->caps_sclk_ds = true;
2814 pi->caps_sclk_ds = false;
2816 pi->enable_auto_thermal_throttling = true;
2817 pi->disable_nb_ps3_in_battery = false;
2818 if (amdgpu_bapm == 0)
2819 pi->bapm_enable = false;
2821 pi->bapm_enable = true;
2822 pi->voltage_drop_t = 0;
2823 pi->caps_sclk_throttle_low_notification = false;
2824 pi->caps_fps = false; /* true? */
2825 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2826 pi->caps_uvd_dpm = true;
2827 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2828 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2829 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2830 pi->caps_stable_p_state = false;
2832 ret = kv_parse_sys_info_table(adev);
2836 kv_patch_voltage_values(adev);
2837 kv_construct_boot_state(adev);
2839 ret = kv_parse_power_table(adev);
2843 pi->enable_dpm = true;
2849 kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
2852 struct kv_power_info *pi = kv_get_pi(adev);
2854 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2855 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
2856 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
2860 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2861 seq_printf(m, "invalid dpm profile %d\n", current_index);
2863 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2864 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2865 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2866 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
2867 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
2868 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2869 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
2870 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
2871 current_index, sclk, vddc);
2876 kv_dpm_print_power_state(struct amdgpu_device *adev,
2877 struct amdgpu_ps *rps)
2880 struct kv_ps *ps = kv_get_ps(rps);
2882 amdgpu_dpm_print_class_info(rps->class, rps->class2);
2883 amdgpu_dpm_print_cap_info(rps->caps);
2884 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2885 for (i = 0; i < ps->num_levels; i++) {
2886 struct kv_pl *pl = &ps->levels[i];
2887 printk("\t\tpower level %d sclk: %u vddc: %u\n",
2889 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
2891 amdgpu_dpm_print_ps_status(adev, rps);
2894 static void kv_dpm_fini(struct amdgpu_device *adev)
2898 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2899 kfree(adev->pm.dpm.ps[i].ps_priv);
2901 kfree(adev->pm.dpm.ps);
2902 kfree(adev->pm.dpm.priv);
2903 amdgpu_free_extended_power_table(adev);
2906 static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev)
2911 static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
2913 struct kv_power_info *pi = kv_get_pi(adev);
2914 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2917 return requested_state->levels[0].sclk;
2919 return requested_state->levels[requested_state->num_levels - 1].sclk;
2922 static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low)
2924 struct kv_power_info *pi = kv_get_pi(adev);
2926 return pi->sys_info.bootup_uma_clk;
2929 /* get temperature in millidegrees */
2930 static int kv_dpm_get_temp(struct amdgpu_device *adev)
2933 int actual_temp = 0;
2935 temp = RREG32_SMC(0xC0300E0C);
2938 actual_temp = (temp / 8) - 49;
2942 actual_temp = actual_temp * 1000;
2947 static int kv_dpm_early_init(void *handle)
2949 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2951 kv_dpm_set_dpm_funcs(adev);
2952 kv_dpm_set_irq_funcs(adev);
2957 static int kv_dpm_late_init(void *handle)
2959 /* powerdown unused blocks for now */
2960 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2966 /* init the sysfs and debugfs files late */
2967 ret = amdgpu_pm_sysfs_init(adev);
2971 kv_dpm_powergate_acp(adev, true);
2972 kv_dpm_powergate_samu(adev, true);
2977 static int kv_dpm_sw_init(void *handle)
2980 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2982 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
2983 &adev->pm.dpm.thermal.irq);
2987 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
2988 &adev->pm.dpm.thermal.irq);
2992 /* default to balanced state */
2993 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
2994 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
2995 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
2996 adev->pm.default_sclk = adev->clock.default_sclk;
2997 adev->pm.default_mclk = adev->clock.default_mclk;
2998 adev->pm.current_sclk = adev->clock.default_sclk;
2999 adev->pm.current_mclk = adev->clock.default_mclk;
3000 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
3002 if (amdgpu_dpm == 0)
3005 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
3006 mutex_lock(&adev->pm.mutex);
3007 ret = kv_dpm_init(adev);
3010 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3011 if (amdgpu_dpm == 1)
3012 amdgpu_pm_print_power_states(adev);
3013 mutex_unlock(&adev->pm.mutex);
3014 DRM_INFO("amdgpu: dpm initialized\n");
3020 mutex_unlock(&adev->pm.mutex);
3021 DRM_ERROR("amdgpu: dpm initialization failed\n");
3025 static int kv_dpm_sw_fini(void *handle)
3027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3029 flush_work(&adev->pm.dpm.thermal.work);
3031 mutex_lock(&adev->pm.mutex);
3032 amdgpu_pm_sysfs_fini(adev);
3034 mutex_unlock(&adev->pm.mutex);
3039 static int kv_dpm_hw_init(void *handle)
3042 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3047 mutex_lock(&adev->pm.mutex);
3048 kv_dpm_setup_asic(adev);
3049 ret = kv_dpm_enable(adev);
3051 adev->pm.dpm_enabled = false;
3053 adev->pm.dpm_enabled = true;
3054 mutex_unlock(&adev->pm.mutex);
3055 amdgpu_pm_compute_clocks(adev);
3059 static int kv_dpm_hw_fini(void *handle)
3061 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3063 if (adev->pm.dpm_enabled) {
3064 mutex_lock(&adev->pm.mutex);
3065 kv_dpm_disable(adev);
3066 mutex_unlock(&adev->pm.mutex);
3072 static int kv_dpm_suspend(void *handle)
3074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3076 if (adev->pm.dpm_enabled) {
3077 mutex_lock(&adev->pm.mutex);
3079 kv_dpm_disable(adev);
3080 /* reset the power state */
3081 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3082 mutex_unlock(&adev->pm.mutex);
3087 static int kv_dpm_resume(void *handle)
3090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3092 if (adev->pm.dpm_enabled) {
3093 /* asic init will reset to the boot state */
3094 mutex_lock(&adev->pm.mutex);
3095 kv_dpm_setup_asic(adev);
3096 ret = kv_dpm_enable(adev);
3098 adev->pm.dpm_enabled = false;
3100 adev->pm.dpm_enabled = true;
3101 mutex_unlock(&adev->pm.mutex);
3102 if (adev->pm.dpm_enabled)
3103 amdgpu_pm_compute_clocks(adev);
3108 static bool kv_dpm_is_idle(void *handle)
3113 static int kv_dpm_wait_for_idle(void *handle)
3119 static int kv_dpm_soft_reset(void *handle)
3124 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
3125 struct amdgpu_irq_src *src,
3127 enum amdgpu_interrupt_state state)
3132 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
3134 case AMDGPU_IRQ_STATE_DISABLE:
3135 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3136 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3137 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3139 case AMDGPU_IRQ_STATE_ENABLE:
3140 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3141 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3142 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3149 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
3151 case AMDGPU_IRQ_STATE_DISABLE:
3152 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3153 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3154 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3156 case AMDGPU_IRQ_STATE_ENABLE:
3157 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3158 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3159 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3172 static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
3173 struct amdgpu_irq_src *source,
3174 struct amdgpu_iv_entry *entry)
3176 bool queue_thermal = false;
3181 switch (entry->src_id) {
3182 case 230: /* thermal low to high */
3183 DRM_DEBUG("IH: thermal low to high\n");
3184 adev->pm.dpm.thermal.high_to_low = false;
3185 queue_thermal = true;
3187 case 231: /* thermal high to low */
3188 DRM_DEBUG("IH: thermal high to low\n");
3189 adev->pm.dpm.thermal.high_to_low = true;
3190 queue_thermal = true;
3197 schedule_work(&adev->pm.dpm.thermal.work);
3202 static int kv_dpm_set_clockgating_state(void *handle,
3203 enum amd_clockgating_state state)
3208 static int kv_dpm_set_powergating_state(void *handle,
3209 enum amd_powergating_state state)
3214 static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
3215 const struct kv_pl *kv_cpl2)
3217 return ((kv_cpl1->sclk == kv_cpl2->sclk) &&
3218 (kv_cpl1->vddc_index == kv_cpl2->vddc_index) &&
3219 (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) &&
3220 (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
3223 static int kv_check_state_equal(struct amdgpu_device *adev,
3224 struct amdgpu_ps *cps,
3225 struct amdgpu_ps *rps,
3228 struct kv_ps *kv_cps;
3229 struct kv_ps *kv_rps;
3232 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
3235 kv_cps = kv_get_ps(cps);
3236 kv_rps = kv_get_ps(rps);
3238 if (kv_cps == NULL) {
3243 if (kv_cps->num_levels != kv_rps->num_levels) {
3248 for (i = 0; i < kv_cps->num_levels; i++) {
3249 if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
3250 &(kv_rps->levels[i]))) {
3256 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
3257 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
3258 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
3263 static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx,
3264 void *value, int *size)
3266 struct kv_power_info *pi = kv_get_pi(adev);
3269 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
3270 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
3271 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
3273 /* size must be at least 4 bytes for all sensors */
3278 case AMDGPU_PP_SENSOR_GFX_SCLK:
3279 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
3281 pi->graphics_level[pl_index].SclkFrequency);
3282 *((uint32_t *)value) = sclk;
3287 case AMDGPU_PP_SENSOR_GPU_TEMP:
3288 *((uint32_t *)value) = kv_dpm_get_temp(adev);
3296 const struct amd_ip_funcs kv_dpm_ip_funcs = {
3298 .early_init = kv_dpm_early_init,
3299 .late_init = kv_dpm_late_init,
3300 .sw_init = kv_dpm_sw_init,
3301 .sw_fini = kv_dpm_sw_fini,
3302 .hw_init = kv_dpm_hw_init,
3303 .hw_fini = kv_dpm_hw_fini,
3304 .suspend = kv_dpm_suspend,
3305 .resume = kv_dpm_resume,
3306 .is_idle = kv_dpm_is_idle,
3307 .wait_for_idle = kv_dpm_wait_for_idle,
3308 .soft_reset = kv_dpm_soft_reset,
3309 .set_clockgating_state = kv_dpm_set_clockgating_state,
3310 .set_powergating_state = kv_dpm_set_powergating_state,
3313 static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
3314 .get_temperature = &kv_dpm_get_temp,
3315 .pre_set_power_state = &kv_dpm_pre_set_power_state,
3316 .set_power_state = &kv_dpm_set_power_state,
3317 .post_set_power_state = &kv_dpm_post_set_power_state,
3318 .display_configuration_changed = &kv_dpm_display_configuration_changed,
3319 .get_sclk = &kv_dpm_get_sclk,
3320 .get_mclk = &kv_dpm_get_mclk,
3321 .print_power_state = &kv_dpm_print_power_state,
3322 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
3323 .force_performance_level = &kv_dpm_force_performance_level,
3324 .powergate_uvd = &kv_dpm_powergate_uvd,
3325 .enable_bapm = &kv_dpm_enable_bapm,
3326 .get_vce_clock_state = amdgpu_get_vce_clock_state,
3327 .check_state_equal = kv_check_state_equal,
3328 .read_sensor = &kv_dpm_read_sensor,
3331 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
3333 if (adev->pm.funcs == NULL)
3334 adev->pm.funcs = &kv_dpm_funcs;
3337 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
3338 .set = kv_dpm_set_interrupt_state,
3339 .process = kv_dpm_process_interrupt,
3342 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
3344 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
3345 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;