2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_atomfirmware.h"
28 #include "vega10/soc15ip.h"
29 #include "vega10/HDP/hdp_4_0_offset.h"
30 #include "vega10/HDP/hdp_4_0_sh_mask.h"
31 #include "vega10/GC/gc_9_0_sh_mask.h"
32 #include "vega10/DC/dce_12_0_offset.h"
33 #include "vega10/DC/dce_12_0_sh_mask.h"
34 #include "vega10/vega10_enum.h"
36 #include "soc15_common.h"
38 #include "nbio_v6_1.h"
39 #include "nbio_v7_0.h"
40 #include "gfxhub_v1_0.h"
41 #include "mmhub_v1_0.h"
43 #define mmDF_CS_AON0_DramBaseAddress0 0x0044
44 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
45 //DF_CS_AON0_DramBaseAddress0
46 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
47 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
48 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
49 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
50 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
51 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
52 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
53 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
54 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
55 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
57 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
58 #define AMDGPU_NUM_OF_VMIDS 8
60 static const u32 golden_settings_vega10_hdp[] =
62 0xf64, 0x0fffffff, 0x00000000,
63 0xf65, 0x0fffffff, 0x00000000,
64 0xf66, 0x0fffffff, 0x00000000,
65 0xf67, 0x0fffffff, 0x00000000,
66 0xf68, 0x0fffffff, 0x00000000,
67 0xf6a, 0x0fffffff, 0x00000000,
68 0xf6b, 0x0fffffff, 0x00000000,
69 0xf6c, 0x0fffffff, 0x00000000,
70 0xf6d, 0x0fffffff, 0x00000000,
71 0xf6e, 0x0fffffff, 0x00000000,
74 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
75 struct amdgpu_irq_src *src,
77 enum amdgpu_interrupt_state state)
79 struct amdgpu_vmhub *hub;
80 u32 tmp, reg, bits, i;
82 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
83 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
84 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
85 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
86 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
87 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
88 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
91 case AMDGPU_IRQ_STATE_DISABLE:
93 hub = &adev->vmhub[AMDGPU_MMHUB];
94 for (i = 0; i< 16; i++) {
95 reg = hub->vm_context0_cntl + i;
102 hub = &adev->vmhub[AMDGPU_GFXHUB];
103 for (i = 0; i < 16; i++) {
104 reg = hub->vm_context0_cntl + i;
110 case AMDGPU_IRQ_STATE_ENABLE:
112 hub = &adev->vmhub[AMDGPU_MMHUB];
113 for (i = 0; i< 16; i++) {
114 reg = hub->vm_context0_cntl + i;
121 hub = &adev->vmhub[AMDGPU_GFXHUB];
122 for (i = 0; i < 16; i++) {
123 reg = hub->vm_context0_cntl + i;
136 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
137 struct amdgpu_irq_src *source,
138 struct amdgpu_iv_entry *entry)
140 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
144 addr = (u64)entry->src_data[0] << 12;
145 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
147 if (!amdgpu_sriov_vf(adev)) {
148 status = RREG32(hub->vm_l2_pro_fault_status);
149 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
152 if (printk_ratelimit()) {
154 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
155 entry->vm_id_src ? "mmhub" : "gfxhub",
156 entry->src_id, entry->ring_id, entry->vm_id,
158 dev_err(adev->dev, " at page 0x%016llx from %d\n",
159 addr, entry->client_id);
160 if (!amdgpu_sriov_vf(adev))
162 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
169 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
170 .set = gmc_v9_0_vm_fault_interrupt_state,
171 .process = gmc_v9_0_process_interrupt,
174 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
176 adev->mc.vm_fault.num_types = 1;
177 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
180 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
184 /* invalidate using legacy mode on vm_id*/
185 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
186 PER_VMID_INVALIDATE_REQ, 1 << vm_id);
187 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
188 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
189 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
190 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
191 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
192 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
193 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
194 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
201 * VMID 0 is the physical GPU addresses as used by the kernel.
202 * VMIDs 1-15 are used for userspace clients and are handled
203 * by the amdgpu vm/hsa code.
207 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
209 * @adev: amdgpu_device pointer
210 * @vmid: vm instance to flush
212 * Flush the TLB for the requested page table.
214 static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
217 /* Use register 17 for GART */
218 const unsigned eng = 17;
221 /* flush hdp cache */
222 if (adev->flags & AMD_IS_APU)
223 nbio_v7_0_hdp_flush(adev);
225 nbio_v6_1_hdp_flush(adev);
227 spin_lock(&adev->mc.invalidate_lock);
229 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
230 struct amdgpu_vmhub *hub = &adev->vmhub[i];
231 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
233 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
235 /* Busy wait for ACK.*/
236 for (j = 0; j < 100; j++) {
237 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
246 /* Wait for ACK with a delay.*/
247 for (j = 0; j < adev->usec_timeout; j++) {
248 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
254 if (j < adev->usec_timeout)
257 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
260 spin_unlock(&adev->mc.invalidate_lock);
264 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
266 * @adev: amdgpu_device pointer
267 * @cpu_pt_addr: cpu address of the page table
268 * @gpu_page_idx: entry in the page table to update
269 * @addr: dst addr to write into pte/pde
270 * @flags: access flags
272 * Update the page tables using the CPU.
274 static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
276 uint32_t gpu_page_idx,
280 void __iomem *ptr = (void *)cpu_pt_addr;
284 * PTE format on VEGA 10:
293 * 47:12 4k physical page base address
303 * PDE format on VEGA 10:
304 * 63:59 block fragment size
308 * 47:6 physical base address of PD or PTE
316 * The following is for PTE only. GART does not have PDEs.
318 value = addr & 0x0000FFFFFFFFF000ULL;
320 writeq(value, ptr + (gpu_page_idx * 8));
324 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
328 uint64_t pte_flag = 0;
330 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
331 pte_flag |= AMDGPU_PTE_EXECUTABLE;
332 if (flags & AMDGPU_VM_PAGE_READABLE)
333 pte_flag |= AMDGPU_PTE_READABLE;
334 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
335 pte_flag |= AMDGPU_PTE_WRITEABLE;
337 switch (flags & AMDGPU_VM_MTYPE_MASK) {
338 case AMDGPU_VM_MTYPE_DEFAULT:
339 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
341 case AMDGPU_VM_MTYPE_NC:
342 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
344 case AMDGPU_VM_MTYPE_WC:
345 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
347 case AMDGPU_VM_MTYPE_CC:
348 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
350 case AMDGPU_VM_MTYPE_UC:
351 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
354 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
358 if (flags & AMDGPU_VM_PAGE_PRT)
359 pte_flag |= AMDGPU_PTE_PRT;
364 static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
366 addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
367 BUG_ON(addr & 0xFFFF00000000003FULL);
371 static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
372 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
373 .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
374 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
375 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
376 .get_vm_pde = gmc_v9_0_get_vm_pde
379 static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
381 if (adev->gart.gart_funcs == NULL)
382 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
385 static int gmc_v9_0_early_init(void *handle)
387 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
389 gmc_v9_0_set_gart_funcs(adev);
390 gmc_v9_0_set_irq_funcs(adev);
395 static int gmc_v9_0_late_init(void *handle)
397 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
399 * The latest engine allocation on gfx9 is:
401 * Engine 2, 3: firmware
402 * Engine 4~13: amdgpu ring, subject to change when ring number changes
404 * Engine 16: kfd tlb invalidation
405 * Engine 17: Gart flushes
407 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
410 for(i = 0; i < adev->num_rings; ++i) {
411 struct amdgpu_ring *ring = adev->rings[i];
412 unsigned vmhub = ring->funcs->vmhub;
414 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
415 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
416 ring->idx, ring->name, ring->vm_inv_eng,
420 /* Engine 16 is used for KFD and 17 for GART flushes */
421 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
422 BUG_ON(vm_inv_eng[i] > 16);
424 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
427 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
428 struct amdgpu_mc *mc)
431 if (!amdgpu_sriov_vf(adev))
432 base = mmhub_v1_0_get_fb_location(adev);
433 amdgpu_vram_location(adev, &adev->mc, base);
434 amdgpu_gart_location(adev, mc);
435 /* base offset of vram pages */
436 if (adev->flags & AMD_IS_APU)
437 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
439 adev->vm_manager.vram_base_offset = 0;
443 * gmc_v9_0_mc_init - initialize the memory controller driver params
445 * @adev: amdgpu_device pointer
447 * Look up the amount of vram, vram width, and decide how to place
448 * vram and gart within the GPU's physical address space.
449 * Returns 0 for success.
451 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
454 int chansize, numchan;
456 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
457 if (!adev->mc.vram_width) {
458 /* hbm memory channel size */
459 if (adev->flags & AMD_IS_APU)
464 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
465 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
466 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
497 adev->mc.vram_width = numchan * chansize;
500 /* Could aper size report 0 ? */
501 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
502 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
503 /* size in MB on si */
504 adev->mc.mc_vram_size =
505 ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
506 nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
507 adev->mc.real_vram_size = adev->mc.mc_vram_size;
508 adev->mc.visible_vram_size = adev->mc.aper_size;
510 /* In case the PCI BAR is larger than the actual amount of vram */
511 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
512 adev->mc.visible_vram_size = adev->mc.real_vram_size;
514 /* set the gart size */
515 if (amdgpu_gart_size == -1) {
516 switch (adev->asic_type) {
517 case CHIP_VEGA10: /* all engines support GPUVM */
519 adev->mc.gart_size = 256ULL << 20;
521 case CHIP_RAVEN: /* DCE SG support */
522 adev->mc.gart_size = 1024ULL << 20;
526 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
529 gmc_v9_0_vram_gtt_location(adev, &adev->mc);
534 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
538 if (adev->gart.robj) {
539 WARN(1, "VEGA10 PCIE GART already initialized\n");
542 /* Initialize common gart structure */
543 r = amdgpu_gart_init(adev);
546 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
547 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
548 AMDGPU_PTE_EXECUTABLE;
549 return amdgpu_gart_table_vram_alloc(adev);
552 static int gmc_v9_0_sw_init(void *handle)
556 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
558 gfxhub_v1_0_init(adev);
559 mmhub_v1_0_init(adev);
561 spin_lock_init(&adev->mc.invalidate_lock);
563 switch (adev->asic_type) {
565 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
566 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
567 adev->vm_manager.vm_size = 1U << 18;
568 adev->vm_manager.block_size = 9;
569 adev->vm_manager.num_level = 3;
570 amdgpu_vm_set_fragment_size(adev, 9);
572 /* vm_size is 64GB for legacy 2-level page support */
573 amdgpu_vm_adjust_size(adev, 64, 9);
574 adev->vm_manager.num_level = 1;
578 /* XXX Don't know how to get VRAM type yet. */
579 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
581 * To fulfill 4-level page support,
582 * vm size is 256TB (48bit), maximum size of Vega10,
583 * block size 512 (9bit)
585 adev->vm_manager.vm_size = 1U << 18;
586 adev->vm_manager.block_size = 9;
587 adev->vm_manager.num_level = 3;
588 amdgpu_vm_set_fragment_size(adev, 9);
594 DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
595 adev->vm_manager.vm_size,
596 adev->vm_manager.block_size,
597 adev->vm_manager.fragment_size);
599 /* This interrupt is VMC page fault.*/
600 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
602 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
608 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
610 /* Set the internal MC address mask
611 * This is the max address of the GPU's
612 * internal address space.
614 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
617 * It needs to reserve 8M stolen memory for vega10
618 * TODO: Figure out how to avoid that...
620 adev->mc.stolen_size = 8 * 1024 * 1024;
622 /* set DMA mask + need_dma32 flags.
623 * PCIE - can handle 44-bits.
624 * IGP - can handle 44-bits
625 * PCI - dma32 for legacy pci gart, 44 bits on vega10
627 adev->need_dma32 = false;
628 dma_bits = adev->need_dma32 ? 32 : 44;
629 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
631 adev->need_dma32 = true;
633 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
635 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
637 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
638 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
641 r = gmc_v9_0_mc_init(adev);
646 r = amdgpu_bo_init(adev);
650 r = gmc_v9_0_gart_init(adev);
656 * VMID 0 is reserved for System
657 * amdgpu graphics/compute will use VMIDs 1-7
658 * amdkfd will use VMIDs 8-15
660 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
661 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
663 amdgpu_vm_manager_init(adev);
669 * gmc_v8_0_gart_fini - vm fini callback
671 * @adev: amdgpu_device pointer
673 * Tears down the driver GART/VM setup (CIK).
675 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
677 amdgpu_gart_table_vram_free(adev);
678 amdgpu_gart_fini(adev);
681 static int gmc_v9_0_sw_fini(void *handle)
683 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
685 amdgpu_vm_manager_fini(adev);
686 gmc_v9_0_gart_fini(adev);
687 amdgpu_gem_force_release(adev);
688 amdgpu_bo_fini(adev);
693 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
695 switch (adev->asic_type) {
706 * gmc_v9_0_gart_enable - gart enable
708 * @adev: amdgpu_device pointer
710 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
716 amdgpu_program_register_sequence(adev,
717 golden_settings_vega10_hdp,
718 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
720 if (adev->gart.robj == NULL) {
721 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
724 r = amdgpu_gart_table_vram_pin(adev);
728 /* After HDP is initialized, flush HDP.*/
729 if (adev->flags & AMD_IS_APU)
730 nbio_v7_0_hdp_flush(adev);
732 nbio_v6_1_hdp_flush(adev);
734 switch (adev->asic_type) {
736 mmhub_v1_0_initialize_power_gating(adev);
737 mmhub_v1_0_update_power_gating(adev, true);
743 r = gfxhub_v1_0_gart_enable(adev);
747 r = mmhub_v1_0_gart_enable(adev);
751 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
752 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
753 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
755 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
756 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
759 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
764 gfxhub_v1_0_set_fault_enable_default(adev, value);
765 mmhub_v1_0_set_fault_enable_default(adev, value);
767 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
769 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
770 (unsigned)(adev->mc.gart_size >> 20),
771 (unsigned long long)adev->gart.table_addr);
772 adev->gart.ready = true;
776 static int gmc_v9_0_hw_init(void *handle)
779 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
781 /* The sequence of these two function calls matters.*/
782 gmc_v9_0_init_golden_registers(adev);
784 if (adev->mode_info.num_crtc) {
787 /* Lockout access through VGA aperture*/
788 tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL);
789 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
790 WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp);
792 /* disable VGA render */
793 tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL);
794 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
795 WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp);
798 r = gmc_v9_0_gart_enable(adev);
804 * gmc_v9_0_gart_disable - gart disable
806 * @adev: amdgpu_device pointer
808 * This disables all VM page table.
810 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
812 gfxhub_v1_0_gart_disable(adev);
813 mmhub_v1_0_gart_disable(adev);
814 amdgpu_gart_table_vram_unpin(adev);
817 static int gmc_v9_0_hw_fini(void *handle)
819 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
821 if (amdgpu_sriov_vf(adev)) {
822 /* full access mode, so don't touch any GMC register */
823 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
827 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
828 gmc_v9_0_gart_disable(adev);
833 static int gmc_v9_0_suspend(void *handle)
835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
837 gmc_v9_0_hw_fini(adev);
842 static int gmc_v9_0_resume(void *handle)
845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
847 r = gmc_v9_0_hw_init(adev);
851 amdgpu_vm_reset_all_ids(adev);
856 static bool gmc_v9_0_is_idle(void *handle)
858 /* MC is always ready in GMC v9.*/
862 static int gmc_v9_0_wait_for_idle(void *handle)
864 /* There is no need to wait for MC idle in GMC v9.*/
868 static int gmc_v9_0_soft_reset(void *handle)
870 /* XXX for emulation.*/
874 static int gmc_v9_0_set_clockgating_state(void *handle,
875 enum amd_clockgating_state state)
877 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
879 return mmhub_v1_0_set_clockgating(adev, state);
882 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
884 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
886 mmhub_v1_0_get_clockgating(adev, flags);
889 static int gmc_v9_0_set_powergating_state(void *handle,
890 enum amd_powergating_state state)
895 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
897 .early_init = gmc_v9_0_early_init,
898 .late_init = gmc_v9_0_late_init,
899 .sw_init = gmc_v9_0_sw_init,
900 .sw_fini = gmc_v9_0_sw_fini,
901 .hw_init = gmc_v9_0_hw_init,
902 .hw_fini = gmc_v9_0_hw_fini,
903 .suspend = gmc_v9_0_suspend,
904 .resume = gmc_v9_0_resume,
905 .is_idle = gmc_v9_0_is_idle,
906 .wait_for_idle = gmc_v9_0_wait_for_idle,
907 .soft_reset = gmc_v9_0_soft_reset,
908 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
909 .set_powergating_state = gmc_v9_0_set_powergating_state,
910 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
913 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
915 .type = AMD_IP_BLOCK_TYPE_GMC,
919 .funcs = &gmc_v9_0_ip_funcs,