drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_cache.h>
  26 #include "amdgpu.h"
  27 #include "gmc_v8_0.h"
  28 #include "amdgpu_ucode.h"
  29 #include "amdgpu_amdkfd.h"
  30
  31 #include "gmc/gmc_8_1_d.h"
  32 #include "gmc/gmc_8_1_sh_mask.h"
  33
  34 #include "bif/bif_5_0_d.h"
  35 #include "bif/bif_5_0_sh_mask.h"
  36
  37 #include "oss/oss_3_0_d.h"
  38 #include "oss/oss_3_0_sh_mask.h"
  39
  40 #include "dce/dce_10_0_d.h"
  41 #include "dce/dce_10_0_sh_mask.h"
  42
  43 #include "vid.h"
  44 #include "vi.h"
  45
  46 #include "amdgpu_atombios.h"
  47
  48 #include "ivsrcid/ivsrcid_vislands30.h"
  49
  50 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
  51 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  52 static int gmc_v8_0_wait_for_idle(void *handle);
  53
  54 /*(DEBLOBBED)*/
  55
  56 static const u32 golden_settings_tonga_a11[] =
  57 {
  58         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  59         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  60         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  61         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  62         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  63         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65 };
  66
  67 static const u32 tonga_mgcg_cgcg_init[] =
  68 {
  69         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  70 };
  71
  72 static const u32 golden_settings_fiji_a10[] =
  73 {
  74         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  76         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  77         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  78 };
  79
  80 static const u32 fiji_mgcg_cgcg_init[] =
  81 {
  82         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  83 };
  84
  85 static const u32 golden_settings_polaris11_a11[] =
  86 {
  87         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  88         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  89         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  91 };
  92
  93 static const u32 golden_settings_polaris10_a11[] =
  94 {
  95         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  96         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  97         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  98         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  99         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 100 };
 101
 102 static const u32 cz_mgcg_cgcg_init[] =
 103 {
 104         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 105 };
 106
 107 static const u32 stoney_mgcg_cgcg_init[] =
 108 {
 109         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 110         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 111 };
 112
 113 static const u32 golden_settings_stoney_common[] =
 114 {
 115         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 116         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 117 };
 118
 119 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 120 {
 121         switch (adev->asic_type) {
 122         case CHIP_FIJI:
 123                 amdgpu_device_program_register_sequence(adev,
 124                                                         fiji_mgcg_cgcg_init,
 125                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 126                 amdgpu_device_program_register_sequence(adev,
 127                                                         golden_settings_fiji_a10,
 128                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 129                 break;
 130         case CHIP_TONGA:
 131                 amdgpu_device_program_register_sequence(adev,
 132                                                         tonga_mgcg_cgcg_init,
 133                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 134                 amdgpu_device_program_register_sequence(adev,
 135                                                         golden_settings_tonga_a11,
 136                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 137                 break;
 138         case CHIP_POLARIS11:
 139         case CHIP_POLARIS12:
 140         case CHIP_VEGAM:
 141                 amdgpu_device_program_register_sequence(adev,
 142                                                         golden_settings_polaris11_a11,
 143                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 144                 break;
 145         case CHIP_POLARIS10:
 146                 amdgpu_device_program_register_sequence(adev,
 147                                                         golden_settings_polaris10_a11,
 148                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 149                 break;
 150         case CHIP_CARRIZO:
 151                 amdgpu_device_program_register_sequence(adev,
 152                                                         cz_mgcg_cgcg_init,
 153                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 154                 break;
 155         case CHIP_STONEY:
 156                 amdgpu_device_program_register_sequence(adev,
 157                                                         stoney_mgcg_cgcg_init,
 158                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 159                 amdgpu_device_program_register_sequence(adev,
 160                                                         golden_settings_stoney_common,
 161                                                         ARRAY_SIZE(golden_settings_stoney_common));
 162                 break;
 163         default:
 164                 break;
 165         }
 166 }
 167
 168 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 169 {
 170         u32 blackout;
 171
 172         gmc_v8_0_wait_for_idle(adev);
 173
 174         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 175         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 176                 /* Block CPU access */
 177                 WREG32(mmBIF_FB_EN, 0);
 178                 /* blackout the MC */
 179                 blackout = REG_SET_FIELD(blackout,
 180                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 181                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 182         }
 183         /* wait for the MC to settle */
 184         udelay(100);
 185 }
 186
 187 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 188 {
 189         u32 tmp;
 190
 191         /* unblackout the MC */
 192         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 193         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 194         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 195         /* allow CPU access */
 196         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 197         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 198         WREG32(mmBIF_FB_EN, tmp);
 199 }
 200
 201 /**
 202  * gmc_v8_0_init_microcode - load ucode images from disk
 203  *
 204  * @adev: amdgpu_device pointer
 205  *
 206  * Use the firmware interface to load the ucode images into
 207  * the driver (not loaded into hw).
 208  * Returns 0 on success, error on failure.
 209  */
 210 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 211 {
 212         const char *chip_name;
 213         char fw_name[30];
 214         int err;
 215
 216         DRM_DEBUG("\n");
 217
 218         switch (adev->asic_type) {
 219         case CHIP_TONGA:
 220                 chip_name = "tonga";
 221                 break;
 222         case CHIP_POLARIS11:
 223                 if (((adev->pdev->device == 0x67ef) &&
 224                      ((adev->pdev->revision == 0xe0) ||
 225                       (adev->pdev->revision == 0xe5))) ||
 226                     ((adev->pdev->device == 0x67ff) &&
 227                      ((adev->pdev->revision == 0xcf) ||
 228                       (adev->pdev->revision == 0xef) ||
 229                       (adev->pdev->revision == 0xff))))
 230                         chip_name = "polaris11_k";
 231                 else if ((adev->pdev->device == 0x67ef) &&
 232                          (adev->pdev->revision == 0xe2))
 233                         chip_name = "polaris11_k";
 234                 else
 235                         chip_name = "polaris11";
 236                 break;
 237         case CHIP_POLARIS10:
 238                 if ((adev->pdev->device == 0x67df) &&
 239                     ((adev->pdev->revision == 0xe1) ||
 240                      (adev->pdev->revision == 0xf7)))
 241                         chip_name = "polaris10_k";
 242                 else
 243                         chip_name = "polaris10";
 244                 break;
 245         case CHIP_POLARIS12:
 246                 if (((adev->pdev->device == 0x6987) &&
 247                      ((adev->pdev->revision == 0xc0) ||
 248                       (adev->pdev->revision == 0xc3))) ||
 249                     ((adev->pdev->device == 0x6981) &&
 250                      ((adev->pdev->revision == 0x00) ||
 251                       (adev->pdev->revision == 0x01) ||
 252                       (adev->pdev->revision == 0x10))))
 253                         chip_name = "polaris12_k";
 254                 else
 255                         chip_name = "polaris12";
 256                 break;
 257         case CHIP_FIJI:
 258         case CHIP_CARRIZO:
 259         case CHIP_STONEY:
 260         case CHIP_VEGAM:
 261                 return 0;
 262         default: BUG();
 263         }
 264
 265         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 266         err = reject_firmware(&adev->gmc.fw, fw_name, adev->dev);
 267         if (err)
 268                 goto out;
 269         err = amdgpu_ucode_validate(adev->gmc.fw);
 270
 271 out:
 272         if (err) {
 273                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 274                 release_firmware(adev->gmc.fw);
 275                 adev->gmc.fw = NULL;
 276         }
 277         return err;
 278 }
 279
 280 /**
 281  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 282  *
 283  * @adev: amdgpu_device pointer
 284  *
 285  * Load the GDDR MC ucode into the hw (CIK).
 286  * Returns 0 on success, error on failure.
 287  */
 288 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 289 {
 290         const struct mc_firmware_header_v1_0 *hdr;
 291         const __le32 *fw_data = NULL;
 292         const __le32 *io_mc_regs = NULL;
 293         u32 running;
 294         int i, ucode_size, regs_size;
 295
 296         /* Skip MC ucode loading on SR-IOV capable boards.
 297          * vbios does this for us in asic_init in that case.
 298          * Skip MC ucode loading on VF, because hypervisor will do that
 299          * for this adaptor.
 300          */
 301         if (amdgpu_sriov_bios(adev))
 302                 return 0;
 303
 304         if (!adev->gmc.fw)
 305                 return -EINVAL;
 306
 307         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 308         amdgpu_ucode_print_mc_hdr(&hdr->header);
 309
 310         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 311         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 312         io_mc_regs = (const __le32 *)
 313                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 314         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 315         fw_data = (const __le32 *)
 316                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 317
 318         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 319
 320         if (running == 0) {
 321                 /* reset the engine and set to writable */
 322                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 323                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 324
 325                 /* load mc io regs */
 326                 for (i = 0; i < regs_size; i++) {
 327                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 328                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 329                 }
 330                 /* load the MC ucode */
 331                 for (i = 0; i < ucode_size; i++)
 332                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 333
 334                 /* put the engine back into the active state */
 335                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 336                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 337                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 338
 339                 /* wait for training to complete */
 340                 for (i = 0; i < adev->usec_timeout; i++) {
 341                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 342                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 343                                 break;
 344                         udelay(1);
 345                 }
 346                 for (i = 0; i < adev->usec_timeout; i++) {
 347                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 348                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 349                                 break;
 350                         udelay(1);
 351                 }
 352         }
 353
 354         return 0;
 355 }
 356
 357 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 358 {
 359         const struct mc_firmware_header_v1_0 *hdr;
 360         const __le32 *fw_data = NULL;
 361         const __le32 *io_mc_regs = NULL;
 362         u32 data;
 363         int i, ucode_size, regs_size;
 364
 365         /* Skip MC ucode loading on SR-IOV capable boards.
 366          * vbios does this for us in asic_init in that case.
 367          * Skip MC ucode loading on VF, because hypervisor will do that
 368          * for this adaptor.
 369          */
 370         if (amdgpu_sriov_bios(adev))
 371                 return 0;
 372
 373         if (!adev->gmc.fw)
 374                 return -EINVAL;
 375
 376         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 377         amdgpu_ucode_print_mc_hdr(&hdr->header);
 378
 379         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 380         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 381         io_mc_regs = (const __le32 *)
 382                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 383         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 384         fw_data = (const __le32 *)
 385                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 386
 387         data = RREG32(mmMC_SEQ_MISC0);
 388         data &= ~(0x40);
 389         WREG32(mmMC_SEQ_MISC0, data);
 390
 391         /* load mc io regs */
 392         for (i = 0; i < regs_size; i++) {
 393                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 394                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 395         }
 396
 397         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 398         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 399
 400         /* load the MC ucode */
 401         for (i = 0; i < ucode_size; i++)
 402                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 403
 404         /* put the engine back into the active state */
 405         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 406         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 407         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 408
 409         /* wait for training to complete */
 410         for (i = 0; i < adev->usec_timeout; i++) {
 411                 data = RREG32(mmMC_SEQ_MISC0);
 412                 if (data & 0x80)
 413                         break;
 414                 udelay(1);
 415         }
 416
 417         return 0;
 418 }
 419
 420 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 421                                        struct amdgpu_gmc *mc)
 422 {
 423         u64 base = 0;
 424
 425         if (!amdgpu_sriov_vf(adev))
 426                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 427         base <<= 24;
 428
 429         amdgpu_device_vram_location(adev, &adev->gmc, base);
 430         amdgpu_device_gart_location(adev, mc);
 431 }
 432
 433 /**
 434  * gmc_v8_0_mc_program - program the GPU memory controller
 435  *
 436  * @adev: amdgpu_device pointer
 437  *
 438  * Set the location of vram, gart, and AGP in the GPU's
 439  * physical address space (CIK).
 440  */
 441 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 442 {
 443         u32 tmp;
 444         int i, j;
 445
 446         /* Initialize HDP */
 447         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 448                 WREG32((0xb05 + j), 0x00000000);
 449                 WREG32((0xb06 + j), 0x00000000);
 450                 WREG32((0xb07 + j), 0x00000000);
 451                 WREG32((0xb08 + j), 0x00000000);
 452                 WREG32((0xb09 + j), 0x00000000);
 453         }
 454         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 455
 456         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 457                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 458         }
 459         if (adev->mode_info.num_crtc) {
 460                 /* Lockout access through VGA aperture*/
 461                 tmp = RREG32(mmVGA_HDP_CONTROL);
 462                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 463                 WREG32(mmVGA_HDP_CONTROL, tmp);
 464
 465                 /* disable VGA render */
 466                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 467                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 468                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 469         }
 470         /* Update configuration */
 471         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 472                adev->gmc.vram_start >> 12);
 473         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 474                adev->gmc.vram_end >> 12);
 475         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 476                adev->vram_scratch.gpu_addr >> 12);
 477
 478         if (amdgpu_sriov_vf(adev)) {
 479                 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 480                 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
 481                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 482                 /* XXX double check these! */
 483                 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 484                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 485                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 486         }
 487
 488         WREG32(mmMC_VM_AGP_BASE, 0);
 489         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 490         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 491         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 492                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 493         }
 494
 495         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 496
 497         tmp = RREG32(mmHDP_MISC_CNTL);
 498         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 499         WREG32(mmHDP_MISC_CNTL, tmp);
 500
 501         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 502         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 503 }
 504
 505 /**
 506  * gmc_v8_0_mc_init - initialize the memory controller driver params
 507  *
 508  * @adev: amdgpu_device pointer
 509  *
 510  * Look up the amount of vram, vram width, and decide how to place
 511  * vram and gart within the GPU's physical address space (CIK).
 512  * Returns 0 for success.
 513  */
 514 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 515 {
 516         int r;
 517         u32 tmp;
 518
 519         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 520         if (!adev->gmc.vram_width) {
 521                 int chansize, numchan;
 522
 523                 /* Get VRAM informations */
 524                 tmp = RREG32(mmMC_ARB_RAMCFG);
 525                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 526                         chansize = 64;
 527                 } else {
 528                         chansize = 32;
 529                 }
 530                 tmp = RREG32(mmMC_SHARED_CHMAP);
 531                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 532                 case 0:
 533                 default:
 534                         numchan = 1;
 535                         break;
 536                 case 1:
 537                         numchan = 2;
 538                         break;
 539                 case 2:
 540                         numchan = 4;
 541                         break;
 542                 case 3:
 543                         numchan = 8;
 544                         break;
 545                 case 4:
 546                         numchan = 3;
 547                         break;
 548                 case 5:
 549                         numchan = 6;
 550                         break;
 551                 case 6:
 552                         numchan = 10;
 553                         break;
 554                 case 7:
 555                         numchan = 12;
 556                         break;
 557                 case 8:
 558                         numchan = 16;
 559                         break;
 560                 }
 561                 adev->gmc.vram_width = numchan * chansize;
 562         }
 563         /* size in MB on si */
 564         tmp = RREG32(mmCONFIG_MEMSIZE);
 565         /* some boards may have garbage in the upper 16 bits */
 566         if (tmp & 0xffff0000) {
 567                 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
 568                 if (tmp & 0xffff)
 569                         tmp &= 0xffff;
 570         }
 571         adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
 572         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 573
 574         if (!(adev->flags & AMD_IS_APU)) {
 575                 r = amdgpu_device_resize_fb_bar(adev);
 576                 if (r)
 577                         return r;
 578         }
 579         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 580         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 581
 582 #ifdef CONFIG_X86_64
 583         if (adev->flags & AMD_IS_APU) {
 584                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 585                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 586         }
 587 #endif
 588
 589         /* In case the PCI BAR is larger than the actual amount of vram */
 590         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 591         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 592                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 593
 594         /* set the gart size */
 595         if (amdgpu_gart_size == -1) {
 596                 switch (adev->asic_type) {
 597                 case CHIP_POLARIS10: /* all engines support GPUVM */
 598                 case CHIP_POLARIS11: /* all engines support GPUVM */
 599                 case CHIP_POLARIS12: /* all engines support GPUVM */
 600                 case CHIP_VEGAM:     /* all engines support GPUVM */
 601                 default:
 602                         adev->gmc.gart_size = 256ULL << 20;
 603                         break;
 604                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 605                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 606                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 607                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 608                         adev->gmc.gart_size = 1024ULL << 20;
 609                         break;
 610                 }
 611         } else {
 612                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 613         }
 614
 615         gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 616
 617         return 0;
 618 }
 619
 620 /*
 621  * GART
 622  * VMID 0 is the physical GPU addresses as used by the kernel.
 623  * VMIDs 1-15 are used for userspace clients and are handled
 624  * by the amdgpu vm/hsa code.
 625  */
 626
 627 /**
 628  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
 629  *
 630  * @adev: amdgpu_device pointer
 631  * @vmid: vm instance to flush
 632  *
 633  * Flush the TLB for the requested page table (CIK).
 634  */
 635 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
 636                                         uint32_t vmid)
 637 {
 638         /* bits 0-15 are the VM contexts0-15 */
 639         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 640 }
 641
 642 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 643                                             unsigned vmid, uint64_t pd_addr)
 644 {
 645         uint32_t reg;
 646
 647         if (vmid < 8)
 648                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 649         else
 650                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 651         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 652
 653         /* bits 0-15 are the VM contexts0-15 */
 654         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 655
 656         return pd_addr;
 657 }
 658
 659 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 660                                         unsigned pasid)
 661 {
 662         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 663 }
 664
 665 /**
 666  * gmc_v8_0_set_pte_pde - update the page tables using MMIO
 667  *
 668  * @adev: amdgpu_device pointer
 669  * @cpu_pt_addr: cpu address of the page table
 670  * @gpu_page_idx: entry in the page table to update
 671  * @addr: dst addr to write into pte/pde
 672  * @flags: access flags
 673  *
 674  * Update the page tables using the CPU.
 675  */
 676 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 677                                 uint32_t gpu_page_idx, uint64_t addr,
 678                                 uint64_t flags)
 679 {
 680         void __iomem *ptr = (void *)cpu_pt_addr;
 681         uint64_t value;
 682
 683         /*
 684          * PTE format on VI:
 685          * 63:40 reserved
 686          * 39:12 4k physical page base address
 687          * 11:7 fragment
 688          * 6 write
 689          * 5 read
 690          * 4 exe
 691          * 3 reserved
 692          * 2 snooped
 693          * 1 system
 694          * 0 valid
 695          *
 696          * PDE format on VI:
 697          * 63:59 block fragment size
 698          * 58:40 reserved
 699          * 39:1 physical base address of PTE
 700          * bits 5:1 must be 0.
 701          * 0 valid
 702          */
 703         value = addr & 0x000000FFFFFFF000ULL;
 704         value |= flags;
 705         writeq(value, ptr + (gpu_page_idx * 8));
 706
 707         return 0;
 708 }
 709
 710 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 711                                           uint32_t flags)
 712 {
 713         uint64_t pte_flag = 0;
 714
 715         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 716                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 717         if (flags & AMDGPU_VM_PAGE_READABLE)
 718                 pte_flag |= AMDGPU_PTE_READABLE;
 719         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 720                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 721         if (flags & AMDGPU_VM_PAGE_PRT)
 722                 pte_flag |= AMDGPU_PTE_PRT;
 723
 724         return pte_flag;
 725 }
 726
 727 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 728                                 uint64_t *addr, uint64_t *flags)
 729 {
 730         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 731 }
 732
 733 /**
 734  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 735  *
 736  * @adev: amdgpu_device pointer
 737  * @value: true redirects VM faults to the default page
 738  */
 739 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 740                                               bool value)
 741 {
 742         u32 tmp;
 743
 744         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 745         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 746                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 747         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 748                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 749         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 750                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 751         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 752                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 753         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 754                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 755         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 756                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 757         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 758                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 759         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 760 }
 761
 762 /**
 763  * gmc_v8_0_set_prt - set PRT VM fault
 764  *
 765  * @adev: amdgpu_device pointer
 766  * @enable: enable/disable VM fault handling for PRT
 767 */
 768 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 769 {
 770         u32 tmp;
 771
 772         if (enable && !adev->gmc.prt_warning) {
 773                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 774                 adev->gmc.prt_warning = true;
 775         }
 776
 777         tmp = RREG32(mmVM_PRT_CNTL);
 778         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 779                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 780         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 781                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 782         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 783                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 784         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 785                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 786         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 787                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 788         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 789                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 790         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 791                             MASK_PDE0_FAULT, enable);
 792         WREG32(mmVM_PRT_CNTL, tmp);
 793
 794         if (enable) {
 795                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 796                 uint32_t high = adev->vm_manager.max_pfn -
 797                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 798
 799                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 800                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 801                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 802                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 803                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 804                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 805                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 806                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 807         } else {
 808                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 809                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 810                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 811                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 812                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 813                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 814                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 815                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 816         }
 817 }
 818
 819 /**
 820  * gmc_v8_0_gart_enable - gart enable
 821  *
 822  * @adev: amdgpu_device pointer
 823  *
 824  * This sets up the TLBs, programs the page tables for VMID0,
 825  * sets up the hw for VMIDs 1-15 which are allocated on
 826  * demand, and sets up the global locations for the LDS, GDS,
 827  * and GPUVM for FSA64 clients (CIK).
 828  * Returns 0 for success, errors for failure.
 829  */
 830 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 831 {
 832         int r, i;
 833         u32 tmp, field;
 834
 835         if (adev->gart.robj == NULL) {
 836                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 837                 return -EINVAL;
 838         }
 839         r = amdgpu_gart_table_vram_pin(adev);
 840         if (r)
 841                 return r;
 842         /* Setup TLB control */
 843         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 844         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 845         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 846         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 847         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 848         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 849         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 850         /* Setup L2 cache */
 851         tmp = RREG32(mmVM_L2_CNTL);
 852         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 853         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 854         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 855         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 856         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 857         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 858         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 859         WREG32(mmVM_L2_CNTL, tmp);
 860         tmp = RREG32(mmVM_L2_CNTL2);
 861         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 862         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 863         WREG32(mmVM_L2_CNTL2, tmp);
 864
 865         field = adev->vm_manager.fragment_size;
 866         tmp = RREG32(mmVM_L2_CNTL3);
 867         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 868         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 869         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 870         WREG32(mmVM_L2_CNTL3, tmp);
 871         /* XXX: set to enable PTE/PDE in system memory */
 872         tmp = RREG32(mmVM_L2_CNTL4);
 873         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 874         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 875         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 876         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 877         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 878         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 879         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 880         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 881         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 882         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 883         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 884         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 885         WREG32(mmVM_L2_CNTL4, tmp);
 886         /* setup context0 */
 887         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 888         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 889         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 890         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 891                         (u32)(adev->dummy_page_addr >> 12));
 892         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 893         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 894         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 895         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 896         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 897         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 898
 899         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 900         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 901         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 902
 903         /* empty context1-15 */
 904         /* FIXME start with 4G, once using 2 level pt switch to full
 905          * vm size space
 906          */
 907         /* set vm size, must be a multiple of 4 */
 908         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 909         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 910         for (i = 1; i < 16; i++) {
 911                 if (i < 8)
 912                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 913                                adev->gart.table_addr >> 12);
 914                 else
 915                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 916                                adev->gart.table_addr >> 12);
 917         }
 918
 919         /* enable context1-15 */
 920         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 921                (u32)(adev->dummy_page_addr >> 12));
 922         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 923         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 924         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 925         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 926         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 927         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 928         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 929         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 930         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 931         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 932         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 933         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 934                             adev->vm_manager.block_size - 9);
 935         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 936         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 937                 gmc_v8_0_set_fault_enable_default(adev, false);
 938         else
 939                 gmc_v8_0_set_fault_enable_default(adev, true);
 940
 941         gmc_v8_0_flush_gpu_tlb(adev, 0);
 942         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 943                  (unsigned)(adev->gmc.gart_size >> 20),
 944                  (unsigned long long)adev->gart.table_addr);
 945         adev->gart.ready = true;
 946         return 0;
 947 }
 948
 949 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 950 {
 951         int r;
 952
 953         if (adev->gart.robj) {
 954                 WARN(1, "R600 PCIE GART already initialized\n");
 955                 return 0;
 956         }
 957         /* Initialize common gart structure */
 958         r = amdgpu_gart_init(adev);
 959         if (r)
 960                 return r;
 961         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 962         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 963         return amdgpu_gart_table_vram_alloc(adev);
 964 }
 965
 966 /**
 967  * gmc_v8_0_gart_disable - gart disable
 968  *
 969  * @adev: amdgpu_device pointer
 970  *
 971  * This disables all VM page table (CIK).
 972  */
 973 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 974 {
 975         u32 tmp;
 976
 977         /* Disable all tables */
 978         WREG32(mmVM_CONTEXT0_CNTL, 0);
 979         WREG32(mmVM_CONTEXT1_CNTL, 0);
 980         /* Setup TLB control */
 981         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 982         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 983         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 984         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 985         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 986         /* Setup L2 cache */
 987         tmp = RREG32(mmVM_L2_CNTL);
 988         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 989         WREG32(mmVM_L2_CNTL, tmp);
 990         WREG32(mmVM_L2_CNTL2, 0);
 991         amdgpu_gart_table_vram_unpin(adev);
 992 }
 993
 994 /**
 995  * gmc_v8_0_vm_decode_fault - print human readable fault info
 996  *
 997  * @adev: amdgpu_device pointer
 998  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 999  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
1000  *
1001  * Print human readable fault information (CIK).
1002  */
1003 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1004                                      u32 addr, u32 mc_client, unsigned pasid)
1005 {
1006         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1007         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1008                                         PROTECTIONS);
1009         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1010                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1011         u32 mc_id;
1012
1013         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1014                               MEMORY_CLIENT_ID);
1015
1016         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1017                protections, vmid, pasid, addr,
1018                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1019                              MEMORY_CLIENT_RW) ?
1020                "write" : "read", block, mc_client, mc_id);
1021 }
1022
1023 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1024 {
1025         switch (mc_seq_vram_type) {
1026         case MC_SEQ_MISC0__MT__GDDR1:
1027                 return AMDGPU_VRAM_TYPE_GDDR1;
1028         case MC_SEQ_MISC0__MT__DDR2:
1029                 return AMDGPU_VRAM_TYPE_DDR2;
1030         case MC_SEQ_MISC0__MT__GDDR3:
1031                 return AMDGPU_VRAM_TYPE_GDDR3;
1032         case MC_SEQ_MISC0__MT__GDDR4:
1033                 return AMDGPU_VRAM_TYPE_GDDR4;
1034         case MC_SEQ_MISC0__MT__GDDR5:
1035                 return AMDGPU_VRAM_TYPE_GDDR5;
1036         case MC_SEQ_MISC0__MT__HBM:
1037                 return AMDGPU_VRAM_TYPE_HBM;
1038         case MC_SEQ_MISC0__MT__DDR3:
1039                 return AMDGPU_VRAM_TYPE_DDR3;
1040         default:
1041                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1042         }
1043 }
1044
1045 static int gmc_v8_0_early_init(void *handle)
1046 {
1047         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1048
1049         gmc_v8_0_set_gmc_funcs(adev);
1050         gmc_v8_0_set_irq_funcs(adev);
1051
1052         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1053         adev->gmc.shared_aperture_end =
1054                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1055         adev->gmc.private_aperture_start =
1056                 adev->gmc.shared_aperture_end + 1;
1057         adev->gmc.private_aperture_end =
1058                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1059
1060         return 0;
1061 }
1062
1063 static int gmc_v8_0_late_init(void *handle)
1064 {
1065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1066
1067         amdgpu_bo_late_init(adev);
1068
1069         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1070                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1071         else
1072                 return 0;
1073 }
1074
1075 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1076 {
1077         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1078         unsigned size;
1079
1080         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1081                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1082         } else {
1083                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1084                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1085                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1086                         4);
1087         }
1088         /* return 0 if the pre-OS buffer uses up most of vram */
1089         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1090                 return 0;
1091         return size;
1092 }
1093
1094 #define mmMC_SEQ_MISC0_FIJI 0xA71
1095
1096 static int gmc_v8_0_sw_init(void *handle)
1097 {
1098         int r;
1099         int dma_bits;
1100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1101
1102         if (adev->flags & AMD_IS_APU) {
1103                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1104         } else {
1105                 u32 tmp;
1106
1107                 if ((adev->asic_type == CHIP_FIJI) ||
1108                     (adev->asic_type == CHIP_VEGAM))
1109                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1110                 else
1111                         tmp = RREG32(mmMC_SEQ_MISC0);
1112                 tmp &= MC_SEQ_MISC0__MT__MASK;
1113                 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1114         }
1115
1116         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1117         if (r)
1118                 return r;
1119
1120         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1121         if (r)
1122                 return r;
1123
1124         /* Adjust VM size here.
1125          * Currently set to 4GB ((1 << 20) 4k pages).
1126          * Max GPUVM size for cayman and SI is 40 bits.
1127          */
1128         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1129
1130         /* Set the internal MC address mask
1131          * This is the max address of the GPU's
1132          * internal address space.
1133          */
1134         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1135
1136         /* set DMA mask + need_dma32 flags.
1137          * PCIE - can handle 40-bits.
1138          * IGP - can handle 40-bits
1139          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1140          */
1141         adev->need_dma32 = false;
1142         dma_bits = adev->need_dma32 ? 32 : 40;
1143         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1144         if (r) {
1145                 adev->need_dma32 = true;
1146                 dma_bits = 32;
1147                 pr_warn("amdgpu: No suitable DMA available\n");
1148         }
1149         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1150         if (r) {
1151                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1152                 pr_warn("amdgpu: No coherent DMA available\n");
1153         }
1154         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1155
1156         r = gmc_v8_0_init_microcode(adev);
1157         if (r) {
1158                 DRM_ERROR("Failed to load mc firmware!\n");
1159                 return r;
1160         }
1161
1162         r = gmc_v8_0_mc_init(adev);
1163         if (r)
1164                 return r;
1165
1166         adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1167
1168         /* Memory manager */
1169         r = amdgpu_bo_init(adev);
1170         if (r)
1171                 return r;
1172
1173         r = gmc_v8_0_gart_init(adev);
1174         if (r)
1175                 return r;
1176
1177         /*
1178          * number of VMs
1179          * VMID 0 is reserved for System
1180          * amdgpu graphics/compute will use VMIDs 1-7
1181          * amdkfd will use VMIDs 8-15
1182          */
1183         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1184         amdgpu_vm_manager_init(adev);
1185
1186         /* base offset of vram pages */
1187         if (adev->flags & AMD_IS_APU) {
1188                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1189
1190                 tmp <<= 22;
1191                 adev->vm_manager.vram_base_offset = tmp;
1192         } else {
1193                 adev->vm_manager.vram_base_offset = 0;
1194         }
1195
1196         adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1197                                         GFP_KERNEL);
1198         if (!adev->gmc.vm_fault_info)
1199                 return -ENOMEM;
1200         atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1201
1202         return 0;
1203 }
1204
1205 static int gmc_v8_0_sw_fini(void *handle)
1206 {
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209         amdgpu_gem_force_release(adev);
1210         amdgpu_vm_manager_fini(adev);
1211         kfree(adev->gmc.vm_fault_info);
1212         amdgpu_gart_table_vram_free(adev);
1213         amdgpu_bo_fini(adev);
1214         amdgpu_gart_fini(adev);
1215         release_firmware(adev->gmc.fw);
1216         adev->gmc.fw = NULL;
1217
1218         return 0;
1219 }
1220
1221 static int gmc_v8_0_hw_init(void *handle)
1222 {
1223         int r;
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225
1226         gmc_v8_0_init_golden_registers(adev);
1227
1228         gmc_v8_0_mc_program(adev);
1229
1230         if (adev->asic_type == CHIP_TONGA) {
1231                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1232                 if (r) {
1233                         DRM_ERROR("Failed to load MC firmware!\n");
1234                         return r;
1235                 }
1236         } else if (adev->asic_type == CHIP_POLARIS11 ||
1237                         adev->asic_type == CHIP_POLARIS10 ||
1238                         adev->asic_type == CHIP_POLARIS12) {
1239                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1240                 if (r) {
1241                         DRM_ERROR("Failed to load MC firmware!\n");
1242                         return r;
1243                 }
1244         }
1245
1246         r = gmc_v8_0_gart_enable(adev);
1247         if (r)
1248                 return r;
1249
1250         return r;
1251 }
1252
1253 static int gmc_v8_0_hw_fini(void *handle)
1254 {
1255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256
1257         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1258         gmc_v8_0_gart_disable(adev);
1259
1260         return 0;
1261 }
1262
1263 static int gmc_v8_0_suspend(void *handle)
1264 {
1265         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266
1267         gmc_v8_0_hw_fini(adev);
1268
1269         return 0;
1270 }
1271
1272 static int gmc_v8_0_resume(void *handle)
1273 {
1274         int r;
1275         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1276
1277         r = gmc_v8_0_hw_init(adev);
1278         if (r)
1279                 return r;
1280
1281         amdgpu_vmid_reset_all(adev);
1282
1283         return 0;
1284 }
1285
1286 static bool gmc_v8_0_is_idle(void *handle)
1287 {
1288         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289         u32 tmp = RREG32(mmSRBM_STATUS);
1290
1291         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1292                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1293                 return false;
1294
1295         return true;
1296 }
1297
1298 static int gmc_v8_0_wait_for_idle(void *handle)
1299 {
1300         unsigned i;
1301         u32 tmp;
1302         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303
1304         for (i = 0; i < adev->usec_timeout; i++) {
1305                 /* read MC_STATUS */
1306                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1307                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1308                                                SRBM_STATUS__MCC_BUSY_MASK |
1309                                                SRBM_STATUS__MCD_BUSY_MASK |
1310                                                SRBM_STATUS__VMC_BUSY_MASK |
1311                                                SRBM_STATUS__VMC1_BUSY_MASK);
1312                 if (!tmp)
1313                         return 0;
1314                 udelay(1);
1315         }
1316         return -ETIMEDOUT;
1317
1318 }
1319
1320 static bool gmc_v8_0_check_soft_reset(void *handle)
1321 {
1322         u32 srbm_soft_reset = 0;
1323         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324         u32 tmp = RREG32(mmSRBM_STATUS);
1325
1326         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1327                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1328                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1329
1330         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1331                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1332                 if (!(adev->flags & AMD_IS_APU))
1333                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1334                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1335         }
1336         if (srbm_soft_reset) {
1337                 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1338                 return true;
1339         } else {
1340                 adev->gmc.srbm_soft_reset = 0;
1341                 return false;
1342         }
1343 }
1344
1345 static int gmc_v8_0_pre_soft_reset(void *handle)
1346 {
1347         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1348
1349         if (!adev->gmc.srbm_soft_reset)
1350                 return 0;
1351
1352         gmc_v8_0_mc_stop(adev);
1353         if (gmc_v8_0_wait_for_idle(adev)) {
1354                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1355         }
1356
1357         return 0;
1358 }
1359
1360 static int gmc_v8_0_soft_reset(void *handle)
1361 {
1362         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1363         u32 srbm_soft_reset;
1364
1365         if (!adev->gmc.srbm_soft_reset)
1366                 return 0;
1367         srbm_soft_reset = adev->gmc.srbm_soft_reset;
1368
1369         if (srbm_soft_reset) {
1370                 u32 tmp;
1371
1372                 tmp = RREG32(mmSRBM_SOFT_RESET);
1373                 tmp |= srbm_soft_reset;
1374                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1375                 WREG32(mmSRBM_SOFT_RESET, tmp);
1376                 tmp = RREG32(mmSRBM_SOFT_RESET);
1377
1378                 udelay(50);
1379
1380                 tmp &= ~srbm_soft_reset;
1381                 WREG32(mmSRBM_SOFT_RESET, tmp);
1382                 tmp = RREG32(mmSRBM_SOFT_RESET);
1383
1384                 /* Wait a little for things to settle down */
1385                 udelay(50);
1386         }
1387
1388         return 0;
1389 }
1390
1391 static int gmc_v8_0_post_soft_reset(void *handle)
1392 {
1393         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1394
1395         if (!adev->gmc.srbm_soft_reset)
1396                 return 0;
1397
1398         gmc_v8_0_mc_resume(adev);
1399         return 0;
1400 }
1401
1402 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1403                                              struct amdgpu_irq_src *src,
1404                                              unsigned type,
1405                                              enum amdgpu_interrupt_state state)
1406 {
1407         u32 tmp;
1408         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1409                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1410                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1411                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1412                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1413                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1414                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1415
1416         switch (state) {
1417         case AMDGPU_IRQ_STATE_DISABLE:
1418                 /* system context */
1419                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1420                 tmp &= ~bits;
1421                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1422                 /* VMs */
1423                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1424                 tmp &= ~bits;
1425                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1426                 break;
1427         case AMDGPU_IRQ_STATE_ENABLE:
1428                 /* system context */
1429                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1430                 tmp |= bits;
1431                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1432                 /* VMs */
1433                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1434                 tmp |= bits;
1435                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1436                 break;
1437         default:
1438                 break;
1439         }
1440
1441         return 0;
1442 }
1443
1444 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1445                                       struct amdgpu_irq_src *source,
1446                                       struct amdgpu_iv_entry *entry)
1447 {
1448         u32 addr, status, mc_client, vmid;
1449
1450         if (amdgpu_sriov_vf(adev)) {
1451                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1452                         entry->src_id, entry->src_data[0]);
1453                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1454                 return 0;
1455         }
1456
1457         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1458         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1459         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1460         /* reset addr and status */
1461         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1462
1463         if (!addr && !status)
1464                 return 0;
1465
1466         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1467                 gmc_v8_0_set_fault_enable_default(adev, false);
1468
1469         if (printk_ratelimit()) {
1470                 struct amdgpu_task_info task_info = { 0 };
1471
1472                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1473
1474                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1475                         entry->src_id, entry->src_data[0], task_info.process_name,
1476                         task_info.tgid, task_info.task_name, task_info.pid);
1477                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1478                         addr);
1479                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1480                         status);
1481                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1482                                          entry->pasid);
1483         }
1484
1485         vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1486                              VMID);
1487         if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1488                 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1489                 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1490                 u32 protections = REG_GET_FIELD(status,
1491                                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1492                                         PROTECTIONS);
1493
1494                 info->vmid = vmid;
1495                 info->mc_id = REG_GET_FIELD(status,
1496                                             VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1497                                             MEMORY_CLIENT_ID);
1498                 info->status = status;
1499                 info->page_addr = addr;
1500                 info->prot_valid = protections & 0x7 ? true : false;
1501                 info->prot_read = protections & 0x8 ? true : false;
1502                 info->prot_write = protections & 0x10 ? true : false;
1503                 info->prot_exec = protections & 0x20 ? true : false;
1504                 mb();
1505                 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1506         }
1507
1508         return 0;
1509 }
1510
1511 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1512                                                      bool enable)
1513 {
1514         uint32_t data;
1515
1516         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1517                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1518                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1519                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1520
1521                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1522                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1523                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1524
1525                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1526                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1527                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1528
1529                 data = RREG32(mmMC_XPB_CLK_GAT);
1530                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1531                 WREG32(mmMC_XPB_CLK_GAT, data);
1532
1533                 data = RREG32(mmATC_MISC_CG);
1534                 data |= ATC_MISC_CG__ENABLE_MASK;
1535                 WREG32(mmATC_MISC_CG, data);
1536
1537                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1538                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1539                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1540
1541                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1542                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1543                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1544
1545                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1546                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1547                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1548
1549                 data = RREG32(mmVM_L2_CG);
1550                 data |= VM_L2_CG__ENABLE_MASK;
1551                 WREG32(mmVM_L2_CG, data);
1552         } else {
1553                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1554                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1555                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1556
1557                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1558                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1559                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1560
1561                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1562                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1563                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1564
1565                 data = RREG32(mmMC_XPB_CLK_GAT);
1566                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1567                 WREG32(mmMC_XPB_CLK_GAT, data);
1568
1569                 data = RREG32(mmATC_MISC_CG);
1570                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1571                 WREG32(mmATC_MISC_CG, data);
1572
1573                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1574                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1575                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1576
1577                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1578                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1579                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1580
1581                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1582                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1583                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1584
1585                 data = RREG32(mmVM_L2_CG);
1586                 data &= ~VM_L2_CG__ENABLE_MASK;
1587                 WREG32(mmVM_L2_CG, data);
1588         }
1589 }
1590
1591 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1592                                        bool enable)
1593 {
1594         uint32_t data;
1595
1596         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1597                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1598                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1599                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1600
1601                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1602                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1603                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1604
1605                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1606                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1607                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1608
1609                 data = RREG32(mmMC_XPB_CLK_GAT);
1610                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1611                 WREG32(mmMC_XPB_CLK_GAT, data);
1612
1613                 data = RREG32(mmATC_MISC_CG);
1614                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1615                 WREG32(mmATC_MISC_CG, data);
1616
1617                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1618                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1619                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1620
1621                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1622                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1623                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1624
1625                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1626                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1627                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1628
1629                 data = RREG32(mmVM_L2_CG);
1630                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1631                 WREG32(mmVM_L2_CG, data);
1632         } else {
1633                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1634                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1635                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1636
1637                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1638                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1639                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1640
1641                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1642                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1643                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1644
1645                 data = RREG32(mmMC_XPB_CLK_GAT);
1646                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1647                 WREG32(mmMC_XPB_CLK_GAT, data);
1648
1649                 data = RREG32(mmATC_MISC_CG);
1650                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1651                 WREG32(mmATC_MISC_CG, data);
1652
1653                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1654                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1655                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1656
1657                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1658                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1659                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1660
1661                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1662                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1663                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1664
1665                 data = RREG32(mmVM_L2_CG);
1666                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1667                 WREG32(mmVM_L2_CG, data);
1668         }
1669 }
1670
1671 static int gmc_v8_0_set_clockgating_state(void *handle,
1672                                           enum amd_clockgating_state state)
1673 {
1674         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1675
1676         if (amdgpu_sriov_vf(adev))
1677                 return 0;
1678
1679         switch (adev->asic_type) {
1680         case CHIP_FIJI:
1681                 fiji_update_mc_medium_grain_clock_gating(adev,
1682                                 state == AMD_CG_STATE_GATE);
1683                 fiji_update_mc_light_sleep(adev,
1684                                 state == AMD_CG_STATE_GATE);
1685                 break;
1686         default:
1687                 break;
1688         }
1689         return 0;
1690 }
1691
1692 static int gmc_v8_0_set_powergating_state(void *handle,
1693                                           enum amd_powergating_state state)
1694 {
1695         return 0;
1696 }
1697
1698 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1699 {
1700         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1701         int data;
1702
1703         if (amdgpu_sriov_vf(adev))
1704                 *flags = 0;
1705
1706         /* AMD_CG_SUPPORT_MC_MGCG */
1707         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1708         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1709                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1710
1711         /* AMD_CG_SUPPORT_MC_LS */
1712         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1713                 *flags |= AMD_CG_SUPPORT_MC_LS;
1714 }
1715
1716 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1717         .name = "gmc_v8_0",
1718         .early_init = gmc_v8_0_early_init,
1719         .late_init = gmc_v8_0_late_init,
1720         .sw_init = gmc_v8_0_sw_init,
1721         .sw_fini = gmc_v8_0_sw_fini,
1722         .hw_init = gmc_v8_0_hw_init,
1723         .hw_fini = gmc_v8_0_hw_fini,
1724         .suspend = gmc_v8_0_suspend,
1725         .resume = gmc_v8_0_resume,
1726         .is_idle = gmc_v8_0_is_idle,
1727         .wait_for_idle = gmc_v8_0_wait_for_idle,
1728         .check_soft_reset = gmc_v8_0_check_soft_reset,
1729         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1730         .soft_reset = gmc_v8_0_soft_reset,
1731         .post_soft_reset = gmc_v8_0_post_soft_reset,
1732         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1733         .set_powergating_state = gmc_v8_0_set_powergating_state,
1734         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1735 };
1736
1737 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1738         .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1739         .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1740         .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1741         .set_pte_pde = gmc_v8_0_set_pte_pde,
1742         .set_prt = gmc_v8_0_set_prt,
1743         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1744         .get_vm_pde = gmc_v8_0_get_vm_pde
1745 };
1746
1747 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1748         .set = gmc_v8_0_vm_fault_interrupt_state,
1749         .process = gmc_v8_0_process_interrupt,
1750 };
1751
1752 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1753 {
1754         if (adev->gmc.gmc_funcs == NULL)
1755                 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1756 }
1757
1758 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1759 {
1760         adev->gmc.vm_fault.num_types = 1;
1761         adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1762 }
1763
1764 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1765 {
1766         .type = AMD_IP_BLOCK_TYPE_GMC,
1767         .major = 8,
1768         .minor = 0,
1769         .rev = 0,
1770         .funcs = &gmc_v8_0_ip_funcs,
1771 };
1772
1773 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1774 {
1775         .type = AMD_IP_BLOCK_TYPE_GMC,
1776         .major = 8,
1777         .minor = 1,
1778         .rev = 0,
1779         .funcs = &gmc_v8_0_ip_funcs,
1780 };
1781
1782 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1783 {
1784         .type = AMD_IP_BLOCK_TYPE_GMC,
1785         .major = 8,
1786         .minor = 5,
1787         .rev = 0,
1788         .funcs = &gmc_v8_0_ip_funcs,
1789 };