drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "dce/dce_10_0_d.h"
  39 #include "dce/dce_10_0_sh_mask.h"
  40
  41 #include "vid.h"
  42 #include "vi.h"
  43
  44 #include "amdgpu_atombios.h"
  45
  46
  47 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  48 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  49 static int gmc_v8_0_wait_for_idle(void *handle);
  50
  51 /*(DEBLOBBED)*/
  52
  53 static const u32 golden_settings_tonga_a11[] =
  54 {
  55         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  56         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  57         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  58         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  59         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  60         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  61         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  62 };
  63
  64 static const u32 tonga_mgcg_cgcg_init[] =
  65 {
  66         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  67 };
  68
  69 static const u32 golden_settings_fiji_a10[] =
  70 {
  71         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  73         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  74         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75 };
  76
  77 static const u32 fiji_mgcg_cgcg_init[] =
  78 {
  79         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  80 };
  81
  82 static const u32 golden_settings_polaris11_a11[] =
  83 {
  84         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  85         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  86         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  87         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  88 };
  89
  90 static const u32 golden_settings_polaris10_a11[] =
  91 {
  92         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  93         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  94         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  95         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  96         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  97 };
  98
  99 static const u32 cz_mgcg_cgcg_init[] =
 100 {
 101         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 102 };
 103
 104 static const u32 stoney_mgcg_cgcg_init[] =
 105 {
 106         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 107         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 108 };
 109
 110 static const u32 golden_settings_stoney_common[] =
 111 {
 112         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 113         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 114 };
 115
 116 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 117 {
 118         switch (adev->asic_type) {
 119         case CHIP_FIJI:
 120                 amdgpu_program_register_sequence(adev,
 121                                                  fiji_mgcg_cgcg_init,
 122                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 123                 amdgpu_program_register_sequence(adev,
 124                                                  golden_settings_fiji_a10,
 125                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 126                 break;
 127         case CHIP_TONGA:
 128                 amdgpu_program_register_sequence(adev,
 129                                                  tonga_mgcg_cgcg_init,
 130                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 131                 amdgpu_program_register_sequence(adev,
 132                                                  golden_settings_tonga_a11,
 133                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 134                 break;
 135         case CHIP_POLARIS11:
 136         case CHIP_POLARIS12:
 137                 amdgpu_program_register_sequence(adev,
 138                                                  golden_settings_polaris11_a11,
 139                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 140                 break;
 141         case CHIP_POLARIS10:
 142                 amdgpu_program_register_sequence(adev,
 143                                                  golden_settings_polaris10_a11,
 144                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 145                 break;
 146         case CHIP_CARRIZO:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  cz_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 150                 break;
 151         case CHIP_STONEY:
 152                 amdgpu_program_register_sequence(adev,
 153                                                  stoney_mgcg_cgcg_init,
 154                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 155                 amdgpu_program_register_sequence(adev,
 156                                                  golden_settings_stoney_common,
 157                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 158                 break;
 159         default:
 160                 break;
 161         }
 162 }
 163
 164 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 165 {
 166         u32 blackout;
 167
 168         gmc_v8_0_wait_for_idle(adev);
 169
 170         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 171         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 172                 /* Block CPU access */
 173                 WREG32(mmBIF_FB_EN, 0);
 174                 /* blackout the MC */
 175                 blackout = REG_SET_FIELD(blackout,
 176                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 177                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 178         }
 179         /* wait for the MC to settle */
 180         udelay(100);
 181 }
 182
 183 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 184 {
 185         u32 tmp;
 186
 187         /* unblackout the MC */
 188         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 189         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 190         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 191         /* allow CPU access */
 192         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 193         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 194         WREG32(mmBIF_FB_EN, tmp);
 195 }
 196
 197 /**
 198  * gmc_v8_0_init_microcode - load ucode images from disk
 199  *
 200  * @adev: amdgpu_device pointer
 201  *
 202  * Use the firmware interface to load the ucode images into
 203  * the driver (not loaded into hw).
 204  * Returns 0 on success, error on failure.
 205  */
 206 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 207 {
 208         const char *chip_name;
 209         char fw_name[30];
 210         int err;
 211
 212         DRM_DEBUG("\n");
 213
 214         switch (adev->asic_type) {
 215         case CHIP_TONGA:
 216                 chip_name = "tonga";
 217                 break;
 218         case CHIP_POLARIS11:
 219                 if (((adev->pdev->device == 0x67ef) &&
 220                      ((adev->pdev->revision == 0xe0) ||
 221                       (adev->pdev->revision == 0xe5))) ||
 222                     ((adev->pdev->device == 0x67ff) &&
 223                      ((adev->pdev->revision == 0xcf) ||
 224                       (adev->pdev->revision == 0xef) ||
 225                       (adev->pdev->revision == 0xff))))
 226                         chip_name = "polaris11_k";
 227                 else if ((adev->pdev->device == 0x67ef) &&
 228                          (adev->pdev->revision == 0xe2))
 229                         chip_name = "polaris11_k";
 230                 else
 231                         chip_name = "polaris11";
 232                 break;
 233         case CHIP_POLARIS10:
 234                 if ((adev->pdev->device == 0x67df) &&
 235                     ((adev->pdev->revision == 0xe1) ||
 236                      (adev->pdev->revision == 0xf7)))
 237                         chip_name = "polaris10_k";
 238                 else
 239                         chip_name = "polaris10";
 240                 break;
 241         case CHIP_POLARIS12:
 242                 if (((adev->pdev->device == 0x6987) &&
 243                      ((adev->pdev->revision == 0xc0) ||
 244                       (adev->pdev->revision == 0xc3))) ||
 245                     ((adev->pdev->device == 0x6981) &&
 246                      ((adev->pdev->revision == 0x00) ||
 247                       (adev->pdev->revision == 0x01) ||
 248                       (adev->pdev->revision == 0x10))))
 249                         chip_name = "polaris12_k";
 250                 else
 251                         chip_name = "polaris12";
 252                 break;
 253         case CHIP_FIJI:
 254         case CHIP_CARRIZO:
 255         case CHIP_STONEY:
 256                 return 0;
 257         default: BUG();
 258         }
 259
 260         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 261         err = reject_firmware(&adev->mc.fw, fw_name, adev->dev);
 262         if (err)
 263                 goto out;
 264         err = amdgpu_ucode_validate(adev->mc.fw);
 265
 266 out:
 267         if (err) {
 268                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 269                 release_firmware(adev->mc.fw);
 270                 adev->mc.fw = NULL;
 271         }
 272         return err;
 273 }
 274
 275 /**
 276  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 277  *
 278  * @adev: amdgpu_device pointer
 279  *
 280  * Load the GDDR MC ucode into the hw (CIK).
 281  * Returns 0 on success, error on failure.
 282  */
 283 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 284 {
 285         const struct mc_firmware_header_v1_0 *hdr;
 286         const __le32 *fw_data = NULL;
 287         const __le32 *io_mc_regs = NULL;
 288         u32 running;
 289         int i, ucode_size, regs_size;
 290
 291         /* Skip MC ucode loading on SR-IOV capable boards.
 292          * vbios does this for us in asic_init in that case.
 293          * Skip MC ucode loading on VF, because hypervisor will do that
 294          * for this adaptor.
 295          */
 296         if (amdgpu_sriov_bios(adev))
 297                 return 0;
 298
 299         if (!adev->mc.fw)
 300                 return -EINVAL;
 301
 302         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 303         amdgpu_ucode_print_mc_hdr(&hdr->header);
 304
 305         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 306         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 307         io_mc_regs = (const __le32 *)
 308                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 309         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 310         fw_data = (const __le32 *)
 311                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 312
 313         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 314
 315         if (running == 0) {
 316                 /* reset the engine and set to writable */
 317                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 318                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 319
 320                 /* load mc io regs */
 321                 for (i = 0; i < regs_size; i++) {
 322                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 323                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 324                 }
 325                 /* load the MC ucode */
 326                 for (i = 0; i < ucode_size; i++)
 327                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 328
 329                 /* put the engine back into the active state */
 330                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 331                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 332                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 333
 334                 /* wait for training to complete */
 335                 for (i = 0; i < adev->usec_timeout; i++) {
 336                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 337                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 338                                 break;
 339                         udelay(1);
 340                 }
 341                 for (i = 0; i < adev->usec_timeout; i++) {
 342                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 343                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 344                                 break;
 345                         udelay(1);
 346                 }
 347         }
 348
 349         return 0;
 350 }
 351
 352 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 353 {
 354         const struct mc_firmware_header_v1_0 *hdr;
 355         const __le32 *fw_data = NULL;
 356         const __le32 *io_mc_regs = NULL;
 357         u32 data, vbios_version;
 358         int i, ucode_size, regs_size;
 359
 360         /* Skip MC ucode loading on SR-IOV capable boards.
 361          * vbios does this for us in asic_init in that case.
 362          * Skip MC ucode loading on VF, because hypervisor will do that
 363          * for this adaptor.
 364          */
 365         if (amdgpu_sriov_bios(adev))
 366                 return 0;
 367
 368         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 369         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 370         vbios_version = data & 0xf;
 371
 372         if (vbios_version == 0)
 373                 return 0;
 374
 375         if (!adev->mc.fw)
 376                 return -EINVAL;
 377
 378         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 379         amdgpu_ucode_print_mc_hdr(&hdr->header);
 380
 381         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 382         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 383         io_mc_regs = (const __le32 *)
 384                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 385         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 386         fw_data = (const __le32 *)
 387                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 388
 389         data = RREG32(mmMC_SEQ_MISC0);
 390         data &= ~(0x40);
 391         WREG32(mmMC_SEQ_MISC0, data);
 392
 393         /* load mc io regs */
 394         for (i = 0; i < regs_size; i++) {
 395                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 396                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 397         }
 398
 399         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 400         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 401
 402         /* load the MC ucode */
 403         for (i = 0; i < ucode_size; i++)
 404                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 405
 406         /* put the engine back into the active state */
 407         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 408         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 409         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 410
 411         /* wait for training to complete */
 412         for (i = 0; i < adev->usec_timeout; i++) {
 413                 data = RREG32(mmMC_SEQ_MISC0);
 414                 if (data & 0x80)
 415                         break;
 416                 udelay(1);
 417         }
 418
 419         return 0;
 420 }
 421
 422 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 423                                        struct amdgpu_mc *mc)
 424 {
 425         u64 base = 0;
 426
 427         if (!amdgpu_sriov_vf(adev))
 428                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 429         base <<= 24;
 430
 431         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 432                 /* leave room for at least 1024M GTT */
 433                 dev_warn(adev->dev, "limiting VRAM\n");
 434                 mc->real_vram_size = 0xFFC0000000ULL;
 435                 mc->mc_vram_size = 0xFFC0000000ULL;
 436         }
 437         amdgpu_vram_location(adev, &adev->mc, base);
 438         amdgpu_gart_location(adev, mc);
 439 }
 440
 441 /**
 442  * gmc_v8_0_mc_program - program the GPU memory controller
 443  *
 444  * @adev: amdgpu_device pointer
 445  *
 446  * Set the location of vram, gart, and AGP in the GPU's
 447  * physical address space (CIK).
 448  */
 449 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 450 {
 451         u32 tmp;
 452         int i, j;
 453
 454         /* Initialize HDP */
 455         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 456                 WREG32((0xb05 + j), 0x00000000);
 457                 WREG32((0xb06 + j), 0x00000000);
 458                 WREG32((0xb07 + j), 0x00000000);
 459                 WREG32((0xb08 + j), 0x00000000);
 460                 WREG32((0xb09 + j), 0x00000000);
 461         }
 462         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 463
 464         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 465                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 466         }
 467         if (adev->mode_info.num_crtc) {
 468                 /* Lockout access through VGA aperture*/
 469                 tmp = RREG32(mmVGA_HDP_CONTROL);
 470                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 471                 WREG32(mmVGA_HDP_CONTROL, tmp);
 472
 473                 /* disable VGA render */
 474                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 475                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 476                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 477         }
 478         /* Update configuration */
 479         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 480                adev->mc.vram_start >> 12);
 481         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 482                adev->mc.vram_end >> 12);
 483         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 484                adev->vram_scratch.gpu_addr >> 12);
 485
 486         if (amdgpu_sriov_vf(adev)) {
 487                 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 488                 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 489                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 490                 /* XXX double check these! */
 491                 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 492                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 493                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 494         }
 495
 496         WREG32(mmMC_VM_AGP_BASE, 0);
 497         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 498         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 499         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 500                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 501         }
 502
 503         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 504
 505         tmp = RREG32(mmHDP_MISC_CNTL);
 506         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 507         WREG32(mmHDP_MISC_CNTL, tmp);
 508
 509         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 510         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 511 }
 512
 513 /**
 514  * gmc_v8_0_mc_init - initialize the memory controller driver params
 515  *
 516  * @adev: amdgpu_device pointer
 517  *
 518  * Look up the amount of vram, vram width, and decide how to place
 519  * vram and gart within the GPU's physical address space (CIK).
 520  * Returns 0 for success.
 521  */
 522 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 523 {
 524         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 525         if (!adev->mc.vram_width) {
 526                 u32 tmp;
 527                 int chansize, numchan;
 528
 529                 /* Get VRAM informations */
 530                 tmp = RREG32(mmMC_ARB_RAMCFG);
 531                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 532                         chansize = 64;
 533                 } else {
 534                         chansize = 32;
 535                 }
 536                 tmp = RREG32(mmMC_SHARED_CHMAP);
 537                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 538                 case 0:
 539                 default:
 540                         numchan = 1;
 541                         break;
 542                 case 1:
 543                         numchan = 2;
 544                         break;
 545                 case 2:
 546                         numchan = 4;
 547                         break;
 548                 case 3:
 549                         numchan = 8;
 550                         break;
 551                 case 4:
 552                         numchan = 3;
 553                         break;
 554                 case 5:
 555                         numchan = 6;
 556                         break;
 557                 case 6:
 558                         numchan = 10;
 559                         break;
 560                 case 7:
 561                         numchan = 12;
 562                         break;
 563                 case 8:
 564                         numchan = 16;
 565                         break;
 566                 }
 567                 adev->mc.vram_width = numchan * chansize;
 568         }
 569         /* Could aper size report 0 ? */
 570         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 571         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 572         /* size in MB on si */
 573         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 574         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 575
 576 #ifdef CONFIG_X86_64
 577         if (adev->flags & AMD_IS_APU) {
 578                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 579                 adev->mc.aper_size = adev->mc.real_vram_size;
 580         }
 581 #endif
 582
 583         /* In case the PCI BAR is larger than the actual amount of vram */
 584         adev->mc.visible_vram_size = adev->mc.aper_size;
 585         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 586                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 587
 588         /* set the gart size */
 589         if (amdgpu_gart_size == -1) {
 590                 switch (adev->asic_type) {
 591                 case CHIP_POLARIS11: /* all engines support GPUVM */
 592                 case CHIP_POLARIS10: /* all engines support GPUVM */
 593                 case CHIP_POLARIS12: /* all engines support GPUVM */
 594                 default:
 595                         adev->mc.gart_size = 256ULL << 20;
 596                         break;
 597                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 598                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 599                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 600                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 601                         adev->mc.gart_size = 1024ULL << 20;
 602                         break;
 603                 }
 604         } else {
 605                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 606         }
 607
 608         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 609
 610         return 0;
 611 }
 612
 613 /*
 614  * GART
 615  * VMID 0 is the physical GPU addresses as used by the kernel.
 616  * VMIDs 1-15 are used for userspace clients and are handled
 617  * by the amdgpu vm/hsa code.
 618  */
 619
 620 /**
 621  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 622  *
 623  * @adev: amdgpu_device pointer
 624  * @vmid: vm instance to flush
 625  *
 626  * Flush the TLB for the requested page table (CIK).
 627  */
 628 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 629                                         uint32_t vmid)
 630 {
 631         /* flush hdp cache */
 632         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 633
 634         /* bits 0-15 are the VM contexts0-15 */
 635         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 636 }
 637
 638 /**
 639  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 640  *
 641  * @adev: amdgpu_device pointer
 642  * @cpu_pt_addr: cpu address of the page table
 643  * @gpu_page_idx: entry in the page table to update
 644  * @addr: dst addr to write into pte/pde
 645  * @flags: access flags
 646  *
 647  * Update the page tables using the CPU.
 648  */
 649 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 650                                      void *cpu_pt_addr,
 651                                      uint32_t gpu_page_idx,
 652                                      uint64_t addr,
 653                                      uint64_t flags)
 654 {
 655         void __iomem *ptr = (void *)cpu_pt_addr;
 656         uint64_t value;
 657
 658         /*
 659          * PTE format on VI:
 660          * 63:40 reserved
 661          * 39:12 4k physical page base address
 662          * 11:7 fragment
 663          * 6 write
 664          * 5 read
 665          * 4 exe
 666          * 3 reserved
 667          * 2 snooped
 668          * 1 system
 669          * 0 valid
 670          *
 671          * PDE format on VI:
 672          * 63:59 block fragment size
 673          * 58:40 reserved
 674          * 39:1 physical base address of PTE
 675          * bits 5:1 must be 0.
 676          * 0 valid
 677          */
 678         value = addr & 0x000000FFFFFFF000ULL;
 679         value |= flags;
 680         writeq(value, ptr + (gpu_page_idx * 8));
 681
 682         return 0;
 683 }
 684
 685 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 686                                           uint32_t flags)
 687 {
 688         uint64_t pte_flag = 0;
 689
 690         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 691                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 692         if (flags & AMDGPU_VM_PAGE_READABLE)
 693                 pte_flag |= AMDGPU_PTE_READABLE;
 694         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 695                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 696         if (flags & AMDGPU_VM_PAGE_PRT)
 697                 pte_flag |= AMDGPU_PTE_PRT;
 698
 699         return pte_flag;
 700 }
 701
 702 static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 703 {
 704         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 705         return addr;
 706 }
 707
 708 /**
 709  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 710  *
 711  * @adev: amdgpu_device pointer
 712  * @value: true redirects VM faults to the default page
 713  */
 714 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 715                                               bool value)
 716 {
 717         u32 tmp;
 718
 719         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 720         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 721                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 722         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 723                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 724         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 725                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 726         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 727                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 728         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 729                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 730         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 731                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 732         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 733                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 734         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 735 }
 736
 737 /**
 738  * gmc_v8_0_set_prt - set PRT VM fault
 739  *
 740  * @adev: amdgpu_device pointer
 741  * @enable: enable/disable VM fault handling for PRT
 742 */
 743 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 744 {
 745         u32 tmp;
 746
 747         if (enable && !adev->mc.prt_warning) {
 748                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 749                 adev->mc.prt_warning = true;
 750         }
 751
 752         tmp = RREG32(mmVM_PRT_CNTL);
 753         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 754                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 755         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 756                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 757         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 758                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 759         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 760                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 761         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 762                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 763         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 764                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 765         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 766                             MASK_PDE0_FAULT, enable);
 767         WREG32(mmVM_PRT_CNTL, tmp);
 768
 769         if (enable) {
 770                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 771                 uint32_t high = adev->vm_manager.max_pfn;
 772
 773                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 774                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 775                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 776                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 777                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 778                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 779                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 780                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 781         } else {
 782                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 783                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 784                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 785                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 786                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 787                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 788                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 789                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 790         }
 791 }
 792
 793 /**
 794  * gmc_v8_0_gart_enable - gart enable
 795  *
 796  * @adev: amdgpu_device pointer
 797  *
 798  * This sets up the TLBs, programs the page tables for VMID0,
 799  * sets up the hw for VMIDs 1-15 which are allocated on
 800  * demand, and sets up the global locations for the LDS, GDS,
 801  * and GPUVM for FSA64 clients (CIK).
 802  * Returns 0 for success, errors for failure.
 803  */
 804 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 805 {
 806         int r, i;
 807         u32 tmp, field;
 808
 809         if (adev->gart.robj == NULL) {
 810                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 811                 return -EINVAL;
 812         }
 813         r = amdgpu_gart_table_vram_pin(adev);
 814         if (r)
 815                 return r;
 816         /* Setup TLB control */
 817         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 818         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 819         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 820         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 821         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 822         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 823         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 824         /* Setup L2 cache */
 825         tmp = RREG32(mmVM_L2_CNTL);
 826         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 827         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 828         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 829         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 830         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 831         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 832         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 833         WREG32(mmVM_L2_CNTL, tmp);
 834         tmp = RREG32(mmVM_L2_CNTL2);
 835         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 836         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 837         WREG32(mmVM_L2_CNTL2, tmp);
 838
 839         field = adev->vm_manager.fragment_size;
 840         tmp = RREG32(mmVM_L2_CNTL3);
 841         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 842         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 843         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 844         WREG32(mmVM_L2_CNTL3, tmp);
 845         /* XXX: set to enable PTE/PDE in system memory */
 846         tmp = RREG32(mmVM_L2_CNTL4);
 847         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 848         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 849         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 850         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 851         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 852         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 853         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 854         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 855         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 856         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 857         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 858         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 859         WREG32(mmVM_L2_CNTL4, tmp);
 860         /* setup context0 */
 861         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 862         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 863         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 864         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 865                         (u32)(adev->dummy_page.addr >> 12));
 866         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 867         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 868         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 869         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 870         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 871         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 872
 873         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 874         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 875         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 876
 877         /* empty context1-15 */
 878         /* FIXME start with 4G, once using 2 level pt switch to full
 879          * vm size space
 880          */
 881         /* set vm size, must be a multiple of 4 */
 882         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 883         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 884         for (i = 1; i < 16; i++) {
 885                 if (i < 8)
 886                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 887                                adev->gart.table_addr >> 12);
 888                 else
 889                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 890                                adev->gart.table_addr >> 12);
 891         }
 892
 893         /* enable context1-15 */
 894         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 895                (u32)(adev->dummy_page.addr >> 12));
 896         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 897         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 898         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 899         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 900         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 901         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 902         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 903         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 904         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 905         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 906         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 907         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 908                             adev->vm_manager.block_size - 9);
 909         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 910         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 911                 gmc_v8_0_set_fault_enable_default(adev, false);
 912         else
 913                 gmc_v8_0_set_fault_enable_default(adev, true);
 914
 915         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 916         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 917                  (unsigned)(adev->mc.gart_size >> 20),
 918                  (unsigned long long)adev->gart.table_addr);
 919         adev->gart.ready = true;
 920         return 0;
 921 }
 922
 923 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 924 {
 925         int r;
 926
 927         if (adev->gart.robj) {
 928                 WARN(1, "R600 PCIE GART already initialized\n");
 929                 return 0;
 930         }
 931         /* Initialize common gart structure */
 932         r = amdgpu_gart_init(adev);
 933         if (r)
 934                 return r;
 935         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 936         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 937         return amdgpu_gart_table_vram_alloc(adev);
 938 }
 939
 940 /**
 941  * gmc_v8_0_gart_disable - gart disable
 942  *
 943  * @adev: amdgpu_device pointer
 944  *
 945  * This disables all VM page table (CIK).
 946  */
 947 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 948 {
 949         u32 tmp;
 950
 951         /* Disable all tables */
 952         WREG32(mmVM_CONTEXT0_CNTL, 0);
 953         WREG32(mmVM_CONTEXT1_CNTL, 0);
 954         /* Setup TLB control */
 955         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 956         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 957         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 958         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 959         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 960         /* Setup L2 cache */
 961         tmp = RREG32(mmVM_L2_CNTL);
 962         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 963         WREG32(mmVM_L2_CNTL, tmp);
 964         WREG32(mmVM_L2_CNTL2, 0);
 965         amdgpu_gart_table_vram_unpin(adev);
 966 }
 967
 968 /**
 969  * gmc_v8_0_gart_fini - vm fini callback
 970  *
 971  * @adev: amdgpu_device pointer
 972  *
 973  * Tears down the driver GART/VM setup (CIK).
 974  */
 975 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 976 {
 977         amdgpu_gart_table_vram_free(adev);
 978         amdgpu_gart_fini(adev);
 979 }
 980
 981 /**
 982  * gmc_v8_0_vm_decode_fault - print human readable fault info
 983  *
 984  * @adev: amdgpu_device pointer
 985  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 986  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 987  *
 988  * Print human readable fault information (CIK).
 989  */
 990 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 991                                      u32 status, u32 addr, u32 mc_client)
 992 {
 993         u32 mc_id;
 994         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 995         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 996                                         PROTECTIONS);
 997         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 998                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 999
1000         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1001                               MEMORY_CLIENT_ID);
1002
1003         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1004                protections, vmid, addr,
1005                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1006                              MEMORY_CLIENT_RW) ?
1007                "write" : "read", block, mc_client, mc_id);
1008 }
1009
1010 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1011 {
1012         switch (mc_seq_vram_type) {
1013         case MC_SEQ_MISC0__MT__GDDR1:
1014                 return AMDGPU_VRAM_TYPE_GDDR1;
1015         case MC_SEQ_MISC0__MT__DDR2:
1016                 return AMDGPU_VRAM_TYPE_DDR2;
1017         case MC_SEQ_MISC0__MT__GDDR3:
1018                 return AMDGPU_VRAM_TYPE_GDDR3;
1019         case MC_SEQ_MISC0__MT__GDDR4:
1020                 return AMDGPU_VRAM_TYPE_GDDR4;
1021         case MC_SEQ_MISC0__MT__GDDR5:
1022                 return AMDGPU_VRAM_TYPE_GDDR5;
1023         case MC_SEQ_MISC0__MT__HBM:
1024                 return AMDGPU_VRAM_TYPE_HBM;
1025         case MC_SEQ_MISC0__MT__DDR3:
1026                 return AMDGPU_VRAM_TYPE_DDR3;
1027         default:
1028                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1029         }
1030 }
1031
1032 static int gmc_v8_0_early_init(void *handle)
1033 {
1034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036         gmc_v8_0_set_gart_funcs(adev);
1037         gmc_v8_0_set_irq_funcs(adev);
1038
1039         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
1040         adev->mc.shared_aperture_end =
1041                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
1042         adev->mc.private_aperture_start =
1043                 adev->mc.shared_aperture_end + 1;
1044         adev->mc.private_aperture_end =
1045                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
1046
1047         return 0;
1048 }
1049
1050 static int gmc_v8_0_late_init(void *handle)
1051 {
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1055                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
1056         else
1057                 return 0;
1058 }
1059
1060 #define mmMC_SEQ_MISC0_FIJI 0xA71
1061
1062 static int gmc_v8_0_sw_init(void *handle)
1063 {
1064         int r;
1065         int dma_bits;
1066         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067
1068         if (adev->flags & AMD_IS_APU) {
1069                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1070         } else {
1071                 u32 tmp;
1072
1073                 if (adev->asic_type == CHIP_FIJI)
1074                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1075                 else
1076                         tmp = RREG32(mmMC_SEQ_MISC0);
1077                 tmp &= MC_SEQ_MISC0__MT__MASK;
1078                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1079         }
1080
1081         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
1082         if (r)
1083                 return r;
1084
1085         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
1086         if (r)
1087                 return r;
1088
1089         /* Adjust VM size here.
1090          * Currently set to 4GB ((1 << 20) 4k pages).
1091          * Max GPUVM size for cayman and SI is 40 bits.
1092          */
1093         amdgpu_vm_adjust_size(adev, 64, 4);
1094         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
1095
1096         /* Set the internal MC address mask
1097          * This is the max address of the GPU's
1098          * internal address space.
1099          */
1100         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1101
1102         adev->mc.stolen_size = 256 * 1024;
1103
1104         /* set DMA mask + need_dma32 flags.
1105          * PCIE - can handle 40-bits.
1106          * IGP - can handle 40-bits
1107          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1108          */
1109         adev->need_dma32 = false;
1110         dma_bits = adev->need_dma32 ? 32 : 40;
1111         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1112         if (r) {
1113                 adev->need_dma32 = true;
1114                 dma_bits = 32;
1115                 pr_warn("amdgpu: No suitable DMA available\n");
1116         }
1117         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1118         if (r) {
1119                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1120                 pr_warn("amdgpu: No coherent DMA available\n");
1121         }
1122
1123         r = gmc_v8_0_init_microcode(adev);
1124         if (r) {
1125                 DRM_ERROR("Failed to load mc firmware!\n");
1126                 return r;
1127         }
1128
1129         r = gmc_v8_0_mc_init(adev);
1130         if (r)
1131                 return r;
1132
1133         /* Memory manager */
1134         r = amdgpu_bo_init(adev);
1135         if (r)
1136                 return r;
1137
1138         r = gmc_v8_0_gart_init(adev);
1139         if (r)
1140                 return r;
1141
1142         /*
1143          * number of VMs
1144          * VMID 0 is reserved for System
1145          * amdgpu graphics/compute will use VMIDs 1-7
1146          * amdkfd will use VMIDs 8-15
1147          */
1148         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1149         adev->vm_manager.num_level = 1;
1150         amdgpu_vm_manager_init(adev);
1151
1152         /* base offset of vram pages */
1153         if (adev->flags & AMD_IS_APU) {
1154                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1155
1156                 tmp <<= 22;
1157                 adev->vm_manager.vram_base_offset = tmp;
1158         } else {
1159                 adev->vm_manager.vram_base_offset = 0;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int gmc_v8_0_sw_fini(void *handle)
1166 {
1167         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1168
1169         amdgpu_vm_manager_fini(adev);
1170         gmc_v8_0_gart_fini(adev);
1171         amdgpu_gem_force_release(adev);
1172         amdgpu_bo_fini(adev);
1173
1174         return 0;
1175 }
1176
1177 static int gmc_v8_0_hw_init(void *handle)
1178 {
1179         int r;
1180         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1181
1182         gmc_v8_0_init_golden_registers(adev);
1183
1184         gmc_v8_0_mc_program(adev);
1185
1186         if (adev->asic_type == CHIP_TONGA) {
1187                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1188                 if (r) {
1189                         DRM_ERROR("Failed to load MC firmware!\n");
1190                         return r;
1191                 }
1192         } else if (adev->asic_type == CHIP_POLARIS11 ||
1193                         adev->asic_type == CHIP_POLARIS10 ||
1194                         adev->asic_type == CHIP_POLARIS12) {
1195                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1196                 if (r) {
1197                         DRM_ERROR("Failed to load MC firmware!\n");
1198                         return r;
1199                 }
1200         }
1201
1202         r = gmc_v8_0_gart_enable(adev);
1203         if (r)
1204                 return r;
1205
1206         return r;
1207 }
1208
1209 static int gmc_v8_0_hw_fini(void *handle)
1210 {
1211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1212
1213         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1214         gmc_v8_0_gart_disable(adev);
1215
1216         return 0;
1217 }
1218
1219 static int gmc_v8_0_suspend(void *handle)
1220 {
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223         gmc_v8_0_hw_fini(adev);
1224
1225         return 0;
1226 }
1227
1228 static int gmc_v8_0_resume(void *handle)
1229 {
1230         int r;
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         r = gmc_v8_0_hw_init(adev);
1234         if (r)
1235                 return r;
1236
1237         amdgpu_vm_reset_all_ids(adev);
1238
1239         return 0;
1240 }
1241
1242 static bool gmc_v8_0_is_idle(void *handle)
1243 {
1244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1245         u32 tmp = RREG32(mmSRBM_STATUS);
1246
1247         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1248                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1249                 return false;
1250
1251         return true;
1252 }
1253
1254 static int gmc_v8_0_wait_for_idle(void *handle)
1255 {
1256         unsigned i;
1257         u32 tmp;
1258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1259
1260         for (i = 0; i < adev->usec_timeout; i++) {
1261                 /* read MC_STATUS */
1262                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1263                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1264                                                SRBM_STATUS__MCC_BUSY_MASK |
1265                                                SRBM_STATUS__MCD_BUSY_MASK |
1266                                                SRBM_STATUS__VMC_BUSY_MASK |
1267                                                SRBM_STATUS__VMC1_BUSY_MASK);
1268                 if (!tmp)
1269                         return 0;
1270                 udelay(1);
1271         }
1272         return -ETIMEDOUT;
1273
1274 }
1275
1276 static bool gmc_v8_0_check_soft_reset(void *handle)
1277 {
1278         u32 srbm_soft_reset = 0;
1279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280         u32 tmp = RREG32(mmSRBM_STATUS);
1281
1282         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1283                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1284                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1285
1286         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1287                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1288                 if (!(adev->flags & AMD_IS_APU))
1289                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1290                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1291         }
1292         if (srbm_soft_reset) {
1293                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1294                 return true;
1295         } else {
1296                 adev->mc.srbm_soft_reset = 0;
1297                 return false;
1298         }
1299 }
1300
1301 static int gmc_v8_0_pre_soft_reset(void *handle)
1302 {
1303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304
1305         if (!adev->mc.srbm_soft_reset)
1306                 return 0;
1307
1308         gmc_v8_0_mc_stop(adev);
1309         if (gmc_v8_0_wait_for_idle(adev)) {
1310                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int gmc_v8_0_soft_reset(void *handle)
1317 {
1318         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1319         u32 srbm_soft_reset;
1320
1321         if (!adev->mc.srbm_soft_reset)
1322                 return 0;
1323         srbm_soft_reset = adev->mc.srbm_soft_reset;
1324
1325         if (srbm_soft_reset) {
1326                 u32 tmp;
1327
1328                 tmp = RREG32(mmSRBM_SOFT_RESET);
1329                 tmp |= srbm_soft_reset;
1330                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1331                 WREG32(mmSRBM_SOFT_RESET, tmp);
1332                 tmp = RREG32(mmSRBM_SOFT_RESET);
1333
1334                 udelay(50);
1335
1336                 tmp &= ~srbm_soft_reset;
1337                 WREG32(mmSRBM_SOFT_RESET, tmp);
1338                 tmp = RREG32(mmSRBM_SOFT_RESET);
1339
1340                 /* Wait a little for things to settle down */
1341                 udelay(50);
1342         }
1343
1344         return 0;
1345 }
1346
1347 static int gmc_v8_0_post_soft_reset(void *handle)
1348 {
1349         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350
1351         if (!adev->mc.srbm_soft_reset)
1352                 return 0;
1353
1354         gmc_v8_0_mc_resume(adev);
1355         return 0;
1356 }
1357
1358 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1359                                              struct amdgpu_irq_src *src,
1360                                              unsigned type,
1361                                              enum amdgpu_interrupt_state state)
1362 {
1363         u32 tmp;
1364         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1365                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1366                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1367                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1368                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1369                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1370                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1371
1372         switch (state) {
1373         case AMDGPU_IRQ_STATE_DISABLE:
1374                 /* system context */
1375                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1376                 tmp &= ~bits;
1377                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1378                 /* VMs */
1379                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1380                 tmp &= ~bits;
1381                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1382                 break;
1383         case AMDGPU_IRQ_STATE_ENABLE:
1384                 /* system context */
1385                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1386                 tmp |= bits;
1387                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1388                 /* VMs */
1389                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1390                 tmp |= bits;
1391                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1392                 break;
1393         default:
1394                 break;
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1401                                       struct amdgpu_irq_src *source,
1402                                       struct amdgpu_iv_entry *entry)
1403 {
1404         u32 addr, status, mc_client;
1405
1406         if (amdgpu_sriov_vf(adev)) {
1407                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1408                         entry->src_id, entry->src_data[0]);
1409                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1410                 return 0;
1411         }
1412
1413         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1414         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1415         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1416         /* reset addr and status */
1417         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1418
1419         if (!addr && !status)
1420                 return 0;
1421
1422         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1423                 gmc_v8_0_set_fault_enable_default(adev, false);
1424
1425         if (printk_ratelimit()) {
1426                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1427                         entry->src_id, entry->src_data[0]);
1428                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1429                         addr);
1430                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1431                         status);
1432                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1439                                                      bool enable)
1440 {
1441         uint32_t data;
1442
1443         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1444                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1445                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1446                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1447
1448                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1449                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1450                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1451
1452                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1453                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1454                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1455
1456                 data = RREG32(mmMC_XPB_CLK_GAT);
1457                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1458                 WREG32(mmMC_XPB_CLK_GAT, data);
1459
1460                 data = RREG32(mmATC_MISC_CG);
1461                 data |= ATC_MISC_CG__ENABLE_MASK;
1462                 WREG32(mmATC_MISC_CG, data);
1463
1464                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1465                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1466                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1467
1468                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1469                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1470                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1471
1472                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1473                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1474                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1475
1476                 data = RREG32(mmVM_L2_CG);
1477                 data |= VM_L2_CG__ENABLE_MASK;
1478                 WREG32(mmVM_L2_CG, data);
1479         } else {
1480                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1481                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1482                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1483
1484                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1485                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1486                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1487
1488                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1489                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1490                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1491
1492                 data = RREG32(mmMC_XPB_CLK_GAT);
1493                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1494                 WREG32(mmMC_XPB_CLK_GAT, data);
1495
1496                 data = RREG32(mmATC_MISC_CG);
1497                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1498                 WREG32(mmATC_MISC_CG, data);
1499
1500                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1501                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1502                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1503
1504                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1505                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1506                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1507
1508                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1509                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1510                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1511
1512                 data = RREG32(mmVM_L2_CG);
1513                 data &= ~VM_L2_CG__ENABLE_MASK;
1514                 WREG32(mmVM_L2_CG, data);
1515         }
1516 }
1517
1518 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1519                                        bool enable)
1520 {
1521         uint32_t data;
1522
1523         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1524                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1525                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1526                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1527
1528                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1529                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1530                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1531
1532                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1533                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1534                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1535
1536                 data = RREG32(mmMC_XPB_CLK_GAT);
1537                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1538                 WREG32(mmMC_XPB_CLK_GAT, data);
1539
1540                 data = RREG32(mmATC_MISC_CG);
1541                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1542                 WREG32(mmATC_MISC_CG, data);
1543
1544                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1545                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1546                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1547
1548                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1549                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1550                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1551
1552                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1553                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1554                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1555
1556                 data = RREG32(mmVM_L2_CG);
1557                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1558                 WREG32(mmVM_L2_CG, data);
1559         } else {
1560                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1561                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1562                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1563
1564                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1565                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1566                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1567
1568                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1569                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1570                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1571
1572                 data = RREG32(mmMC_XPB_CLK_GAT);
1573                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1574                 WREG32(mmMC_XPB_CLK_GAT, data);
1575
1576                 data = RREG32(mmATC_MISC_CG);
1577                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1578                 WREG32(mmATC_MISC_CG, data);
1579
1580                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1581                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1582                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1583
1584                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1585                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1586                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1587
1588                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1589                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1590                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1591
1592                 data = RREG32(mmVM_L2_CG);
1593                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1594                 WREG32(mmVM_L2_CG, data);
1595         }
1596 }
1597
1598 static int gmc_v8_0_set_clockgating_state(void *handle,
1599                                           enum amd_clockgating_state state)
1600 {
1601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1602
1603         if (amdgpu_sriov_vf(adev))
1604                 return 0;
1605
1606         switch (adev->asic_type) {
1607         case CHIP_FIJI:
1608                 fiji_update_mc_medium_grain_clock_gating(adev,
1609                                 state == AMD_CG_STATE_GATE);
1610                 fiji_update_mc_light_sleep(adev,
1611                                 state == AMD_CG_STATE_GATE);
1612                 break;
1613         default:
1614                 break;
1615         }
1616         return 0;
1617 }
1618
1619 static int gmc_v8_0_set_powergating_state(void *handle,
1620                                           enum amd_powergating_state state)
1621 {
1622         return 0;
1623 }
1624
1625 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1626 {
1627         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1628         int data;
1629
1630         if (amdgpu_sriov_vf(adev))
1631                 *flags = 0;
1632
1633         /* AMD_CG_SUPPORT_MC_MGCG */
1634         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1635         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1636                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1637
1638         /* AMD_CG_SUPPORT_MC_LS */
1639         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1640                 *flags |= AMD_CG_SUPPORT_MC_LS;
1641 }
1642
1643 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1644         .name = "gmc_v8_0",
1645         .early_init = gmc_v8_0_early_init,
1646         .late_init = gmc_v8_0_late_init,
1647         .sw_init = gmc_v8_0_sw_init,
1648         .sw_fini = gmc_v8_0_sw_fini,
1649         .hw_init = gmc_v8_0_hw_init,
1650         .hw_fini = gmc_v8_0_hw_fini,
1651         .suspend = gmc_v8_0_suspend,
1652         .resume = gmc_v8_0_resume,
1653         .is_idle = gmc_v8_0_is_idle,
1654         .wait_for_idle = gmc_v8_0_wait_for_idle,
1655         .check_soft_reset = gmc_v8_0_check_soft_reset,
1656         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1657         .soft_reset = gmc_v8_0_soft_reset,
1658         .post_soft_reset = gmc_v8_0_post_soft_reset,
1659         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1660         .set_powergating_state = gmc_v8_0_set_powergating_state,
1661         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1662 };
1663
1664 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1665         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1666         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1667         .set_prt = gmc_v8_0_set_prt,
1668         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1669         .get_vm_pde = gmc_v8_0_get_vm_pde
1670 };
1671
1672 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1673         .set = gmc_v8_0_vm_fault_interrupt_state,
1674         .process = gmc_v8_0_process_interrupt,
1675 };
1676
1677 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1678 {
1679         if (adev->gart.gart_funcs == NULL)
1680                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1681 }
1682
1683 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1684 {
1685         adev->mc.vm_fault.num_types = 1;
1686         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1687 }
1688
1689 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1690 {
1691         .type = AMD_IP_BLOCK_TYPE_GMC,
1692         .major = 8,
1693         .minor = 0,
1694         .rev = 0,
1695         .funcs = &gmc_v8_0_ip_funcs,
1696 };
1697
1698 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1699 {
1700         .type = AMD_IP_BLOCK_TYPE_GMC,
1701         .major = 8,
1702         .minor = 1,
1703         .rev = 0,
1704         .funcs = &gmc_v8_0_ip_funcs,
1705 };
1706
1707 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1708 {
1709         .type = AMD_IP_BLOCK_TYPE_GMC,
1710         .major = 8,
1711         .minor = 5,
1712         .rev = 0,
1713         .funcs = &gmc_v8_0_ip_funcs,
1714 };