2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include <drm/drm_cache.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_amdkfd.h"
33 #include "bif/bif_4_1_d.h"
34 #include "bif/bif_4_1_sh_mask.h"
36 #include "gmc/gmc_7_1_d.h"
37 #include "gmc/gmc_7_1_sh_mask.h"
39 #include "oss/oss_2_0_d.h"
40 #include "oss/oss_2_0_sh_mask.h"
42 #include "dce/dce_8_0_d.h"
43 #include "dce/dce_8_0_sh_mask.h"
45 #include "amdgpu_atombios.h"
47 #include "ivsrcid/ivsrcid_vislands30.h"
49 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
50 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
51 static int gmc_v7_0_wait_for_idle(void *handle);
55 static const u32 golden_settings_iceland_a11[] =
57 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
58 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
59 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
60 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
63 static const u32 iceland_mgcg_cgcg_init[] =
65 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
68 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
70 switch (adev->asic_type) {
72 amdgpu_device_program_register_sequence(adev,
73 iceland_mgcg_cgcg_init,
74 ARRAY_SIZE(iceland_mgcg_cgcg_init));
75 amdgpu_device_program_register_sequence(adev,
76 golden_settings_iceland_a11,
77 ARRAY_SIZE(golden_settings_iceland_a11));
84 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
88 gmc_v7_0_wait_for_idle((void *)adev);
90 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
91 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
92 /* Block CPU access */
93 WREG32(mmBIF_FB_EN, 0);
95 blackout = REG_SET_FIELD(blackout,
96 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
97 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
99 /* wait for the MC to settle */
103 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
107 /* unblackout the MC */
108 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
109 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
110 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
111 /* allow CPU access */
112 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
113 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
114 WREG32(mmBIF_FB_EN, tmp);
118 * gmc_v7_0_init_microcode - load ucode images from disk
120 * @adev: amdgpu_device pointer
122 * Use the firmware interface to load the ucode images into
123 * the driver (not loaded into hw).
124 * Returns 0 on success, error on failure.
126 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
128 const char *chip_name;
134 switch (adev->asic_type) {
136 chip_name = "bonaire";
139 chip_name = "hawaii";
151 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
153 err = reject_firmware(&adev->gmc.fw, fw_name, adev->dev);
156 err = amdgpu_ucode_validate(adev->gmc.fw);
160 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
161 release_firmware(adev->gmc.fw);
168 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
170 * @adev: amdgpu_device pointer
172 * Load the GDDR MC ucode into the hw (CIK).
173 * Returns 0 on success, error on failure.
175 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
177 const struct mc_firmware_header_v1_0 *hdr;
178 const __le32 *fw_data = NULL;
179 const __le32 *io_mc_regs = NULL;
181 int i, ucode_size, regs_size;
186 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
187 amdgpu_ucode_print_mc_hdr(&hdr->header);
189 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
190 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
191 io_mc_regs = (const __le32 *)
192 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
193 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
194 fw_data = (const __le32 *)
195 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
197 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
200 /* reset the engine and set to writable */
201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
202 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
204 /* load mc io regs */
205 for (i = 0; i < regs_size; i++) {
206 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
207 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
209 /* load the MC ucode */
210 for (i = 0; i < ucode_size; i++)
211 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
213 /* put the engine back into the active state */
214 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
215 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
216 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
218 /* wait for training to complete */
219 for (i = 0; i < adev->usec_timeout; i++) {
220 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
221 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
225 for (i = 0; i < adev->usec_timeout; i++) {
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
236 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
237 struct amdgpu_gmc *mc)
239 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
242 amdgpu_device_vram_location(adev, &adev->gmc, base);
243 amdgpu_device_gart_location(adev, mc);
247 * gmc_v7_0_mc_program - program the GPU memory controller
249 * @adev: amdgpu_device pointer
251 * Set the location of vram, gart, and AGP in the GPU's
252 * physical address space (CIK).
254 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
260 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
261 WREG32((0xb05 + j), 0x00000000);
262 WREG32((0xb06 + j), 0x00000000);
263 WREG32((0xb07 + j), 0x00000000);
264 WREG32((0xb08 + j), 0x00000000);
265 WREG32((0xb09 + j), 0x00000000);
267 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
269 if (gmc_v7_0_wait_for_idle((void *)adev)) {
270 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
272 if (adev->mode_info.num_crtc) {
273 /* Lockout access through VGA aperture*/
274 tmp = RREG32(mmVGA_HDP_CONTROL);
275 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
276 WREG32(mmVGA_HDP_CONTROL, tmp);
278 /* disable VGA render */
279 tmp = RREG32(mmVGA_RENDER_CONTROL);
280 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
281 WREG32(mmVGA_RENDER_CONTROL, tmp);
283 /* Update configuration */
284 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
285 adev->gmc.vram_start >> 12);
286 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
287 adev->gmc.vram_end >> 12);
288 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
289 adev->vram_scratch.gpu_addr >> 12);
290 WREG32(mmMC_VM_AGP_BASE, 0);
291 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
292 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
293 if (gmc_v7_0_wait_for_idle((void *)adev)) {
294 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
297 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
299 tmp = RREG32(mmHDP_MISC_CNTL);
300 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
301 WREG32(mmHDP_MISC_CNTL, tmp);
303 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
304 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
308 * gmc_v7_0_mc_init - initialize the memory controller driver params
310 * @adev: amdgpu_device pointer
312 * Look up the amount of vram, vram width, and decide how to place
313 * vram and gart within the GPU's physical address space (CIK).
314 * Returns 0 for success.
316 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
320 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
321 if (!adev->gmc.vram_width) {
323 int chansize, numchan;
325 /* Get VRAM informations */
326 tmp = RREG32(mmMC_ARB_RAMCFG);
327 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
332 tmp = RREG32(mmMC_SHARED_CHMAP);
333 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
363 adev->gmc.vram_width = numchan * chansize;
365 /* size in MB on si */
366 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
367 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
369 if (!(adev->flags & AMD_IS_APU)) {
370 r = amdgpu_device_resize_fb_bar(adev);
374 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
375 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
378 if (adev->flags & AMD_IS_APU) {
379 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
380 adev->gmc.aper_size = adev->gmc.real_vram_size;
384 /* In case the PCI BAR is larger than the actual amount of vram */
385 adev->gmc.visible_vram_size = adev->gmc.aper_size;
386 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
387 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
389 /* set the gart size */
390 if (amdgpu_gart_size == -1) {
391 switch (adev->asic_type) {
392 case CHIP_TOPAZ: /* no MM engines */
394 adev->gmc.gart_size = 256ULL << 20;
396 #ifdef CONFIG_DRM_AMDGPU_CIK
397 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
398 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
399 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
400 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
401 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
402 adev->gmc.gart_size = 1024ULL << 20;
407 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
410 gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
417 * VMID 0 is the physical GPU addresses as used by the kernel.
418 * VMIDs 1-15 are used for userspace clients and are handled
419 * by the amdgpu vm/hsa code.
423 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
425 * @adev: amdgpu_device pointer
426 * @vmid: vm instance to flush
428 * Flush the TLB for the requested page table (CIK).
430 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
432 /* bits 0-15 are the VM contexts0-15 */
433 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
436 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
437 unsigned vmid, uint64_t pd_addr)
442 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
444 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
445 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
447 /* bits 0-15 are the VM contexts0-15 */
448 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
453 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
456 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
460 * gmc_v7_0_set_pte_pde - update the page tables using MMIO
462 * @adev: amdgpu_device pointer
463 * @cpu_pt_addr: cpu address of the page table
464 * @gpu_page_idx: entry in the page table to update
465 * @addr: dst addr to write into pte/pde
466 * @flags: access flags
468 * Update the page tables using the CPU.
470 static int gmc_v7_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
471 uint32_t gpu_page_idx, uint64_t addr,
474 void __iomem *ptr = (void *)cpu_pt_addr;
477 value = addr & 0xFFFFFFFFFFFFF000ULL;
479 writeq(value, ptr + (gpu_page_idx * 8));
484 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
487 uint64_t pte_flag = 0;
489 if (flags & AMDGPU_VM_PAGE_READABLE)
490 pte_flag |= AMDGPU_PTE_READABLE;
491 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
492 pte_flag |= AMDGPU_PTE_WRITEABLE;
493 if (flags & AMDGPU_VM_PAGE_PRT)
494 pte_flag |= AMDGPU_PTE_PRT;
499 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
500 uint64_t *addr, uint64_t *flags)
502 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
506 * gmc_v8_0_set_fault_enable_default - update VM fault handling
508 * @adev: amdgpu_device pointer
509 * @value: true redirects VM faults to the default page
511 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
516 tmp = RREG32(mmVM_CONTEXT1_CNTL);
517 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
518 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
519 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
520 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
521 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
522 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
523 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
524 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
526 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
528 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
529 WREG32(mmVM_CONTEXT1_CNTL, tmp);
533 * gmc_v7_0_set_prt - set PRT VM fault
535 * @adev: amdgpu_device pointer
536 * @enable: enable/disable VM fault handling for PRT
538 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
542 if (enable && !adev->gmc.prt_warning) {
543 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
544 adev->gmc.prt_warning = true;
547 tmp = RREG32(mmVM_PRT_CNTL);
548 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
549 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
550 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
551 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
552 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
553 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
554 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
555 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
556 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
557 L2_CACHE_STORE_INVALID_ENTRIES, enable);
558 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
559 L1_TLB_STORE_INVALID_ENTRIES, enable);
560 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
561 MASK_PDE0_FAULT, enable);
562 WREG32(mmVM_PRT_CNTL, tmp);
565 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
566 uint32_t high = adev->vm_manager.max_pfn -
567 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
569 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
570 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
571 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
572 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
573 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
574 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
575 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
576 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
578 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
579 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
580 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
581 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
582 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
583 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
584 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
585 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
590 * gmc_v7_0_gart_enable - gart enable
592 * @adev: amdgpu_device pointer
594 * This sets up the TLBs, programs the page tables for VMID0,
595 * sets up the hw for VMIDs 1-15 which are allocated on
596 * demand, and sets up the global locations for the LDS, GDS,
597 * and GPUVM for FSA64 clients (CIK).
598 * Returns 0 for success, errors for failure.
600 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
605 if (adev->gart.robj == NULL) {
606 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
609 r = amdgpu_gart_table_vram_pin(adev);
612 /* Setup TLB control */
613 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
614 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
615 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
616 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
617 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
618 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
619 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
621 tmp = RREG32(mmVM_L2_CNTL);
622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
629 WREG32(mmVM_L2_CNTL, tmp);
630 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
632 WREG32(mmVM_L2_CNTL2, tmp);
634 field = adev->vm_manager.fragment_size;
635 tmp = RREG32(mmVM_L2_CNTL3);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
639 WREG32(mmVM_L2_CNTL3, tmp);
641 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
642 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
643 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
644 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
645 (u32)(adev->dummy_page_addr >> 12));
646 WREG32(mmVM_CONTEXT0_CNTL2, 0);
647 tmp = RREG32(mmVM_CONTEXT0_CNTL);
648 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
649 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
650 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
651 WREG32(mmVM_CONTEXT0_CNTL, tmp);
657 /* empty context1-15 */
658 /* FIXME start with 4G, once using 2 level pt switch to full
661 /* set vm size, must be a multiple of 4 */
662 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
663 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
664 for (i = 1; i < 16; i++) {
666 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
667 adev->gart.table_addr >> 12);
669 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
670 adev->gart.table_addr >> 12);
673 /* enable context1-15 */
674 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
675 (u32)(adev->dummy_page_addr >> 12));
676 WREG32(mmVM_CONTEXT1_CNTL2, 4);
677 tmp = RREG32(mmVM_CONTEXT1_CNTL);
678 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
681 adev->vm_manager.block_size - 9);
682 WREG32(mmVM_CONTEXT1_CNTL, tmp);
683 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
684 gmc_v7_0_set_fault_enable_default(adev, false);
686 gmc_v7_0_set_fault_enable_default(adev, true);
688 if (adev->asic_type == CHIP_KAVERI) {
689 tmp = RREG32(mmCHUB_CONTROL);
691 WREG32(mmCHUB_CONTROL, tmp);
694 gmc_v7_0_flush_gpu_tlb(adev, 0);
695 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
696 (unsigned)(adev->gmc.gart_size >> 20),
697 (unsigned long long)adev->gart.table_addr);
698 adev->gart.ready = true;
702 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
706 if (adev->gart.robj) {
707 WARN(1, "R600 PCIE GART already initialized\n");
710 /* Initialize common gart structure */
711 r = amdgpu_gart_init(adev);
714 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
715 adev->gart.gart_pte_flags = 0;
716 return amdgpu_gart_table_vram_alloc(adev);
720 * gmc_v7_0_gart_disable - gart disable
722 * @adev: amdgpu_device pointer
724 * This disables all VM page table (CIK).
726 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
730 /* Disable all tables */
731 WREG32(mmVM_CONTEXT0_CNTL, 0);
732 WREG32(mmVM_CONTEXT1_CNTL, 0);
733 /* Setup TLB control */
734 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
735 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
736 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
737 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
738 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
740 tmp = RREG32(mmVM_L2_CNTL);
741 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
742 WREG32(mmVM_L2_CNTL, tmp);
743 WREG32(mmVM_L2_CNTL2, 0);
744 amdgpu_gart_table_vram_unpin(adev);
748 * gmc_v7_0_vm_decode_fault - print human readable fault info
750 * @adev: amdgpu_device pointer
751 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
752 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
754 * Print human readable fault information (CIK).
756 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
757 u32 addr, u32 mc_client, unsigned pasid)
759 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
760 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
762 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
763 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
766 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
769 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
770 protections, vmid, pasid, addr,
771 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
773 "write" : "read", block, mc_client, mc_id);
777 static const u32 mc_cg_registers[] = {
778 mmMC_HUB_MISC_HUB_CG,
779 mmMC_HUB_MISC_SIP_CG,
783 mmMC_CITF_MISC_WR_CG,
784 mmMC_CITF_MISC_RD_CG,
785 mmMC_CITF_MISC_VM_CG,
789 static const u32 mc_cg_ls_en[] = {
790 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
791 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
792 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
793 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
794 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
795 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
796 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
797 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
798 VM_L2_CG__MEM_LS_ENABLE_MASK,
801 static const u32 mc_cg_en[] = {
802 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
803 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
804 MC_HUB_MISC_VM_CG__ENABLE_MASK,
805 MC_XPB_CLK_GAT__ENABLE_MASK,
806 ATC_MISC_CG__ENABLE_MASK,
807 MC_CITF_MISC_WR_CG__ENABLE_MASK,
808 MC_CITF_MISC_RD_CG__ENABLE_MASK,
809 MC_CITF_MISC_VM_CG__ENABLE_MASK,
810 VM_L2_CG__ENABLE_MASK,
813 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
819 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
820 orig = data = RREG32(mc_cg_registers[i]);
821 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
822 data |= mc_cg_ls_en[i];
824 data &= ~mc_cg_ls_en[i];
826 WREG32(mc_cg_registers[i], data);
830 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
836 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
837 orig = data = RREG32(mc_cg_registers[i]);
838 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
841 data &= ~mc_cg_en[i];
843 WREG32(mc_cg_registers[i], data);
847 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
852 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
854 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
855 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
856 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
857 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
858 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
860 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
861 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
862 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
863 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
867 WREG32_PCIE(ixPCIE_CNTL2, data);
870 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
875 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
877 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
878 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
880 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
883 WREG32(mmHDP_HOST_PATH_CNTL, data);
886 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
891 orig = data = RREG32(mmHDP_MEM_POWER_LS);
893 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
894 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
896 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
899 WREG32(mmHDP_MEM_POWER_LS, data);
902 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
904 switch (mc_seq_vram_type) {
905 case MC_SEQ_MISC0__MT__GDDR1:
906 return AMDGPU_VRAM_TYPE_GDDR1;
907 case MC_SEQ_MISC0__MT__DDR2:
908 return AMDGPU_VRAM_TYPE_DDR2;
909 case MC_SEQ_MISC0__MT__GDDR3:
910 return AMDGPU_VRAM_TYPE_GDDR3;
911 case MC_SEQ_MISC0__MT__GDDR4:
912 return AMDGPU_VRAM_TYPE_GDDR4;
913 case MC_SEQ_MISC0__MT__GDDR5:
914 return AMDGPU_VRAM_TYPE_GDDR5;
915 case MC_SEQ_MISC0__MT__HBM:
916 return AMDGPU_VRAM_TYPE_HBM;
917 case MC_SEQ_MISC0__MT__DDR3:
918 return AMDGPU_VRAM_TYPE_DDR3;
920 return AMDGPU_VRAM_TYPE_UNKNOWN;
924 static int gmc_v7_0_early_init(void *handle)
926 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
928 gmc_v7_0_set_gmc_funcs(adev);
929 gmc_v7_0_set_irq_funcs(adev);
931 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
932 adev->gmc.shared_aperture_end =
933 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
934 adev->gmc.private_aperture_start =
935 adev->gmc.shared_aperture_end + 1;
936 adev->gmc.private_aperture_end =
937 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
942 static int gmc_v7_0_late_init(void *handle)
944 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
946 amdgpu_bo_late_init(adev);
948 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
949 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
954 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
956 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
959 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
960 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
962 u32 viewport = RREG32(mmVIEWPORT_SIZE);
963 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
964 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
967 /* return 0 if the pre-OS buffer uses up most of vram */
968 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
973 static int gmc_v7_0_sw_init(void *handle)
977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
979 if (adev->flags & AMD_IS_APU) {
980 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
982 u32 tmp = RREG32(mmMC_SEQ_MISC0);
983 tmp &= MC_SEQ_MISC0__MT__MASK;
984 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
987 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
991 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
995 /* Adjust VM size here.
996 * Currently set to 4GB ((1 << 20) 4k pages).
997 * Max GPUVM size for cayman and SI is 40 bits.
999 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1001 /* Set the internal MC address mask
1002 * This is the max address of the GPU's
1003 * internal address space.
1005 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1007 /* set DMA mask + need_dma32 flags.
1008 * PCIE - can handle 40-bits.
1009 * IGP - can handle 40-bits
1010 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1012 adev->need_dma32 = false;
1013 dma_bits = adev->need_dma32 ? 32 : 40;
1014 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1016 adev->need_dma32 = true;
1018 pr_warn("amdgpu: No suitable DMA available\n");
1020 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1022 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1023 pr_warn("amdgpu: No coherent DMA available\n");
1025 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1027 r = gmc_v7_0_init_microcode(adev);
1029 DRM_ERROR("Failed to load mc firmware!\n");
1033 r = gmc_v7_0_mc_init(adev);
1037 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev);
1039 /* Memory manager */
1040 r = amdgpu_bo_init(adev);
1044 r = gmc_v7_0_gart_init(adev);
1050 * VMID 0 is reserved for System
1051 * amdgpu graphics/compute will use VMIDs 1-7
1052 * amdkfd will use VMIDs 8-15
1054 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1055 amdgpu_vm_manager_init(adev);
1057 /* base offset of vram pages */
1058 if (adev->flags & AMD_IS_APU) {
1059 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1062 adev->vm_manager.vram_base_offset = tmp;
1064 adev->vm_manager.vram_base_offset = 0;
1067 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1069 if (!adev->gmc.vm_fault_info)
1071 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1076 static int gmc_v7_0_sw_fini(void *handle)
1078 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1080 amdgpu_gem_force_release(adev);
1081 amdgpu_vm_manager_fini(adev);
1082 kfree(adev->gmc.vm_fault_info);
1083 amdgpu_gart_table_vram_free(adev);
1084 amdgpu_bo_fini(adev);
1085 amdgpu_gart_fini(adev);
1086 release_firmware(adev->gmc.fw);
1087 adev->gmc.fw = NULL;
1092 static int gmc_v7_0_hw_init(void *handle)
1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097 gmc_v7_0_init_golden_registers(adev);
1099 gmc_v7_0_mc_program(adev);
1101 if (!(adev->flags & AMD_IS_APU)) {
1102 r = gmc_v7_0_mc_load_microcode(adev);
1104 DRM_ERROR("Failed to load MC firmware!\n");
1109 r = gmc_v7_0_gart_enable(adev);
1116 static int gmc_v7_0_hw_fini(void *handle)
1118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1121 gmc_v7_0_gart_disable(adev);
1126 static int gmc_v7_0_suspend(void *handle)
1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1130 gmc_v7_0_hw_fini(adev);
1135 static int gmc_v7_0_resume(void *handle)
1138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140 r = gmc_v7_0_hw_init(adev);
1144 amdgpu_vmid_reset_all(adev);
1149 static bool gmc_v7_0_is_idle(void *handle)
1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1152 u32 tmp = RREG32(mmSRBM_STATUS);
1154 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1155 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1161 static int gmc_v7_0_wait_for_idle(void *handle)
1165 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167 for (i = 0; i < adev->usec_timeout; i++) {
1168 /* read MC_STATUS */
1169 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1170 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1171 SRBM_STATUS__MCC_BUSY_MASK |
1172 SRBM_STATUS__MCD_BUSY_MASK |
1173 SRBM_STATUS__VMC_BUSY_MASK);
1182 static int gmc_v7_0_soft_reset(void *handle)
1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185 u32 srbm_soft_reset = 0;
1186 u32 tmp = RREG32(mmSRBM_STATUS);
1188 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1189 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1190 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1192 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1193 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1194 if (!(adev->flags & AMD_IS_APU))
1195 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1196 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1199 if (srbm_soft_reset) {
1200 gmc_v7_0_mc_stop(adev);
1201 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1202 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1206 tmp = RREG32(mmSRBM_SOFT_RESET);
1207 tmp |= srbm_soft_reset;
1208 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1209 WREG32(mmSRBM_SOFT_RESET, tmp);
1210 tmp = RREG32(mmSRBM_SOFT_RESET);
1214 tmp &= ~srbm_soft_reset;
1215 WREG32(mmSRBM_SOFT_RESET, tmp);
1216 tmp = RREG32(mmSRBM_SOFT_RESET);
1218 /* Wait a little for things to settle down */
1221 gmc_v7_0_mc_resume(adev);
1228 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1229 struct amdgpu_irq_src *src,
1231 enum amdgpu_interrupt_state state)
1234 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1235 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1236 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1237 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1238 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1239 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1242 case AMDGPU_IRQ_STATE_DISABLE:
1243 /* system context */
1244 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1246 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1248 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1250 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1252 case AMDGPU_IRQ_STATE_ENABLE:
1253 /* system context */
1254 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1256 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1258 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1260 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1269 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1270 struct amdgpu_irq_src *source,
1271 struct amdgpu_iv_entry *entry)
1273 u32 addr, status, mc_client, vmid;
1275 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1276 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1277 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1278 /* reset addr and status */
1279 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1281 if (!addr && !status)
1284 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1285 gmc_v7_0_set_fault_enable_default(adev, false);
1287 if (printk_ratelimit()) {
1288 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1289 entry->src_id, entry->src_data[0]);
1290 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1292 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1294 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1298 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1300 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1301 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1302 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1303 u32 protections = REG_GET_FIELD(status,
1304 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1308 info->mc_id = REG_GET_FIELD(status,
1309 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1311 info->status = status;
1312 info->page_addr = addr;
1313 info->prot_valid = protections & 0x7 ? true : false;
1314 info->prot_read = protections & 0x8 ? true : false;
1315 info->prot_write = protections & 0x10 ? true : false;
1316 info->prot_exec = protections & 0x20 ? true : false;
1318 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1324 static int gmc_v7_0_set_clockgating_state(void *handle,
1325 enum amd_clockgating_state state)
1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330 if (state == AMD_CG_STATE_GATE)
1333 if (!(adev->flags & AMD_IS_APU)) {
1334 gmc_v7_0_enable_mc_mgcg(adev, gate);
1335 gmc_v7_0_enable_mc_ls(adev, gate);
1337 gmc_v7_0_enable_bif_mgls(adev, gate);
1338 gmc_v7_0_enable_hdp_mgcg(adev, gate);
1339 gmc_v7_0_enable_hdp_ls(adev, gate);
1344 static int gmc_v7_0_set_powergating_state(void *handle,
1345 enum amd_powergating_state state)
1350 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1352 .early_init = gmc_v7_0_early_init,
1353 .late_init = gmc_v7_0_late_init,
1354 .sw_init = gmc_v7_0_sw_init,
1355 .sw_fini = gmc_v7_0_sw_fini,
1356 .hw_init = gmc_v7_0_hw_init,
1357 .hw_fini = gmc_v7_0_hw_fini,
1358 .suspend = gmc_v7_0_suspend,
1359 .resume = gmc_v7_0_resume,
1360 .is_idle = gmc_v7_0_is_idle,
1361 .wait_for_idle = gmc_v7_0_wait_for_idle,
1362 .soft_reset = gmc_v7_0_soft_reset,
1363 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1364 .set_powergating_state = gmc_v7_0_set_powergating_state,
1367 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1368 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1369 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1370 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1371 .set_pte_pde = gmc_v7_0_set_pte_pde,
1372 .set_prt = gmc_v7_0_set_prt,
1373 .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
1374 .get_vm_pde = gmc_v7_0_get_vm_pde
1377 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1378 .set = gmc_v7_0_vm_fault_interrupt_state,
1379 .process = gmc_v7_0_process_interrupt,
1382 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1384 if (adev->gmc.gmc_funcs == NULL)
1385 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1388 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1390 adev->gmc.vm_fault.num_types = 1;
1391 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1394 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1396 .type = AMD_IP_BLOCK_TYPE_GMC,
1400 .funcs = &gmc_v7_0_ip_funcs,
1403 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1405 .type = AMD_IP_BLOCK_TYPE_GMC,
1409 .funcs = &gmc_v7_0_ip_funcs,