drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int gmc_v7_0_wait_for_idle(void *handle);
  43
  44 /*(DEBLOBBED)*/
  45
  46 static const u32 golden_settings_iceland_a11[] =
  47 {
  48         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  49         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  50         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  51         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  52 };
  53
  54 static const u32 iceland_mgcg_cgcg_init[] =
  55 {
  56         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  57 };
  58
  59 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  60 {
  61         switch (adev->asic_type) {
  62         case CHIP_TOPAZ:
  63                 amdgpu_program_register_sequence(adev,
  64                                                  iceland_mgcg_cgcg_init,
  65                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  66                 amdgpu_program_register_sequence(adev,
  67                                                  golden_settings_iceland_a11,
  68                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  69                 break;
  70         default:
  71                 break;
  72         }
  73 }
  74
  75 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
  76                              struct amdgpu_mode_mc_save *save)
  77 {
  78         u32 blackout;
  79
  80         if (adev->mode_info.num_crtc)
  81                 amdgpu_display_stop_mc_access(adev, save);
  82
  83         gmc_v7_0_wait_for_idle((void *)adev);
  84
  85         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  86         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  87                 /* Block CPU access */
  88                 WREG32(mmBIF_FB_EN, 0);
  89                 /* blackout the MC */
  90                 blackout = REG_SET_FIELD(blackout,
  91                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  92                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  93         }
  94         /* wait for the MC to settle */
  95         udelay(100);
  96 }
  97
  98 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
  99                                struct amdgpu_mode_mc_save *save)
 100 {
 101         u32 tmp;
 102
 103         /* unblackout the MC */
 104         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 105         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 106         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 107         /* allow CPU access */
 108         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 109         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 110         WREG32(mmBIF_FB_EN, tmp);
 111
 112         if (adev->mode_info.num_crtc)
 113                 amdgpu_display_resume_mc_access(adev, save);
 114 }
 115
 116 /**
 117  * gmc_v7_0_init_microcode - load ucode images from disk
 118  *
 119  * @adev: amdgpu_device pointer
 120  *
 121  * Use the firmware interface to load the ucode images into
 122  * the driver (not loaded into hw).
 123  * Returns 0 on success, error on failure.
 124  */
 125 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 126 {
 127         const char *chip_name;
 128         char fw_name[30];
 129         int err;
 130
 131         DRM_DEBUG("\n");
 132
 133         switch (adev->asic_type) {
 134         case CHIP_BONAIRE:
 135                 chip_name = "bonaire";
 136                 break;
 137         case CHIP_HAWAII:
 138                 chip_name = "hawaii";
 139                 break;
 140         case CHIP_TOPAZ:
 141                 chip_name = "topaz";
 142                 break;
 143         case CHIP_KAVERI:
 144         case CHIP_KABINI:
 145         case CHIP_MULLINS:
 146                 return 0;
 147         default: BUG();
 148         }
 149
 150         if (adev->asic_type == CHIP_TOPAZ)
 151                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 152         else
 153                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 154
 155         err = reject_firmware(&adev->mc.fw, fw_name, adev->dev);
 156         if (err)
 157                 goto out;
 158         err = amdgpu_ucode_validate(adev->mc.fw);
 159
 160 out:
 161         if (err) {
 162                 printk(KERN_ERR
 163                        "cik_mc: Failed to load firmware \"%s\"\n",
 164                        fw_name);
 165                 release_firmware(adev->mc.fw);
 166                 adev->mc.fw = NULL;
 167         }
 168         return err;
 169 }
 170
 171 /**
 172  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 173  *
 174  * @adev: amdgpu_device pointer
 175  *
 176  * Load the GDDR MC ucode into the hw (CIK).
 177  * Returns 0 on success, error on failure.
 178  */
 179 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 180 {
 181         const struct mc_firmware_header_v1_0 *hdr;
 182         const __le32 *fw_data = NULL;
 183         const __le32 *io_mc_regs = NULL;
 184         u32 running;
 185         int i, ucode_size, regs_size;
 186
 187         if (!adev->mc.fw)
 188                 return -EINVAL;
 189
 190         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 191         amdgpu_ucode_print_mc_hdr(&hdr->header);
 192
 193         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 194         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 195         io_mc_regs = (const __le32 *)
 196                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 197         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 198         fw_data = (const __le32 *)
 199                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 200
 201         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 202
 203         if (running == 0) {
 204                 /* reset the engine and set to writable */
 205                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 206                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 207
 208                 /* load mc io regs */
 209                 for (i = 0; i < regs_size; i++) {
 210                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 211                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 212                 }
 213                 /* load the MC ucode */
 214                 for (i = 0; i < ucode_size; i++)
 215                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 216
 217                 /* put the engine back into the active state */
 218                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 219                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 220                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 221
 222                 /* wait for training to complete */
 223                 for (i = 0; i < adev->usec_timeout; i++) {
 224                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 225                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 226                                 break;
 227                         udelay(1);
 228                 }
 229                 for (i = 0; i < adev->usec_timeout; i++) {
 230                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 231                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 232                                 break;
 233                         udelay(1);
 234                 }
 235         }
 236
 237         return 0;
 238 }
 239
 240 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 241                                        struct amdgpu_mc *mc)
 242 {
 243         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 244                 /* leave room for at least 1024M GTT */
 245                 dev_warn(adev->dev, "limiting VRAM\n");
 246                 mc->real_vram_size = 0xFFC0000000ULL;
 247                 mc->mc_vram_size = 0xFFC0000000ULL;
 248         }
 249         amdgpu_vram_location(adev, &adev->mc, 0);
 250         adev->mc.gtt_base_align = 0;
 251         amdgpu_gtt_location(adev, mc);
 252 }
 253
 254 /**
 255  * gmc_v7_0_mc_program - program the GPU memory controller
 256  *
 257  * @adev: amdgpu_device pointer
 258  *
 259  * Set the location of vram, gart, and AGP in the GPU's
 260  * physical address space (CIK).
 261  */
 262 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 263 {
 264         struct amdgpu_mode_mc_save save;
 265         u32 tmp;
 266         int i, j;
 267
 268         /* Initialize HDP */
 269         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 270                 WREG32((0xb05 + j), 0x00000000);
 271                 WREG32((0xb06 + j), 0x00000000);
 272                 WREG32((0xb07 + j), 0x00000000);
 273                 WREG32((0xb08 + j), 0x00000000);
 274                 WREG32((0xb09 + j), 0x00000000);
 275         }
 276         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 277
 278         if (adev->mode_info.num_crtc)
 279                 amdgpu_display_set_vga_render_state(adev, false);
 280
 281         gmc_v7_0_mc_stop(adev, &save);
 282         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 283                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 284         }
 285         /* Update configuration */
 286         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 287                adev->mc.vram_start >> 12);
 288         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 289                adev->mc.vram_end >> 12);
 290         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 291                adev->vram_scratch.gpu_addr >> 12);
 292         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 293         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 294         WREG32(mmMC_VM_FB_LOCATION, tmp);
 295         /* XXX double check these! */
 296         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 297         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 298         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 299         WREG32(mmMC_VM_AGP_BASE, 0);
 300         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 301         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 302         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 303                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 304         }
 305         gmc_v7_0_mc_resume(adev, &save);
 306
 307         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 308
 309         tmp = RREG32(mmHDP_MISC_CNTL);
 310         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 311         WREG32(mmHDP_MISC_CNTL, tmp);
 312
 313         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 314         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 315 }
 316
 317 /**
 318  * gmc_v7_0_mc_init - initialize the memory controller driver params
 319  *
 320  * @adev: amdgpu_device pointer
 321  *
 322  * Look up the amount of vram, vram width, and decide how to place
 323  * vram and gart within the GPU's physical address space (CIK).
 324  * Returns 0 for success.
 325  */
 326 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 327 {
 328         u32 tmp;
 329         int chansize, numchan;
 330
 331         /* Get VRAM informations */
 332         tmp = RREG32(mmMC_ARB_RAMCFG);
 333         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 334                 chansize = 64;
 335         } else {
 336                 chansize = 32;
 337         }
 338         tmp = RREG32(mmMC_SHARED_CHMAP);
 339         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 340         case 0:
 341         default:
 342                 numchan = 1;
 343                 break;
 344         case 1:
 345                 numchan = 2;
 346                 break;
 347         case 2:
 348                 numchan = 4;
 349                 break;
 350         case 3:
 351                 numchan = 8;
 352                 break;
 353         case 4:
 354                 numchan = 3;
 355                 break;
 356         case 5:
 357                 numchan = 6;
 358                 break;
 359         case 6:
 360                 numchan = 10;
 361                 break;
 362         case 7:
 363                 numchan = 12;
 364                 break;
 365         case 8:
 366                 numchan = 16;
 367                 break;
 368         }
 369         adev->mc.vram_width = numchan * chansize;
 370         /* Could aper size report 0 ? */
 371         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 372         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 373         /* size in MB on si */
 374         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 375         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 376         adev->mc.visible_vram_size = adev->mc.aper_size;
 377
 378         /* In case the PCI BAR is larger than the actual amount of vram */
 379         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 380                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 381
 382         /* unless the user had overridden it, set the gart
 383          * size equal to the 1024 or vram, whichever is larger.
 384          */
 385         if (amdgpu_gart_size == -1)
 386                 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
 387         else
 388                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 389
 390         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 391
 392         return 0;
 393 }
 394
 395 /*
 396  * GART
 397  * VMID 0 is the physical GPU addresses as used by the kernel.
 398  * VMIDs 1-15 are used for userspace clients and are handled
 399  * by the amdgpu vm/hsa code.
 400  */
 401
 402 /**
 403  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 404  *
 405  * @adev: amdgpu_device pointer
 406  * @vmid: vm instance to flush
 407  *
 408  * Flush the TLB for the requested page table (CIK).
 409  */
 410 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 411                                         uint32_t vmid)
 412 {
 413         /* flush hdp cache */
 414         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 415
 416         /* bits 0-15 are the VM contexts0-15 */
 417         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 418 }
 419
 420 /**
 421  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 422  *
 423  * @adev: amdgpu_device pointer
 424  * @cpu_pt_addr: cpu address of the page table
 425  * @gpu_page_idx: entry in the page table to update
 426  * @addr: dst addr to write into pte/pde
 427  * @flags: access flags
 428  *
 429  * Update the page tables using the CPU.
 430  */
 431 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 432                                      void *cpu_pt_addr,
 433                                      uint32_t gpu_page_idx,
 434                                      uint64_t addr,
 435                                      uint32_t flags)
 436 {
 437         void __iomem *ptr = (void *)cpu_pt_addr;
 438         uint64_t value;
 439
 440         value = addr & 0xFFFFFFFFFFFFF000ULL;
 441         value |= flags;
 442         writeq(value, ptr + (gpu_page_idx * 8));
 443
 444         return 0;
 445 }
 446
 447 /**
 448  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 449  *
 450  * @adev: amdgpu_device pointer
 451  * @value: true redirects VM faults to the default page
 452  */
 453 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 454                                               bool value)
 455 {
 456         u32 tmp;
 457
 458         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 459         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 460                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 461         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 462                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 463         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 464                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 465         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 466                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 467         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 468                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 469         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 470                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 471         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 472 }
 473
 474 /**
 475  * gmc_v7_0_gart_enable - gart enable
 476  *
 477  * @adev: amdgpu_device pointer
 478  *
 479  * This sets up the TLBs, programs the page tables for VMID0,
 480  * sets up the hw for VMIDs 1-15 which are allocated on
 481  * demand, and sets up the global locations for the LDS, GDS,
 482  * and GPUVM for FSA64 clients (CIK).
 483  * Returns 0 for success, errors for failure.
 484  */
 485 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 486 {
 487         int r, i;
 488         u32 tmp;
 489
 490         if (adev->gart.robj == NULL) {
 491                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 492                 return -EINVAL;
 493         }
 494         r = amdgpu_gart_table_vram_pin(adev);
 495         if (r)
 496                 return r;
 497         /* Setup TLB control */
 498         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 499         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 500         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 501         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 502         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 503         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 504         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 505         /* Setup L2 cache */
 506         tmp = RREG32(mmVM_L2_CNTL);
 507         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 508         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 509         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 510         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 511         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 512         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 513         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 514         WREG32(mmVM_L2_CNTL, tmp);
 515         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 516         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 517         WREG32(mmVM_L2_CNTL2, tmp);
 518         tmp = RREG32(mmVM_L2_CNTL3);
 519         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 520         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 521         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 522         WREG32(mmVM_L2_CNTL3, tmp);
 523         /* setup context0 */
 524         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 525         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 526         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 527         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 528                         (u32)(adev->dummy_page.addr >> 12));
 529         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 530         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 531         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 532         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 533         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 534         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 535
 536         WREG32(0x575, 0);
 537         WREG32(0x576, 0);
 538         WREG32(0x577, 0);
 539
 540         /* empty context1-15 */
 541         /* FIXME start with 4G, once using 2 level pt switch to full
 542          * vm size space
 543          */
 544         /* set vm size, must be a multiple of 4 */
 545         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 546         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 547         for (i = 1; i < 16; i++) {
 548                 if (i < 8)
 549                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 550                                adev->gart.table_addr >> 12);
 551                 else
 552                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 553                                adev->gart.table_addr >> 12);
 554         }
 555
 556         /* enable context1-15 */
 557         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 558                (u32)(adev->dummy_page.addr >> 12));
 559         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 560         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 561         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 562         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 563         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 564                             amdgpu_vm_block_size - 9);
 565         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 566         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 567                 gmc_v7_0_set_fault_enable_default(adev, false);
 568         else
 569                 gmc_v7_0_set_fault_enable_default(adev, true);
 570
 571         if (adev->asic_type == CHIP_KAVERI) {
 572                 tmp = RREG32(mmCHUB_CONTROL);
 573                 tmp &= ~BYPASS_VM;
 574                 WREG32(mmCHUB_CONTROL, tmp);
 575         }
 576
 577         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 578         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 579                  (unsigned)(adev->mc.gtt_size >> 20),
 580                  (unsigned long long)adev->gart.table_addr);
 581         adev->gart.ready = true;
 582         return 0;
 583 }
 584
 585 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 586 {
 587         int r;
 588
 589         if (adev->gart.robj) {
 590                 WARN(1, "R600 PCIE GART already initialized\n");
 591                 return 0;
 592         }
 593         /* Initialize common gart structure */
 594         r = amdgpu_gart_init(adev);
 595         if (r)
 596                 return r;
 597         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 598         return amdgpu_gart_table_vram_alloc(adev);
 599 }
 600
 601 /**
 602  * gmc_v7_0_gart_disable - gart disable
 603  *
 604  * @adev: amdgpu_device pointer
 605  *
 606  * This disables all VM page table (CIK).
 607  */
 608 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 609 {
 610         u32 tmp;
 611
 612         /* Disable all tables */
 613         WREG32(mmVM_CONTEXT0_CNTL, 0);
 614         WREG32(mmVM_CONTEXT1_CNTL, 0);
 615         /* Setup TLB control */
 616         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 617         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 618         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 619         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 620         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 621         /* Setup L2 cache */
 622         tmp = RREG32(mmVM_L2_CNTL);
 623         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 624         WREG32(mmVM_L2_CNTL, tmp);
 625         WREG32(mmVM_L2_CNTL2, 0);
 626         amdgpu_gart_table_vram_unpin(adev);
 627 }
 628
 629 /**
 630  * gmc_v7_0_gart_fini - vm fini callback
 631  *
 632  * @adev: amdgpu_device pointer
 633  *
 634  * Tears down the driver GART/VM setup (CIK).
 635  */
 636 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 637 {
 638         amdgpu_gart_table_vram_free(adev);
 639         amdgpu_gart_fini(adev);
 640 }
 641
 642 /*
 643  * vm
 644  * VMID 0 is the physical GPU addresses as used by the kernel.
 645  * VMIDs 1-15 are used for userspace clients and are handled
 646  * by the amdgpu vm/hsa code.
 647  */
 648 /**
 649  * gmc_v7_0_vm_init - cik vm init callback
 650  *
 651  * @adev: amdgpu_device pointer
 652  *
 653  * Inits cik specific vm parameters (number of VMs, base of vram for
 654  * VMIDs 1-15) (CIK).
 655  * Returns 0 for success.
 656  */
 657 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 658 {
 659         /*
 660          * number of VMs
 661          * VMID 0 is reserved for System
 662          * amdgpu graphics/compute will use VMIDs 1-7
 663          * amdkfd will use VMIDs 8-15
 664          */
 665         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 666         amdgpu_vm_manager_init(adev);
 667
 668         /* base offset of vram pages */
 669         if (adev->flags & AMD_IS_APU) {
 670                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 671                 tmp <<= 22;
 672                 adev->vm_manager.vram_base_offset = tmp;
 673         } else
 674                 adev->vm_manager.vram_base_offset = 0;
 675
 676         return 0;
 677 }
 678
 679 /**
 680  * gmc_v7_0_vm_fini - cik vm fini callback
 681  *
 682  * @adev: amdgpu_device pointer
 683  *
 684  * Tear down any asic specific VM setup (CIK).
 685  */
 686 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
 687 {
 688 }
 689
 690 /**
 691  * gmc_v7_0_vm_decode_fault - print human readable fault info
 692  *
 693  * @adev: amdgpu_device pointer
 694  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 695  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 696  *
 697  * Print human readable fault information (CIK).
 698  */
 699 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 700                                      u32 status, u32 addr, u32 mc_client)
 701 {
 702         u32 mc_id;
 703         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 704         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 705                                         PROTECTIONS);
 706         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 707                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 708
 709         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 710                               MEMORY_CLIENT_ID);
 711
 712         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 713                protections, vmid, addr,
 714                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 715                              MEMORY_CLIENT_RW) ?
 716                "write" : "read", block, mc_client, mc_id);
 717 }
 718
 719
 720 static const u32 mc_cg_registers[] = {
 721         mmMC_HUB_MISC_HUB_CG,
 722         mmMC_HUB_MISC_SIP_CG,
 723         mmMC_HUB_MISC_VM_CG,
 724         mmMC_XPB_CLK_GAT,
 725         mmATC_MISC_CG,
 726         mmMC_CITF_MISC_WR_CG,
 727         mmMC_CITF_MISC_RD_CG,
 728         mmMC_CITF_MISC_VM_CG,
 729         mmVM_L2_CG,
 730 };
 731
 732 static const u32 mc_cg_ls_en[] = {
 733         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 734         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 735         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 736         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 737         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 738         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 739         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 740         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 741         VM_L2_CG__MEM_LS_ENABLE_MASK,
 742 };
 743
 744 static const u32 mc_cg_en[] = {
 745         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 746         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 747         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 748         MC_XPB_CLK_GAT__ENABLE_MASK,
 749         ATC_MISC_CG__ENABLE_MASK,
 750         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 751         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 752         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 753         VM_L2_CG__ENABLE_MASK,
 754 };
 755
 756 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 757                                   bool enable)
 758 {
 759         int i;
 760         u32 orig, data;
 761
 762         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 763                 orig = data = RREG32(mc_cg_registers[i]);
 764                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 765                         data |= mc_cg_ls_en[i];
 766                 else
 767                         data &= ~mc_cg_ls_en[i];
 768                 if (data != orig)
 769                         WREG32(mc_cg_registers[i], data);
 770         }
 771 }
 772
 773 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 774                                     bool enable)
 775 {
 776         int i;
 777         u32 orig, data;
 778
 779         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 780                 orig = data = RREG32(mc_cg_registers[i]);
 781                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 782                         data |= mc_cg_en[i];
 783                 else
 784                         data &= ~mc_cg_en[i];
 785                 if (data != orig)
 786                         WREG32(mc_cg_registers[i], data);
 787         }
 788 }
 789
 790 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 791                                      bool enable)
 792 {
 793         u32 orig, data;
 794
 795         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 796
 797         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 798                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 799                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 800                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 801                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 802         } else {
 803                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 804                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 805                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 806                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 807         }
 808
 809         if (orig != data)
 810                 WREG32_PCIE(ixPCIE_CNTL2, data);
 811 }
 812
 813 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 814                                      bool enable)
 815 {
 816         u32 orig, data;
 817
 818         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 819
 820         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 821                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 822         else
 823                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 824
 825         if (orig != data)
 826                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 827 }
 828
 829 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 830                                    bool enable)
 831 {
 832         u32 orig, data;
 833
 834         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 835
 836         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 837                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 838         else
 839                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 840
 841         if (orig != data)
 842                 WREG32(mmHDP_MEM_POWER_LS, data);
 843 }
 844
 845 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 846 {
 847         switch (mc_seq_vram_type) {
 848         case MC_SEQ_MISC0__MT__GDDR1:
 849                 return AMDGPU_VRAM_TYPE_GDDR1;
 850         case MC_SEQ_MISC0__MT__DDR2:
 851                 return AMDGPU_VRAM_TYPE_DDR2;
 852         case MC_SEQ_MISC0__MT__GDDR3:
 853                 return AMDGPU_VRAM_TYPE_GDDR3;
 854         case MC_SEQ_MISC0__MT__GDDR4:
 855                 return AMDGPU_VRAM_TYPE_GDDR4;
 856         case MC_SEQ_MISC0__MT__GDDR5:
 857                 return AMDGPU_VRAM_TYPE_GDDR5;
 858         case MC_SEQ_MISC0__MT__HBM:
 859                 return AMDGPU_VRAM_TYPE_HBM;
 860         case MC_SEQ_MISC0__MT__DDR3:
 861                 return AMDGPU_VRAM_TYPE_DDR3;
 862         default:
 863                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 864         }
 865 }
 866
 867 static int gmc_v7_0_early_init(void *handle)
 868 {
 869         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 870
 871         gmc_v7_0_set_gart_funcs(adev);
 872         gmc_v7_0_set_irq_funcs(adev);
 873
 874         return 0;
 875 }
 876
 877 static int gmc_v7_0_late_init(void *handle)
 878 {
 879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 880
 881         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 882                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 883         else
 884                 return 0;
 885 }
 886
 887 static int gmc_v7_0_sw_init(void *handle)
 888 {
 889         int r;
 890         int dma_bits;
 891         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 892
 893         if (adev->flags & AMD_IS_APU) {
 894                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 895         } else {
 896                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 897                 tmp &= MC_SEQ_MISC0__MT__MASK;
 898                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 899         }
 900
 901         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 902         if (r)
 903                 return r;
 904
 905         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 906         if (r)
 907                 return r;
 908
 909         /* Adjust VM size here.
 910          * Currently set to 4GB ((1 << 20) 4k pages).
 911          * Max GPUVM size for cayman and SI is 40 bits.
 912          */
 913         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 914
 915         /* Set the internal MC address mask
 916          * This is the max address of the GPU's
 917          * internal address space.
 918          */
 919         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 920
 921         /* set DMA mask + need_dma32 flags.
 922          * PCIE - can handle 40-bits.
 923          * IGP - can handle 40-bits
 924          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 925          */
 926         adev->need_dma32 = false;
 927         dma_bits = adev->need_dma32 ? 32 : 40;
 928         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 929         if (r) {
 930                 adev->need_dma32 = true;
 931                 dma_bits = 32;
 932                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 933         }
 934         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 935         if (r) {
 936                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 937                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 938         }
 939
 940         r = gmc_v7_0_init_microcode(adev);
 941         if (r) {
 942                 DRM_ERROR("Failed to load mc firmware!\n");
 943                 return r;
 944         }
 945
 946         r = amdgpu_ttm_global_init(adev);
 947         if (r) {
 948                 return r;
 949         }
 950
 951         r = gmc_v7_0_mc_init(adev);
 952         if (r)
 953                 return r;
 954
 955         /* Memory manager */
 956         r = amdgpu_bo_init(adev);
 957         if (r)
 958                 return r;
 959
 960         r = gmc_v7_0_gart_init(adev);
 961         if (r)
 962                 return r;
 963
 964         if (!adev->vm_manager.enabled) {
 965                 r = gmc_v7_0_vm_init(adev);
 966                 if (r) {
 967                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 968                         return r;
 969                 }
 970                 adev->vm_manager.enabled = true;
 971         }
 972
 973         return r;
 974 }
 975
 976 static int gmc_v7_0_sw_fini(void *handle)
 977 {
 978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 979
 980         if (adev->vm_manager.enabled) {
 981                 amdgpu_vm_manager_fini(adev);
 982                 gmc_v7_0_vm_fini(adev);
 983                 adev->vm_manager.enabled = false;
 984         }
 985         gmc_v7_0_gart_fini(adev);
 986         amdgpu_gem_force_release(adev);
 987         amdgpu_bo_fini(adev);
 988
 989         return 0;
 990 }
 991
 992 static int gmc_v7_0_hw_init(void *handle)
 993 {
 994         int r;
 995         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 996
 997         gmc_v7_0_init_golden_registers(adev);
 998
 999         gmc_v7_0_mc_program(adev);
1000
1001         if (!(adev->flags & AMD_IS_APU)) {
1002                 r = gmc_v7_0_mc_load_microcode(adev);
1003                 if (r) {
1004                         DRM_ERROR("Failed to load MC firmware!\n");
1005                         return r;
1006                 }
1007         }
1008
1009         r = gmc_v7_0_gart_enable(adev);
1010         if (r)
1011                 return r;
1012
1013         return r;
1014 }
1015
1016 static int gmc_v7_0_hw_fini(void *handle)
1017 {
1018         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019
1020         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1021         gmc_v7_0_gart_disable(adev);
1022
1023         return 0;
1024 }
1025
1026 static int gmc_v7_0_suspend(void *handle)
1027 {
1028         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029
1030         if (adev->vm_manager.enabled) {
1031                 gmc_v7_0_vm_fini(adev);
1032                 adev->vm_manager.enabled = false;
1033         }
1034         gmc_v7_0_hw_fini(adev);
1035
1036         return 0;
1037 }
1038
1039 static int gmc_v7_0_resume(void *handle)
1040 {
1041         int r;
1042         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1043
1044         r = gmc_v7_0_hw_init(adev);
1045         if (r)
1046                 return r;
1047
1048         if (!adev->vm_manager.enabled) {
1049                 r = gmc_v7_0_vm_init(adev);
1050                 if (r) {
1051                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1052                         return r;
1053                 }
1054                 adev->vm_manager.enabled = true;
1055         }
1056
1057         return r;
1058 }
1059
1060 static bool gmc_v7_0_is_idle(void *handle)
1061 {
1062         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1063         u32 tmp = RREG32(mmSRBM_STATUS);
1064
1065         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1066                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1067                 return false;
1068
1069         return true;
1070 }
1071
1072 static int gmc_v7_0_wait_for_idle(void *handle)
1073 {
1074         unsigned i;
1075         u32 tmp;
1076         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1077
1078         for (i = 0; i < adev->usec_timeout; i++) {
1079                 /* read MC_STATUS */
1080                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1081                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1082                                                SRBM_STATUS__MCC_BUSY_MASK |
1083                                                SRBM_STATUS__MCD_BUSY_MASK |
1084                                                SRBM_STATUS__VMC_BUSY_MASK);
1085                 if (!tmp)
1086                         return 0;
1087                 udelay(1);
1088         }
1089         return -ETIMEDOUT;
1090
1091 }
1092
1093 static int gmc_v7_0_soft_reset(void *handle)
1094 {
1095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096         struct amdgpu_mode_mc_save save;
1097         u32 srbm_soft_reset = 0;
1098         u32 tmp = RREG32(mmSRBM_STATUS);
1099
1100         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1101                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1102                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1103
1104         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1105                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1106                 if (!(adev->flags & AMD_IS_APU))
1107                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1108                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1109         }
1110
1111         if (srbm_soft_reset) {
1112                 gmc_v7_0_mc_stop(adev, &save);
1113                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1114                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1115                 }
1116
1117
1118                 tmp = RREG32(mmSRBM_SOFT_RESET);
1119                 tmp |= srbm_soft_reset;
1120                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1121                 WREG32(mmSRBM_SOFT_RESET, tmp);
1122                 tmp = RREG32(mmSRBM_SOFT_RESET);
1123
1124                 udelay(50);
1125
1126                 tmp &= ~srbm_soft_reset;
1127                 WREG32(mmSRBM_SOFT_RESET, tmp);
1128                 tmp = RREG32(mmSRBM_SOFT_RESET);
1129
1130                 /* Wait a little for things to settle down */
1131                 udelay(50);
1132
1133                 gmc_v7_0_mc_resume(adev, &save);
1134                 udelay(50);
1135         }
1136
1137         return 0;
1138 }
1139
1140 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1141                                              struct amdgpu_irq_src *src,
1142                                              unsigned type,
1143                                              enum amdgpu_interrupt_state state)
1144 {
1145         u32 tmp;
1146         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1147                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1148                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1149                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1150                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1151                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1152
1153         switch (state) {
1154         case AMDGPU_IRQ_STATE_DISABLE:
1155                 /* system context */
1156                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1157                 tmp &= ~bits;
1158                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1159                 /* VMs */
1160                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1161                 tmp &= ~bits;
1162                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1163                 break;
1164         case AMDGPU_IRQ_STATE_ENABLE:
1165                 /* system context */
1166                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1167                 tmp |= bits;
1168                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1169                 /* VMs */
1170                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1171                 tmp |= bits;
1172                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1173                 break;
1174         default:
1175                 break;
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1182                                       struct amdgpu_irq_src *source,
1183                                       struct amdgpu_iv_entry *entry)
1184 {
1185         u32 addr, status, mc_client;
1186
1187         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1188         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1189         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1190         /* reset addr and status */
1191         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1192
1193         if (!addr && !status)
1194                 return 0;
1195
1196         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1197                 gmc_v7_0_set_fault_enable_default(adev, false);
1198
1199         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1200                 entry->src_id, entry->src_data);
1201         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1202                 addr);
1203         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1204                 status);
1205         gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1206
1207         return 0;
1208 }
1209
1210 static int gmc_v7_0_set_clockgating_state(void *handle,
1211                                           enum amd_clockgating_state state)
1212 {
1213         bool gate = false;
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215
1216         if (state == AMD_CG_STATE_GATE)
1217                 gate = true;
1218
1219         if (!(adev->flags & AMD_IS_APU)) {
1220                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1221                 gmc_v7_0_enable_mc_ls(adev, gate);
1222         }
1223         gmc_v7_0_enable_bif_mgls(adev, gate);
1224         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1225         gmc_v7_0_enable_hdp_ls(adev, gate);
1226
1227         return 0;
1228 }
1229
1230 static int gmc_v7_0_set_powergating_state(void *handle,
1231                                           enum amd_powergating_state state)
1232 {
1233         return 0;
1234 }
1235
1236 const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1237         .name = "gmc_v7_0",
1238         .early_init = gmc_v7_0_early_init,
1239         .late_init = gmc_v7_0_late_init,
1240         .sw_init = gmc_v7_0_sw_init,
1241         .sw_fini = gmc_v7_0_sw_fini,
1242         .hw_init = gmc_v7_0_hw_init,
1243         .hw_fini = gmc_v7_0_hw_fini,
1244         .suspend = gmc_v7_0_suspend,
1245         .resume = gmc_v7_0_resume,
1246         .is_idle = gmc_v7_0_is_idle,
1247         .wait_for_idle = gmc_v7_0_wait_for_idle,
1248         .soft_reset = gmc_v7_0_soft_reset,
1249         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1250         .set_powergating_state = gmc_v7_0_set_powergating_state,
1251 };
1252
1253 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1254         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1255         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1256 };
1257
1258 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1259         .set = gmc_v7_0_vm_fault_interrupt_state,
1260         .process = gmc_v7_0_process_interrupt,
1261 };
1262
1263 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1264 {
1265         if (adev->gart.gart_funcs == NULL)
1266                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1267 }
1268
1269 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1270 {
1271         adev->mc.vm_fault.num_types = 1;
1272         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1273 }