2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
29 #include "bif/bif_3_0_d.h"
30 #include "bif/bif_3_0_sh_mask.h"
31 #include "oss/oss_1_0_d.h"
32 #include "oss/oss_1_0_sh_mask.h"
33 #include "gmc/gmc_6_0_d.h"
34 #include "gmc/gmc_6_0_sh_mask.h"
35 #include "dce/dce_6_0_d.h"
36 #include "dce/dce_6_0_sh_mask.h"
39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41 static int gmc_v6_0_wait_for_idle(void *handle);
45 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
46 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
47 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
48 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
49 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
50 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
51 #define MC_SEQ_MISC0__MT__HBM 0x60000000
52 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
55 static const u32 crtc_offsets[6] =
57 SI_CRTC0_REGISTER_OFFSET,
58 SI_CRTC1_REGISTER_OFFSET,
59 SI_CRTC2_REGISTER_OFFSET,
60 SI_CRTC3_REGISTER_OFFSET,
61 SI_CRTC4_REGISTER_OFFSET,
62 SI_CRTC5_REGISTER_OFFSET
65 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
69 gmc_v6_0_wait_for_idle((void *)adev);
71 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
72 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
73 /* Block CPU access */
74 WREG32(mmBIF_FB_EN, 0);
76 blackout = REG_SET_FIELD(blackout,
77 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
78 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
80 /* wait for the MC to settle */
85 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
89 /* unblackout the MC */
90 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
91 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
92 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
93 /* allow CPU access */
94 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
95 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
96 WREG32(mmBIF_FB_EN, tmp);
99 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
101 const char *chip_name;
104 bool is_58_fw = false;
108 switch (adev->asic_type) {
110 chip_name = "tahiti";
113 chip_name = "pitcairn";
122 chip_name = "hainan";
127 /* this memory configuration requires special firmware */
128 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
132 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/");
134 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
135 err = reject_firmware(&adev->mc.fw, fw_name, adev->dev);
139 err = amdgpu_ucode_validate(adev->mc.fw);
144 "si_mc: Failed to load firmware \"%s\"\n",
146 release_firmware(adev->mc.fw);
152 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
154 const __le32 *new_fw_data = NULL;
156 const __le32 *new_io_mc_regs = NULL;
157 int i, regs_size, ucode_size;
158 const struct mc_firmware_header_v1_0 *hdr;
163 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
165 amdgpu_ucode_print_mc_hdr(&hdr->header);
167 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
168 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
169 new_io_mc_regs = (const __le32 *)
170 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
171 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
172 new_fw_data = (const __le32 *)
173 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
175 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
179 /* reset the engine and set to writable */
180 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
181 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
183 /* load mc io regs */
184 for (i = 0; i < regs_size; i++) {
185 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
186 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
188 /* load the MC ucode */
189 for (i = 0; i < ucode_size; i++) {
190 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
193 /* put the engine back into the active state */
194 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
195 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
196 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
198 /* wait for training to complete */
199 for (i = 0; i < adev->usec_timeout; i++) {
200 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
204 for (i = 0; i < adev->usec_timeout; i++) {
205 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
215 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
216 struct amdgpu_mc *mc)
218 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
221 if (mc->mc_vram_size > 0xFFC0000000ULL) {
222 dev_warn(adev->dev, "limiting VRAM\n");
223 mc->real_vram_size = 0xFFC0000000ULL;
224 mc->mc_vram_size = 0xFFC0000000ULL;
226 amdgpu_vram_location(adev, &adev->mc, base);
227 amdgpu_gart_location(adev, mc);
230 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
235 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
236 WREG32((0xb05 + j), 0x00000000);
237 WREG32((0xb06 + j), 0x00000000);
238 WREG32((0xb07 + j), 0x00000000);
239 WREG32((0xb08 + j), 0x00000000);
240 WREG32((0xb09 + j), 0x00000000);
242 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
244 if (gmc_v6_0_wait_for_idle((void *)adev)) {
245 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
248 if (adev->mode_info.num_crtc) {
251 /* Lockout access through VGA aperture*/
252 tmp = RREG32(mmVGA_HDP_CONTROL);
253 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
254 WREG32(mmVGA_HDP_CONTROL, tmp);
256 /* disable VGA render */
257 tmp = RREG32(mmVGA_RENDER_CONTROL);
258 tmp &= ~VGA_VSTATUS_CNTL;
259 WREG32(mmVGA_RENDER_CONTROL, tmp);
261 /* Update configuration */
262 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
263 adev->mc.vram_start >> 12);
264 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
265 adev->mc.vram_end >> 12);
266 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
267 adev->vram_scratch.gpu_addr >> 12);
268 WREG32(mmMC_VM_AGP_BASE, 0);
269 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
270 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
272 if (gmc_v6_0_wait_for_idle((void *)adev)) {
273 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
277 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
281 int chansize, numchan;
283 tmp = RREG32(mmMC_ARB_RAMCFG);
284 if (tmp & (1 << 11)) {
286 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
291 tmp = RREG32(mmMC_SHARED_CHMAP);
292 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
322 adev->mc.vram_width = numchan * chansize;
323 /* Could aper size report 0 ? */
324 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
325 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
326 /* size in MB on si */
327 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
328 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
329 adev->mc.visible_vram_size = adev->mc.aper_size;
331 /* set the gart size */
332 if (amdgpu_gart_size == -1) {
333 switch (adev->asic_type) {
334 case CHIP_HAINAN: /* no MM engines */
336 adev->mc.gart_size = 256ULL << 20;
338 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
339 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
340 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
341 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
342 adev->mc.gart_size = 1024ULL << 20;
346 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
349 gmc_v6_0_vram_gtt_location(adev, &adev->mc);
354 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
357 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
359 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
362 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
364 uint32_t gpu_page_idx,
368 void __iomem *ptr = (void *)cpu_pt_addr;
371 value = addr & 0xFFFFFFFFFFFFF000ULL;
373 writeq(value, ptr + (gpu_page_idx * 8));
378 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
381 uint64_t pte_flag = 0;
383 if (flags & AMDGPU_VM_PAGE_READABLE)
384 pte_flag |= AMDGPU_PTE_READABLE;
385 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
386 pte_flag |= AMDGPU_PTE_WRITEABLE;
387 if (flags & AMDGPU_VM_PAGE_PRT)
388 pte_flag |= AMDGPU_PTE_PRT;
393 static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
395 BUG_ON(addr & 0xFFFFFF0000000FFFULL);
399 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
404 tmp = RREG32(mmVM_CONTEXT1_CNTL);
405 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
406 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
407 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
408 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
409 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
410 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
411 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
412 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
413 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
414 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
415 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
416 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
417 WREG32(mmVM_CONTEXT1_CNTL, tmp);
421 + * gmc_v8_0_set_prt - set PRT VM fault
423 + * @adev: amdgpu_device pointer
424 + * @enable: enable/disable VM fault handling for PRT
426 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
430 if (enable && !adev->mc.prt_warning) {
431 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
432 adev->mc.prt_warning = true;
435 tmp = RREG32(mmVM_PRT_CNTL);
436 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
437 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
439 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
440 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
442 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
443 L2_CACHE_STORE_INVALID_ENTRIES,
445 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
446 L1_TLB_STORE_INVALID_ENTRIES,
448 WREG32(mmVM_PRT_CNTL, tmp);
451 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
452 uint32_t high = adev->vm_manager.max_pfn;
454 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
455 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
456 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
457 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
458 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
459 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
460 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
461 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
463 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
464 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
465 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
466 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
467 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
468 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
469 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
470 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
474 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
479 if (adev->gart.robj == NULL) {
480 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
483 r = amdgpu_gart_table_vram_pin(adev);
486 /* Setup TLB control */
487 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
489 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
490 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
491 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
492 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
493 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
496 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
497 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
498 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
499 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
500 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
501 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
502 WREG32(mmVM_L2_CNTL2,
503 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
504 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
506 field = adev->vm_manager.fragment_size;
507 WREG32(mmVM_L2_CNTL3,
508 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
509 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
510 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
512 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
513 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
514 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
515 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
516 (u32)(adev->dummy_page.addr >> 12));
517 WREG32(mmVM_CONTEXT0_CNTL2, 0);
518 WREG32(mmVM_CONTEXT0_CNTL,
519 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
520 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
521 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
527 /* empty context1-15 */
528 /* set vm size, must be a multiple of 4 */
529 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
530 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
531 /* Assign the pt base to something valid for now; the pts used for
532 * the VMs are determined by the application and setup and assigned
533 * on the fly in the vm part of radeon_gart.c
535 for (i = 1; i < 16; i++) {
537 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
538 adev->gart.table_addr >> 12);
540 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
541 adev->gart.table_addr >> 12);
544 /* enable context1-15 */
545 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
546 (u32)(adev->dummy_page.addr >> 12));
547 WREG32(mmVM_CONTEXT1_CNTL2, 4);
548 WREG32(mmVM_CONTEXT1_CNTL,
549 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
550 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
551 ((adev->vm_manager.block_size - 9)
552 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
553 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
554 gmc_v6_0_set_fault_enable_default(adev, false);
556 gmc_v6_0_set_fault_enable_default(adev, true);
558 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
559 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
560 (unsigned)(adev->mc.gart_size >> 20),
561 (unsigned long long)adev->gart.table_addr);
562 adev->gart.ready = true;
566 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
570 if (adev->gart.robj) {
571 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
574 r = amdgpu_gart_init(adev);
577 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
578 adev->gart.gart_pte_flags = 0;
579 return amdgpu_gart_table_vram_alloc(adev);
582 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
586 for (i = 1; i < 16; ++i) {
589 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
591 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
592 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
595 /* Disable all tables */
596 WREG32(mmVM_CONTEXT0_CNTL, 0);
597 WREG32(mmVM_CONTEXT1_CNTL, 0);
598 /* Setup TLB control */
599 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
600 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
601 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
604 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
605 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
606 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
607 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
608 WREG32(mmVM_L2_CNTL2, 0);
609 WREG32(mmVM_L2_CNTL3,
610 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
611 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
612 amdgpu_gart_table_vram_unpin(adev);
615 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
617 amdgpu_gart_table_vram_free(adev);
618 amdgpu_gart_fini(adev);
621 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
622 u32 status, u32 addr, u32 mc_client)
625 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
626 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
628 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
629 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
631 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
634 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
635 protections, vmid, addr,
636 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
638 "write" : "read", block, mc_client, mc_id);
642 static const u32 mc_cg_registers[] = {
654 static const u32 mc_cg_ls_en[] = {
655 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
656 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
657 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
658 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
659 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
660 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
661 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
662 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
663 VM_L2_CG__MEM_LS_ENABLE_MASK,
666 static const u32 mc_cg_en[] = {
667 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
668 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
669 MC_HUB_MISC_VM_CG__ENABLE_MASK,
670 MC_XPB_CLK_GAT__ENABLE_MASK,
671 ATC_MISC_CG__ENABLE_MASK,
672 MC_CITF_MISC_WR_CG__ENABLE_MASK,
673 MC_CITF_MISC_RD_CG__ENABLE_MASK,
674 MC_CITF_MISC_VM_CG__ENABLE_MASK,
675 VM_L2_CG__ENABLE_MASK,
678 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
684 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
685 orig = data = RREG32(mc_cg_registers[i]);
686 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
687 data |= mc_cg_ls_en[i];
689 data &= ~mc_cg_ls_en[i];
691 WREG32(mc_cg_registers[i], data);
695 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
701 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
702 orig = data = RREG32(mc_cg_registers[i]);
703 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
706 data &= ~mc_cg_en[i];
708 WREG32(mc_cg_registers[i], data);
712 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
717 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
719 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
720 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
721 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
722 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
723 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
725 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
726 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
727 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
728 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
732 WREG32_PCIE(ixPCIE_CNTL2, data);
735 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
740 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
742 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
743 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
745 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
748 WREG32(mmHDP_HOST_PATH_CNTL, data);
751 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
756 orig = data = RREG32(mmHDP_MEM_POWER_LS);
758 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
759 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
761 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
764 WREG32(mmHDP_MEM_POWER_LS, data);
768 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
770 switch (mc_seq_vram_type) {
771 case MC_SEQ_MISC0__MT__GDDR1:
772 return AMDGPU_VRAM_TYPE_GDDR1;
773 case MC_SEQ_MISC0__MT__DDR2:
774 return AMDGPU_VRAM_TYPE_DDR2;
775 case MC_SEQ_MISC0__MT__GDDR3:
776 return AMDGPU_VRAM_TYPE_GDDR3;
777 case MC_SEQ_MISC0__MT__GDDR4:
778 return AMDGPU_VRAM_TYPE_GDDR4;
779 case MC_SEQ_MISC0__MT__GDDR5:
780 return AMDGPU_VRAM_TYPE_GDDR5;
781 case MC_SEQ_MISC0__MT__DDR3:
782 return AMDGPU_VRAM_TYPE_DDR3;
784 return AMDGPU_VRAM_TYPE_UNKNOWN;
788 static int gmc_v6_0_early_init(void *handle)
790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
792 gmc_v6_0_set_gart_funcs(adev);
793 gmc_v6_0_set_irq_funcs(adev);
798 static int gmc_v6_0_late_init(void *handle)
800 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
802 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
803 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
808 static int gmc_v6_0_sw_init(void *handle)
812 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
814 if (adev->flags & AMD_IS_APU) {
815 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
817 u32 tmp = RREG32(mmMC_SEQ_MISC0);
818 tmp &= MC_SEQ_MISC0__MT__MASK;
819 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
822 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
826 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
830 amdgpu_vm_adjust_size(adev, 64, 4);
831 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
833 adev->mc.mc_mask = 0xffffffffffULL;
835 adev->mc.stolen_size = 256 * 1024;
837 adev->need_dma32 = false;
838 dma_bits = adev->need_dma32 ? 32 : 40;
839 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
841 adev->need_dma32 = true;
843 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
845 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
847 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
848 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
851 r = gmc_v6_0_init_microcode(adev);
853 dev_err(adev->dev, "Failed to load mc firmware!\n");
857 r = gmc_v6_0_mc_init(adev);
861 r = amdgpu_bo_init(adev);
865 r = gmc_v6_0_gart_init(adev);
871 * VMID 0 is reserved for System
872 * amdgpu graphics/compute will use VMIDs 1-7
873 * amdkfd will use VMIDs 8-15
875 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
876 adev->vm_manager.num_level = 1;
877 amdgpu_vm_manager_init(adev);
879 /* base offset of vram pages */
880 if (adev->flags & AMD_IS_APU) {
881 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
884 adev->vm_manager.vram_base_offset = tmp;
886 adev->vm_manager.vram_base_offset = 0;
892 static int gmc_v6_0_sw_fini(void *handle)
894 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
896 amdgpu_vm_manager_fini(adev);
897 gmc_v6_0_gart_fini(adev);
898 amdgpu_gem_force_release(adev);
899 amdgpu_bo_fini(adev);
904 static int gmc_v6_0_hw_init(void *handle)
907 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
909 gmc_v6_0_mc_program(adev);
911 if (!(adev->flags & AMD_IS_APU)) {
912 r = gmc_v6_0_mc_load_microcode(adev);
914 dev_err(adev->dev, "Failed to load MC firmware!\n");
919 r = gmc_v6_0_gart_enable(adev);
926 static int gmc_v6_0_hw_fini(void *handle)
928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
930 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
931 gmc_v6_0_gart_disable(adev);
936 static int gmc_v6_0_suspend(void *handle)
938 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
940 gmc_v6_0_hw_fini(adev);
945 static int gmc_v6_0_resume(void *handle)
948 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
950 r = gmc_v6_0_hw_init(adev);
954 amdgpu_vm_reset_all_ids(adev);
959 static bool gmc_v6_0_is_idle(void *handle)
961 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
962 u32 tmp = RREG32(mmSRBM_STATUS);
964 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
965 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
971 static int gmc_v6_0_wait_for_idle(void *handle)
974 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
976 for (i = 0; i < adev->usec_timeout; i++) {
977 if (gmc_v6_0_is_idle(handle))
985 static int gmc_v6_0_soft_reset(void *handle)
987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
988 u32 srbm_soft_reset = 0;
989 u32 tmp = RREG32(mmSRBM_STATUS);
991 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
992 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
993 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
995 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
996 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
997 if (!(adev->flags & AMD_IS_APU))
998 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
999 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1002 if (srbm_soft_reset) {
1003 gmc_v6_0_mc_stop(adev);
1004 if (gmc_v6_0_wait_for_idle(adev)) {
1005 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1009 tmp = RREG32(mmSRBM_SOFT_RESET);
1010 tmp |= srbm_soft_reset;
1011 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1012 WREG32(mmSRBM_SOFT_RESET, tmp);
1013 tmp = RREG32(mmSRBM_SOFT_RESET);
1017 tmp &= ~srbm_soft_reset;
1018 WREG32(mmSRBM_SOFT_RESET, tmp);
1019 tmp = RREG32(mmSRBM_SOFT_RESET);
1023 gmc_v6_0_mc_resume(adev);
1030 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1031 struct amdgpu_irq_src *src,
1033 enum amdgpu_interrupt_state state)
1036 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1037 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1038 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1039 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1040 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1041 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1044 case AMDGPU_IRQ_STATE_DISABLE:
1045 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1047 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1048 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1050 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1052 case AMDGPU_IRQ_STATE_ENABLE:
1053 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1055 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1056 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1058 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1067 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1068 struct amdgpu_irq_src *source,
1069 struct amdgpu_iv_entry *entry)
1073 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1074 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1075 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1077 if (!addr && !status)
1080 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1081 gmc_v6_0_set_fault_enable_default(adev, false);
1083 if (printk_ratelimit()) {
1084 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1085 entry->src_id, entry->src_data[0]);
1086 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1088 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1090 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1096 static int gmc_v6_0_set_clockgating_state(void *handle,
1097 enum amd_clockgating_state state)
1102 static int gmc_v6_0_set_powergating_state(void *handle,
1103 enum amd_powergating_state state)
1108 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1110 .early_init = gmc_v6_0_early_init,
1111 .late_init = gmc_v6_0_late_init,
1112 .sw_init = gmc_v6_0_sw_init,
1113 .sw_fini = gmc_v6_0_sw_fini,
1114 .hw_init = gmc_v6_0_hw_init,
1115 .hw_fini = gmc_v6_0_hw_fini,
1116 .suspend = gmc_v6_0_suspend,
1117 .resume = gmc_v6_0_resume,
1118 .is_idle = gmc_v6_0_is_idle,
1119 .wait_for_idle = gmc_v6_0_wait_for_idle,
1120 .soft_reset = gmc_v6_0_soft_reset,
1121 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1122 .set_powergating_state = gmc_v6_0_set_powergating_state,
1125 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1126 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1127 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1128 .set_prt = gmc_v6_0_set_prt,
1129 .get_vm_pde = gmc_v6_0_get_vm_pde,
1130 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1133 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1134 .set = gmc_v6_0_vm_fault_interrupt_state,
1135 .process = gmc_v6_0_process_interrupt,
1138 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1140 if (adev->gart.gart_funcs == NULL)
1141 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1144 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1146 adev->mc.vm_fault.num_types = 1;
1147 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1150 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1152 .type = AMD_IP_BLOCK_TYPE_GMC,
1156 .funcs = &gmc_v6_0_ip_funcs,