2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
30 #include "cik_structs.h"
32 #include "amdgpu_ucode.h"
33 #include "clearstate_ci.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "bif/bif_4_1_d.h"
39 #include "bif/bif_4_1_sh_mask.h"
41 #include "gca/gfx_7_0_d.h"
42 #include "gca/gfx_7_2_enum.h"
43 #include "gca/gfx_7_2_sh_mask.h"
45 #include "gmc/gmc_7_0_d.h"
46 #include "gmc/gmc_7_0_sh_mask.h"
48 #include "oss/oss_2_0_d.h"
49 #include "oss/oss_2_0_sh_mask.h"
51 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
53 #define GFX7_NUM_GFX_RINGS 1
54 #define GFX7_MEC_HPD_SIZE 2048
56 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
57 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
58 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
62 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
64 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
65 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
66 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
67 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
68 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
69 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
70 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
71 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
72 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
73 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
74 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
75 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
76 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
77 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
78 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
79 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
82 static const u32 spectre_rlc_save_restore_register_list[] =
84 (0x0e00 << 16) | (0xc12c >> 2),
86 (0x0e00 << 16) | (0xc140 >> 2),
88 (0x0e00 << 16) | (0xc150 >> 2),
90 (0x0e00 << 16) | (0xc15c >> 2),
92 (0x0e00 << 16) | (0xc168 >> 2),
94 (0x0e00 << 16) | (0xc170 >> 2),
96 (0x0e00 << 16) | (0xc178 >> 2),
98 (0x0e00 << 16) | (0xc204 >> 2),
100 (0x0e00 << 16) | (0xc2b4 >> 2),
102 (0x0e00 << 16) | (0xc2b8 >> 2),
104 (0x0e00 << 16) | (0xc2bc >> 2),
106 (0x0e00 << 16) | (0xc2c0 >> 2),
108 (0x0e00 << 16) | (0x8228 >> 2),
110 (0x0e00 << 16) | (0x829c >> 2),
112 (0x0e00 << 16) | (0x869c >> 2),
114 (0x0600 << 16) | (0x98f4 >> 2),
116 (0x0e00 << 16) | (0x98f8 >> 2),
118 (0x0e00 << 16) | (0x9900 >> 2),
120 (0x0e00 << 16) | (0xc260 >> 2),
122 (0x0e00 << 16) | (0x90e8 >> 2),
124 (0x0e00 << 16) | (0x3c000 >> 2),
126 (0x0e00 << 16) | (0x3c00c >> 2),
128 (0x0e00 << 16) | (0x8c1c >> 2),
130 (0x0e00 << 16) | (0x9700 >> 2),
132 (0x0e00 << 16) | (0xcd20 >> 2),
134 (0x4e00 << 16) | (0xcd20 >> 2),
136 (0x5e00 << 16) | (0xcd20 >> 2),
138 (0x6e00 << 16) | (0xcd20 >> 2),
140 (0x7e00 << 16) | (0xcd20 >> 2),
142 (0x8e00 << 16) | (0xcd20 >> 2),
144 (0x9e00 << 16) | (0xcd20 >> 2),
146 (0xae00 << 16) | (0xcd20 >> 2),
148 (0xbe00 << 16) | (0xcd20 >> 2),
150 (0x0e00 << 16) | (0x89bc >> 2),
152 (0x0e00 << 16) | (0x8900 >> 2),
155 (0x0e00 << 16) | (0xc130 >> 2),
157 (0x0e00 << 16) | (0xc134 >> 2),
159 (0x0e00 << 16) | (0xc1fc >> 2),
161 (0x0e00 << 16) | (0xc208 >> 2),
163 (0x0e00 << 16) | (0xc264 >> 2),
165 (0x0e00 << 16) | (0xc268 >> 2),
167 (0x0e00 << 16) | (0xc26c >> 2),
169 (0x0e00 << 16) | (0xc270 >> 2),
171 (0x0e00 << 16) | (0xc274 >> 2),
173 (0x0e00 << 16) | (0xc278 >> 2),
175 (0x0e00 << 16) | (0xc27c >> 2),
177 (0x0e00 << 16) | (0xc280 >> 2),
179 (0x0e00 << 16) | (0xc284 >> 2),
181 (0x0e00 << 16) | (0xc288 >> 2),
183 (0x0e00 << 16) | (0xc28c >> 2),
185 (0x0e00 << 16) | (0xc290 >> 2),
187 (0x0e00 << 16) | (0xc294 >> 2),
189 (0x0e00 << 16) | (0xc298 >> 2),
191 (0x0e00 << 16) | (0xc29c >> 2),
193 (0x0e00 << 16) | (0xc2a0 >> 2),
195 (0x0e00 << 16) | (0xc2a4 >> 2),
197 (0x0e00 << 16) | (0xc2a8 >> 2),
199 (0x0e00 << 16) | (0xc2ac >> 2),
201 (0x0e00 << 16) | (0xc2b0 >> 2),
203 (0x0e00 << 16) | (0x301d0 >> 2),
205 (0x0e00 << 16) | (0x30238 >> 2),
207 (0x0e00 << 16) | (0x30250 >> 2),
209 (0x0e00 << 16) | (0x30254 >> 2),
211 (0x0e00 << 16) | (0x30258 >> 2),
213 (0x0e00 << 16) | (0x3025c >> 2),
215 (0x4e00 << 16) | (0xc900 >> 2),
217 (0x5e00 << 16) | (0xc900 >> 2),
219 (0x6e00 << 16) | (0xc900 >> 2),
221 (0x7e00 << 16) | (0xc900 >> 2),
223 (0x8e00 << 16) | (0xc900 >> 2),
225 (0x9e00 << 16) | (0xc900 >> 2),
227 (0xae00 << 16) | (0xc900 >> 2),
229 (0xbe00 << 16) | (0xc900 >> 2),
231 (0x4e00 << 16) | (0xc904 >> 2),
233 (0x5e00 << 16) | (0xc904 >> 2),
235 (0x6e00 << 16) | (0xc904 >> 2),
237 (0x7e00 << 16) | (0xc904 >> 2),
239 (0x8e00 << 16) | (0xc904 >> 2),
241 (0x9e00 << 16) | (0xc904 >> 2),
243 (0xae00 << 16) | (0xc904 >> 2),
245 (0xbe00 << 16) | (0xc904 >> 2),
247 (0x4e00 << 16) | (0xc908 >> 2),
249 (0x5e00 << 16) | (0xc908 >> 2),
251 (0x6e00 << 16) | (0xc908 >> 2),
253 (0x7e00 << 16) | (0xc908 >> 2),
255 (0x8e00 << 16) | (0xc908 >> 2),
257 (0x9e00 << 16) | (0xc908 >> 2),
259 (0xae00 << 16) | (0xc908 >> 2),
261 (0xbe00 << 16) | (0xc908 >> 2),
263 (0x4e00 << 16) | (0xc90c >> 2),
265 (0x5e00 << 16) | (0xc90c >> 2),
267 (0x6e00 << 16) | (0xc90c >> 2),
269 (0x7e00 << 16) | (0xc90c >> 2),
271 (0x8e00 << 16) | (0xc90c >> 2),
273 (0x9e00 << 16) | (0xc90c >> 2),
275 (0xae00 << 16) | (0xc90c >> 2),
277 (0xbe00 << 16) | (0xc90c >> 2),
279 (0x4e00 << 16) | (0xc910 >> 2),
281 (0x5e00 << 16) | (0xc910 >> 2),
283 (0x6e00 << 16) | (0xc910 >> 2),
285 (0x7e00 << 16) | (0xc910 >> 2),
287 (0x8e00 << 16) | (0xc910 >> 2),
289 (0x9e00 << 16) | (0xc910 >> 2),
291 (0xae00 << 16) | (0xc910 >> 2),
293 (0xbe00 << 16) | (0xc910 >> 2),
295 (0x0e00 << 16) | (0xc99c >> 2),
297 (0x0e00 << 16) | (0x9834 >> 2),
299 (0x0000 << 16) | (0x30f00 >> 2),
301 (0x0001 << 16) | (0x30f00 >> 2),
303 (0x0000 << 16) | (0x30f04 >> 2),
305 (0x0001 << 16) | (0x30f04 >> 2),
307 (0x0000 << 16) | (0x30f08 >> 2),
309 (0x0001 << 16) | (0x30f08 >> 2),
311 (0x0000 << 16) | (0x30f0c >> 2),
313 (0x0001 << 16) | (0x30f0c >> 2),
315 (0x0600 << 16) | (0x9b7c >> 2),
317 (0x0e00 << 16) | (0x8a14 >> 2),
319 (0x0e00 << 16) | (0x8a18 >> 2),
321 (0x0600 << 16) | (0x30a00 >> 2),
323 (0x0e00 << 16) | (0x8bf0 >> 2),
325 (0x0e00 << 16) | (0x8bcc >> 2),
327 (0x0e00 << 16) | (0x8b24 >> 2),
329 (0x0e00 << 16) | (0x30a04 >> 2),
331 (0x0600 << 16) | (0x30a10 >> 2),
333 (0x0600 << 16) | (0x30a14 >> 2),
335 (0x0600 << 16) | (0x30a18 >> 2),
337 (0x0600 << 16) | (0x30a2c >> 2),
339 (0x0e00 << 16) | (0xc700 >> 2),
341 (0x0e00 << 16) | (0xc704 >> 2),
343 (0x0e00 << 16) | (0xc708 >> 2),
345 (0x0e00 << 16) | (0xc768 >> 2),
347 (0x0400 << 16) | (0xc770 >> 2),
349 (0x0400 << 16) | (0xc774 >> 2),
351 (0x0400 << 16) | (0xc778 >> 2),
353 (0x0400 << 16) | (0xc77c >> 2),
355 (0x0400 << 16) | (0xc780 >> 2),
357 (0x0400 << 16) | (0xc784 >> 2),
359 (0x0400 << 16) | (0xc788 >> 2),
361 (0x0400 << 16) | (0xc78c >> 2),
363 (0x0400 << 16) | (0xc798 >> 2),
365 (0x0400 << 16) | (0xc79c >> 2),
367 (0x0400 << 16) | (0xc7a0 >> 2),
369 (0x0400 << 16) | (0xc7a4 >> 2),
371 (0x0400 << 16) | (0xc7a8 >> 2),
373 (0x0400 << 16) | (0xc7ac >> 2),
375 (0x0400 << 16) | (0xc7b0 >> 2),
377 (0x0400 << 16) | (0xc7b4 >> 2),
379 (0x0e00 << 16) | (0x9100 >> 2),
381 (0x0e00 << 16) | (0x3c010 >> 2),
383 (0x0e00 << 16) | (0x92a8 >> 2),
385 (0x0e00 << 16) | (0x92ac >> 2),
387 (0x0e00 << 16) | (0x92b4 >> 2),
389 (0x0e00 << 16) | (0x92b8 >> 2),
391 (0x0e00 << 16) | (0x92bc >> 2),
393 (0x0e00 << 16) | (0x92c0 >> 2),
395 (0x0e00 << 16) | (0x92c4 >> 2),
397 (0x0e00 << 16) | (0x92c8 >> 2),
399 (0x0e00 << 16) | (0x92cc >> 2),
401 (0x0e00 << 16) | (0x92d0 >> 2),
403 (0x0e00 << 16) | (0x8c00 >> 2),
405 (0x0e00 << 16) | (0x8c04 >> 2),
407 (0x0e00 << 16) | (0x8c20 >> 2),
409 (0x0e00 << 16) | (0x8c38 >> 2),
411 (0x0e00 << 16) | (0x8c3c >> 2),
413 (0x0e00 << 16) | (0xae00 >> 2),
415 (0x0e00 << 16) | (0x9604 >> 2),
417 (0x0e00 << 16) | (0xac08 >> 2),
419 (0x0e00 << 16) | (0xac0c >> 2),
421 (0x0e00 << 16) | (0xac10 >> 2),
423 (0x0e00 << 16) | (0xac14 >> 2),
425 (0x0e00 << 16) | (0xac58 >> 2),
427 (0x0e00 << 16) | (0xac68 >> 2),
429 (0x0e00 << 16) | (0xac6c >> 2),
431 (0x0e00 << 16) | (0xac70 >> 2),
433 (0x0e00 << 16) | (0xac74 >> 2),
435 (0x0e00 << 16) | (0xac78 >> 2),
437 (0x0e00 << 16) | (0xac7c >> 2),
439 (0x0e00 << 16) | (0xac80 >> 2),
441 (0x0e00 << 16) | (0xac84 >> 2),
443 (0x0e00 << 16) | (0xac88 >> 2),
445 (0x0e00 << 16) | (0xac8c >> 2),
447 (0x0e00 << 16) | (0x970c >> 2),
449 (0x0e00 << 16) | (0x9714 >> 2),
451 (0x0e00 << 16) | (0x9718 >> 2),
453 (0x0e00 << 16) | (0x971c >> 2),
455 (0x0e00 << 16) | (0x31068 >> 2),
457 (0x4e00 << 16) | (0x31068 >> 2),
459 (0x5e00 << 16) | (0x31068 >> 2),
461 (0x6e00 << 16) | (0x31068 >> 2),
463 (0x7e00 << 16) | (0x31068 >> 2),
465 (0x8e00 << 16) | (0x31068 >> 2),
467 (0x9e00 << 16) | (0x31068 >> 2),
469 (0xae00 << 16) | (0x31068 >> 2),
471 (0xbe00 << 16) | (0x31068 >> 2),
473 (0x0e00 << 16) | (0xcd10 >> 2),
475 (0x0e00 << 16) | (0xcd14 >> 2),
477 (0x0e00 << 16) | (0x88b0 >> 2),
479 (0x0e00 << 16) | (0x88b4 >> 2),
481 (0x0e00 << 16) | (0x88b8 >> 2),
483 (0x0e00 << 16) | (0x88bc >> 2),
485 (0x0400 << 16) | (0x89c0 >> 2),
487 (0x0e00 << 16) | (0x88c4 >> 2),
489 (0x0e00 << 16) | (0x88c8 >> 2),
491 (0x0e00 << 16) | (0x88d0 >> 2),
493 (0x0e00 << 16) | (0x88d4 >> 2),
495 (0x0e00 << 16) | (0x88d8 >> 2),
497 (0x0e00 << 16) | (0x8980 >> 2),
499 (0x0e00 << 16) | (0x30938 >> 2),
501 (0x0e00 << 16) | (0x3093c >> 2),
503 (0x0e00 << 16) | (0x30940 >> 2),
505 (0x0e00 << 16) | (0x89a0 >> 2),
507 (0x0e00 << 16) | (0x30900 >> 2),
509 (0x0e00 << 16) | (0x30904 >> 2),
511 (0x0e00 << 16) | (0x89b4 >> 2),
513 (0x0e00 << 16) | (0x3c210 >> 2),
515 (0x0e00 << 16) | (0x3c214 >> 2),
517 (0x0e00 << 16) | (0x3c218 >> 2),
519 (0x0e00 << 16) | (0x8904 >> 2),
522 (0x0e00 << 16) | (0x8c28 >> 2),
523 (0x0e00 << 16) | (0x8c2c >> 2),
524 (0x0e00 << 16) | (0x8c30 >> 2),
525 (0x0e00 << 16) | (0x8c34 >> 2),
526 (0x0e00 << 16) | (0x9600 >> 2),
529 static const u32 kalindi_rlc_save_restore_register_list[] =
531 (0x0e00 << 16) | (0xc12c >> 2),
533 (0x0e00 << 16) | (0xc140 >> 2),
535 (0x0e00 << 16) | (0xc150 >> 2),
537 (0x0e00 << 16) | (0xc15c >> 2),
539 (0x0e00 << 16) | (0xc168 >> 2),
541 (0x0e00 << 16) | (0xc170 >> 2),
543 (0x0e00 << 16) | (0xc204 >> 2),
545 (0x0e00 << 16) | (0xc2b4 >> 2),
547 (0x0e00 << 16) | (0xc2b8 >> 2),
549 (0x0e00 << 16) | (0xc2bc >> 2),
551 (0x0e00 << 16) | (0xc2c0 >> 2),
553 (0x0e00 << 16) | (0x8228 >> 2),
555 (0x0e00 << 16) | (0x829c >> 2),
557 (0x0e00 << 16) | (0x869c >> 2),
559 (0x0600 << 16) | (0x98f4 >> 2),
561 (0x0e00 << 16) | (0x98f8 >> 2),
563 (0x0e00 << 16) | (0x9900 >> 2),
565 (0x0e00 << 16) | (0xc260 >> 2),
567 (0x0e00 << 16) | (0x90e8 >> 2),
569 (0x0e00 << 16) | (0x3c000 >> 2),
571 (0x0e00 << 16) | (0x3c00c >> 2),
573 (0x0e00 << 16) | (0x8c1c >> 2),
575 (0x0e00 << 16) | (0x9700 >> 2),
577 (0x0e00 << 16) | (0xcd20 >> 2),
579 (0x4e00 << 16) | (0xcd20 >> 2),
581 (0x5e00 << 16) | (0xcd20 >> 2),
583 (0x6e00 << 16) | (0xcd20 >> 2),
585 (0x7e00 << 16) | (0xcd20 >> 2),
587 (0x0e00 << 16) | (0x89bc >> 2),
589 (0x0e00 << 16) | (0x8900 >> 2),
592 (0x0e00 << 16) | (0xc130 >> 2),
594 (0x0e00 << 16) | (0xc134 >> 2),
596 (0x0e00 << 16) | (0xc1fc >> 2),
598 (0x0e00 << 16) | (0xc208 >> 2),
600 (0x0e00 << 16) | (0xc264 >> 2),
602 (0x0e00 << 16) | (0xc268 >> 2),
604 (0x0e00 << 16) | (0xc26c >> 2),
606 (0x0e00 << 16) | (0xc270 >> 2),
608 (0x0e00 << 16) | (0xc274 >> 2),
610 (0x0e00 << 16) | (0xc28c >> 2),
612 (0x0e00 << 16) | (0xc290 >> 2),
614 (0x0e00 << 16) | (0xc294 >> 2),
616 (0x0e00 << 16) | (0xc298 >> 2),
618 (0x0e00 << 16) | (0xc2a0 >> 2),
620 (0x0e00 << 16) | (0xc2a4 >> 2),
622 (0x0e00 << 16) | (0xc2a8 >> 2),
624 (0x0e00 << 16) | (0xc2ac >> 2),
626 (0x0e00 << 16) | (0x301d0 >> 2),
628 (0x0e00 << 16) | (0x30238 >> 2),
630 (0x0e00 << 16) | (0x30250 >> 2),
632 (0x0e00 << 16) | (0x30254 >> 2),
634 (0x0e00 << 16) | (0x30258 >> 2),
636 (0x0e00 << 16) | (0x3025c >> 2),
638 (0x4e00 << 16) | (0xc900 >> 2),
640 (0x5e00 << 16) | (0xc900 >> 2),
642 (0x6e00 << 16) | (0xc900 >> 2),
644 (0x7e00 << 16) | (0xc900 >> 2),
646 (0x4e00 << 16) | (0xc904 >> 2),
648 (0x5e00 << 16) | (0xc904 >> 2),
650 (0x6e00 << 16) | (0xc904 >> 2),
652 (0x7e00 << 16) | (0xc904 >> 2),
654 (0x4e00 << 16) | (0xc908 >> 2),
656 (0x5e00 << 16) | (0xc908 >> 2),
658 (0x6e00 << 16) | (0xc908 >> 2),
660 (0x7e00 << 16) | (0xc908 >> 2),
662 (0x4e00 << 16) | (0xc90c >> 2),
664 (0x5e00 << 16) | (0xc90c >> 2),
666 (0x6e00 << 16) | (0xc90c >> 2),
668 (0x7e00 << 16) | (0xc90c >> 2),
670 (0x4e00 << 16) | (0xc910 >> 2),
672 (0x5e00 << 16) | (0xc910 >> 2),
674 (0x6e00 << 16) | (0xc910 >> 2),
676 (0x7e00 << 16) | (0xc910 >> 2),
678 (0x0e00 << 16) | (0xc99c >> 2),
680 (0x0e00 << 16) | (0x9834 >> 2),
682 (0x0000 << 16) | (0x30f00 >> 2),
684 (0x0000 << 16) | (0x30f04 >> 2),
686 (0x0000 << 16) | (0x30f08 >> 2),
688 (0x0000 << 16) | (0x30f0c >> 2),
690 (0x0600 << 16) | (0x9b7c >> 2),
692 (0x0e00 << 16) | (0x8a14 >> 2),
694 (0x0e00 << 16) | (0x8a18 >> 2),
696 (0x0600 << 16) | (0x30a00 >> 2),
698 (0x0e00 << 16) | (0x8bf0 >> 2),
700 (0x0e00 << 16) | (0x8bcc >> 2),
702 (0x0e00 << 16) | (0x8b24 >> 2),
704 (0x0e00 << 16) | (0x30a04 >> 2),
706 (0x0600 << 16) | (0x30a10 >> 2),
708 (0x0600 << 16) | (0x30a14 >> 2),
710 (0x0600 << 16) | (0x30a18 >> 2),
712 (0x0600 << 16) | (0x30a2c >> 2),
714 (0x0e00 << 16) | (0xc700 >> 2),
716 (0x0e00 << 16) | (0xc704 >> 2),
718 (0x0e00 << 16) | (0xc708 >> 2),
720 (0x0e00 << 16) | (0xc768 >> 2),
722 (0x0400 << 16) | (0xc770 >> 2),
724 (0x0400 << 16) | (0xc774 >> 2),
726 (0x0400 << 16) | (0xc798 >> 2),
728 (0x0400 << 16) | (0xc79c >> 2),
730 (0x0e00 << 16) | (0x9100 >> 2),
732 (0x0e00 << 16) | (0x3c010 >> 2),
734 (0x0e00 << 16) | (0x8c00 >> 2),
736 (0x0e00 << 16) | (0x8c04 >> 2),
738 (0x0e00 << 16) | (0x8c20 >> 2),
740 (0x0e00 << 16) | (0x8c38 >> 2),
742 (0x0e00 << 16) | (0x8c3c >> 2),
744 (0x0e00 << 16) | (0xae00 >> 2),
746 (0x0e00 << 16) | (0x9604 >> 2),
748 (0x0e00 << 16) | (0xac08 >> 2),
750 (0x0e00 << 16) | (0xac0c >> 2),
752 (0x0e00 << 16) | (0xac10 >> 2),
754 (0x0e00 << 16) | (0xac14 >> 2),
756 (0x0e00 << 16) | (0xac58 >> 2),
758 (0x0e00 << 16) | (0xac68 >> 2),
760 (0x0e00 << 16) | (0xac6c >> 2),
762 (0x0e00 << 16) | (0xac70 >> 2),
764 (0x0e00 << 16) | (0xac74 >> 2),
766 (0x0e00 << 16) | (0xac78 >> 2),
768 (0x0e00 << 16) | (0xac7c >> 2),
770 (0x0e00 << 16) | (0xac80 >> 2),
772 (0x0e00 << 16) | (0xac84 >> 2),
774 (0x0e00 << 16) | (0xac88 >> 2),
776 (0x0e00 << 16) | (0xac8c >> 2),
778 (0x0e00 << 16) | (0x970c >> 2),
780 (0x0e00 << 16) | (0x9714 >> 2),
782 (0x0e00 << 16) | (0x9718 >> 2),
784 (0x0e00 << 16) | (0x971c >> 2),
786 (0x0e00 << 16) | (0x31068 >> 2),
788 (0x4e00 << 16) | (0x31068 >> 2),
790 (0x5e00 << 16) | (0x31068 >> 2),
792 (0x6e00 << 16) | (0x31068 >> 2),
794 (0x7e00 << 16) | (0x31068 >> 2),
796 (0x0e00 << 16) | (0xcd10 >> 2),
798 (0x0e00 << 16) | (0xcd14 >> 2),
800 (0x0e00 << 16) | (0x88b0 >> 2),
802 (0x0e00 << 16) | (0x88b4 >> 2),
804 (0x0e00 << 16) | (0x88b8 >> 2),
806 (0x0e00 << 16) | (0x88bc >> 2),
808 (0x0400 << 16) | (0x89c0 >> 2),
810 (0x0e00 << 16) | (0x88c4 >> 2),
812 (0x0e00 << 16) | (0x88c8 >> 2),
814 (0x0e00 << 16) | (0x88d0 >> 2),
816 (0x0e00 << 16) | (0x88d4 >> 2),
818 (0x0e00 << 16) | (0x88d8 >> 2),
820 (0x0e00 << 16) | (0x8980 >> 2),
822 (0x0e00 << 16) | (0x30938 >> 2),
824 (0x0e00 << 16) | (0x3093c >> 2),
826 (0x0e00 << 16) | (0x30940 >> 2),
828 (0x0e00 << 16) | (0x89a0 >> 2),
830 (0x0e00 << 16) | (0x30900 >> 2),
832 (0x0e00 << 16) | (0x30904 >> 2),
834 (0x0e00 << 16) | (0x89b4 >> 2),
836 (0x0e00 << 16) | (0x3e1fc >> 2),
838 (0x0e00 << 16) | (0x3c210 >> 2),
840 (0x0e00 << 16) | (0x3c214 >> 2),
842 (0x0e00 << 16) | (0x3c218 >> 2),
844 (0x0e00 << 16) | (0x8904 >> 2),
847 (0x0e00 << 16) | (0x8c28 >> 2),
848 (0x0e00 << 16) | (0x8c2c >> 2),
849 (0x0e00 << 16) | (0x8c30 >> 2),
850 (0x0e00 << 16) | (0x8c34 >> 2),
851 (0x0e00 << 16) | (0x9600 >> 2),
854 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
855 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
856 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
857 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
858 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
864 * gfx_v7_0_init_microcode - load ucode images from disk
866 * @adev: amdgpu_device pointer
868 * Use the firmware interface to load the ucode images into
869 * the driver (not loaded into hw).
870 * Returns 0 on success, error on failure.
872 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
874 const char *chip_name;
880 switch (adev->asic_type) {
882 chip_name = "bonaire";
885 chip_name = "hawaii";
888 chip_name = "kaveri";
891 chip_name = "kabini";
894 chip_name = "mullins";
899 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
900 err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
903 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
907 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
908 err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
911 err = amdgpu_ucode_validate(adev->gfx.me_fw);
915 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
916 err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
919 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
923 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
924 err = reject_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
927 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
931 if (adev->asic_type == CHIP_KAVERI) {
932 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
933 err = reject_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
936 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
941 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
942 err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
945 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
949 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
950 release_firmware(adev->gfx.pfp_fw);
951 adev->gfx.pfp_fw = NULL;
952 release_firmware(adev->gfx.me_fw);
953 adev->gfx.me_fw = NULL;
954 release_firmware(adev->gfx.ce_fw);
955 adev->gfx.ce_fw = NULL;
956 release_firmware(adev->gfx.mec_fw);
957 adev->gfx.mec_fw = NULL;
958 release_firmware(adev->gfx.mec2_fw);
959 adev->gfx.mec2_fw = NULL;
960 release_firmware(adev->gfx.rlc_fw);
961 adev->gfx.rlc_fw = NULL;
966 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
968 release_firmware(adev->gfx.pfp_fw);
969 adev->gfx.pfp_fw = NULL;
970 release_firmware(adev->gfx.me_fw);
971 adev->gfx.me_fw = NULL;
972 release_firmware(adev->gfx.ce_fw);
973 adev->gfx.ce_fw = NULL;
974 release_firmware(adev->gfx.mec_fw);
975 adev->gfx.mec_fw = NULL;
976 release_firmware(adev->gfx.mec2_fw);
977 adev->gfx.mec2_fw = NULL;
978 release_firmware(adev->gfx.rlc_fw);
979 adev->gfx.rlc_fw = NULL;
983 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
985 * @adev: amdgpu_device pointer
987 * Starting with SI, the tiling setup is done globally in a
988 * set of 32 tiling modes. Rather than selecting each set of
989 * parameters per surface as on older asics, we just select
990 * which index in the tiling table we want to use, and the
991 * surface uses those parameters (CIK).
993 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
995 const u32 num_tile_mode_states =
996 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
997 const u32 num_secondary_tile_mode_states =
998 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
999 u32 reg_offset, split_equal_to_row_size;
1000 uint32_t *tile, *macrotile;
1002 tile = adev->gfx.config.tile_mode_array;
1003 macrotile = adev->gfx.config.macrotile_mode_array;
1005 switch (adev->gfx.config.mem_row_size_in_kb) {
1007 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1011 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1014 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1018 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1019 tile[reg_offset] = 0;
1020 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1021 macrotile[reg_offset] = 0;
1023 switch (adev->asic_type) {
1025 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1028 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1029 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1030 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1031 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1032 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1033 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1035 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1036 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1037 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1040 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1043 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1044 TILE_SPLIT(split_equal_to_row_size));
1045 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1046 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1048 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1049 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1050 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1051 TILE_SPLIT(split_equal_to_row_size));
1052 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1053 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1055 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1056 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1058 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1059 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1061 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1062 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1063 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1065 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1066 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1067 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1070 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1074 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1078 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1079 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1080 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1081 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1082 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1083 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1086 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1087 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1088 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1089 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1090 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1094 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1095 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1096 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1097 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1098 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1102 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1103 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1104 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1105 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1107 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1108 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1109 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1110 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1111 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1118 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1122 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1126 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1128 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1129 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1130 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1131 NUM_BANKS(ADDR_SURF_16_BANK));
1132 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1135 NUM_BANKS(ADDR_SURF_16_BANK));
1136 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1139 NUM_BANKS(ADDR_SURF_16_BANK));
1140 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1143 NUM_BANKS(ADDR_SURF_16_BANK));
1144 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1147 NUM_BANKS(ADDR_SURF_16_BANK));
1148 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_8_BANK));
1152 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1155 NUM_BANKS(ADDR_SURF_4_BANK));
1156 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163 NUM_BANKS(ADDR_SURF_16_BANK));
1164 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1167 NUM_BANKS(ADDR_SURF_16_BANK));
1168 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179 NUM_BANKS(ADDR_SURF_8_BANK));
1180 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_4_BANK));
1185 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1186 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1187 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1188 if (reg_offset != 7)
1189 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1192 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1193 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1195 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1196 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1197 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1198 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1199 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1200 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1201 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1202 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1203 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1204 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1207 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1208 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1210 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1211 TILE_SPLIT(split_equal_to_row_size));
1212 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1214 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1215 TILE_SPLIT(split_equal_to_row_size));
1216 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1217 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1218 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1219 TILE_SPLIT(split_equal_to_row_size));
1220 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1223 TILE_SPLIT(split_equal_to_row_size));
1224 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1226 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1227 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1228 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1229 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1230 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1233 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1237 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1238 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1239 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1240 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1241 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1244 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1247 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1248 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1250 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1251 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1252 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1254 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1255 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1256 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1260 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1264 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1267 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1268 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1269 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1270 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1271 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1273 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1275 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1276 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1277 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1279 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1280 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1283 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1287 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1292 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1295 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1298 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1300 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1302 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1304 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1306 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1307 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1308 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1311 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1312 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1313 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1314 NUM_BANKS(ADDR_SURF_16_BANK));
1315 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1316 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1317 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1318 NUM_BANKS(ADDR_SURF_16_BANK));
1319 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1322 NUM_BANKS(ADDR_SURF_16_BANK));
1323 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1326 NUM_BANKS(ADDR_SURF_16_BANK));
1327 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1330 NUM_BANKS(ADDR_SURF_8_BANK));
1331 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1334 NUM_BANKS(ADDR_SURF_4_BANK));
1335 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1338 NUM_BANKS(ADDR_SURF_4_BANK));
1339 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342 NUM_BANKS(ADDR_SURF_16_BANK));
1343 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346 NUM_BANKS(ADDR_SURF_16_BANK));
1347 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_16_BANK));
1351 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354 NUM_BANKS(ADDR_SURF_8_BANK));
1355 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1358 NUM_BANKS(ADDR_SURF_16_BANK));
1359 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1362 NUM_BANKS(ADDR_SURF_8_BANK));
1363 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_4_BANK));
1368 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1369 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1370 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1371 if (reg_offset != 7)
1372 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1378 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1379 PIPE_CONFIG(ADDR_SURF_P2) |
1380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1381 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1382 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1383 PIPE_CONFIG(ADDR_SURF_P2) |
1384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1385 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1386 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1387 PIPE_CONFIG(ADDR_SURF_P2) |
1388 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1389 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1390 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391 PIPE_CONFIG(ADDR_SURF_P2) |
1392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1393 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1394 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395 PIPE_CONFIG(ADDR_SURF_P2) |
1396 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1397 TILE_SPLIT(split_equal_to_row_size));
1398 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1399 PIPE_CONFIG(ADDR_SURF_P2) |
1400 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1401 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1402 PIPE_CONFIG(ADDR_SURF_P2) |
1403 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1404 TILE_SPLIT(split_equal_to_row_size));
1405 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1406 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1407 PIPE_CONFIG(ADDR_SURF_P2));
1408 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1409 PIPE_CONFIG(ADDR_SURF_P2) |
1410 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1411 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1412 PIPE_CONFIG(ADDR_SURF_P2) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1414 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1415 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1416 PIPE_CONFIG(ADDR_SURF_P2) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1418 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1419 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1420 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1421 PIPE_CONFIG(ADDR_SURF_P2) |
1422 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1423 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424 PIPE_CONFIG(ADDR_SURF_P2) |
1425 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P2) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1431 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1432 PIPE_CONFIG(ADDR_SURF_P2) |
1433 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1434 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1435 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1436 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1437 PIPE_CONFIG(ADDR_SURF_P2) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1440 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1441 PIPE_CONFIG(ADDR_SURF_P2) |
1442 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1443 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1447 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1448 PIPE_CONFIG(ADDR_SURF_P2) |
1449 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1450 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1451 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1452 PIPE_CONFIG(ADDR_SURF_P2) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1455 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1456 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1457 PIPE_CONFIG(ADDR_SURF_P2) |
1458 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1459 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1460 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1461 PIPE_CONFIG(ADDR_SURF_P2) |
1462 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1464 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1465 PIPE_CONFIG(ADDR_SURF_P2) |
1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1471 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1472 PIPE_CONFIG(ADDR_SURF_P2) |
1473 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1475 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1476 PIPE_CONFIG(ADDR_SURF_P2) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1479 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1481 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1484 NUM_BANKS(ADDR_SURF_8_BANK));
1485 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1488 NUM_BANKS(ADDR_SURF_8_BANK));
1489 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1492 NUM_BANKS(ADDR_SURF_8_BANK));
1493 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1496 NUM_BANKS(ADDR_SURF_8_BANK));
1497 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1500 NUM_BANKS(ADDR_SURF_8_BANK));
1501 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1504 NUM_BANKS(ADDR_SURF_8_BANK));
1505 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1508 NUM_BANKS(ADDR_SURF_8_BANK));
1509 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512 NUM_BANKS(ADDR_SURF_16_BANK));
1513 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516 NUM_BANKS(ADDR_SURF_16_BANK));
1517 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1520 NUM_BANKS(ADDR_SURF_16_BANK));
1521 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1524 NUM_BANKS(ADDR_SURF_16_BANK));
1525 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528 NUM_BANKS(ADDR_SURF_16_BANK));
1529 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532 NUM_BANKS(ADDR_SURF_16_BANK));
1533 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536 NUM_BANKS(ADDR_SURF_8_BANK));
1538 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1539 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1540 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1541 if (reg_offset != 7)
1542 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1548 * gfx_v7_0_select_se_sh - select which SE, SH to address
1550 * @adev: amdgpu_device pointer
1551 * @se_num: shader engine to address
1552 * @sh_num: sh block to address
1554 * Select which SE, SH combinations to address. Certain
1555 * registers are instanced per SE or SH. 0xffffffff means
1556 * broadcast to all SEs or SHs (CIK).
1558 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1559 u32 se_num, u32 sh_num, u32 instance)
1563 if (instance == 0xffffffff)
1564 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1566 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1568 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1569 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1570 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1571 else if (se_num == 0xffffffff)
1572 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1573 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1574 else if (sh_num == 0xffffffff)
1575 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1576 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1578 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1579 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1580 WREG32(mmGRBM_GFX_INDEX, data);
1584 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1586 * @adev: amdgpu_device pointer
1588 * Calculates the bitmask of enabled RBs (CIK).
1589 * Returns the enabled RB bitmask.
1591 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1595 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1596 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1598 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1599 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1601 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1602 adev->gfx.config.max_sh_per_se);
1604 return (~data) & mask;
1608 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1610 switch (adev->asic_type) {
1612 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1613 SE_XSEL(1) | SE_YSEL(1);
1617 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1618 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1619 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1621 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1625 *rconf |= RB_MAP_PKR0(2);
1634 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1640 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1641 u32 raster_config, u32 raster_config_1,
1642 unsigned rb_mask, unsigned num_rb)
1644 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1645 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1646 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1647 unsigned rb_per_se = num_rb / num_se;
1648 unsigned se_mask[4];
1651 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1652 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1653 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1654 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1656 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1657 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1658 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1660 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1661 (!se_mask[2] && !se_mask[3]))) {
1662 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1664 if (!se_mask[0] && !se_mask[1]) {
1666 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1669 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1673 for (se = 0; se < num_se; se++) {
1674 unsigned raster_config_se = raster_config;
1675 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1676 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1677 int idx = (se / 2) * 2;
1679 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1680 raster_config_se &= ~SE_MAP_MASK;
1682 if (!se_mask[idx]) {
1683 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1685 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1689 pkr0_mask &= rb_mask;
1690 pkr1_mask &= rb_mask;
1691 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1692 raster_config_se &= ~PKR_MAP_MASK;
1695 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1697 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1701 if (rb_per_se >= 2) {
1702 unsigned rb0_mask = 1 << (se * rb_per_se);
1703 unsigned rb1_mask = rb0_mask << 1;
1705 rb0_mask &= rb_mask;
1706 rb1_mask &= rb_mask;
1707 if (!rb0_mask || !rb1_mask) {
1708 raster_config_se &= ~RB_MAP_PKR0_MASK;
1712 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1715 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1719 if (rb_per_se > 2) {
1720 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1721 rb1_mask = rb0_mask << 1;
1722 rb0_mask &= rb_mask;
1723 rb1_mask &= rb_mask;
1724 if (!rb0_mask || !rb1_mask) {
1725 raster_config_se &= ~RB_MAP_PKR1_MASK;
1729 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1732 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1738 /* GRBM_GFX_INDEX has a different offset on CI+ */
1739 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1740 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1741 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1744 /* GRBM_GFX_INDEX has a different offset on CI+ */
1745 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1749 * gfx_v7_0_setup_rb - setup the RBs on the asic
1751 * @adev: amdgpu_device pointer
1752 * @se_num: number of SEs (shader engines) for the asic
1753 * @sh_per_se: number of SH blocks per SE for the asic
1755 * Configures per-SE/SH RB registers (CIK).
1757 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1761 u32 raster_config = 0, raster_config_1 = 0;
1763 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1764 adev->gfx.config.max_sh_per_se;
1765 unsigned num_rb_pipes;
1767 mutex_lock(&adev->grbm_idx_mutex);
1768 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1769 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1770 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1771 data = gfx_v7_0_get_rb_active_bitmap(adev);
1772 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1773 rb_bitmap_width_per_sh);
1776 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1778 adev->gfx.config.backend_enable_mask = active_rbs;
1779 adev->gfx.config.num_rbs = hweight32(active_rbs);
1781 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1782 adev->gfx.config.max_shader_engines, 16);
1784 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1786 if (!adev->gfx.config.backend_enable_mask ||
1787 adev->gfx.config.num_rbs >= num_rb_pipes) {
1788 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1789 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1791 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1792 adev->gfx.config.backend_enable_mask,
1796 /* cache the values for userspace */
1797 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1798 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1799 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1800 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1801 RREG32(mmCC_RB_BACKEND_DISABLE);
1802 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1803 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1804 adev->gfx.config.rb_config[i][j].raster_config =
1805 RREG32(mmPA_SC_RASTER_CONFIG);
1806 adev->gfx.config.rb_config[i][j].raster_config_1 =
1807 RREG32(mmPA_SC_RASTER_CONFIG_1);
1810 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1811 mutex_unlock(&adev->grbm_idx_mutex);
1815 * gfx_v7_0_init_compute_vmid - gart enable
1817 * @adev: amdgpu_device pointer
1819 * Initialize compute vmid sh_mem registers
1822 #define DEFAULT_SH_MEM_BASES (0x6000)
1823 #define FIRST_COMPUTE_VMID (8)
1824 #define LAST_COMPUTE_VMID (16)
1825 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1828 uint32_t sh_mem_config;
1829 uint32_t sh_mem_bases;
1832 * Configure apertures:
1833 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1834 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1835 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1837 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1838 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1839 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1840 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1841 mutex_lock(&adev->srbm_mutex);
1842 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1843 cik_srbm_select(adev, 0, 0, 0, i);
1844 /* CP and shaders */
1845 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1846 WREG32(mmSH_MEM_APE1_BASE, 1);
1847 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1848 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1850 cik_srbm_select(adev, 0, 0, 0, 0);
1851 mutex_unlock(&adev->srbm_mutex);
1854 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1856 adev->gfx.config.double_offchip_lds_buf = 1;
1860 * gfx_v7_0_gpu_init - setup the 3D engine
1862 * @adev: amdgpu_device pointer
1864 * Configures the 3D engine and tiling configuration
1865 * registers so that the 3D engine is usable.
1867 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1869 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1873 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1875 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1876 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1877 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1879 gfx_v7_0_tiling_mode_table_init(adev);
1881 gfx_v7_0_setup_rb(adev);
1882 gfx_v7_0_get_cu_info(adev);
1883 gfx_v7_0_config_init(adev);
1885 /* set HW defaults for 3D engine */
1886 WREG32(mmCP_MEQ_THRESHOLDS,
1887 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1888 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1890 mutex_lock(&adev->grbm_idx_mutex);
1892 * making sure that the following register writes will be broadcasted
1893 * to all the shaders
1895 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1897 /* XXX SH_MEM regs */
1898 /* where to put LDS, scratch, GPUVM in FSA64 space */
1899 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1900 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1901 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1903 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1905 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1907 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1909 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1911 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1913 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1915 mutex_lock(&adev->srbm_mutex);
1916 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1920 sh_mem_base = adev->gmc.shared_aperture_start >> 48;
1921 cik_srbm_select(adev, 0, 0, 0, i);
1922 /* CP and shaders */
1923 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1924 WREG32(mmSH_MEM_APE1_BASE, 1);
1925 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1926 WREG32(mmSH_MEM_BASES, sh_mem_base);
1928 cik_srbm_select(adev, 0, 0, 0, 0);
1929 mutex_unlock(&adev->srbm_mutex);
1931 gfx_v7_0_init_compute_vmid(adev);
1933 WREG32(mmSX_DEBUG_1, 0x20);
1935 WREG32(mmTA_CNTL_AUX, 0x00010000);
1937 tmp = RREG32(mmSPI_CONFIG_CNTL);
1939 WREG32(mmSPI_CONFIG_CNTL, tmp);
1941 WREG32(mmSQ_CONFIG, 1);
1943 WREG32(mmDB_DEBUG, 0);
1945 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1947 WREG32(mmDB_DEBUG2, tmp);
1949 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1951 WREG32(mmDB_DEBUG3, tmp);
1953 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1955 WREG32(mmCB_HW_CONTROL, tmp);
1957 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1959 WREG32(mmPA_SC_FIFO_SIZE,
1960 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1961 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1962 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1963 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1965 WREG32(mmVGT_NUM_INSTANCES, 1);
1967 WREG32(mmCP_PERFMON_CNTL, 0);
1969 WREG32(mmSQ_CONFIG, 0);
1971 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1972 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1973 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1975 WREG32(mmVGT_CACHE_INVALIDATION,
1976 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1977 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1979 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1980 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1982 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1983 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1984 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1986 tmp = RREG32(mmSPI_ARB_PRIORITY);
1987 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
1988 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
1989 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
1990 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
1991 WREG32(mmSPI_ARB_PRIORITY, tmp);
1993 mutex_unlock(&adev->grbm_idx_mutex);
1999 * GPU scratch registers helpers function.
2002 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2004 * @adev: amdgpu_device pointer
2006 * Set up the number and offset of the CP scratch registers.
2007 * NOTE: use of CP scratch registers is a legacy inferface and
2008 * is not used by default on newer asics (r6xx+). On newer asics,
2009 * memory buffers are used for fences rather than scratch regs.
2011 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2013 adev->gfx.scratch.num_reg = 8;
2014 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2015 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2019 * gfx_v7_0_ring_test_ring - basic gfx ring test
2021 * @adev: amdgpu_device pointer
2022 * @ring: amdgpu_ring structure holding ring information
2024 * Allocate a scratch register and write to it using the gfx ring (CIK).
2025 * Provides a basic gfx ring test to verify that the ring is working.
2026 * Used by gfx_v7_0_cp_gfx_resume();
2027 * Returns 0 on success, error on failure.
2029 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2031 struct amdgpu_device *adev = ring->adev;
2037 r = amdgpu_gfx_scratch_get(adev, &scratch);
2039 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2042 WREG32(scratch, 0xCAFEDEAD);
2043 r = amdgpu_ring_alloc(ring, 3);
2045 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2046 amdgpu_gfx_scratch_free(adev, scratch);
2049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2050 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2051 amdgpu_ring_write(ring, 0xDEADBEEF);
2052 amdgpu_ring_commit(ring);
2054 for (i = 0; i < adev->usec_timeout; i++) {
2055 tmp = RREG32(scratch);
2056 if (tmp == 0xDEADBEEF)
2060 if (i < adev->usec_timeout) {
2061 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2063 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2064 ring->idx, scratch, tmp);
2067 amdgpu_gfx_scratch_free(adev, scratch);
2072 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2074 * @adev: amdgpu_device pointer
2075 * @ridx: amdgpu ring index
2077 * Emits an hdp flush on the cp.
2079 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2082 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2084 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2087 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2090 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2096 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2099 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2100 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2101 WAIT_REG_MEM_FUNCTION(3) | /* == */
2102 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2103 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2104 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2105 amdgpu_ring_write(ring, ref_and_mask);
2106 amdgpu_ring_write(ring, ref_and_mask);
2107 amdgpu_ring_write(ring, 0x20); /* poll interval */
2110 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2112 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2113 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2116 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2117 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2122 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2124 * @adev: amdgpu_device pointer
2125 * @fence: amdgpu fence object
2127 * Emits a fence sequnce number on the gfx ring and flushes
2130 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2131 u64 seq, unsigned flags)
2133 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2134 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2135 /* Workaround for cache flush problems. First send a dummy EOP
2136 * event down the pipe with seq one below.
2138 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2139 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2141 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2143 amdgpu_ring_write(ring, addr & 0xfffffffc);
2144 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2145 DATA_SEL(1) | INT_SEL(0));
2146 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2147 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2149 /* Then send the real EOP event down the pipe. */
2150 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2151 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2153 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2155 amdgpu_ring_write(ring, addr & 0xfffffffc);
2156 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2157 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2158 amdgpu_ring_write(ring, lower_32_bits(seq));
2159 amdgpu_ring_write(ring, upper_32_bits(seq));
2163 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2165 * @adev: amdgpu_device pointer
2166 * @fence: amdgpu fence object
2168 * Emits a fence sequnce number on the compute ring and flushes
2171 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2175 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2176 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2178 /* RELEASE_MEM - flush caches, send int */
2179 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2180 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2182 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2184 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2185 amdgpu_ring_write(ring, addr & 0xfffffffc);
2186 amdgpu_ring_write(ring, upper_32_bits(addr));
2187 amdgpu_ring_write(ring, lower_32_bits(seq));
2188 amdgpu_ring_write(ring, upper_32_bits(seq));
2195 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2197 * @ring: amdgpu_ring structure holding ring information
2198 * @ib: amdgpu indirect buffer object
2200 * Emits an DE (drawing engine) or CE (constant engine) IB
2201 * on the gfx ring. IBs are usually generated by userspace
2202 * acceleration drivers and submitted to the kernel for
2203 * sheduling on the ring. This function schedules the IB
2204 * on the gfx ring for execution by the GPU.
2206 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2207 struct amdgpu_ib *ib,
2208 unsigned vmid, bool ctx_switch)
2210 u32 header, control = 0;
2212 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2214 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2215 amdgpu_ring_write(ring, 0);
2218 if (ib->flags & AMDGPU_IB_FLAG_CE)
2219 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2221 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2223 control |= ib->length_dw | (vmid << 24);
2225 amdgpu_ring_write(ring, header);
2226 amdgpu_ring_write(ring,
2230 (ib->gpu_addr & 0xFFFFFFFC));
2231 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2232 amdgpu_ring_write(ring, control);
2235 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2236 struct amdgpu_ib *ib,
2237 unsigned vmid, bool ctx_switch)
2239 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2241 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2242 amdgpu_ring_write(ring,
2246 (ib->gpu_addr & 0xFFFFFFFC));
2247 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2248 amdgpu_ring_write(ring, control);
2251 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2255 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2256 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2257 gfx_v7_0_ring_emit_vgt_flush(ring);
2258 /* set load_global_config & load_global_uconfig */
2260 /* set load_cs_sh_regs */
2262 /* set load_per_context_state & load_gfx_sh_regs */
2266 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2267 amdgpu_ring_write(ring, dw2);
2268 amdgpu_ring_write(ring, 0);
2272 * gfx_v7_0_ring_test_ib - basic ring IB test
2274 * @ring: amdgpu_ring structure holding ring information
2276 * Allocate an IB and execute it on the gfx ring (CIK).
2277 * Provides a basic gfx ring test to verify that IBs are working.
2278 * Returns 0 on success, error on failure.
2280 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2282 struct amdgpu_device *adev = ring->adev;
2283 struct amdgpu_ib ib;
2284 struct dma_fence *f = NULL;
2289 r = amdgpu_gfx_scratch_get(adev, &scratch);
2291 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
2294 WREG32(scratch, 0xCAFEDEAD);
2295 memset(&ib, 0, sizeof(ib));
2296 r = amdgpu_ib_get(adev, NULL, 256, &ib);
2298 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
2301 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2302 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2303 ib.ptr[2] = 0xDEADBEEF;
2306 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2310 r = dma_fence_wait_timeout(f, false, timeout);
2312 DRM_ERROR("amdgpu: IB test timed out\n");
2316 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
2319 tmp = RREG32(scratch);
2320 if (tmp == 0xDEADBEEF) {
2321 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
2324 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2330 amdgpu_ib_free(adev, &ib, NULL);
2333 amdgpu_gfx_scratch_free(adev, scratch);
2339 * On CIK, gfx and compute now have independant command processors.
2342 * Gfx consists of a single ring and can process both gfx jobs and
2343 * compute jobs. The gfx CP consists of three microengines (ME):
2344 * PFP - Pre-Fetch Parser
2346 * CE - Constant Engine
2347 * The PFP and ME make up what is considered the Drawing Engine (DE).
2348 * The CE is an asynchronous engine used for updating buffer desciptors
2349 * used by the DE so that they can be loaded into cache in parallel
2350 * while the DE is processing state update packets.
2353 * The compute CP consists of two microengines (ME):
2354 * MEC1 - Compute MicroEngine 1
2355 * MEC2 - Compute MicroEngine 2
2356 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2357 * The queues are exposed to userspace and are programmed directly
2358 * by the compute runtime.
2361 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2363 * @adev: amdgpu_device pointer
2364 * @enable: enable or disable the MEs
2366 * Halts or unhalts the gfx MEs.
2368 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2373 WREG32(mmCP_ME_CNTL, 0);
2375 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2376 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2377 adev->gfx.gfx_ring[i].ready = false;
2383 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2385 * @adev: amdgpu_device pointer
2387 * Loads the gfx PFP, ME, and CE ucode.
2388 * Returns 0 for success, -EINVAL if the ucode is not available.
2390 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2392 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2393 const struct gfx_firmware_header_v1_0 *ce_hdr;
2394 const struct gfx_firmware_header_v1_0 *me_hdr;
2395 const __le32 *fw_data;
2396 unsigned i, fw_size;
2398 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2401 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2402 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2403 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2405 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2406 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2407 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2408 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2409 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2410 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2411 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2412 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2413 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2415 gfx_v7_0_cp_gfx_enable(adev, false);
2418 fw_data = (const __le32 *)
2419 (adev->gfx.pfp_fw->data +
2420 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2421 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2422 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2423 for (i = 0; i < fw_size; i++)
2424 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2425 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2428 fw_data = (const __le32 *)
2429 (adev->gfx.ce_fw->data +
2430 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2431 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2432 WREG32(mmCP_CE_UCODE_ADDR, 0);
2433 for (i = 0; i < fw_size; i++)
2434 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2435 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2438 fw_data = (const __le32 *)
2439 (adev->gfx.me_fw->data +
2440 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2441 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2442 WREG32(mmCP_ME_RAM_WADDR, 0);
2443 for (i = 0; i < fw_size; i++)
2444 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2445 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2451 * gfx_v7_0_cp_gfx_start - start the gfx ring
2453 * @adev: amdgpu_device pointer
2455 * Enables the ring and loads the clear state context and other
2456 * packets required to init the ring.
2457 * Returns 0 for success, error for failure.
2459 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2461 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2462 const struct cs_section_def *sect = NULL;
2463 const struct cs_extent_def *ext = NULL;
2467 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2468 WREG32(mmCP_ENDIAN_SWAP, 0);
2469 WREG32(mmCP_DEVICE_ID, 1);
2471 gfx_v7_0_cp_gfx_enable(adev, true);
2473 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2475 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2479 /* init the CE partitions. CE only used for gfx on CIK */
2480 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2481 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2482 amdgpu_ring_write(ring, 0x8000);
2483 amdgpu_ring_write(ring, 0x8000);
2485 /* clear state buffer */
2486 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2487 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2489 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2490 amdgpu_ring_write(ring, 0x80000000);
2491 amdgpu_ring_write(ring, 0x80000000);
2493 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2494 for (ext = sect->section; ext->extent != NULL; ++ext) {
2495 if (sect->id == SECT_CONTEXT) {
2496 amdgpu_ring_write(ring,
2497 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2498 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2499 for (i = 0; i < ext->reg_count; i++)
2500 amdgpu_ring_write(ring, ext->extent[i]);
2505 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2506 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2507 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
2508 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
2510 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2511 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2513 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2514 amdgpu_ring_write(ring, 0);
2516 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2517 amdgpu_ring_write(ring, 0x00000316);
2518 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2519 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2521 amdgpu_ring_commit(ring);
2527 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2529 * @adev: amdgpu_device pointer
2531 * Program the location and size of the gfx ring buffer
2532 * and test it to make sure it's working.
2533 * Returns 0 for success, error for failure.
2535 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2537 struct amdgpu_ring *ring;
2540 u64 rb_addr, rptr_addr;
2543 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2544 if (adev->asic_type != CHIP_HAWAII)
2545 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2547 /* Set the write pointer delay */
2548 WREG32(mmCP_RB_WPTR_DELAY, 0);
2550 /* set the RB to use vmid 0 */
2551 WREG32(mmCP_RB_VMID, 0);
2553 WREG32(mmSCRATCH_ADDR, 0);
2555 /* ring 0 - compute and gfx */
2556 /* Set ring buffer size */
2557 ring = &adev->gfx.gfx_ring[0];
2558 rb_bufsz = order_base_2(ring->ring_size / 8);
2559 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2561 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2563 WREG32(mmCP_RB0_CNTL, tmp);
2565 /* Initialize the ring buffer's read and write pointers */
2566 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2568 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2570 /* set the wb address wether it's enabled or not */
2571 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2572 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2573 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2575 /* scratch register shadowing is no longer supported */
2576 WREG32(mmSCRATCH_UMSK, 0);
2579 WREG32(mmCP_RB0_CNTL, tmp);
2581 rb_addr = ring->gpu_addr >> 8;
2582 WREG32(mmCP_RB0_BASE, rb_addr);
2583 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2585 /* start the ring */
2586 gfx_v7_0_cp_gfx_start(adev);
2588 r = amdgpu_ring_test_ring(ring);
2590 ring->ready = false;
2597 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2599 return ring->adev->wb.wb[ring->rptr_offs];
2602 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2604 struct amdgpu_device *adev = ring->adev;
2606 return RREG32(mmCP_RB0_WPTR);
2609 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2611 struct amdgpu_device *adev = ring->adev;
2613 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2614 (void)RREG32(mmCP_RB0_WPTR);
2617 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2619 /* XXX check if swapping is necessary on BE */
2620 return ring->adev->wb.wb[ring->wptr_offs];
2623 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2625 struct amdgpu_device *adev = ring->adev;
2627 /* XXX check if swapping is necessary on BE */
2628 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2629 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2633 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2635 * @adev: amdgpu_device pointer
2636 * @enable: enable or disable the MEs
2638 * Halts or unhalts the compute MEs.
2640 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2645 WREG32(mmCP_MEC_CNTL, 0);
2647 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2648 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2649 adev->gfx.compute_ring[i].ready = false;
2655 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2657 * @adev: amdgpu_device pointer
2659 * Loads the compute MEC1&2 ucode.
2660 * Returns 0 for success, -EINVAL if the ucode is not available.
2662 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2664 const struct gfx_firmware_header_v1_0 *mec_hdr;
2665 const __le32 *fw_data;
2666 unsigned i, fw_size;
2668 if (!adev->gfx.mec_fw)
2671 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2672 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2673 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2674 adev->gfx.mec_feature_version = le32_to_cpu(
2675 mec_hdr->ucode_feature_version);
2677 gfx_v7_0_cp_compute_enable(adev, false);
2680 fw_data = (const __le32 *)
2681 (adev->gfx.mec_fw->data +
2682 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2683 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2684 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2685 for (i = 0; i < fw_size; i++)
2686 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2687 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2689 if (adev->asic_type == CHIP_KAVERI) {
2690 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2692 if (!adev->gfx.mec2_fw)
2695 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2696 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2697 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2698 adev->gfx.mec2_feature_version = le32_to_cpu(
2699 mec2_hdr->ucode_feature_version);
2702 fw_data = (const __le32 *)
2703 (adev->gfx.mec2_fw->data +
2704 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2705 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2706 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2707 for (i = 0; i < fw_size; i++)
2708 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2709 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2716 * gfx_v7_0_cp_compute_fini - stop the compute queues
2718 * @adev: amdgpu_device pointer
2720 * Stop the compute queues and tear down the driver queue
2723 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2727 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2728 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2730 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2734 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2736 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2739 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2743 size_t mec_hpd_size;
2745 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2747 /* take ownership of the relevant compute queues */
2748 amdgpu_gfx_compute_queue_acquire(adev);
2750 /* allocate space for ALL pipes (even the ones we don't own) */
2751 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2752 * GFX7_MEC_HPD_SIZE * 2;
2754 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2755 AMDGPU_GEM_DOMAIN_GTT,
2756 &adev->gfx.mec.hpd_eop_obj,
2757 &adev->gfx.mec.hpd_eop_gpu_addr,
2760 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2761 gfx_v7_0_mec_fini(adev);
2765 /* clear memory. Not sure if this is required or not */
2766 memset(hpd, 0, mec_hpd_size);
2768 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2769 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2774 struct hqd_registers
2776 u32 cp_mqd_base_addr;
2777 u32 cp_mqd_base_addr_hi;
2780 u32 cp_hqd_persistent_state;
2781 u32 cp_hqd_pipe_priority;
2782 u32 cp_hqd_queue_priority;
2785 u32 cp_hqd_pq_base_hi;
2787 u32 cp_hqd_pq_rptr_report_addr;
2788 u32 cp_hqd_pq_rptr_report_addr_hi;
2789 u32 cp_hqd_pq_wptr_poll_addr;
2790 u32 cp_hqd_pq_wptr_poll_addr_hi;
2791 u32 cp_hqd_pq_doorbell_control;
2793 u32 cp_hqd_pq_control;
2794 u32 cp_hqd_ib_base_addr;
2795 u32 cp_hqd_ib_base_addr_hi;
2797 u32 cp_hqd_ib_control;
2798 u32 cp_hqd_iq_timer;
2800 u32 cp_hqd_dequeue_request;
2801 u32 cp_hqd_dma_offload;
2802 u32 cp_hqd_sema_cmd;
2803 u32 cp_hqd_msg_type;
2804 u32 cp_hqd_atomic0_preop_lo;
2805 u32 cp_hqd_atomic0_preop_hi;
2806 u32 cp_hqd_atomic1_preop_lo;
2807 u32 cp_hqd_atomic1_preop_hi;
2808 u32 cp_hqd_hq_scheduler0;
2809 u32 cp_hqd_hq_scheduler1;
2813 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2818 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2819 * GFX7_MEC_HPD_SIZE * 2;
2821 mutex_lock(&adev->srbm_mutex);
2822 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2824 cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2826 /* write the EOP addr */
2827 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2828 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2830 /* set the VMID assigned */
2831 WREG32(mmCP_HPD_EOP_VMID, 0);
2833 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2834 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2835 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2836 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2837 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2839 cik_srbm_select(adev, 0, 0, 0, 0);
2840 mutex_unlock(&adev->srbm_mutex);
2843 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2847 /* disable the queue if it's active */
2848 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2849 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2850 for (i = 0; i < adev->usec_timeout; i++) {
2851 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2856 if (i == adev->usec_timeout)
2859 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2860 WREG32(mmCP_HQD_PQ_RPTR, 0);
2861 WREG32(mmCP_HQD_PQ_WPTR, 0);
2867 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2868 struct cik_mqd *mqd,
2869 uint64_t mqd_gpu_addr,
2870 struct amdgpu_ring *ring)
2875 /* init the mqd struct */
2876 memset(mqd, 0, sizeof(struct cik_mqd));
2878 mqd->header = 0xC0310800;
2879 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2880 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2881 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2882 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2884 /* enable doorbell? */
2885 mqd->cp_hqd_pq_doorbell_control =
2886 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2887 if (ring->use_doorbell)
2888 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2890 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2892 /* set the pointer to the MQD */
2893 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2894 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2896 /* set MQD vmid to 0 */
2897 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2898 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2900 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2901 hqd_gpu_addr = ring->gpu_addr >> 8;
2902 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2903 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2905 /* set up the HQD, this is similar to CP_RB0_CNTL */
2906 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2907 mqd->cp_hqd_pq_control &=
2908 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2909 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2911 mqd->cp_hqd_pq_control |=
2912 order_base_2(ring->ring_size / 8);
2913 mqd->cp_hqd_pq_control |=
2914 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2916 mqd->cp_hqd_pq_control |=
2917 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2919 mqd->cp_hqd_pq_control &=
2920 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2921 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2922 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2923 mqd->cp_hqd_pq_control |=
2924 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2925 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2927 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2928 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2929 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2930 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2932 /* set the wb address wether it's enabled or not */
2933 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2934 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2935 mqd->cp_hqd_pq_rptr_report_addr_hi =
2936 upper_32_bits(wb_gpu_addr) & 0xffff;
2938 /* enable the doorbell if requested */
2939 if (ring->use_doorbell) {
2940 mqd->cp_hqd_pq_doorbell_control =
2941 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2942 mqd->cp_hqd_pq_doorbell_control &=
2943 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2944 mqd->cp_hqd_pq_doorbell_control |=
2945 (ring->doorbell_index <<
2946 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2947 mqd->cp_hqd_pq_doorbell_control |=
2948 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2949 mqd->cp_hqd_pq_doorbell_control &=
2950 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2951 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2954 mqd->cp_hqd_pq_doorbell_control = 0;
2957 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2959 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
2960 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2962 /* set the vmid for the queue */
2963 mqd->cp_hqd_vmid = 0;
2966 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
2967 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
2968 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
2969 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
2970 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
2971 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
2972 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
2973 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
2974 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
2975 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
2976 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
2977 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2978 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
2979 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
2980 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
2981 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
2983 /* activate the queue */
2984 mqd->cp_hqd_active = 1;
2987 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
2993 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
2994 mqd_data = &mqd->cp_mqd_base_addr_lo;
2996 /* disable wptr polling */
2997 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2998 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2999 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3001 /* program all HQD registers */
3002 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
3003 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3005 /* activate the HQD */
3006 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3007 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3012 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
3016 struct cik_mqd *mqd;
3017 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3019 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
3020 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
3021 &mqd_gpu_addr, (void **)&mqd);
3023 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3027 mutex_lock(&adev->srbm_mutex);
3028 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3030 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
3031 gfx_v7_0_mqd_deactivate(adev);
3032 gfx_v7_0_mqd_commit(adev, mqd);
3034 cik_srbm_select(adev, 0, 0, 0, 0);
3035 mutex_unlock(&adev->srbm_mutex);
3037 amdgpu_bo_kunmap(ring->mqd_obj);
3038 amdgpu_bo_unreserve(ring->mqd_obj);
3043 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3045 * @adev: amdgpu_device pointer
3047 * Program the compute queues and test them to make sure they
3049 * Returns 0 for success, error for failure.
3051 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3055 struct amdgpu_ring *ring;
3057 /* fix up chicken bits */
3058 tmp = RREG32(mmCP_CPF_DEBUG);
3060 WREG32(mmCP_CPF_DEBUG, tmp);
3062 /* init all pipes (even the ones we don't own) */
3063 for (i = 0; i < adev->gfx.mec.num_mec; i++)
3064 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3065 gfx_v7_0_compute_pipe_init(adev, i, j);
3067 /* init the queues */
3068 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3069 r = gfx_v7_0_compute_queue_init(adev, i);
3071 gfx_v7_0_cp_compute_fini(adev);
3076 gfx_v7_0_cp_compute_enable(adev, true);
3078 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3079 ring = &adev->gfx.compute_ring[i];
3081 r = amdgpu_ring_test_ring(ring);
3083 ring->ready = false;
3089 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3091 gfx_v7_0_cp_gfx_enable(adev, enable);
3092 gfx_v7_0_cp_compute_enable(adev, enable);
3095 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3099 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3102 r = gfx_v7_0_cp_compute_load_microcode(adev);
3109 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3112 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3115 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3116 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3118 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3119 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3120 WREG32(mmCP_INT_CNTL_RING0, tmp);
3123 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3127 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3129 r = gfx_v7_0_cp_load_microcode(adev);
3133 r = gfx_v7_0_cp_gfx_resume(adev);
3136 r = gfx_v7_0_cp_compute_resume(adev);
3140 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3146 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3148 * @ring: the ring to emmit the commands to
3150 * Sync the command pipeline with the PFP. E.g. wait for everything
3153 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3155 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3156 uint32_t seq = ring->fence_drv.sync_seq;
3157 uint64_t addr = ring->fence_drv.gpu_addr;
3159 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3160 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3161 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3162 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3163 amdgpu_ring_write(ring, addr & 0xfffffffc);
3164 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3165 amdgpu_ring_write(ring, seq);
3166 amdgpu_ring_write(ring, 0xffffffff);
3167 amdgpu_ring_write(ring, 4); /* poll interval */
3170 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3171 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3172 amdgpu_ring_write(ring, 0);
3173 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3174 amdgpu_ring_write(ring, 0);
3180 * VMID 0 is the physical GPU addresses as used by the kernel.
3181 * VMIDs 1-15 are used for userspace clients and are handled
3182 * by the amdgpu vm/hsa code.
3185 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3187 * @adev: amdgpu_device pointer
3189 * Update the page table base and flush the VM TLB
3190 * using the CP (CIK).
3192 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3193 unsigned vmid, uint64_t pd_addr)
3195 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3197 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3199 /* wait for the invalidate to complete */
3200 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3201 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3202 WAIT_REG_MEM_FUNCTION(0) | /* always */
3203 WAIT_REG_MEM_ENGINE(0))); /* me */
3204 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3205 amdgpu_ring_write(ring, 0);
3206 amdgpu_ring_write(ring, 0); /* ref */
3207 amdgpu_ring_write(ring, 0); /* mask */
3208 amdgpu_ring_write(ring, 0x20); /* poll interval */
3210 /* compute doesn't have PFP */
3212 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3213 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3214 amdgpu_ring_write(ring, 0x0);
3216 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3217 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3218 amdgpu_ring_write(ring, 0);
3219 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3220 amdgpu_ring_write(ring, 0);
3224 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
3225 uint32_t reg, uint32_t val)
3227 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3229 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3230 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3231 WRITE_DATA_DST_SEL(0)));
3232 amdgpu_ring_write(ring, reg);
3233 amdgpu_ring_write(ring, 0);
3234 amdgpu_ring_write(ring, val);
3239 * The RLC is a multi-purpose microengine that handles a
3240 * variety of functions.
3242 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3244 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
3245 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
3246 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
3249 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3252 volatile u32 *dst_ptr;
3254 const struct cs_section_def *cs_data;
3257 /* allocate rlc buffers */
3258 if (adev->flags & AMD_IS_APU) {
3259 if (adev->asic_type == CHIP_KAVERI) {
3260 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3261 adev->gfx.rlc.reg_list_size =
3262 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3264 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3265 adev->gfx.rlc.reg_list_size =
3266 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3269 adev->gfx.rlc.cs_data = ci_cs_data;
3270 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3271 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3273 src_ptr = adev->gfx.rlc.reg_list;
3274 dws = adev->gfx.rlc.reg_list_size;
3275 dws += (5 * 16) + 48 + 48 + 64;
3277 cs_data = adev->gfx.rlc.cs_data;
3280 /* save restore block */
3281 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3282 AMDGPU_GEM_DOMAIN_VRAM,
3283 &adev->gfx.rlc.save_restore_obj,
3284 &adev->gfx.rlc.save_restore_gpu_addr,
3285 (void **)&adev->gfx.rlc.sr_ptr);
3287 dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r);
3288 gfx_v7_0_rlc_fini(adev);
3292 /* write the sr buffer */
3293 dst_ptr = adev->gfx.rlc.sr_ptr;
3294 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3295 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3296 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3297 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3301 /* clear state block */
3302 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3304 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3305 AMDGPU_GEM_DOMAIN_VRAM,
3306 &adev->gfx.rlc.clear_state_obj,
3307 &adev->gfx.rlc.clear_state_gpu_addr,
3308 (void **)&adev->gfx.rlc.cs_ptr);
3310 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3311 gfx_v7_0_rlc_fini(adev);
3315 /* set up the cs buffer */
3316 dst_ptr = adev->gfx.rlc.cs_ptr;
3317 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3318 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3319 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3322 if (adev->gfx.rlc.cp_table_size) {
3324 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
3325 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
3326 &adev->gfx.rlc.cp_table_obj,
3327 &adev->gfx.rlc.cp_table_gpu_addr,
3328 (void **)&adev->gfx.rlc.cp_table_ptr);
3330 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3331 gfx_v7_0_rlc_fini(adev);
3335 gfx_v7_0_init_cp_pg_table(adev);
3337 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3338 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3345 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3349 tmp = RREG32(mmRLC_LB_CNTL);
3351 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3353 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3354 WREG32(mmRLC_LB_CNTL, tmp);
3357 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3362 mutex_lock(&adev->grbm_idx_mutex);
3363 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3364 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3365 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3366 for (k = 0; k < adev->usec_timeout; k++) {
3367 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3373 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3374 mutex_unlock(&adev->grbm_idx_mutex);
3376 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3377 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3378 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3379 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3380 for (k = 0; k < adev->usec_timeout; k++) {
3381 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3387 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3391 tmp = RREG32(mmRLC_CNTL);
3393 WREG32(mmRLC_CNTL, rlc);
3396 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3400 orig = data = RREG32(mmRLC_CNTL);
3402 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3405 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3406 WREG32(mmRLC_CNTL, data);
3408 for (i = 0; i < adev->usec_timeout; i++) {
3409 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3414 gfx_v7_0_wait_for_rlc_serdes(adev);
3420 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3424 tmp = 0x1 | (1 << 1);
3425 WREG32(mmRLC_GPR_REG2, tmp);
3427 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3428 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3429 for (i = 0; i < adev->usec_timeout; i++) {
3430 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3435 for (i = 0; i < adev->usec_timeout; i++) {
3436 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3442 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3446 tmp = 0x1 | (0 << 1);
3447 WREG32(mmRLC_GPR_REG2, tmp);
3451 * gfx_v7_0_rlc_stop - stop the RLC ME
3453 * @adev: amdgpu_device pointer
3455 * Halt the RLC ME (MicroEngine) (CIK).
3457 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3459 WREG32(mmRLC_CNTL, 0);
3461 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3463 gfx_v7_0_wait_for_rlc_serdes(adev);
3467 * gfx_v7_0_rlc_start - start the RLC ME
3469 * @adev: amdgpu_device pointer
3471 * Unhalt the RLC ME (MicroEngine) (CIK).
3473 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3475 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3477 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3482 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3484 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3486 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3487 WREG32(mmGRBM_SOFT_RESET, tmp);
3489 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3490 WREG32(mmGRBM_SOFT_RESET, tmp);
3495 * gfx_v7_0_rlc_resume - setup the RLC hw
3497 * @adev: amdgpu_device pointer
3499 * Initialize the RLC registers, load the ucode,
3500 * and start the RLC (CIK).
3501 * Returns 0 for success, -EINVAL if the ucode is not available.
3503 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3505 const struct rlc_firmware_header_v1_0 *hdr;
3506 const __le32 *fw_data;
3507 unsigned i, fw_size;
3510 if (!adev->gfx.rlc_fw)
3513 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3514 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3515 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3516 adev->gfx.rlc_feature_version = le32_to_cpu(
3517 hdr->ucode_feature_version);
3519 gfx_v7_0_rlc_stop(adev);
3522 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3523 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3525 gfx_v7_0_rlc_reset(adev);
3527 gfx_v7_0_init_pg(adev);
3529 WREG32(mmRLC_LB_CNTR_INIT, 0);
3530 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3532 mutex_lock(&adev->grbm_idx_mutex);
3533 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3534 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3535 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3536 WREG32(mmRLC_LB_CNTL, 0x80000004);
3537 mutex_unlock(&adev->grbm_idx_mutex);
3539 WREG32(mmRLC_MC_CNTL, 0);
3540 WREG32(mmRLC_UCODE_CNTL, 0);
3542 fw_data = (const __le32 *)
3543 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3544 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3545 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3546 for (i = 0; i < fw_size; i++)
3547 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3548 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3550 /* XXX - find out what chips support lbpw */
3551 gfx_v7_0_enable_lbpw(adev, false);
3553 if (adev->asic_type == CHIP_BONAIRE)
3554 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3556 gfx_v7_0_rlc_start(adev);
3561 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3563 u32 data, orig, tmp, tmp2;
3565 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3567 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3568 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3570 tmp = gfx_v7_0_halt_rlc(adev);
3572 mutex_lock(&adev->grbm_idx_mutex);
3573 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3574 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3575 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3576 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3577 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3578 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3579 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3580 mutex_unlock(&adev->grbm_idx_mutex);
3582 gfx_v7_0_update_rlc(adev, tmp);
3584 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3586 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3589 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3591 RREG32(mmCB_CGTT_SCLK_CTRL);
3592 RREG32(mmCB_CGTT_SCLK_CTRL);
3593 RREG32(mmCB_CGTT_SCLK_CTRL);
3594 RREG32(mmCB_CGTT_SCLK_CTRL);
3596 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3598 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3600 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3604 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3606 u32 data, orig, tmp = 0;
3608 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3609 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3610 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3611 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3612 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3614 WREG32(mmCP_MEM_SLP_CNTL, data);
3618 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3622 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3624 tmp = gfx_v7_0_halt_rlc(adev);
3626 mutex_lock(&adev->grbm_idx_mutex);
3627 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3628 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3629 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3630 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3631 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3632 WREG32(mmRLC_SERDES_WR_CTRL, data);
3633 mutex_unlock(&adev->grbm_idx_mutex);
3635 gfx_v7_0_update_rlc(adev, tmp);
3637 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3638 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3639 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3640 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3641 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3642 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3643 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3644 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3645 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3646 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3647 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3648 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3650 WREG32(mmCGTS_SM_CTRL_REG, data);
3653 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3656 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3658 data = RREG32(mmRLC_MEM_SLP_CNTL);
3659 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3660 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3661 WREG32(mmRLC_MEM_SLP_CNTL, data);
3664 data = RREG32(mmCP_MEM_SLP_CNTL);
3665 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3666 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3667 WREG32(mmCP_MEM_SLP_CNTL, data);
3670 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3671 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3673 WREG32(mmCGTS_SM_CTRL_REG, data);
3675 tmp = gfx_v7_0_halt_rlc(adev);
3677 mutex_lock(&adev->grbm_idx_mutex);
3678 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3679 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3680 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3681 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3682 WREG32(mmRLC_SERDES_WR_CTRL, data);
3683 mutex_unlock(&adev->grbm_idx_mutex);
3685 gfx_v7_0_update_rlc(adev, tmp);
3689 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3692 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3693 /* order matters! */
3695 gfx_v7_0_enable_mgcg(adev, true);
3696 gfx_v7_0_enable_cgcg(adev, true);
3698 gfx_v7_0_enable_cgcg(adev, false);
3699 gfx_v7_0_enable_mgcg(adev, false);
3701 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3704 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3709 orig = data = RREG32(mmRLC_PG_CNTL);
3710 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3711 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3713 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3715 WREG32(mmRLC_PG_CNTL, data);
3718 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3723 orig = data = RREG32(mmRLC_PG_CNTL);
3724 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3725 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3727 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3729 WREG32(mmRLC_PG_CNTL, data);
3732 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3736 orig = data = RREG32(mmRLC_PG_CNTL);
3737 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3742 WREG32(mmRLC_PG_CNTL, data);
3745 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3749 orig = data = RREG32(mmRLC_PG_CNTL);
3750 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3755 WREG32(mmRLC_PG_CNTL, data);
3758 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3760 const __le32 *fw_data;
3761 volatile u32 *dst_ptr;
3762 int me, i, max_me = 4;
3764 u32 table_offset, table_size;
3766 if (adev->asic_type == CHIP_KAVERI)
3769 if (adev->gfx.rlc.cp_table_ptr == NULL)
3772 /* write the cp table buffer */
3773 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3774 for (me = 0; me < max_me; me++) {
3776 const struct gfx_firmware_header_v1_0 *hdr =
3777 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3778 fw_data = (const __le32 *)
3779 (adev->gfx.ce_fw->data +
3780 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3781 table_offset = le32_to_cpu(hdr->jt_offset);
3782 table_size = le32_to_cpu(hdr->jt_size);
3783 } else if (me == 1) {
3784 const struct gfx_firmware_header_v1_0 *hdr =
3785 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3786 fw_data = (const __le32 *)
3787 (adev->gfx.pfp_fw->data +
3788 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3789 table_offset = le32_to_cpu(hdr->jt_offset);
3790 table_size = le32_to_cpu(hdr->jt_size);
3791 } else if (me == 2) {
3792 const struct gfx_firmware_header_v1_0 *hdr =
3793 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3794 fw_data = (const __le32 *)
3795 (adev->gfx.me_fw->data +
3796 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3797 table_offset = le32_to_cpu(hdr->jt_offset);
3798 table_size = le32_to_cpu(hdr->jt_size);
3799 } else if (me == 3) {
3800 const struct gfx_firmware_header_v1_0 *hdr =
3801 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3802 fw_data = (const __le32 *)
3803 (adev->gfx.mec_fw->data +
3804 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3805 table_offset = le32_to_cpu(hdr->jt_offset);
3806 table_size = le32_to_cpu(hdr->jt_size);
3808 const struct gfx_firmware_header_v1_0 *hdr =
3809 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3810 fw_data = (const __le32 *)
3811 (adev->gfx.mec2_fw->data +
3812 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3813 table_offset = le32_to_cpu(hdr->jt_offset);
3814 table_size = le32_to_cpu(hdr->jt_size);
3817 for (i = 0; i < table_size; i ++) {
3818 dst_ptr[bo_offset + i] =
3819 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3822 bo_offset += table_size;
3826 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3831 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3832 orig = data = RREG32(mmRLC_PG_CNTL);
3833 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3835 WREG32(mmRLC_PG_CNTL, data);
3837 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3838 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3840 WREG32(mmRLC_AUTO_PG_CTRL, data);
3842 orig = data = RREG32(mmRLC_PG_CNTL);
3843 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3845 WREG32(mmRLC_PG_CNTL, data);
3847 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3848 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3850 WREG32(mmRLC_AUTO_PG_CTRL, data);
3852 data = RREG32(mmDB_RENDER_CONTROL);
3856 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3864 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3865 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3867 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3870 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3874 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3875 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3877 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3878 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3880 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3882 return (~data) & mask;
3885 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3889 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3891 tmp = RREG32(mmRLC_MAX_PG_CU);
3892 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3893 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3894 WREG32(mmRLC_MAX_PG_CU, tmp);
3897 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3902 orig = data = RREG32(mmRLC_PG_CNTL);
3903 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3904 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3906 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3908 WREG32(mmRLC_PG_CNTL, data);
3911 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3916 orig = data = RREG32(mmRLC_PG_CNTL);
3917 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3918 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3920 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3922 WREG32(mmRLC_PG_CNTL, data);
3925 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3926 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3928 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3933 if (adev->gfx.rlc.cs_data) {
3934 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3935 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3936 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3937 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3939 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3940 for (i = 0; i < 3; i++)
3941 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3943 if (adev->gfx.rlc.reg_list) {
3944 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3945 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3946 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3949 orig = data = RREG32(mmRLC_PG_CNTL);
3950 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3952 WREG32(mmRLC_PG_CNTL, data);
3954 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3955 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3957 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3958 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3959 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3960 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3963 WREG32(mmRLC_PG_DELAY, data);
3965 data = RREG32(mmRLC_PG_DELAY_2);
3968 WREG32(mmRLC_PG_DELAY_2, data);
3970 data = RREG32(mmRLC_AUTO_PG_CTRL);
3971 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3972 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3973 WREG32(mmRLC_AUTO_PG_CTRL, data);
3977 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3979 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3980 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3981 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3984 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3987 const struct cs_section_def *sect = NULL;
3988 const struct cs_extent_def *ext = NULL;
3990 if (adev->gfx.rlc.cs_data == NULL)
3993 /* begin clear state */
3995 /* context control state */
3998 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3999 for (ext = sect->section; ext->extent != NULL; ++ext) {
4000 if (sect->id == SECT_CONTEXT)
4001 count += 2 + ext->reg_count;
4006 /* pa_sc_raster_config/pa_sc_raster_config1 */
4008 /* end clear state */
4016 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4017 volatile u32 *buffer)
4020 const struct cs_section_def *sect = NULL;
4021 const struct cs_extent_def *ext = NULL;
4023 if (adev->gfx.rlc.cs_data == NULL)
4028 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4029 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4031 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4032 buffer[count++] = cpu_to_le32(0x80000000);
4033 buffer[count++] = cpu_to_le32(0x80000000);
4035 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4036 for (ext = sect->section; ext->extent != NULL; ++ext) {
4037 if (sect->id == SECT_CONTEXT) {
4039 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4040 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4041 for (i = 0; i < ext->reg_count; i++)
4042 buffer[count++] = cpu_to_le32(ext->extent[i]);
4049 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4050 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4051 switch (adev->asic_type) {
4053 buffer[count++] = cpu_to_le32(0x16000012);
4054 buffer[count++] = cpu_to_le32(0x00000000);
4057 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4058 buffer[count++] = cpu_to_le32(0x00000000);
4062 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4063 buffer[count++] = cpu_to_le32(0x00000000);
4066 buffer[count++] = cpu_to_le32(0x3a00161a);
4067 buffer[count++] = cpu_to_le32(0x0000002e);
4070 buffer[count++] = cpu_to_le32(0x00000000);
4071 buffer[count++] = cpu_to_le32(0x00000000);
4075 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4076 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4078 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4079 buffer[count++] = cpu_to_le32(0);
4082 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4084 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4085 AMD_PG_SUPPORT_GFX_SMG |
4086 AMD_PG_SUPPORT_GFX_DMG |
4088 AMD_PG_SUPPORT_GDS |
4089 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4090 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4091 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4092 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4093 gfx_v7_0_init_gfx_cgpg(adev);
4094 gfx_v7_0_enable_cp_pg(adev, true);
4095 gfx_v7_0_enable_gds_pg(adev, true);
4097 gfx_v7_0_init_ao_cu_mask(adev);
4098 gfx_v7_0_update_gfx_pg(adev, true);
4102 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4104 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4105 AMD_PG_SUPPORT_GFX_SMG |
4106 AMD_PG_SUPPORT_GFX_DMG |
4108 AMD_PG_SUPPORT_GDS |
4109 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4110 gfx_v7_0_update_gfx_pg(adev, false);
4111 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4112 gfx_v7_0_enable_cp_pg(adev, false);
4113 gfx_v7_0_enable_gds_pg(adev, false);
4119 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4121 * @adev: amdgpu_device pointer
4123 * Fetches a GPU clock counter snapshot (SI).
4124 * Returns the 64 bit clock counter snapshot.
4126 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4130 mutex_lock(&adev->gfx.gpu_clock_mutex);
4131 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4132 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4133 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4134 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4138 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4140 uint32_t gds_base, uint32_t gds_size,
4141 uint32_t gws_base, uint32_t gws_size,
4142 uint32_t oa_base, uint32_t oa_size)
4144 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4145 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4147 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4148 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4150 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4151 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4154 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4155 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4156 WRITE_DATA_DST_SEL(0)));
4157 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4158 amdgpu_ring_write(ring, 0);
4159 amdgpu_ring_write(ring, gds_base);
4162 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4163 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4164 WRITE_DATA_DST_SEL(0)));
4165 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4166 amdgpu_ring_write(ring, 0);
4167 amdgpu_ring_write(ring, gds_size);
4170 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4171 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4172 WRITE_DATA_DST_SEL(0)));
4173 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4174 amdgpu_ring_write(ring, 0);
4175 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4178 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4179 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4180 WRITE_DATA_DST_SEL(0)));
4181 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4182 amdgpu_ring_write(ring, 0);
4183 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4186 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4188 WREG32(mmSQ_IND_INDEX,
4189 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4190 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4191 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4192 (SQ_IND_INDEX__FORCE_READ_MASK));
4193 return RREG32(mmSQ_IND_DATA);
4196 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4197 uint32_t wave, uint32_t thread,
4198 uint32_t regno, uint32_t num, uint32_t *out)
4200 WREG32(mmSQ_IND_INDEX,
4201 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4202 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4203 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4204 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4205 (SQ_IND_INDEX__FORCE_READ_MASK) |
4206 (SQ_IND_INDEX__AUTO_INCR_MASK));
4208 *(out++) = RREG32(mmSQ_IND_DATA);
4211 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4213 /* type 0 wave data */
4214 dst[(*no_fields)++] = 0;
4215 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4216 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4217 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4218 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4219 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4220 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4221 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4227 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4228 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4229 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4230 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4231 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4232 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4235 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4236 uint32_t wave, uint32_t start,
4237 uint32_t size, uint32_t *dst)
4240 adev, simd, wave, 0,
4241 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4244 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
4245 u32 me, u32 pipe, u32 q)
4247 cik_srbm_select(adev, me, pipe, q, 0);
4250 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4251 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4252 .select_se_sh = &gfx_v7_0_select_se_sh,
4253 .read_wave_data = &gfx_v7_0_read_wave_data,
4254 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4255 .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
4258 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4259 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4260 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4263 static int gfx_v7_0_early_init(void *handle)
4265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4267 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4268 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
4269 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4270 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4271 gfx_v7_0_set_ring_funcs(adev);
4272 gfx_v7_0_set_irq_funcs(adev);
4273 gfx_v7_0_set_gds_init(adev);
4278 static int gfx_v7_0_late_init(void *handle)
4280 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4283 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4287 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4294 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4297 u32 mc_shared_chmap, mc_arb_ramcfg;
4298 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4301 switch (adev->asic_type) {
4303 adev->gfx.config.max_shader_engines = 2;
4304 adev->gfx.config.max_tile_pipes = 4;
4305 adev->gfx.config.max_cu_per_sh = 7;
4306 adev->gfx.config.max_sh_per_se = 1;
4307 adev->gfx.config.max_backends_per_se = 2;
4308 adev->gfx.config.max_texture_channel_caches = 4;
4309 adev->gfx.config.max_gprs = 256;
4310 adev->gfx.config.max_gs_threads = 32;
4311 adev->gfx.config.max_hw_contexts = 8;
4313 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4314 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4315 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4316 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4317 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4320 adev->gfx.config.max_shader_engines = 4;
4321 adev->gfx.config.max_tile_pipes = 16;
4322 adev->gfx.config.max_cu_per_sh = 11;
4323 adev->gfx.config.max_sh_per_se = 1;
4324 adev->gfx.config.max_backends_per_se = 4;
4325 adev->gfx.config.max_texture_channel_caches = 16;
4326 adev->gfx.config.max_gprs = 256;
4327 adev->gfx.config.max_gs_threads = 32;
4328 adev->gfx.config.max_hw_contexts = 8;
4330 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4331 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4332 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4333 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4334 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4337 adev->gfx.config.max_shader_engines = 1;
4338 adev->gfx.config.max_tile_pipes = 4;
4339 adev->gfx.config.max_cu_per_sh = 8;
4340 adev->gfx.config.max_backends_per_se = 2;
4341 adev->gfx.config.max_sh_per_se = 1;
4342 adev->gfx.config.max_texture_channel_caches = 4;
4343 adev->gfx.config.max_gprs = 256;
4344 adev->gfx.config.max_gs_threads = 16;
4345 adev->gfx.config.max_hw_contexts = 8;
4347 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4348 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4349 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4350 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4351 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4356 adev->gfx.config.max_shader_engines = 1;
4357 adev->gfx.config.max_tile_pipes = 2;
4358 adev->gfx.config.max_cu_per_sh = 2;
4359 adev->gfx.config.max_sh_per_se = 1;
4360 adev->gfx.config.max_backends_per_se = 1;
4361 adev->gfx.config.max_texture_channel_caches = 2;
4362 adev->gfx.config.max_gprs = 256;
4363 adev->gfx.config.max_gs_threads = 16;
4364 adev->gfx.config.max_hw_contexts = 8;
4366 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4367 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4368 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4369 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4370 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4374 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4375 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4376 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4378 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4379 adev->gfx.config.mem_max_burst_length_bytes = 256;
4380 if (adev->flags & AMD_IS_APU) {
4381 /* Get memory bank mapping mode. */
4382 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4383 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4384 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4386 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4387 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4388 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4390 /* Validate settings in case only one DIMM installed. */
4391 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4392 dimm00_addr_map = 0;
4393 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4394 dimm01_addr_map = 0;
4395 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4396 dimm10_addr_map = 0;
4397 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4398 dimm11_addr_map = 0;
4400 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4401 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4402 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4403 adev->gfx.config.mem_row_size_in_kb = 2;
4405 adev->gfx.config.mem_row_size_in_kb = 1;
4407 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4408 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4409 if (adev->gfx.config.mem_row_size_in_kb > 4)
4410 adev->gfx.config.mem_row_size_in_kb = 4;
4412 /* XXX use MC settings? */
4413 adev->gfx.config.shader_engine_tile_size = 32;
4414 adev->gfx.config.num_gpus = 1;
4415 adev->gfx.config.multi_gpu_tile_size = 64;
4417 /* fix up row size */
4418 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4419 switch (adev->gfx.config.mem_row_size_in_kb) {
4422 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4425 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4428 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4431 adev->gfx.config.gb_addr_config = gb_addr_config;
4434 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4435 int mec, int pipe, int queue)
4439 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4444 ring->queue = queue;
4446 ring->ring_obj = NULL;
4447 ring->use_doorbell = true;
4448 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
4449 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4451 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4452 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4455 /* type-2 packets are deprecated on MEC, use type-3 instead */
4456 r = amdgpu_ring_init(adev, ring, 1024,
4457 &adev->gfx.eop_irq, irq_type);
4465 static int gfx_v7_0_sw_init(void *handle)
4467 struct amdgpu_ring *ring;
4468 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4469 int i, j, k, r, ring_id;
4471 switch (adev->asic_type) {
4473 adev->gfx.mec.num_mec = 2;
4480 adev->gfx.mec.num_mec = 1;
4483 adev->gfx.mec.num_pipe_per_mec = 4;
4484 adev->gfx.mec.num_queue_per_pipe = 8;
4487 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4491 /* Privileged reg */
4492 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
4493 &adev->gfx.priv_reg_irq);
4497 /* Privileged inst */
4498 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
4499 &adev->gfx.priv_inst_irq);
4503 gfx_v7_0_scratch_init(adev);
4505 r = gfx_v7_0_init_microcode(adev);
4507 DRM_ERROR("Failed to load gfx firmware!\n");
4511 r = gfx_v7_0_rlc_init(adev);
4513 DRM_ERROR("Failed to init rlc BOs!\n");
4517 /* allocate mec buffers */
4518 r = gfx_v7_0_mec_init(adev);
4520 DRM_ERROR("Failed to init MEC BOs!\n");
4524 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4525 ring = &adev->gfx.gfx_ring[i];
4526 ring->ring_obj = NULL;
4527 sprintf(ring->name, "gfx");
4528 r = amdgpu_ring_init(adev, ring, 1024,
4529 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
4534 /* set up the compute queues - allocate horizontally across pipes */
4536 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4537 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4538 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4539 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
4542 r = gfx_v7_0_compute_ring_init(adev,
4553 /* reserve GDS, GWS and OA resource for gfx */
4554 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4555 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4556 &adev->gds.gds_gfx_bo, NULL, NULL);
4560 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4561 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4562 &adev->gds.gws_gfx_bo, NULL, NULL);
4566 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4567 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4568 &adev->gds.oa_gfx_bo, NULL, NULL);
4572 adev->gfx.ce_ram_size = 0x8000;
4574 gfx_v7_0_gpu_early_init(adev);
4579 static int gfx_v7_0_sw_fini(void *handle)
4582 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4584 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4585 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4586 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4588 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4589 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4590 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4591 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4593 gfx_v7_0_cp_compute_fini(adev);
4594 gfx_v7_0_rlc_fini(adev);
4595 gfx_v7_0_mec_fini(adev);
4596 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4597 &adev->gfx.rlc.clear_state_gpu_addr,
4598 (void **)&adev->gfx.rlc.cs_ptr);
4599 if (adev->gfx.rlc.cp_table_size) {
4600 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4601 &adev->gfx.rlc.cp_table_gpu_addr,
4602 (void **)&adev->gfx.rlc.cp_table_ptr);
4604 gfx_v7_0_free_microcode(adev);
4609 static int gfx_v7_0_hw_init(void *handle)
4612 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4614 gfx_v7_0_gpu_init(adev);
4617 r = gfx_v7_0_rlc_resume(adev);
4621 r = gfx_v7_0_cp_resume(adev);
4628 static int gfx_v7_0_hw_fini(void *handle)
4630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4632 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4633 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4634 gfx_v7_0_cp_enable(adev, false);
4635 gfx_v7_0_rlc_stop(adev);
4636 gfx_v7_0_fini_pg(adev);
4641 static int gfx_v7_0_suspend(void *handle)
4643 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4645 return gfx_v7_0_hw_fini(adev);
4648 static int gfx_v7_0_resume(void *handle)
4650 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4652 return gfx_v7_0_hw_init(adev);
4655 static bool gfx_v7_0_is_idle(void *handle)
4657 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4659 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4665 static int gfx_v7_0_wait_for_idle(void *handle)
4669 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4671 for (i = 0; i < adev->usec_timeout; i++) {
4672 /* read MC_STATUS */
4673 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4682 static int gfx_v7_0_soft_reset(void *handle)
4684 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4686 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4689 tmp = RREG32(mmGRBM_STATUS);
4690 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4691 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4692 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4693 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4694 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4695 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4696 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4697 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4699 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4700 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4701 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4705 tmp = RREG32(mmGRBM_STATUS2);
4706 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4707 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4710 tmp = RREG32(mmSRBM_STATUS);
4711 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4712 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4714 if (grbm_soft_reset || srbm_soft_reset) {
4716 gfx_v7_0_fini_pg(adev);
4717 gfx_v7_0_update_cg(adev, false);
4720 gfx_v7_0_rlc_stop(adev);
4722 /* Disable GFX parsing/prefetching */
4723 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4725 /* Disable MEC parsing/prefetching */
4726 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4728 if (grbm_soft_reset) {
4729 tmp = RREG32(mmGRBM_SOFT_RESET);
4730 tmp |= grbm_soft_reset;
4731 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4732 WREG32(mmGRBM_SOFT_RESET, tmp);
4733 tmp = RREG32(mmGRBM_SOFT_RESET);
4737 tmp &= ~grbm_soft_reset;
4738 WREG32(mmGRBM_SOFT_RESET, tmp);
4739 tmp = RREG32(mmGRBM_SOFT_RESET);
4742 if (srbm_soft_reset) {
4743 tmp = RREG32(mmSRBM_SOFT_RESET);
4744 tmp |= srbm_soft_reset;
4745 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4746 WREG32(mmSRBM_SOFT_RESET, tmp);
4747 tmp = RREG32(mmSRBM_SOFT_RESET);
4751 tmp &= ~srbm_soft_reset;
4752 WREG32(mmSRBM_SOFT_RESET, tmp);
4753 tmp = RREG32(mmSRBM_SOFT_RESET);
4755 /* Wait a little for things to settle down */
4761 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4762 enum amdgpu_interrupt_state state)
4767 case AMDGPU_IRQ_STATE_DISABLE:
4768 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4769 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4770 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4772 case AMDGPU_IRQ_STATE_ENABLE:
4773 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4774 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4775 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4782 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4784 enum amdgpu_interrupt_state state)
4786 u32 mec_int_cntl, mec_int_cntl_reg;
4789 * amdgpu controls only the first MEC. That's why this function only
4790 * handles the setting of interrupts for this specific MEC. All other
4791 * pipes' interrupts are set by amdkfd.
4797 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4800 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4803 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4806 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4809 DRM_DEBUG("invalid pipe %d\n", pipe);
4813 DRM_DEBUG("invalid me %d\n", me);
4818 case AMDGPU_IRQ_STATE_DISABLE:
4819 mec_int_cntl = RREG32(mec_int_cntl_reg);
4820 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4821 WREG32(mec_int_cntl_reg, mec_int_cntl);
4823 case AMDGPU_IRQ_STATE_ENABLE:
4824 mec_int_cntl = RREG32(mec_int_cntl_reg);
4825 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4826 WREG32(mec_int_cntl_reg, mec_int_cntl);
4833 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4834 struct amdgpu_irq_src *src,
4836 enum amdgpu_interrupt_state state)
4841 case AMDGPU_IRQ_STATE_DISABLE:
4842 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4843 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4844 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4846 case AMDGPU_IRQ_STATE_ENABLE:
4847 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4848 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4849 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4858 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4859 struct amdgpu_irq_src *src,
4861 enum amdgpu_interrupt_state state)
4866 case AMDGPU_IRQ_STATE_DISABLE:
4867 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4868 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4869 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4871 case AMDGPU_IRQ_STATE_ENABLE:
4872 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4873 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4874 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4883 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4884 struct amdgpu_irq_src *src,
4886 enum amdgpu_interrupt_state state)
4889 case AMDGPU_CP_IRQ_GFX_EOP:
4890 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4892 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4893 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4895 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4896 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4898 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4899 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4901 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4902 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4904 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4905 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4907 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4908 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4910 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4911 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4913 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4914 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4922 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4923 struct amdgpu_irq_src *source,
4924 struct amdgpu_iv_entry *entry)
4927 struct amdgpu_ring *ring;
4930 DRM_DEBUG("IH: CP EOP\n");
4931 me_id = (entry->ring_id & 0x0c) >> 2;
4932 pipe_id = (entry->ring_id & 0x03) >> 0;
4935 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4939 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4940 ring = &adev->gfx.compute_ring[i];
4941 if ((ring->me == me_id) && (ring->pipe == pipe_id))
4942 amdgpu_fence_process(ring);
4949 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4950 struct amdgpu_irq_src *source,
4951 struct amdgpu_iv_entry *entry)
4953 DRM_ERROR("Illegal register access in command stream\n");
4954 schedule_work(&adev->reset_work);
4958 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4959 struct amdgpu_irq_src *source,
4960 struct amdgpu_iv_entry *entry)
4962 DRM_ERROR("Illegal instruction in command stream\n");
4963 // XXX soft reset the gfx block only
4964 schedule_work(&adev->reset_work);
4968 static int gfx_v7_0_set_clockgating_state(void *handle,
4969 enum amd_clockgating_state state)
4972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4974 if (state == AMD_CG_STATE_GATE)
4977 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4978 /* order matters! */
4980 gfx_v7_0_enable_mgcg(adev, true);
4981 gfx_v7_0_enable_cgcg(adev, true);
4983 gfx_v7_0_enable_cgcg(adev, false);
4984 gfx_v7_0_enable_mgcg(adev, false);
4986 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4991 static int gfx_v7_0_set_powergating_state(void *handle,
4992 enum amd_powergating_state state)
4995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4997 if (state == AMD_PG_STATE_GATE)
5000 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5001 AMD_PG_SUPPORT_GFX_SMG |
5002 AMD_PG_SUPPORT_GFX_DMG |
5004 AMD_PG_SUPPORT_GDS |
5005 AMD_PG_SUPPORT_RLC_SMU_HS)) {
5006 gfx_v7_0_update_gfx_pg(adev, gate);
5007 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5008 gfx_v7_0_enable_cp_pg(adev, gate);
5009 gfx_v7_0_enable_gds_pg(adev, gate);
5016 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5018 .early_init = gfx_v7_0_early_init,
5019 .late_init = gfx_v7_0_late_init,
5020 .sw_init = gfx_v7_0_sw_init,
5021 .sw_fini = gfx_v7_0_sw_fini,
5022 .hw_init = gfx_v7_0_hw_init,
5023 .hw_fini = gfx_v7_0_hw_fini,
5024 .suspend = gfx_v7_0_suspend,
5025 .resume = gfx_v7_0_resume,
5026 .is_idle = gfx_v7_0_is_idle,
5027 .wait_for_idle = gfx_v7_0_wait_for_idle,
5028 .soft_reset = gfx_v7_0_soft_reset,
5029 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5030 .set_powergating_state = gfx_v7_0_set_powergating_state,
5033 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5034 .type = AMDGPU_RING_TYPE_GFX,
5036 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5037 .support_64bit_ptrs = false,
5038 .get_rptr = gfx_v7_0_ring_get_rptr,
5039 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5040 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5042 20 + /* gfx_v7_0_ring_emit_gds_switch */
5043 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5044 5 + /* hdp invalidate */
5045 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5046 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5047 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5048 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5049 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5050 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5051 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5052 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5053 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5054 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5055 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5056 .test_ring = gfx_v7_0_ring_test_ring,
5057 .test_ib = gfx_v7_0_ring_test_ib,
5058 .insert_nop = amdgpu_ring_insert_nop,
5059 .pad_ib = amdgpu_ring_generic_pad_ib,
5060 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5061 .emit_wreg = gfx_v7_0_ring_emit_wreg,
5064 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5065 .type = AMDGPU_RING_TYPE_COMPUTE,
5067 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5068 .support_64bit_ptrs = false,
5069 .get_rptr = gfx_v7_0_ring_get_rptr,
5070 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5071 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5073 20 + /* gfx_v7_0_ring_emit_gds_switch */
5074 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5075 5 + /* hdp invalidate */
5076 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5077 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
5078 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5079 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5080 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5081 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5082 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5083 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5084 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5085 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5086 .test_ring = gfx_v7_0_ring_test_ring,
5087 .test_ib = gfx_v7_0_ring_test_ib,
5088 .insert_nop = amdgpu_ring_insert_nop,
5089 .pad_ib = amdgpu_ring_generic_pad_ib,
5090 .emit_wreg = gfx_v7_0_ring_emit_wreg,
5093 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5097 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5098 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5099 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5100 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5103 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5104 .set = gfx_v7_0_set_eop_interrupt_state,
5105 .process = gfx_v7_0_eop_irq,
5108 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5109 .set = gfx_v7_0_set_priv_reg_fault_state,
5110 .process = gfx_v7_0_priv_reg_irq,
5113 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5114 .set = gfx_v7_0_set_priv_inst_fault_state,
5115 .process = gfx_v7_0_priv_inst_irq,
5118 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5120 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5121 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5123 adev->gfx.priv_reg_irq.num_types = 1;
5124 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5126 adev->gfx.priv_inst_irq.num_types = 1;
5127 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5130 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5132 /* init asci gds info */
5133 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5134 adev->gds.gws.total_size = 64;
5135 adev->gds.oa.total_size = 16;
5137 if (adev->gds.mem.total_size == 64 * 1024) {
5138 adev->gds.mem.gfx_partition_size = 4096;
5139 adev->gds.mem.cs_partition_size = 4096;
5141 adev->gds.gws.gfx_partition_size = 4;
5142 adev->gds.gws.cs_partition_size = 4;
5144 adev->gds.oa.gfx_partition_size = 4;
5145 adev->gds.oa.cs_partition_size = 1;
5147 adev->gds.mem.gfx_partition_size = 1024;
5148 adev->gds.mem.cs_partition_size = 1024;
5150 adev->gds.gws.gfx_partition_size = 16;
5151 adev->gds.gws.cs_partition_size = 16;
5153 adev->gds.oa.gfx_partition_size = 4;
5154 adev->gds.oa.cs_partition_size = 4;
5159 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5161 int i, j, k, counter, active_cu_number = 0;
5162 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5163 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5164 unsigned disable_masks[4 * 2];
5167 if (adev->flags & AMD_IS_APU)
5170 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5172 memset(cu_info, 0, sizeof(*cu_info));
5174 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5176 mutex_lock(&adev->grbm_idx_mutex);
5177 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5178 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5182 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5184 gfx_v7_0_set_user_cu_inactive_bitmap(
5185 adev, disable_masks[i * 2 + j]);
5186 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5187 cu_info->bitmap[i][j] = bitmap;
5189 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5190 if (bitmap & mask) {
5191 if (counter < ao_cu_num)
5197 active_cu_number += counter;
5199 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5200 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5203 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5204 mutex_unlock(&adev->grbm_idx_mutex);
5206 cu_info->number = active_cu_number;
5207 cu_info->ao_cu_mask = ao_cu_mask;
5208 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5209 cu_info->max_waves_per_simd = 10;
5210 cu_info->max_scratch_slots_per_cu = 32;
5211 cu_info->wave_front_size = 64;
5212 cu_info->lds_size = 64;
5215 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5217 .type = AMD_IP_BLOCK_TYPE_GFX,
5221 .funcs = &gfx_v7_0_ip_funcs,
5224 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5226 .type = AMD_IP_BLOCK_TYPE_GFX,
5230 .funcs = &gfx_v7_0_ip_funcs,
5233 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5235 .type = AMD_IP_BLOCK_TYPE_GFX,
5239 .funcs = &gfx_v7_0_ip_funcs,
5242 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5244 .type = AMD_IP_BLOCK_TYPE_GFX,
5248 .funcs = &gfx_v7_0_ip_funcs,