2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
31 #include "amdgpu_ucode.h"
32 #include "clearstate_ci.h"
34 #include "dce/dce_8_0_d.h"
35 #include "dce/dce_8_0_sh_mask.h"
37 #include "bif/bif_4_1_d.h"
38 #include "bif/bif_4_1_sh_mask.h"
40 #include "gca/gfx_7_0_d.h"
41 #include "gca/gfx_7_2_enum.h"
42 #include "gca/gfx_7_2_sh_mask.h"
44 #include "gmc/gmc_7_0_d.h"
45 #include "gmc/gmc_7_0_sh_mask.h"
47 #include "oss/oss_2_0_d.h"
48 #include "oss/oss_2_0_sh_mask.h"
50 #define GFX7_NUM_GFX_RINGS 1
51 #define GFX7_NUM_COMPUTE_RINGS 8
53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
59 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
61 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
62 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
63 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
64 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
65 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
66 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
67 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
68 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
69 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
70 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
71 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
72 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
73 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
74 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
75 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
76 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
79 static const u32 spectre_rlc_save_restore_register_list[] =
81 (0x0e00 << 16) | (0xc12c >> 2),
83 (0x0e00 << 16) | (0xc140 >> 2),
85 (0x0e00 << 16) | (0xc150 >> 2),
87 (0x0e00 << 16) | (0xc15c >> 2),
89 (0x0e00 << 16) | (0xc168 >> 2),
91 (0x0e00 << 16) | (0xc170 >> 2),
93 (0x0e00 << 16) | (0xc178 >> 2),
95 (0x0e00 << 16) | (0xc204 >> 2),
97 (0x0e00 << 16) | (0xc2b4 >> 2),
99 (0x0e00 << 16) | (0xc2b8 >> 2),
101 (0x0e00 << 16) | (0xc2bc >> 2),
103 (0x0e00 << 16) | (0xc2c0 >> 2),
105 (0x0e00 << 16) | (0x8228 >> 2),
107 (0x0e00 << 16) | (0x829c >> 2),
109 (0x0e00 << 16) | (0x869c >> 2),
111 (0x0600 << 16) | (0x98f4 >> 2),
113 (0x0e00 << 16) | (0x98f8 >> 2),
115 (0x0e00 << 16) | (0x9900 >> 2),
117 (0x0e00 << 16) | (0xc260 >> 2),
119 (0x0e00 << 16) | (0x90e8 >> 2),
121 (0x0e00 << 16) | (0x3c000 >> 2),
123 (0x0e00 << 16) | (0x3c00c >> 2),
125 (0x0e00 << 16) | (0x8c1c >> 2),
127 (0x0e00 << 16) | (0x9700 >> 2),
129 (0x0e00 << 16) | (0xcd20 >> 2),
131 (0x4e00 << 16) | (0xcd20 >> 2),
133 (0x5e00 << 16) | (0xcd20 >> 2),
135 (0x6e00 << 16) | (0xcd20 >> 2),
137 (0x7e00 << 16) | (0xcd20 >> 2),
139 (0x8e00 << 16) | (0xcd20 >> 2),
141 (0x9e00 << 16) | (0xcd20 >> 2),
143 (0xae00 << 16) | (0xcd20 >> 2),
145 (0xbe00 << 16) | (0xcd20 >> 2),
147 (0x0e00 << 16) | (0x89bc >> 2),
149 (0x0e00 << 16) | (0x8900 >> 2),
152 (0x0e00 << 16) | (0xc130 >> 2),
154 (0x0e00 << 16) | (0xc134 >> 2),
156 (0x0e00 << 16) | (0xc1fc >> 2),
158 (0x0e00 << 16) | (0xc208 >> 2),
160 (0x0e00 << 16) | (0xc264 >> 2),
162 (0x0e00 << 16) | (0xc268 >> 2),
164 (0x0e00 << 16) | (0xc26c >> 2),
166 (0x0e00 << 16) | (0xc270 >> 2),
168 (0x0e00 << 16) | (0xc274 >> 2),
170 (0x0e00 << 16) | (0xc278 >> 2),
172 (0x0e00 << 16) | (0xc27c >> 2),
174 (0x0e00 << 16) | (0xc280 >> 2),
176 (0x0e00 << 16) | (0xc284 >> 2),
178 (0x0e00 << 16) | (0xc288 >> 2),
180 (0x0e00 << 16) | (0xc28c >> 2),
182 (0x0e00 << 16) | (0xc290 >> 2),
184 (0x0e00 << 16) | (0xc294 >> 2),
186 (0x0e00 << 16) | (0xc298 >> 2),
188 (0x0e00 << 16) | (0xc29c >> 2),
190 (0x0e00 << 16) | (0xc2a0 >> 2),
192 (0x0e00 << 16) | (0xc2a4 >> 2),
194 (0x0e00 << 16) | (0xc2a8 >> 2),
196 (0x0e00 << 16) | (0xc2ac >> 2),
198 (0x0e00 << 16) | (0xc2b0 >> 2),
200 (0x0e00 << 16) | (0x301d0 >> 2),
202 (0x0e00 << 16) | (0x30238 >> 2),
204 (0x0e00 << 16) | (0x30250 >> 2),
206 (0x0e00 << 16) | (0x30254 >> 2),
208 (0x0e00 << 16) | (0x30258 >> 2),
210 (0x0e00 << 16) | (0x3025c >> 2),
212 (0x4e00 << 16) | (0xc900 >> 2),
214 (0x5e00 << 16) | (0xc900 >> 2),
216 (0x6e00 << 16) | (0xc900 >> 2),
218 (0x7e00 << 16) | (0xc900 >> 2),
220 (0x8e00 << 16) | (0xc900 >> 2),
222 (0x9e00 << 16) | (0xc900 >> 2),
224 (0xae00 << 16) | (0xc900 >> 2),
226 (0xbe00 << 16) | (0xc900 >> 2),
228 (0x4e00 << 16) | (0xc904 >> 2),
230 (0x5e00 << 16) | (0xc904 >> 2),
232 (0x6e00 << 16) | (0xc904 >> 2),
234 (0x7e00 << 16) | (0xc904 >> 2),
236 (0x8e00 << 16) | (0xc904 >> 2),
238 (0x9e00 << 16) | (0xc904 >> 2),
240 (0xae00 << 16) | (0xc904 >> 2),
242 (0xbe00 << 16) | (0xc904 >> 2),
244 (0x4e00 << 16) | (0xc908 >> 2),
246 (0x5e00 << 16) | (0xc908 >> 2),
248 (0x6e00 << 16) | (0xc908 >> 2),
250 (0x7e00 << 16) | (0xc908 >> 2),
252 (0x8e00 << 16) | (0xc908 >> 2),
254 (0x9e00 << 16) | (0xc908 >> 2),
256 (0xae00 << 16) | (0xc908 >> 2),
258 (0xbe00 << 16) | (0xc908 >> 2),
260 (0x4e00 << 16) | (0xc90c >> 2),
262 (0x5e00 << 16) | (0xc90c >> 2),
264 (0x6e00 << 16) | (0xc90c >> 2),
266 (0x7e00 << 16) | (0xc90c >> 2),
268 (0x8e00 << 16) | (0xc90c >> 2),
270 (0x9e00 << 16) | (0xc90c >> 2),
272 (0xae00 << 16) | (0xc90c >> 2),
274 (0xbe00 << 16) | (0xc90c >> 2),
276 (0x4e00 << 16) | (0xc910 >> 2),
278 (0x5e00 << 16) | (0xc910 >> 2),
280 (0x6e00 << 16) | (0xc910 >> 2),
282 (0x7e00 << 16) | (0xc910 >> 2),
284 (0x8e00 << 16) | (0xc910 >> 2),
286 (0x9e00 << 16) | (0xc910 >> 2),
288 (0xae00 << 16) | (0xc910 >> 2),
290 (0xbe00 << 16) | (0xc910 >> 2),
292 (0x0e00 << 16) | (0xc99c >> 2),
294 (0x0e00 << 16) | (0x9834 >> 2),
296 (0x0000 << 16) | (0x30f00 >> 2),
298 (0x0001 << 16) | (0x30f00 >> 2),
300 (0x0000 << 16) | (0x30f04 >> 2),
302 (0x0001 << 16) | (0x30f04 >> 2),
304 (0x0000 << 16) | (0x30f08 >> 2),
306 (0x0001 << 16) | (0x30f08 >> 2),
308 (0x0000 << 16) | (0x30f0c >> 2),
310 (0x0001 << 16) | (0x30f0c >> 2),
312 (0x0600 << 16) | (0x9b7c >> 2),
314 (0x0e00 << 16) | (0x8a14 >> 2),
316 (0x0e00 << 16) | (0x8a18 >> 2),
318 (0x0600 << 16) | (0x30a00 >> 2),
320 (0x0e00 << 16) | (0x8bf0 >> 2),
322 (0x0e00 << 16) | (0x8bcc >> 2),
324 (0x0e00 << 16) | (0x8b24 >> 2),
326 (0x0e00 << 16) | (0x30a04 >> 2),
328 (0x0600 << 16) | (0x30a10 >> 2),
330 (0x0600 << 16) | (0x30a14 >> 2),
332 (0x0600 << 16) | (0x30a18 >> 2),
334 (0x0600 << 16) | (0x30a2c >> 2),
336 (0x0e00 << 16) | (0xc700 >> 2),
338 (0x0e00 << 16) | (0xc704 >> 2),
340 (0x0e00 << 16) | (0xc708 >> 2),
342 (0x0e00 << 16) | (0xc768 >> 2),
344 (0x0400 << 16) | (0xc770 >> 2),
346 (0x0400 << 16) | (0xc774 >> 2),
348 (0x0400 << 16) | (0xc778 >> 2),
350 (0x0400 << 16) | (0xc77c >> 2),
352 (0x0400 << 16) | (0xc780 >> 2),
354 (0x0400 << 16) | (0xc784 >> 2),
356 (0x0400 << 16) | (0xc788 >> 2),
358 (0x0400 << 16) | (0xc78c >> 2),
360 (0x0400 << 16) | (0xc798 >> 2),
362 (0x0400 << 16) | (0xc79c >> 2),
364 (0x0400 << 16) | (0xc7a0 >> 2),
366 (0x0400 << 16) | (0xc7a4 >> 2),
368 (0x0400 << 16) | (0xc7a8 >> 2),
370 (0x0400 << 16) | (0xc7ac >> 2),
372 (0x0400 << 16) | (0xc7b0 >> 2),
374 (0x0400 << 16) | (0xc7b4 >> 2),
376 (0x0e00 << 16) | (0x9100 >> 2),
378 (0x0e00 << 16) | (0x3c010 >> 2),
380 (0x0e00 << 16) | (0x92a8 >> 2),
382 (0x0e00 << 16) | (0x92ac >> 2),
384 (0x0e00 << 16) | (0x92b4 >> 2),
386 (0x0e00 << 16) | (0x92b8 >> 2),
388 (0x0e00 << 16) | (0x92bc >> 2),
390 (0x0e00 << 16) | (0x92c0 >> 2),
392 (0x0e00 << 16) | (0x92c4 >> 2),
394 (0x0e00 << 16) | (0x92c8 >> 2),
396 (0x0e00 << 16) | (0x92cc >> 2),
398 (0x0e00 << 16) | (0x92d0 >> 2),
400 (0x0e00 << 16) | (0x8c00 >> 2),
402 (0x0e00 << 16) | (0x8c04 >> 2),
404 (0x0e00 << 16) | (0x8c20 >> 2),
406 (0x0e00 << 16) | (0x8c38 >> 2),
408 (0x0e00 << 16) | (0x8c3c >> 2),
410 (0x0e00 << 16) | (0xae00 >> 2),
412 (0x0e00 << 16) | (0x9604 >> 2),
414 (0x0e00 << 16) | (0xac08 >> 2),
416 (0x0e00 << 16) | (0xac0c >> 2),
418 (0x0e00 << 16) | (0xac10 >> 2),
420 (0x0e00 << 16) | (0xac14 >> 2),
422 (0x0e00 << 16) | (0xac58 >> 2),
424 (0x0e00 << 16) | (0xac68 >> 2),
426 (0x0e00 << 16) | (0xac6c >> 2),
428 (0x0e00 << 16) | (0xac70 >> 2),
430 (0x0e00 << 16) | (0xac74 >> 2),
432 (0x0e00 << 16) | (0xac78 >> 2),
434 (0x0e00 << 16) | (0xac7c >> 2),
436 (0x0e00 << 16) | (0xac80 >> 2),
438 (0x0e00 << 16) | (0xac84 >> 2),
440 (0x0e00 << 16) | (0xac88 >> 2),
442 (0x0e00 << 16) | (0xac8c >> 2),
444 (0x0e00 << 16) | (0x970c >> 2),
446 (0x0e00 << 16) | (0x9714 >> 2),
448 (0x0e00 << 16) | (0x9718 >> 2),
450 (0x0e00 << 16) | (0x971c >> 2),
452 (0x0e00 << 16) | (0x31068 >> 2),
454 (0x4e00 << 16) | (0x31068 >> 2),
456 (0x5e00 << 16) | (0x31068 >> 2),
458 (0x6e00 << 16) | (0x31068 >> 2),
460 (0x7e00 << 16) | (0x31068 >> 2),
462 (0x8e00 << 16) | (0x31068 >> 2),
464 (0x9e00 << 16) | (0x31068 >> 2),
466 (0xae00 << 16) | (0x31068 >> 2),
468 (0xbe00 << 16) | (0x31068 >> 2),
470 (0x0e00 << 16) | (0xcd10 >> 2),
472 (0x0e00 << 16) | (0xcd14 >> 2),
474 (0x0e00 << 16) | (0x88b0 >> 2),
476 (0x0e00 << 16) | (0x88b4 >> 2),
478 (0x0e00 << 16) | (0x88b8 >> 2),
480 (0x0e00 << 16) | (0x88bc >> 2),
482 (0x0400 << 16) | (0x89c0 >> 2),
484 (0x0e00 << 16) | (0x88c4 >> 2),
486 (0x0e00 << 16) | (0x88c8 >> 2),
488 (0x0e00 << 16) | (0x88d0 >> 2),
490 (0x0e00 << 16) | (0x88d4 >> 2),
492 (0x0e00 << 16) | (0x88d8 >> 2),
494 (0x0e00 << 16) | (0x8980 >> 2),
496 (0x0e00 << 16) | (0x30938 >> 2),
498 (0x0e00 << 16) | (0x3093c >> 2),
500 (0x0e00 << 16) | (0x30940 >> 2),
502 (0x0e00 << 16) | (0x89a0 >> 2),
504 (0x0e00 << 16) | (0x30900 >> 2),
506 (0x0e00 << 16) | (0x30904 >> 2),
508 (0x0e00 << 16) | (0x89b4 >> 2),
510 (0x0e00 << 16) | (0x3c210 >> 2),
512 (0x0e00 << 16) | (0x3c214 >> 2),
514 (0x0e00 << 16) | (0x3c218 >> 2),
516 (0x0e00 << 16) | (0x8904 >> 2),
519 (0x0e00 << 16) | (0x8c28 >> 2),
520 (0x0e00 << 16) | (0x8c2c >> 2),
521 (0x0e00 << 16) | (0x8c30 >> 2),
522 (0x0e00 << 16) | (0x8c34 >> 2),
523 (0x0e00 << 16) | (0x9600 >> 2),
526 static const u32 kalindi_rlc_save_restore_register_list[] =
528 (0x0e00 << 16) | (0xc12c >> 2),
530 (0x0e00 << 16) | (0xc140 >> 2),
532 (0x0e00 << 16) | (0xc150 >> 2),
534 (0x0e00 << 16) | (0xc15c >> 2),
536 (0x0e00 << 16) | (0xc168 >> 2),
538 (0x0e00 << 16) | (0xc170 >> 2),
540 (0x0e00 << 16) | (0xc204 >> 2),
542 (0x0e00 << 16) | (0xc2b4 >> 2),
544 (0x0e00 << 16) | (0xc2b8 >> 2),
546 (0x0e00 << 16) | (0xc2bc >> 2),
548 (0x0e00 << 16) | (0xc2c0 >> 2),
550 (0x0e00 << 16) | (0x8228 >> 2),
552 (0x0e00 << 16) | (0x829c >> 2),
554 (0x0e00 << 16) | (0x869c >> 2),
556 (0x0600 << 16) | (0x98f4 >> 2),
558 (0x0e00 << 16) | (0x98f8 >> 2),
560 (0x0e00 << 16) | (0x9900 >> 2),
562 (0x0e00 << 16) | (0xc260 >> 2),
564 (0x0e00 << 16) | (0x90e8 >> 2),
566 (0x0e00 << 16) | (0x3c000 >> 2),
568 (0x0e00 << 16) | (0x3c00c >> 2),
570 (0x0e00 << 16) | (0x8c1c >> 2),
572 (0x0e00 << 16) | (0x9700 >> 2),
574 (0x0e00 << 16) | (0xcd20 >> 2),
576 (0x4e00 << 16) | (0xcd20 >> 2),
578 (0x5e00 << 16) | (0xcd20 >> 2),
580 (0x6e00 << 16) | (0xcd20 >> 2),
582 (0x7e00 << 16) | (0xcd20 >> 2),
584 (0x0e00 << 16) | (0x89bc >> 2),
586 (0x0e00 << 16) | (0x8900 >> 2),
589 (0x0e00 << 16) | (0xc130 >> 2),
591 (0x0e00 << 16) | (0xc134 >> 2),
593 (0x0e00 << 16) | (0xc1fc >> 2),
595 (0x0e00 << 16) | (0xc208 >> 2),
597 (0x0e00 << 16) | (0xc264 >> 2),
599 (0x0e00 << 16) | (0xc268 >> 2),
601 (0x0e00 << 16) | (0xc26c >> 2),
603 (0x0e00 << 16) | (0xc270 >> 2),
605 (0x0e00 << 16) | (0xc274 >> 2),
607 (0x0e00 << 16) | (0xc28c >> 2),
609 (0x0e00 << 16) | (0xc290 >> 2),
611 (0x0e00 << 16) | (0xc294 >> 2),
613 (0x0e00 << 16) | (0xc298 >> 2),
615 (0x0e00 << 16) | (0xc2a0 >> 2),
617 (0x0e00 << 16) | (0xc2a4 >> 2),
619 (0x0e00 << 16) | (0xc2a8 >> 2),
621 (0x0e00 << 16) | (0xc2ac >> 2),
623 (0x0e00 << 16) | (0x301d0 >> 2),
625 (0x0e00 << 16) | (0x30238 >> 2),
627 (0x0e00 << 16) | (0x30250 >> 2),
629 (0x0e00 << 16) | (0x30254 >> 2),
631 (0x0e00 << 16) | (0x30258 >> 2),
633 (0x0e00 << 16) | (0x3025c >> 2),
635 (0x4e00 << 16) | (0xc900 >> 2),
637 (0x5e00 << 16) | (0xc900 >> 2),
639 (0x6e00 << 16) | (0xc900 >> 2),
641 (0x7e00 << 16) | (0xc900 >> 2),
643 (0x4e00 << 16) | (0xc904 >> 2),
645 (0x5e00 << 16) | (0xc904 >> 2),
647 (0x6e00 << 16) | (0xc904 >> 2),
649 (0x7e00 << 16) | (0xc904 >> 2),
651 (0x4e00 << 16) | (0xc908 >> 2),
653 (0x5e00 << 16) | (0xc908 >> 2),
655 (0x6e00 << 16) | (0xc908 >> 2),
657 (0x7e00 << 16) | (0xc908 >> 2),
659 (0x4e00 << 16) | (0xc90c >> 2),
661 (0x5e00 << 16) | (0xc90c >> 2),
663 (0x6e00 << 16) | (0xc90c >> 2),
665 (0x7e00 << 16) | (0xc90c >> 2),
667 (0x4e00 << 16) | (0xc910 >> 2),
669 (0x5e00 << 16) | (0xc910 >> 2),
671 (0x6e00 << 16) | (0xc910 >> 2),
673 (0x7e00 << 16) | (0xc910 >> 2),
675 (0x0e00 << 16) | (0xc99c >> 2),
677 (0x0e00 << 16) | (0x9834 >> 2),
679 (0x0000 << 16) | (0x30f00 >> 2),
681 (0x0000 << 16) | (0x30f04 >> 2),
683 (0x0000 << 16) | (0x30f08 >> 2),
685 (0x0000 << 16) | (0x30f0c >> 2),
687 (0x0600 << 16) | (0x9b7c >> 2),
689 (0x0e00 << 16) | (0x8a14 >> 2),
691 (0x0e00 << 16) | (0x8a18 >> 2),
693 (0x0600 << 16) | (0x30a00 >> 2),
695 (0x0e00 << 16) | (0x8bf0 >> 2),
697 (0x0e00 << 16) | (0x8bcc >> 2),
699 (0x0e00 << 16) | (0x8b24 >> 2),
701 (0x0e00 << 16) | (0x30a04 >> 2),
703 (0x0600 << 16) | (0x30a10 >> 2),
705 (0x0600 << 16) | (0x30a14 >> 2),
707 (0x0600 << 16) | (0x30a18 >> 2),
709 (0x0600 << 16) | (0x30a2c >> 2),
711 (0x0e00 << 16) | (0xc700 >> 2),
713 (0x0e00 << 16) | (0xc704 >> 2),
715 (0x0e00 << 16) | (0xc708 >> 2),
717 (0x0e00 << 16) | (0xc768 >> 2),
719 (0x0400 << 16) | (0xc770 >> 2),
721 (0x0400 << 16) | (0xc774 >> 2),
723 (0x0400 << 16) | (0xc798 >> 2),
725 (0x0400 << 16) | (0xc79c >> 2),
727 (0x0e00 << 16) | (0x9100 >> 2),
729 (0x0e00 << 16) | (0x3c010 >> 2),
731 (0x0e00 << 16) | (0x8c00 >> 2),
733 (0x0e00 << 16) | (0x8c04 >> 2),
735 (0x0e00 << 16) | (0x8c20 >> 2),
737 (0x0e00 << 16) | (0x8c38 >> 2),
739 (0x0e00 << 16) | (0x8c3c >> 2),
741 (0x0e00 << 16) | (0xae00 >> 2),
743 (0x0e00 << 16) | (0x9604 >> 2),
745 (0x0e00 << 16) | (0xac08 >> 2),
747 (0x0e00 << 16) | (0xac0c >> 2),
749 (0x0e00 << 16) | (0xac10 >> 2),
751 (0x0e00 << 16) | (0xac14 >> 2),
753 (0x0e00 << 16) | (0xac58 >> 2),
755 (0x0e00 << 16) | (0xac68 >> 2),
757 (0x0e00 << 16) | (0xac6c >> 2),
759 (0x0e00 << 16) | (0xac70 >> 2),
761 (0x0e00 << 16) | (0xac74 >> 2),
763 (0x0e00 << 16) | (0xac78 >> 2),
765 (0x0e00 << 16) | (0xac7c >> 2),
767 (0x0e00 << 16) | (0xac80 >> 2),
769 (0x0e00 << 16) | (0xac84 >> 2),
771 (0x0e00 << 16) | (0xac88 >> 2),
773 (0x0e00 << 16) | (0xac8c >> 2),
775 (0x0e00 << 16) | (0x970c >> 2),
777 (0x0e00 << 16) | (0x9714 >> 2),
779 (0x0e00 << 16) | (0x9718 >> 2),
781 (0x0e00 << 16) | (0x971c >> 2),
783 (0x0e00 << 16) | (0x31068 >> 2),
785 (0x4e00 << 16) | (0x31068 >> 2),
787 (0x5e00 << 16) | (0x31068 >> 2),
789 (0x6e00 << 16) | (0x31068 >> 2),
791 (0x7e00 << 16) | (0x31068 >> 2),
793 (0x0e00 << 16) | (0xcd10 >> 2),
795 (0x0e00 << 16) | (0xcd14 >> 2),
797 (0x0e00 << 16) | (0x88b0 >> 2),
799 (0x0e00 << 16) | (0x88b4 >> 2),
801 (0x0e00 << 16) | (0x88b8 >> 2),
803 (0x0e00 << 16) | (0x88bc >> 2),
805 (0x0400 << 16) | (0x89c0 >> 2),
807 (0x0e00 << 16) | (0x88c4 >> 2),
809 (0x0e00 << 16) | (0x88c8 >> 2),
811 (0x0e00 << 16) | (0x88d0 >> 2),
813 (0x0e00 << 16) | (0x88d4 >> 2),
815 (0x0e00 << 16) | (0x88d8 >> 2),
817 (0x0e00 << 16) | (0x8980 >> 2),
819 (0x0e00 << 16) | (0x30938 >> 2),
821 (0x0e00 << 16) | (0x3093c >> 2),
823 (0x0e00 << 16) | (0x30940 >> 2),
825 (0x0e00 << 16) | (0x89a0 >> 2),
827 (0x0e00 << 16) | (0x30900 >> 2),
829 (0x0e00 << 16) | (0x30904 >> 2),
831 (0x0e00 << 16) | (0x89b4 >> 2),
833 (0x0e00 << 16) | (0x3e1fc >> 2),
835 (0x0e00 << 16) | (0x3c210 >> 2),
837 (0x0e00 << 16) | (0x3c214 >> 2),
839 (0x0e00 << 16) | (0x3c218 >> 2),
841 (0x0e00 << 16) | (0x8904 >> 2),
844 (0x0e00 << 16) | (0x8c28 >> 2),
845 (0x0e00 << 16) | (0x8c2c >> 2),
846 (0x0e00 << 16) | (0x8c30 >> 2),
847 (0x0e00 << 16) | (0x8c34 >> 2),
848 (0x0e00 << 16) | (0x9600 >> 2),
851 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
852 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
853 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
854 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
855 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
861 * gfx_v7_0_init_microcode - load ucode images from disk
863 * @adev: amdgpu_device pointer
865 * Use the firmware interface to load the ucode images into
866 * the driver (not loaded into hw).
867 * Returns 0 on success, error on failure.
869 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
871 const char *chip_name;
877 switch (adev->asic_type) {
879 chip_name = "bonaire";
882 chip_name = "hawaii";
885 chip_name = "kaveri";
888 chip_name = "kabini";
891 chip_name = "mullins";
896 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
897 err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
900 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
904 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
905 err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
908 err = amdgpu_ucode_validate(adev->gfx.me_fw);
912 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
913 err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
916 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
920 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
921 err = reject_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
924 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
928 if (adev->asic_type == CHIP_KAVERI) {
929 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
930 err = reject_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
933 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
938 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
939 err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
942 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
947 "gfx7: Failed to load firmware \"%s\"\n",
949 release_firmware(adev->gfx.pfp_fw);
950 adev->gfx.pfp_fw = NULL;
951 release_firmware(adev->gfx.me_fw);
952 adev->gfx.me_fw = NULL;
953 release_firmware(adev->gfx.ce_fw);
954 adev->gfx.ce_fw = NULL;
955 release_firmware(adev->gfx.mec_fw);
956 adev->gfx.mec_fw = NULL;
957 release_firmware(adev->gfx.mec2_fw);
958 adev->gfx.mec2_fw = NULL;
959 release_firmware(adev->gfx.rlc_fw);
960 adev->gfx.rlc_fw = NULL;
965 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
967 release_firmware(adev->gfx.pfp_fw);
968 adev->gfx.pfp_fw = NULL;
969 release_firmware(adev->gfx.me_fw);
970 adev->gfx.me_fw = NULL;
971 release_firmware(adev->gfx.ce_fw);
972 adev->gfx.ce_fw = NULL;
973 release_firmware(adev->gfx.mec_fw);
974 adev->gfx.mec_fw = NULL;
975 release_firmware(adev->gfx.mec2_fw);
976 adev->gfx.mec2_fw = NULL;
977 release_firmware(adev->gfx.rlc_fw);
978 adev->gfx.rlc_fw = NULL;
982 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
984 * @adev: amdgpu_device pointer
986 * Starting with SI, the tiling setup is done globally in a
987 * set of 32 tiling modes. Rather than selecting each set of
988 * parameters per surface as on older asics, we just select
989 * which index in the tiling table we want to use, and the
990 * surface uses those parameters (CIK).
992 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
994 const u32 num_tile_mode_states =
995 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
996 const u32 num_secondary_tile_mode_states =
997 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
998 u32 reg_offset, split_equal_to_row_size;
999 uint32_t *tile, *macrotile;
1001 tile = adev->gfx.config.tile_mode_array;
1002 macrotile = adev->gfx.config.macrotile_mode_array;
1004 switch (adev->gfx.config.mem_row_size_in_kb) {
1006 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1010 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1013 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1017 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1018 tile[reg_offset] = 0;
1019 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1020 macrotile[reg_offset] = 0;
1022 switch (adev->asic_type) {
1024 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1025 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1027 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1028 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1029 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1030 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1031 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1032 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1033 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1034 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1035 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1036 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1037 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1039 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1040 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1041 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1042 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1043 TILE_SPLIT(split_equal_to_row_size));
1044 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1045 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1046 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1047 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1048 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1049 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1050 TILE_SPLIT(split_equal_to_row_size));
1051 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1052 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1053 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1054 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1055 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1057 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1060 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1061 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1064 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1065 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1066 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1067 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1069 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1071 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1072 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1073 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1076 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1077 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1078 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1079 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1080 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1081 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1082 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1086 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1089 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1090 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1091 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1093 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1094 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1095 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1096 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1097 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1098 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1099 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1101 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1102 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1106 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1110 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1115 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1116 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1117 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1118 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1120 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1121 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1122 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1123 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1125 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1127 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1130 NUM_BANKS(ADDR_SURF_16_BANK));
1131 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1132 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1133 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1134 NUM_BANKS(ADDR_SURF_16_BANK));
1135 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1138 NUM_BANKS(ADDR_SURF_16_BANK));
1139 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1140 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1141 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1142 NUM_BANKS(ADDR_SURF_16_BANK));
1143 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1144 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1145 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1146 NUM_BANKS(ADDR_SURF_16_BANK));
1147 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1148 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1149 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1150 NUM_BANKS(ADDR_SURF_8_BANK));
1151 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1152 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1153 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1154 NUM_BANKS(ADDR_SURF_4_BANK));
1155 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1156 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1157 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1158 NUM_BANKS(ADDR_SURF_16_BANK));
1159 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1160 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1161 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1162 NUM_BANKS(ADDR_SURF_16_BANK));
1163 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1164 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1165 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1166 NUM_BANKS(ADDR_SURF_16_BANK));
1167 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1170 NUM_BANKS(ADDR_SURF_16_BANK));
1171 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1172 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1173 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1174 NUM_BANKS(ADDR_SURF_16_BANK));
1175 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1178 NUM_BANKS(ADDR_SURF_8_BANK));
1179 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1182 NUM_BANKS(ADDR_SURF_4_BANK));
1184 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1185 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1186 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1187 if (reg_offset != 7)
1188 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1191 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1192 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1193 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1194 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1195 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1196 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1197 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1198 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1199 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1200 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1201 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1202 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1203 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1204 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1205 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1206 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1207 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1208 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1209 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1210 TILE_SPLIT(split_equal_to_row_size));
1211 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1212 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1213 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1214 TILE_SPLIT(split_equal_to_row_size));
1215 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1216 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1217 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1218 TILE_SPLIT(split_equal_to_row_size));
1219 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1220 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1221 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1222 TILE_SPLIT(split_equal_to_row_size));
1223 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1224 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1225 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1226 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1228 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1231 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1232 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1235 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1236 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1237 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1239 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1240 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1243 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1244 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1245 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1246 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1247 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1248 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1249 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1250 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1251 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1252 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1253 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1254 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1255 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1256 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1257 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1258 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1259 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1260 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1261 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1262 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1263 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1264 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1265 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1266 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1267 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1268 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1269 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1270 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1271 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1272 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1273 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1274 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1275 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1276 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1277 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1278 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1279 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1280 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1281 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1282 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1283 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1284 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1285 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1286 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1287 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1288 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1289 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1290 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1291 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1292 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1293 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1294 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1296 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1297 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1298 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1299 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1301 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1302 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1303 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1304 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1305 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1306 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1307 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1308 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1310 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1311 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1312 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1313 NUM_BANKS(ADDR_SURF_16_BANK));
1314 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1315 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1316 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1317 NUM_BANKS(ADDR_SURF_16_BANK));
1318 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1319 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1320 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1321 NUM_BANKS(ADDR_SURF_16_BANK));
1322 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1323 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1324 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1325 NUM_BANKS(ADDR_SURF_16_BANK));
1326 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1327 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1328 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1329 NUM_BANKS(ADDR_SURF_8_BANK));
1330 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1331 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1332 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1333 NUM_BANKS(ADDR_SURF_4_BANK));
1334 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1335 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1336 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1337 NUM_BANKS(ADDR_SURF_4_BANK));
1338 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1339 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1340 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1341 NUM_BANKS(ADDR_SURF_16_BANK));
1342 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1343 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1344 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1345 NUM_BANKS(ADDR_SURF_16_BANK));
1346 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1349 NUM_BANKS(ADDR_SURF_16_BANK));
1350 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1351 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1352 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1353 NUM_BANKS(ADDR_SURF_8_BANK));
1354 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1355 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1356 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1357 NUM_BANKS(ADDR_SURF_16_BANK));
1358 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1359 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1360 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1361 NUM_BANKS(ADDR_SURF_8_BANK));
1362 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1363 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1364 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1365 NUM_BANKS(ADDR_SURF_4_BANK));
1367 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1368 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1369 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1370 if (reg_offset != 7)
1371 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1377 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1378 PIPE_CONFIG(ADDR_SURF_P2) |
1379 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1380 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1381 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1382 PIPE_CONFIG(ADDR_SURF_P2) |
1383 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1384 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1385 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1386 PIPE_CONFIG(ADDR_SURF_P2) |
1387 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1388 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1389 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1390 PIPE_CONFIG(ADDR_SURF_P2) |
1391 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1392 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1393 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1394 PIPE_CONFIG(ADDR_SURF_P2) |
1395 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1396 TILE_SPLIT(split_equal_to_row_size));
1397 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1398 PIPE_CONFIG(ADDR_SURF_P2) |
1399 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1400 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1401 PIPE_CONFIG(ADDR_SURF_P2) |
1402 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1403 TILE_SPLIT(split_equal_to_row_size));
1404 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1405 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1406 PIPE_CONFIG(ADDR_SURF_P2));
1407 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1408 PIPE_CONFIG(ADDR_SURF_P2) |
1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1410 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1413 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1414 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1415 PIPE_CONFIG(ADDR_SURF_P2) |
1416 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1417 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1418 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1419 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1420 PIPE_CONFIG(ADDR_SURF_P2) |
1421 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1422 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423 PIPE_CONFIG(ADDR_SURF_P2) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1425 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1426 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1427 PIPE_CONFIG(ADDR_SURF_P2) |
1428 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1429 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1430 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1431 PIPE_CONFIG(ADDR_SURF_P2) |
1432 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1433 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1434 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1435 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1436 PIPE_CONFIG(ADDR_SURF_P2) |
1437 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1439 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1442 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1443 PIPE_CONFIG(ADDR_SURF_P2) |
1444 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1445 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1446 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1447 PIPE_CONFIG(ADDR_SURF_P2) |
1448 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1449 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1450 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1451 PIPE_CONFIG(ADDR_SURF_P2) |
1452 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1453 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1454 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1455 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1459 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1463 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1464 PIPE_CONFIG(ADDR_SURF_P2) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1468 PIPE_CONFIG(ADDR_SURF_P2) |
1469 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1470 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1471 PIPE_CONFIG(ADDR_SURF_P2) |
1472 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1473 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1474 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1475 PIPE_CONFIG(ADDR_SURF_P2) |
1476 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1477 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1478 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1480 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1483 NUM_BANKS(ADDR_SURF_8_BANK));
1484 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1487 NUM_BANKS(ADDR_SURF_8_BANK));
1488 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1489 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1490 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1491 NUM_BANKS(ADDR_SURF_8_BANK));
1492 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1495 NUM_BANKS(ADDR_SURF_8_BANK));
1496 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1497 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1498 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1499 NUM_BANKS(ADDR_SURF_8_BANK));
1500 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1503 NUM_BANKS(ADDR_SURF_8_BANK));
1504 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1505 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1506 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1507 NUM_BANKS(ADDR_SURF_8_BANK));
1508 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1509 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1510 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1511 NUM_BANKS(ADDR_SURF_16_BANK));
1512 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1513 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1514 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1515 NUM_BANKS(ADDR_SURF_16_BANK));
1516 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1517 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1518 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1519 NUM_BANKS(ADDR_SURF_16_BANK));
1520 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1523 NUM_BANKS(ADDR_SURF_16_BANK));
1524 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1525 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1526 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1527 NUM_BANKS(ADDR_SURF_16_BANK));
1528 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1529 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1530 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1531 NUM_BANKS(ADDR_SURF_16_BANK));
1532 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1535 NUM_BANKS(ADDR_SURF_8_BANK));
1537 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1538 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1539 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1540 if (reg_offset != 7)
1541 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1547 * gfx_v7_0_select_se_sh - select which SE, SH to address
1549 * @adev: amdgpu_device pointer
1550 * @se_num: shader engine to address
1551 * @sh_num: sh block to address
1553 * Select which SE, SH combinations to address. Certain
1554 * registers are instanced per SE or SH. 0xffffffff means
1555 * broadcast to all SEs or SHs (CIK).
1557 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1558 u32 se_num, u32 sh_num, u32 instance)
1562 if (instance == 0xffffffff)
1563 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1565 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1567 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1568 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1569 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1570 else if (se_num == 0xffffffff)
1571 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1572 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1573 else if (sh_num == 0xffffffff)
1574 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1575 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1577 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1578 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1579 WREG32(mmGRBM_GFX_INDEX, data);
1583 * gfx_v7_0_create_bitmask - create a bitmask
1585 * @bit_width: length of the mask
1587 * create a variable length bit mask (CIK).
1588 * Returns the bitmask.
1590 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1592 return (u32)((1ULL << bit_width) - 1);
1596 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1598 * @adev: amdgpu_device pointer
1600 * Calculates the bitmask of enabled RBs (CIK).
1601 * Returns the enabled RB bitmask.
1603 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1607 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1608 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1610 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1611 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1613 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1614 adev->gfx.config.max_sh_per_se);
1616 return (~data) & mask;
1620 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1622 switch (adev->asic_type) {
1624 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1625 SE_XSEL(1) | SE_YSEL(1);
1629 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1630 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1631 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1633 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1637 *rconf |= RB_MAP_PKR0(2);
1646 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1652 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1653 u32 raster_config, u32 raster_config_1,
1654 unsigned rb_mask, unsigned num_rb)
1656 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1657 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1658 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1659 unsigned rb_per_se = num_rb / num_se;
1660 unsigned se_mask[4];
1663 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1664 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1665 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1666 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1668 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1669 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1670 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1672 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1673 (!se_mask[2] && !se_mask[3]))) {
1674 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1676 if (!se_mask[0] && !se_mask[1]) {
1678 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1681 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1685 for (se = 0; se < num_se; se++) {
1686 unsigned raster_config_se = raster_config;
1687 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1688 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1689 int idx = (se / 2) * 2;
1691 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1692 raster_config_se &= ~SE_MAP_MASK;
1694 if (!se_mask[idx]) {
1695 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1697 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1701 pkr0_mask &= rb_mask;
1702 pkr1_mask &= rb_mask;
1703 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1704 raster_config_se &= ~PKR_MAP_MASK;
1707 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1709 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1713 if (rb_per_se >= 2) {
1714 unsigned rb0_mask = 1 << (se * rb_per_se);
1715 unsigned rb1_mask = rb0_mask << 1;
1717 rb0_mask &= rb_mask;
1718 rb1_mask &= rb_mask;
1719 if (!rb0_mask || !rb1_mask) {
1720 raster_config_se &= ~RB_MAP_PKR0_MASK;
1724 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1727 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1731 if (rb_per_se > 2) {
1732 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1733 rb1_mask = rb0_mask << 1;
1734 rb0_mask &= rb_mask;
1735 rb1_mask &= rb_mask;
1736 if (!rb0_mask || !rb1_mask) {
1737 raster_config_se &= ~RB_MAP_PKR1_MASK;
1741 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1744 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1750 /* GRBM_GFX_INDEX has a different offset on CI+ */
1751 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1752 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1753 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1756 /* GRBM_GFX_INDEX has a different offset on CI+ */
1757 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1761 * gfx_v7_0_setup_rb - setup the RBs on the asic
1763 * @adev: amdgpu_device pointer
1764 * @se_num: number of SEs (shader engines) for the asic
1765 * @sh_per_se: number of SH blocks per SE for the asic
1767 * Configures per-SE/SH RB registers (CIK).
1769 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1773 u32 raster_config = 0, raster_config_1 = 0;
1775 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1776 adev->gfx.config.max_sh_per_se;
1777 unsigned num_rb_pipes;
1779 mutex_lock(&adev->grbm_idx_mutex);
1780 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1781 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1782 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1783 data = gfx_v7_0_get_rb_active_bitmap(adev);
1784 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1785 rb_bitmap_width_per_sh);
1788 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1790 adev->gfx.config.backend_enable_mask = active_rbs;
1791 adev->gfx.config.num_rbs = hweight32(active_rbs);
1793 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1794 adev->gfx.config.max_shader_engines, 16);
1796 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1798 if (!adev->gfx.config.backend_enable_mask ||
1799 adev->gfx.config.num_rbs >= num_rb_pipes) {
1800 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1801 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1803 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1804 adev->gfx.config.backend_enable_mask,
1807 mutex_unlock(&adev->grbm_idx_mutex);
1811 * gmc_v7_0_init_compute_vmid - gart enable
1813 * @rdev: amdgpu_device pointer
1815 * Initialize compute vmid sh_mem registers
1818 #define DEFAULT_SH_MEM_BASES (0x6000)
1819 #define FIRST_COMPUTE_VMID (8)
1820 #define LAST_COMPUTE_VMID (16)
1821 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1824 uint32_t sh_mem_config;
1825 uint32_t sh_mem_bases;
1828 * Configure apertures:
1829 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1830 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1831 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1833 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1834 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1835 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1836 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1837 mutex_lock(&adev->srbm_mutex);
1838 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1839 cik_srbm_select(adev, 0, 0, 0, i);
1840 /* CP and shaders */
1841 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1842 WREG32(mmSH_MEM_APE1_BASE, 1);
1843 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1844 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1846 cik_srbm_select(adev, 0, 0, 0, 0);
1847 mutex_unlock(&adev->srbm_mutex);
1851 * gfx_v7_0_gpu_init - setup the 3D engine
1853 * @adev: amdgpu_device pointer
1855 * Configures the 3D engine and tiling configuration
1856 * registers so that the 3D engine is usable.
1858 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1860 u32 tmp, sh_mem_cfg;
1863 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1865 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1866 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1867 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1869 gfx_v7_0_tiling_mode_table_init(adev);
1871 gfx_v7_0_setup_rb(adev);
1872 gfx_v7_0_get_cu_info(adev);
1874 /* set HW defaults for 3D engine */
1875 WREG32(mmCP_MEQ_THRESHOLDS,
1876 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1877 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1879 mutex_lock(&adev->grbm_idx_mutex);
1881 * making sure that the following register writes will be broadcasted
1882 * to all the shaders
1884 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1886 /* XXX SH_MEM regs */
1887 /* where to put LDS, scratch, GPUVM in FSA64 space */
1888 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1889 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1891 mutex_lock(&adev->srbm_mutex);
1892 for (i = 0; i < 16; i++) {
1893 cik_srbm_select(adev, 0, 0, 0, i);
1894 /* CP and shaders */
1895 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1896 WREG32(mmSH_MEM_APE1_BASE, 1);
1897 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1898 WREG32(mmSH_MEM_BASES, 0);
1900 cik_srbm_select(adev, 0, 0, 0, 0);
1901 mutex_unlock(&adev->srbm_mutex);
1903 gmc_v7_0_init_compute_vmid(adev);
1905 WREG32(mmSX_DEBUG_1, 0x20);
1907 WREG32(mmTA_CNTL_AUX, 0x00010000);
1909 tmp = RREG32(mmSPI_CONFIG_CNTL);
1911 WREG32(mmSPI_CONFIG_CNTL, tmp);
1913 WREG32(mmSQ_CONFIG, 1);
1915 WREG32(mmDB_DEBUG, 0);
1917 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1919 WREG32(mmDB_DEBUG2, tmp);
1921 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1923 WREG32(mmDB_DEBUG3, tmp);
1925 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1927 WREG32(mmCB_HW_CONTROL, tmp);
1929 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1931 WREG32(mmPA_SC_FIFO_SIZE,
1932 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1933 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1934 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1935 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1937 WREG32(mmVGT_NUM_INSTANCES, 1);
1939 WREG32(mmCP_PERFMON_CNTL, 0);
1941 WREG32(mmSQ_CONFIG, 0);
1943 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1944 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1945 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1947 WREG32(mmVGT_CACHE_INVALIDATION,
1948 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1949 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1951 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1952 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1954 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1955 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1956 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1957 mutex_unlock(&adev->grbm_idx_mutex);
1963 * GPU scratch registers helpers function.
1966 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1968 * @adev: amdgpu_device pointer
1970 * Set up the number and offset of the CP scratch registers.
1971 * NOTE: use of CP scratch registers is a legacy inferface and
1972 * is not used by default on newer asics (r6xx+). On newer asics,
1973 * memory buffers are used for fences rather than scratch regs.
1975 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1979 adev->gfx.scratch.num_reg = 7;
1980 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1981 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1982 adev->gfx.scratch.free[i] = true;
1983 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1988 * gfx_v7_0_ring_test_ring - basic gfx ring test
1990 * @adev: amdgpu_device pointer
1991 * @ring: amdgpu_ring structure holding ring information
1993 * Allocate a scratch register and write to it using the gfx ring (CIK).
1994 * Provides a basic gfx ring test to verify that the ring is working.
1995 * Used by gfx_v7_0_cp_gfx_resume();
1996 * Returns 0 on success, error on failure.
1998 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2000 struct amdgpu_device *adev = ring->adev;
2006 r = amdgpu_gfx_scratch_get(adev, &scratch);
2008 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2011 WREG32(scratch, 0xCAFEDEAD);
2012 r = amdgpu_ring_alloc(ring, 3);
2014 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2015 amdgpu_gfx_scratch_free(adev, scratch);
2018 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2019 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2020 amdgpu_ring_write(ring, 0xDEADBEEF);
2021 amdgpu_ring_commit(ring);
2023 for (i = 0; i < adev->usec_timeout; i++) {
2024 tmp = RREG32(scratch);
2025 if (tmp == 0xDEADBEEF)
2029 if (i < adev->usec_timeout) {
2030 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2032 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2033 ring->idx, scratch, tmp);
2036 amdgpu_gfx_scratch_free(adev, scratch);
2041 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2043 * @adev: amdgpu_device pointer
2044 * @ridx: amdgpu ring index
2046 * Emits an hdp flush on the cp.
2048 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2051 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2053 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
2056 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2059 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2065 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2068 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2069 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2070 WAIT_REG_MEM_FUNCTION(3) | /* == */
2071 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2072 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2073 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2074 amdgpu_ring_write(ring, ref_and_mask);
2075 amdgpu_ring_write(ring, ref_and_mask);
2076 amdgpu_ring_write(ring, 0x20); /* poll interval */
2080 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2082 * @adev: amdgpu_device pointer
2083 * @ridx: amdgpu ring index
2085 * Emits an hdp invalidate on the cp.
2087 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2089 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2090 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2091 WRITE_DATA_DST_SEL(0) |
2093 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2094 amdgpu_ring_write(ring, 0);
2095 amdgpu_ring_write(ring, 1);
2099 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2101 * @adev: amdgpu_device pointer
2102 * @fence: amdgpu fence object
2104 * Emits a fence sequnce number on the gfx ring and flushes
2107 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2108 u64 seq, unsigned flags)
2110 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2111 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2112 /* Workaround for cache flush problems. First send a dummy EOP
2113 * event down the pipe with seq one below.
2115 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2116 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2118 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2120 amdgpu_ring_write(ring, addr & 0xfffffffc);
2121 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2122 DATA_SEL(1) | INT_SEL(0));
2123 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2124 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2126 /* Then send the real EOP event down the pipe. */
2127 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2128 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2130 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2132 amdgpu_ring_write(ring, addr & 0xfffffffc);
2133 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2134 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2135 amdgpu_ring_write(ring, lower_32_bits(seq));
2136 amdgpu_ring_write(ring, upper_32_bits(seq));
2140 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2142 * @adev: amdgpu_device pointer
2143 * @fence: amdgpu fence object
2145 * Emits a fence sequnce number on the compute ring and flushes
2148 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2152 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2153 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2155 /* RELEASE_MEM - flush caches, send int */
2156 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2157 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2159 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2161 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2162 amdgpu_ring_write(ring, addr & 0xfffffffc);
2163 amdgpu_ring_write(ring, upper_32_bits(addr));
2164 amdgpu_ring_write(ring, lower_32_bits(seq));
2165 amdgpu_ring_write(ring, upper_32_bits(seq));
2172 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2174 * @ring: amdgpu_ring structure holding ring information
2175 * @ib: amdgpu indirect buffer object
2177 * Emits an DE (drawing engine) or CE (constant engine) IB
2178 * on the gfx ring. IBs are usually generated by userspace
2179 * acceleration drivers and submitted to the kernel for
2180 * sheduling on the ring. This function schedules the IB
2181 * on the gfx ring for execution by the GPU.
2183 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2184 struct amdgpu_ib *ib,
2185 unsigned vm_id, bool ctx_switch)
2187 u32 header, control = 0;
2189 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2191 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2192 amdgpu_ring_write(ring, 0);
2195 if (ib->flags & AMDGPU_IB_FLAG_CE)
2196 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2198 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2200 control |= ib->length_dw | (vm_id << 24);
2202 amdgpu_ring_write(ring, header);
2203 amdgpu_ring_write(ring,
2207 (ib->gpu_addr & 0xFFFFFFFC));
2208 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2209 amdgpu_ring_write(ring, control);
2212 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2213 struct amdgpu_ib *ib,
2214 unsigned vm_id, bool ctx_switch)
2216 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2218 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2219 amdgpu_ring_write(ring,
2223 (ib->gpu_addr & 0xFFFFFFFC));
2224 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2225 amdgpu_ring_write(ring, control);
2228 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2232 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2233 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2234 /* set load_global_config & load_global_uconfig */
2236 /* set load_cs_sh_regs */
2238 /* set load_per_context_state & load_gfx_sh_regs */
2242 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2243 amdgpu_ring_write(ring, dw2);
2244 amdgpu_ring_write(ring, 0);
2248 * gfx_v7_0_ring_test_ib - basic ring IB test
2250 * @ring: amdgpu_ring structure holding ring information
2252 * Allocate an IB and execute it on the gfx ring (CIK).
2253 * Provides a basic gfx ring test to verify that IBs are working.
2254 * Returns 0 on success, error on failure.
2256 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2258 struct amdgpu_device *adev = ring->adev;
2259 struct amdgpu_ib ib;
2260 struct fence *f = NULL;
2265 r = amdgpu_gfx_scratch_get(adev, &scratch);
2267 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
2270 WREG32(scratch, 0xCAFEDEAD);
2271 memset(&ib, 0, sizeof(ib));
2272 r = amdgpu_ib_get(adev, NULL, 256, &ib);
2274 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
2277 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2278 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2279 ib.ptr[2] = 0xDEADBEEF;
2282 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
2286 r = fence_wait_timeout(f, false, timeout);
2288 DRM_ERROR("amdgpu: IB test timed out\n");
2292 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
2295 tmp = RREG32(scratch);
2296 if (tmp == 0xDEADBEEF) {
2297 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
2300 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2306 amdgpu_ib_free(adev, &ib, NULL);
2309 amdgpu_gfx_scratch_free(adev, scratch);
2315 * On CIK, gfx and compute now have independant command processors.
2318 * Gfx consists of a single ring and can process both gfx jobs and
2319 * compute jobs. The gfx CP consists of three microengines (ME):
2320 * PFP - Pre-Fetch Parser
2322 * CE - Constant Engine
2323 * The PFP and ME make up what is considered the Drawing Engine (DE).
2324 * The CE is an asynchronous engine used for updating buffer desciptors
2325 * used by the DE so that they can be loaded into cache in parallel
2326 * while the DE is processing state update packets.
2329 * The compute CP consists of two microengines (ME):
2330 * MEC1 - Compute MicroEngine 1
2331 * MEC2 - Compute MicroEngine 2
2332 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2333 * The queues are exposed to userspace and are programmed directly
2334 * by the compute runtime.
2337 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2339 * @adev: amdgpu_device pointer
2340 * @enable: enable or disable the MEs
2342 * Halts or unhalts the gfx MEs.
2344 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2349 WREG32(mmCP_ME_CNTL, 0);
2351 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2352 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2353 adev->gfx.gfx_ring[i].ready = false;
2359 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2361 * @adev: amdgpu_device pointer
2363 * Loads the gfx PFP, ME, and CE ucode.
2364 * Returns 0 for success, -EINVAL if the ucode is not available.
2366 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2368 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2369 const struct gfx_firmware_header_v1_0 *ce_hdr;
2370 const struct gfx_firmware_header_v1_0 *me_hdr;
2371 const __le32 *fw_data;
2372 unsigned i, fw_size;
2374 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2377 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2378 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2379 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2381 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2382 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2383 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2384 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2385 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2386 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2387 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2388 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2389 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2391 gfx_v7_0_cp_gfx_enable(adev, false);
2394 fw_data = (const __le32 *)
2395 (adev->gfx.pfp_fw->data +
2396 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2397 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2398 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2399 for (i = 0; i < fw_size; i++)
2400 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2401 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2404 fw_data = (const __le32 *)
2405 (adev->gfx.ce_fw->data +
2406 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2407 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2408 WREG32(mmCP_CE_UCODE_ADDR, 0);
2409 for (i = 0; i < fw_size; i++)
2410 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2411 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2414 fw_data = (const __le32 *)
2415 (adev->gfx.me_fw->data +
2416 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2417 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2418 WREG32(mmCP_ME_RAM_WADDR, 0);
2419 for (i = 0; i < fw_size; i++)
2420 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2421 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2427 * gfx_v7_0_cp_gfx_start - start the gfx ring
2429 * @adev: amdgpu_device pointer
2431 * Enables the ring and loads the clear state context and other
2432 * packets required to init the ring.
2433 * Returns 0 for success, error for failure.
2435 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2437 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2438 const struct cs_section_def *sect = NULL;
2439 const struct cs_extent_def *ext = NULL;
2443 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2444 WREG32(mmCP_ENDIAN_SWAP, 0);
2445 WREG32(mmCP_DEVICE_ID, 1);
2447 gfx_v7_0_cp_gfx_enable(adev, true);
2449 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2451 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2455 /* init the CE partitions. CE only used for gfx on CIK */
2456 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2457 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2458 amdgpu_ring_write(ring, 0x8000);
2459 amdgpu_ring_write(ring, 0x8000);
2461 /* clear state buffer */
2462 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2463 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2465 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2466 amdgpu_ring_write(ring, 0x80000000);
2467 amdgpu_ring_write(ring, 0x80000000);
2469 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2470 for (ext = sect->section; ext->extent != NULL; ++ext) {
2471 if (sect->id == SECT_CONTEXT) {
2472 amdgpu_ring_write(ring,
2473 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2474 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2475 for (i = 0; i < ext->reg_count; i++)
2476 amdgpu_ring_write(ring, ext->extent[i]);
2481 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2482 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2483 switch (adev->asic_type) {
2485 amdgpu_ring_write(ring, 0x16000012);
2486 amdgpu_ring_write(ring, 0x00000000);
2489 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2490 amdgpu_ring_write(ring, 0x00000000);
2494 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2495 amdgpu_ring_write(ring, 0x00000000);
2498 amdgpu_ring_write(ring, 0x3a00161a);
2499 amdgpu_ring_write(ring, 0x0000002e);
2502 amdgpu_ring_write(ring, 0x00000000);
2503 amdgpu_ring_write(ring, 0x00000000);
2507 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2508 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2510 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2511 amdgpu_ring_write(ring, 0);
2513 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2514 amdgpu_ring_write(ring, 0x00000316);
2515 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2516 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2518 amdgpu_ring_commit(ring);
2524 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2526 * @adev: amdgpu_device pointer
2528 * Program the location and size of the gfx ring buffer
2529 * and test it to make sure it's working.
2530 * Returns 0 for success, error for failure.
2532 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2534 struct amdgpu_ring *ring;
2537 u64 rb_addr, rptr_addr;
2540 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2541 if (adev->asic_type != CHIP_HAWAII)
2542 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2544 /* Set the write pointer delay */
2545 WREG32(mmCP_RB_WPTR_DELAY, 0);
2547 /* set the RB to use vmid 0 */
2548 WREG32(mmCP_RB_VMID, 0);
2550 WREG32(mmSCRATCH_ADDR, 0);
2552 /* ring 0 - compute and gfx */
2553 /* Set ring buffer size */
2554 ring = &adev->gfx.gfx_ring[0];
2555 rb_bufsz = order_base_2(ring->ring_size / 8);
2556 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2558 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2560 WREG32(mmCP_RB0_CNTL, tmp);
2562 /* Initialize the ring buffer's read and write pointers */
2563 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2565 WREG32(mmCP_RB0_WPTR, ring->wptr);
2567 /* set the wb address wether it's enabled or not */
2568 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2569 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2570 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2572 /* scratch register shadowing is no longer supported */
2573 WREG32(mmSCRATCH_UMSK, 0);
2576 WREG32(mmCP_RB0_CNTL, tmp);
2578 rb_addr = ring->gpu_addr >> 8;
2579 WREG32(mmCP_RB0_BASE, rb_addr);
2580 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2582 /* start the ring */
2583 gfx_v7_0_cp_gfx_start(adev);
2585 r = amdgpu_ring_test_ring(ring);
2587 ring->ready = false;
2594 static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2596 return ring->adev->wb.wb[ring->rptr_offs];
2599 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2601 struct amdgpu_device *adev = ring->adev;
2603 return RREG32(mmCP_RB0_WPTR);
2606 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2608 struct amdgpu_device *adev = ring->adev;
2610 WREG32(mmCP_RB0_WPTR, ring->wptr);
2611 (void)RREG32(mmCP_RB0_WPTR);
2614 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2616 /* XXX check if swapping is necessary on BE */
2617 return ring->adev->wb.wb[ring->wptr_offs];
2620 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2622 struct amdgpu_device *adev = ring->adev;
2624 /* XXX check if swapping is necessary on BE */
2625 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2626 WDOORBELL32(ring->doorbell_index, ring->wptr);
2630 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2632 * @adev: amdgpu_device pointer
2633 * @enable: enable or disable the MEs
2635 * Halts or unhalts the compute MEs.
2637 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2642 WREG32(mmCP_MEC_CNTL, 0);
2644 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2645 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2646 adev->gfx.compute_ring[i].ready = false;
2652 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2654 * @adev: amdgpu_device pointer
2656 * Loads the compute MEC1&2 ucode.
2657 * Returns 0 for success, -EINVAL if the ucode is not available.
2659 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2661 const struct gfx_firmware_header_v1_0 *mec_hdr;
2662 const __le32 *fw_data;
2663 unsigned i, fw_size;
2665 if (!adev->gfx.mec_fw)
2668 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2669 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2670 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2671 adev->gfx.mec_feature_version = le32_to_cpu(
2672 mec_hdr->ucode_feature_version);
2674 gfx_v7_0_cp_compute_enable(adev, false);
2677 fw_data = (const __le32 *)
2678 (adev->gfx.mec_fw->data +
2679 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2680 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2681 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2682 for (i = 0; i < fw_size; i++)
2683 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2684 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2686 if (adev->asic_type == CHIP_KAVERI) {
2687 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2689 if (!adev->gfx.mec2_fw)
2692 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2693 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2694 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2695 adev->gfx.mec2_feature_version = le32_to_cpu(
2696 mec2_hdr->ucode_feature_version);
2699 fw_data = (const __le32 *)
2700 (adev->gfx.mec2_fw->data +
2701 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2702 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2703 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2704 for (i = 0; i < fw_size; i++)
2705 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2706 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2713 * gfx_v7_0_cp_compute_fini - stop the compute queues
2715 * @adev: amdgpu_device pointer
2717 * Stop the compute queues and tear down the driver queue
2720 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2724 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2725 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2727 if (ring->mqd_obj) {
2728 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2729 if (unlikely(r != 0))
2730 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2732 amdgpu_bo_unpin(ring->mqd_obj);
2733 amdgpu_bo_unreserve(ring->mqd_obj);
2735 amdgpu_bo_unref(&ring->mqd_obj);
2736 ring->mqd_obj = NULL;
2741 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2745 if (adev->gfx.mec.hpd_eop_obj) {
2746 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2747 if (unlikely(r != 0))
2748 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2749 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2750 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2752 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2753 adev->gfx.mec.hpd_eop_obj = NULL;
2757 #define MEC_HPD_SIZE 2048
2759 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2765 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2766 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2767 * Nonetheless, we assign only 1 pipe because all other pipes will
2770 adev->gfx.mec.num_mec = 1;
2771 adev->gfx.mec.num_pipe = 1;
2772 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2774 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2775 r = amdgpu_bo_create(adev,
2776 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2778 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2779 &adev->gfx.mec.hpd_eop_obj);
2781 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2786 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2787 if (unlikely(r != 0)) {
2788 gfx_v7_0_mec_fini(adev);
2791 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2792 &adev->gfx.mec.hpd_eop_gpu_addr);
2794 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2795 gfx_v7_0_mec_fini(adev);
2798 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2800 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2801 gfx_v7_0_mec_fini(adev);
2805 /* clear memory. Not sure if this is required or not */
2806 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2808 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2809 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2814 struct hqd_registers
2816 u32 cp_mqd_base_addr;
2817 u32 cp_mqd_base_addr_hi;
2820 u32 cp_hqd_persistent_state;
2821 u32 cp_hqd_pipe_priority;
2822 u32 cp_hqd_queue_priority;
2825 u32 cp_hqd_pq_base_hi;
2827 u32 cp_hqd_pq_rptr_report_addr;
2828 u32 cp_hqd_pq_rptr_report_addr_hi;
2829 u32 cp_hqd_pq_wptr_poll_addr;
2830 u32 cp_hqd_pq_wptr_poll_addr_hi;
2831 u32 cp_hqd_pq_doorbell_control;
2833 u32 cp_hqd_pq_control;
2834 u32 cp_hqd_ib_base_addr;
2835 u32 cp_hqd_ib_base_addr_hi;
2837 u32 cp_hqd_ib_control;
2838 u32 cp_hqd_iq_timer;
2840 u32 cp_hqd_dequeue_request;
2841 u32 cp_hqd_dma_offload;
2842 u32 cp_hqd_sema_cmd;
2843 u32 cp_hqd_msg_type;
2844 u32 cp_hqd_atomic0_preop_lo;
2845 u32 cp_hqd_atomic0_preop_hi;
2846 u32 cp_hqd_atomic1_preop_lo;
2847 u32 cp_hqd_atomic1_preop_hi;
2848 u32 cp_hqd_hq_scheduler0;
2849 u32 cp_hqd_hq_scheduler1;
2856 u32 dispatch_initiator;
2860 u32 pipeline_stat_enable;
2861 u32 perf_counter_enable;
2867 u32 resource_limits;
2868 u32 static_thread_mgmt01[2];
2870 u32 static_thread_mgmt23[2];
2872 u32 thread_trace_enable;
2875 u32 vgtcs_invoke_count[2];
2876 struct hqd_registers queue_state;
2878 u32 interrupt_queue[64];
2882 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2884 * @adev: amdgpu_device pointer
2886 * Program the compute queues and test them to make sure they
2888 * Returns 0 for success, error for failure.
2890 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2894 bool use_doorbell = true;
2900 struct bonaire_mqd *mqd;
2901 struct amdgpu_ring *ring;
2903 /* fix up chicken bits */
2904 tmp = RREG32(mmCP_CPF_DEBUG);
2906 WREG32(mmCP_CPF_DEBUG, tmp);
2908 /* init the pipes */
2909 mutex_lock(&adev->srbm_mutex);
2910 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2911 int me = (i < 4) ? 1 : 2;
2912 int pipe = (i < 4) ? i : (i - 4);
2914 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2916 cik_srbm_select(adev, me, pipe, 0, 0);
2918 /* write the EOP addr */
2919 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2920 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2922 /* set the VMID assigned */
2923 WREG32(mmCP_HPD_EOP_VMID, 0);
2925 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2926 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2927 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2928 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2929 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2931 cik_srbm_select(adev, 0, 0, 0, 0);
2932 mutex_unlock(&adev->srbm_mutex);
2934 /* init the queues. Just two for now. */
2935 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2936 ring = &adev->gfx.compute_ring[i];
2938 if (ring->mqd_obj == NULL) {
2939 r = amdgpu_bo_create(adev,
2940 sizeof(struct bonaire_mqd),
2942 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2945 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2950 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2951 if (unlikely(r != 0)) {
2952 gfx_v7_0_cp_compute_fini(adev);
2955 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2958 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2959 gfx_v7_0_cp_compute_fini(adev);
2962 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2964 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2965 gfx_v7_0_cp_compute_fini(adev);
2969 /* init the mqd struct */
2970 memset(buf, 0, sizeof(struct bonaire_mqd));
2972 mqd = (struct bonaire_mqd *)buf;
2973 mqd->header = 0xC0310800;
2974 mqd->static_thread_mgmt01[0] = 0xffffffff;
2975 mqd->static_thread_mgmt01[1] = 0xffffffff;
2976 mqd->static_thread_mgmt23[0] = 0xffffffff;
2977 mqd->static_thread_mgmt23[1] = 0xffffffff;
2979 mutex_lock(&adev->srbm_mutex);
2980 cik_srbm_select(adev, ring->me,
2984 /* disable wptr polling */
2985 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2986 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2987 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2989 /* enable doorbell? */
2990 mqd->queue_state.cp_hqd_pq_doorbell_control =
2991 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2993 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2995 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2996 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2997 mqd->queue_state.cp_hqd_pq_doorbell_control);
2999 /* disable the queue if it's active */
3000 mqd->queue_state.cp_hqd_dequeue_request = 0;
3001 mqd->queue_state.cp_hqd_pq_rptr = 0;
3002 mqd->queue_state.cp_hqd_pq_wptr= 0;
3003 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3004 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3005 for (j = 0; j < adev->usec_timeout; j++) {
3006 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3010 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3011 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3012 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3015 /* set the pointer to the MQD */
3016 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3017 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3018 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3019 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3020 /* set MQD vmid to 0 */
3021 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3022 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3023 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3025 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3026 hqd_gpu_addr = ring->gpu_addr >> 8;
3027 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3028 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3029 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3030 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3032 /* set up the HQD, this is similar to CP_RB0_CNTL */
3033 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3034 mqd->queue_state.cp_hqd_pq_control &=
3035 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3036 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3038 mqd->queue_state.cp_hqd_pq_control |=
3039 order_base_2(ring->ring_size / 8);
3040 mqd->queue_state.cp_hqd_pq_control |=
3041 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3043 mqd->queue_state.cp_hqd_pq_control |=
3044 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
3046 mqd->queue_state.cp_hqd_pq_control &=
3047 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3048 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3049 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3050 mqd->queue_state.cp_hqd_pq_control |=
3051 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3052 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3053 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3055 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3056 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3057 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3058 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3059 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3060 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3061 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3063 /* set the wb address wether it's enabled or not */
3064 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3065 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3066 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3067 upper_32_bits(wb_gpu_addr) & 0xffff;
3068 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3069 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3070 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3071 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3073 /* enable the doorbell if requested */
3075 mqd->queue_state.cp_hqd_pq_doorbell_control =
3076 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3077 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3078 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3079 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3080 (ring->doorbell_index <<
3081 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3082 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3083 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3084 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3085 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3086 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3089 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3091 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3092 mqd->queue_state.cp_hqd_pq_doorbell_control);
3094 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3096 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3097 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3098 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3100 /* set the vmid for the queue */
3101 mqd->queue_state.cp_hqd_vmid = 0;
3102 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3104 /* activate the queue */
3105 mqd->queue_state.cp_hqd_active = 1;
3106 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3108 cik_srbm_select(adev, 0, 0, 0, 0);
3109 mutex_unlock(&adev->srbm_mutex);
3111 amdgpu_bo_kunmap(ring->mqd_obj);
3112 amdgpu_bo_unreserve(ring->mqd_obj);
3117 gfx_v7_0_cp_compute_enable(adev, true);
3119 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3120 ring = &adev->gfx.compute_ring[i];
3122 r = amdgpu_ring_test_ring(ring);
3124 ring->ready = false;
3130 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3132 gfx_v7_0_cp_gfx_enable(adev, enable);
3133 gfx_v7_0_cp_compute_enable(adev, enable);
3136 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3140 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3143 r = gfx_v7_0_cp_compute_load_microcode(adev);
3150 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3153 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3156 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3157 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3159 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3160 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3161 WREG32(mmCP_INT_CNTL_RING0, tmp);
3164 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3168 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3170 r = gfx_v7_0_cp_load_microcode(adev);
3174 r = gfx_v7_0_cp_gfx_resume(adev);
3177 r = gfx_v7_0_cp_compute_resume(adev);
3181 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3187 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3189 * @ring: the ring to emmit the commands to
3191 * Sync the command pipeline with the PFP. E.g. wait for everything
3194 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3196 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3197 uint32_t seq = ring->fence_drv.sync_seq;
3198 uint64_t addr = ring->fence_drv.gpu_addr;
3200 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3201 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3202 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3203 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3204 amdgpu_ring_write(ring, addr & 0xfffffffc);
3205 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3206 amdgpu_ring_write(ring, seq);
3207 amdgpu_ring_write(ring, 0xffffffff);
3208 amdgpu_ring_write(ring, 4); /* poll interval */
3211 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3212 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3213 amdgpu_ring_write(ring, 0);
3214 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3215 amdgpu_ring_write(ring, 0);
3221 * VMID 0 is the physical GPU addresses as used by the kernel.
3222 * VMIDs 1-15 are used for userspace clients and are handled
3223 * by the amdgpu vm/hsa code.
3226 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3228 * @adev: amdgpu_device pointer
3230 * Update the page table base and flush the VM TLB
3231 * using the CP (CIK).
3233 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3234 unsigned vm_id, uint64_t pd_addr)
3236 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3238 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3239 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3240 WRITE_DATA_DST_SEL(0)));
3242 amdgpu_ring_write(ring,
3243 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3245 amdgpu_ring_write(ring,
3246 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3248 amdgpu_ring_write(ring, 0);
3249 amdgpu_ring_write(ring, pd_addr >> 12);
3251 /* bits 0-15 are the VM contexts0-15 */
3252 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3253 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3254 WRITE_DATA_DST_SEL(0)));
3255 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3256 amdgpu_ring_write(ring, 0);
3257 amdgpu_ring_write(ring, 1 << vm_id);
3259 /* wait for the invalidate to complete */
3260 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3261 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3262 WAIT_REG_MEM_FUNCTION(0) | /* always */
3263 WAIT_REG_MEM_ENGINE(0))); /* me */
3264 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3265 amdgpu_ring_write(ring, 0);
3266 amdgpu_ring_write(ring, 0); /* ref */
3267 amdgpu_ring_write(ring, 0); /* mask */
3268 amdgpu_ring_write(ring, 0x20); /* poll interval */
3270 /* compute doesn't have PFP */
3272 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3273 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3274 amdgpu_ring_write(ring, 0x0);
3276 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3277 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3278 amdgpu_ring_write(ring, 0);
3279 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3280 amdgpu_ring_write(ring, 0);
3286 * The RLC is a multi-purpose microengine that handles a
3287 * variety of functions.
3289 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3293 /* save restore block */
3294 if (adev->gfx.rlc.save_restore_obj) {
3295 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3296 if (unlikely(r != 0))
3297 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3298 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3299 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3301 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3302 adev->gfx.rlc.save_restore_obj = NULL;
3305 /* clear state block */
3306 if (adev->gfx.rlc.clear_state_obj) {
3307 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3308 if (unlikely(r != 0))
3309 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3310 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3311 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3313 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3314 adev->gfx.rlc.clear_state_obj = NULL;
3317 /* clear state block */
3318 if (adev->gfx.rlc.cp_table_obj) {
3319 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3320 if (unlikely(r != 0))
3321 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3322 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3323 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3325 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3326 adev->gfx.rlc.cp_table_obj = NULL;
3330 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3333 volatile u32 *dst_ptr;
3335 const struct cs_section_def *cs_data;
3338 /* allocate rlc buffers */
3339 if (adev->flags & AMD_IS_APU) {
3340 if (adev->asic_type == CHIP_KAVERI) {
3341 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3342 adev->gfx.rlc.reg_list_size =
3343 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3345 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3346 adev->gfx.rlc.reg_list_size =
3347 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3350 adev->gfx.rlc.cs_data = ci_cs_data;
3351 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3352 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3354 src_ptr = adev->gfx.rlc.reg_list;
3355 dws = adev->gfx.rlc.reg_list_size;
3356 dws += (5 * 16) + 48 + 48 + 64;
3358 cs_data = adev->gfx.rlc.cs_data;
3361 /* save restore block */
3362 if (adev->gfx.rlc.save_restore_obj == NULL) {
3363 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3364 AMDGPU_GEM_DOMAIN_VRAM,
3365 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3367 &adev->gfx.rlc.save_restore_obj);
3369 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3374 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3375 if (unlikely(r != 0)) {
3376 gfx_v7_0_rlc_fini(adev);
3379 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3380 &adev->gfx.rlc.save_restore_gpu_addr);
3382 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3383 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3384 gfx_v7_0_rlc_fini(adev);
3388 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3390 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3391 gfx_v7_0_rlc_fini(adev);
3394 /* write the sr buffer */
3395 dst_ptr = adev->gfx.rlc.sr_ptr;
3396 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3397 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3398 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3399 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3403 /* clear state block */
3404 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3406 if (adev->gfx.rlc.clear_state_obj == NULL) {
3407 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3408 AMDGPU_GEM_DOMAIN_VRAM,
3409 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3411 &adev->gfx.rlc.clear_state_obj);
3413 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3414 gfx_v7_0_rlc_fini(adev);
3418 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3419 if (unlikely(r != 0)) {
3420 gfx_v7_0_rlc_fini(adev);
3423 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3424 &adev->gfx.rlc.clear_state_gpu_addr);
3426 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3427 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3428 gfx_v7_0_rlc_fini(adev);
3432 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3434 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3435 gfx_v7_0_rlc_fini(adev);
3438 /* set up the cs buffer */
3439 dst_ptr = adev->gfx.rlc.cs_ptr;
3440 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3441 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3442 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3445 if (adev->gfx.rlc.cp_table_size) {
3446 if (adev->gfx.rlc.cp_table_obj == NULL) {
3447 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3448 AMDGPU_GEM_DOMAIN_VRAM,
3449 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3451 &adev->gfx.rlc.cp_table_obj);
3453 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3454 gfx_v7_0_rlc_fini(adev);
3459 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3460 if (unlikely(r != 0)) {
3461 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3462 gfx_v7_0_rlc_fini(adev);
3465 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3466 &adev->gfx.rlc.cp_table_gpu_addr);
3468 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3469 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3470 gfx_v7_0_rlc_fini(adev);
3473 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3475 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3476 gfx_v7_0_rlc_fini(adev);
3480 gfx_v7_0_init_cp_pg_table(adev);
3482 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3483 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3490 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3494 tmp = RREG32(mmRLC_LB_CNTL);
3496 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3498 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3499 WREG32(mmRLC_LB_CNTL, tmp);
3502 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3507 mutex_lock(&adev->grbm_idx_mutex);
3508 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3509 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3510 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3511 for (k = 0; k < adev->usec_timeout; k++) {
3512 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3518 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3519 mutex_unlock(&adev->grbm_idx_mutex);
3521 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3522 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3523 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3524 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3525 for (k = 0; k < adev->usec_timeout; k++) {
3526 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3532 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3536 tmp = RREG32(mmRLC_CNTL);
3538 WREG32(mmRLC_CNTL, rlc);
3541 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3545 orig = data = RREG32(mmRLC_CNTL);
3547 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3550 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3551 WREG32(mmRLC_CNTL, data);
3553 for (i = 0; i < adev->usec_timeout; i++) {
3554 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3559 gfx_v7_0_wait_for_rlc_serdes(adev);
3565 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3569 tmp = 0x1 | (1 << 1);
3570 WREG32(mmRLC_GPR_REG2, tmp);
3572 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3573 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3574 for (i = 0; i < adev->usec_timeout; i++) {
3575 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3580 for (i = 0; i < adev->usec_timeout; i++) {
3581 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3587 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3591 tmp = 0x1 | (0 << 1);
3592 WREG32(mmRLC_GPR_REG2, tmp);
3596 * gfx_v7_0_rlc_stop - stop the RLC ME
3598 * @adev: amdgpu_device pointer
3600 * Halt the RLC ME (MicroEngine) (CIK).
3602 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3604 WREG32(mmRLC_CNTL, 0);
3606 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3608 gfx_v7_0_wait_for_rlc_serdes(adev);
3612 * gfx_v7_0_rlc_start - start the RLC ME
3614 * @adev: amdgpu_device pointer
3616 * Unhalt the RLC ME (MicroEngine) (CIK).
3618 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3620 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3622 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3627 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3629 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3631 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3632 WREG32(mmGRBM_SOFT_RESET, tmp);
3634 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3635 WREG32(mmGRBM_SOFT_RESET, tmp);
3640 * gfx_v7_0_rlc_resume - setup the RLC hw
3642 * @adev: amdgpu_device pointer
3644 * Initialize the RLC registers, load the ucode,
3645 * and start the RLC (CIK).
3646 * Returns 0 for success, -EINVAL if the ucode is not available.
3648 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3650 const struct rlc_firmware_header_v1_0 *hdr;
3651 const __le32 *fw_data;
3652 unsigned i, fw_size;
3655 if (!adev->gfx.rlc_fw)
3658 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3659 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3660 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3661 adev->gfx.rlc_feature_version = le32_to_cpu(
3662 hdr->ucode_feature_version);
3664 gfx_v7_0_rlc_stop(adev);
3667 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3668 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3670 gfx_v7_0_rlc_reset(adev);
3672 gfx_v7_0_init_pg(adev);
3674 WREG32(mmRLC_LB_CNTR_INIT, 0);
3675 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3677 mutex_lock(&adev->grbm_idx_mutex);
3678 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3679 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3680 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3681 WREG32(mmRLC_LB_CNTL, 0x80000004);
3682 mutex_unlock(&adev->grbm_idx_mutex);
3684 WREG32(mmRLC_MC_CNTL, 0);
3685 WREG32(mmRLC_UCODE_CNTL, 0);
3687 fw_data = (const __le32 *)
3688 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3689 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3690 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3691 for (i = 0; i < fw_size; i++)
3692 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3693 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3695 /* XXX - find out what chips support lbpw */
3696 gfx_v7_0_enable_lbpw(adev, false);
3698 if (adev->asic_type == CHIP_BONAIRE)
3699 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3701 gfx_v7_0_rlc_start(adev);
3706 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3708 u32 data, orig, tmp, tmp2;
3710 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3712 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3713 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3715 tmp = gfx_v7_0_halt_rlc(adev);
3717 mutex_lock(&adev->grbm_idx_mutex);
3718 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3719 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3720 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3721 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3722 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3723 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3724 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3725 mutex_unlock(&adev->grbm_idx_mutex);
3727 gfx_v7_0_update_rlc(adev, tmp);
3729 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3731 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3733 RREG32(mmCB_CGTT_SCLK_CTRL);
3734 RREG32(mmCB_CGTT_SCLK_CTRL);
3735 RREG32(mmCB_CGTT_SCLK_CTRL);
3736 RREG32(mmCB_CGTT_SCLK_CTRL);
3738 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3742 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3746 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3748 u32 data, orig, tmp = 0;
3750 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3751 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3752 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3753 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3754 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3756 WREG32(mmCP_MEM_SLP_CNTL, data);
3760 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3764 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3766 tmp = gfx_v7_0_halt_rlc(adev);
3768 mutex_lock(&adev->grbm_idx_mutex);
3769 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3770 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3771 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3772 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3773 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3774 WREG32(mmRLC_SERDES_WR_CTRL, data);
3775 mutex_unlock(&adev->grbm_idx_mutex);
3777 gfx_v7_0_update_rlc(adev, tmp);
3779 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3780 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3781 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3782 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3783 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3784 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3785 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3786 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3787 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3788 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3789 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3790 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3792 WREG32(mmCGTS_SM_CTRL_REG, data);
3795 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3798 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3800 data = RREG32(mmRLC_MEM_SLP_CNTL);
3801 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3802 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3803 WREG32(mmRLC_MEM_SLP_CNTL, data);
3806 data = RREG32(mmCP_MEM_SLP_CNTL);
3807 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3808 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3809 WREG32(mmCP_MEM_SLP_CNTL, data);
3812 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3813 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3815 WREG32(mmCGTS_SM_CTRL_REG, data);
3817 tmp = gfx_v7_0_halt_rlc(adev);
3819 mutex_lock(&adev->grbm_idx_mutex);
3820 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3821 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3822 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3823 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3824 WREG32(mmRLC_SERDES_WR_CTRL, data);
3825 mutex_unlock(&adev->grbm_idx_mutex);
3827 gfx_v7_0_update_rlc(adev, tmp);
3831 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3834 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3835 /* order matters! */
3837 gfx_v7_0_enable_mgcg(adev, true);
3838 gfx_v7_0_enable_cgcg(adev, true);
3840 gfx_v7_0_enable_cgcg(adev, false);
3841 gfx_v7_0_enable_mgcg(adev, false);
3843 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3846 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3851 orig = data = RREG32(mmRLC_PG_CNTL);
3852 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3853 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3855 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3857 WREG32(mmRLC_PG_CNTL, data);
3860 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3865 orig = data = RREG32(mmRLC_PG_CNTL);
3866 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3867 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3869 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3871 WREG32(mmRLC_PG_CNTL, data);
3874 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3878 orig = data = RREG32(mmRLC_PG_CNTL);
3879 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3884 WREG32(mmRLC_PG_CNTL, data);
3887 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3891 orig = data = RREG32(mmRLC_PG_CNTL);
3892 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3897 WREG32(mmRLC_PG_CNTL, data);
3900 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3902 const __le32 *fw_data;
3903 volatile u32 *dst_ptr;
3904 int me, i, max_me = 4;
3906 u32 table_offset, table_size;
3908 if (adev->asic_type == CHIP_KAVERI)
3911 if (adev->gfx.rlc.cp_table_ptr == NULL)
3914 /* write the cp table buffer */
3915 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3916 for (me = 0; me < max_me; me++) {
3918 const struct gfx_firmware_header_v1_0 *hdr =
3919 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3920 fw_data = (const __le32 *)
3921 (adev->gfx.ce_fw->data +
3922 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3923 table_offset = le32_to_cpu(hdr->jt_offset);
3924 table_size = le32_to_cpu(hdr->jt_size);
3925 } else if (me == 1) {
3926 const struct gfx_firmware_header_v1_0 *hdr =
3927 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3928 fw_data = (const __le32 *)
3929 (adev->gfx.pfp_fw->data +
3930 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3931 table_offset = le32_to_cpu(hdr->jt_offset);
3932 table_size = le32_to_cpu(hdr->jt_size);
3933 } else if (me == 2) {
3934 const struct gfx_firmware_header_v1_0 *hdr =
3935 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3936 fw_data = (const __le32 *)
3937 (adev->gfx.me_fw->data +
3938 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3939 table_offset = le32_to_cpu(hdr->jt_offset);
3940 table_size = le32_to_cpu(hdr->jt_size);
3941 } else if (me == 3) {
3942 const struct gfx_firmware_header_v1_0 *hdr =
3943 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3944 fw_data = (const __le32 *)
3945 (adev->gfx.mec_fw->data +
3946 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3947 table_offset = le32_to_cpu(hdr->jt_offset);
3948 table_size = le32_to_cpu(hdr->jt_size);
3950 const struct gfx_firmware_header_v1_0 *hdr =
3951 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3952 fw_data = (const __le32 *)
3953 (adev->gfx.mec2_fw->data +
3954 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3955 table_offset = le32_to_cpu(hdr->jt_offset);
3956 table_size = le32_to_cpu(hdr->jt_size);
3959 for (i = 0; i < table_size; i ++) {
3960 dst_ptr[bo_offset + i] =
3961 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3964 bo_offset += table_size;
3968 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3973 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3974 orig = data = RREG32(mmRLC_PG_CNTL);
3975 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3977 WREG32(mmRLC_PG_CNTL, data);
3979 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3980 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3982 WREG32(mmRLC_AUTO_PG_CTRL, data);
3984 orig = data = RREG32(mmRLC_PG_CNTL);
3985 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3987 WREG32(mmRLC_PG_CNTL, data);
3989 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3990 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3992 WREG32(mmRLC_AUTO_PG_CTRL, data);
3994 data = RREG32(mmDB_RENDER_CONTROL);
3998 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4006 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4007 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4009 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
4012 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4016 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4017 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4019 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4020 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4022 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
4024 return (~data) & mask;
4027 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4031 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4033 tmp = RREG32(mmRLC_MAX_PG_CU);
4034 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
4035 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
4036 WREG32(mmRLC_MAX_PG_CU, tmp);
4039 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4044 orig = data = RREG32(mmRLC_PG_CNTL);
4045 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
4046 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4048 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4050 WREG32(mmRLC_PG_CNTL, data);
4053 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4058 orig = data = RREG32(mmRLC_PG_CNTL);
4059 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
4060 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4062 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4064 WREG32(mmRLC_PG_CNTL, data);
4067 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4068 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4070 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4075 if (adev->gfx.rlc.cs_data) {
4076 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4077 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4078 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4079 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4081 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4082 for (i = 0; i < 3; i++)
4083 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4085 if (adev->gfx.rlc.reg_list) {
4086 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4087 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4088 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4091 orig = data = RREG32(mmRLC_PG_CNTL);
4092 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4094 WREG32(mmRLC_PG_CNTL, data);
4096 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4097 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4099 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4100 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4101 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4102 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4105 WREG32(mmRLC_PG_DELAY, data);
4107 data = RREG32(mmRLC_PG_DELAY_2);
4110 WREG32(mmRLC_PG_DELAY_2, data);
4112 data = RREG32(mmRLC_AUTO_PG_CTRL);
4113 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4114 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4115 WREG32(mmRLC_AUTO_PG_CTRL, data);
4119 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4121 gfx_v7_0_enable_gfx_cgpg(adev, enable);
4122 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4123 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4126 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4129 const struct cs_section_def *sect = NULL;
4130 const struct cs_extent_def *ext = NULL;
4132 if (adev->gfx.rlc.cs_data == NULL)
4135 /* begin clear state */
4137 /* context control state */
4140 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4141 for (ext = sect->section; ext->extent != NULL; ++ext) {
4142 if (sect->id == SECT_CONTEXT)
4143 count += 2 + ext->reg_count;
4148 /* pa_sc_raster_config/pa_sc_raster_config1 */
4150 /* end clear state */
4158 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4159 volatile u32 *buffer)
4162 const struct cs_section_def *sect = NULL;
4163 const struct cs_extent_def *ext = NULL;
4165 if (adev->gfx.rlc.cs_data == NULL)
4170 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4171 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4173 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4174 buffer[count++] = cpu_to_le32(0x80000000);
4175 buffer[count++] = cpu_to_le32(0x80000000);
4177 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4178 for (ext = sect->section; ext->extent != NULL; ++ext) {
4179 if (sect->id == SECT_CONTEXT) {
4181 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4182 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4183 for (i = 0; i < ext->reg_count; i++)
4184 buffer[count++] = cpu_to_le32(ext->extent[i]);
4191 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4192 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4193 switch (adev->asic_type) {
4195 buffer[count++] = cpu_to_le32(0x16000012);
4196 buffer[count++] = cpu_to_le32(0x00000000);
4199 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4200 buffer[count++] = cpu_to_le32(0x00000000);
4204 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4205 buffer[count++] = cpu_to_le32(0x00000000);
4208 buffer[count++] = cpu_to_le32(0x3a00161a);
4209 buffer[count++] = cpu_to_le32(0x0000002e);
4212 buffer[count++] = cpu_to_le32(0x00000000);
4213 buffer[count++] = cpu_to_le32(0x00000000);
4217 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4218 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4220 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4221 buffer[count++] = cpu_to_le32(0);
4224 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4226 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4227 AMD_PG_SUPPORT_GFX_SMG |
4228 AMD_PG_SUPPORT_GFX_DMG |
4230 AMD_PG_SUPPORT_GDS |
4231 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4232 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4233 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4234 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4235 gfx_v7_0_init_gfx_cgpg(adev);
4236 gfx_v7_0_enable_cp_pg(adev, true);
4237 gfx_v7_0_enable_gds_pg(adev, true);
4239 gfx_v7_0_init_ao_cu_mask(adev);
4240 gfx_v7_0_update_gfx_pg(adev, true);
4244 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4246 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4247 AMD_PG_SUPPORT_GFX_SMG |
4248 AMD_PG_SUPPORT_GFX_DMG |
4250 AMD_PG_SUPPORT_GDS |
4251 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4252 gfx_v7_0_update_gfx_pg(adev, false);
4253 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4254 gfx_v7_0_enable_cp_pg(adev, false);
4255 gfx_v7_0_enable_gds_pg(adev, false);
4261 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4263 * @adev: amdgpu_device pointer
4265 * Fetches a GPU clock counter snapshot (SI).
4266 * Returns the 64 bit clock counter snapshot.
4268 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4272 mutex_lock(&adev->gfx.gpu_clock_mutex);
4273 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4274 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4275 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4276 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4280 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4282 uint32_t gds_base, uint32_t gds_size,
4283 uint32_t gws_base, uint32_t gws_size,
4284 uint32_t oa_base, uint32_t oa_size)
4286 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4287 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4289 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4290 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4292 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4293 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4296 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4297 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4298 WRITE_DATA_DST_SEL(0)));
4299 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4300 amdgpu_ring_write(ring, 0);
4301 amdgpu_ring_write(ring, gds_base);
4304 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4305 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4306 WRITE_DATA_DST_SEL(0)));
4307 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4308 amdgpu_ring_write(ring, 0);
4309 amdgpu_ring_write(ring, gds_size);
4312 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4313 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4314 WRITE_DATA_DST_SEL(0)));
4315 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4316 amdgpu_ring_write(ring, 0);
4317 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4320 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4321 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4322 WRITE_DATA_DST_SEL(0)));
4323 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4324 amdgpu_ring_write(ring, 0);
4325 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4328 static unsigned gfx_v7_0_ring_get_emit_ib_size_gfx(struct amdgpu_ring *ring)
4331 4; /* gfx_v7_0_ring_emit_ib_gfx */
4334 static unsigned gfx_v7_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
4337 20 + /* gfx_v7_0_ring_emit_gds_switch */
4338 7 + /* gfx_v7_0_ring_emit_hdp_flush */
4339 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
4340 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
4341 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
4342 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
4343 3; /* gfx_v7_ring_emit_cntxcntl */
4346 static unsigned gfx_v7_0_ring_get_emit_ib_size_compute(struct amdgpu_ring *ring)
4349 4; /* gfx_v7_0_ring_emit_ib_compute */
4352 static unsigned gfx_v7_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring)
4355 20 + /* gfx_v7_0_ring_emit_gds_switch */
4356 7 + /* gfx_v7_0_ring_emit_hdp_flush */
4357 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
4358 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
4359 17 + /* gfx_v7_0_ring_emit_vm_flush */
4360 7 + 7 + 7; /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
4363 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4364 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4365 .select_se_sh = &gfx_v7_0_select_se_sh,
4368 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4369 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4370 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4373 static int gfx_v7_0_early_init(void *handle)
4375 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4377 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4378 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4379 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4380 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4381 gfx_v7_0_set_ring_funcs(adev);
4382 gfx_v7_0_set_irq_funcs(adev);
4383 gfx_v7_0_set_gds_init(adev);
4388 static int gfx_v7_0_late_init(void *handle)
4390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4393 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4397 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4404 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4407 u32 mc_shared_chmap, mc_arb_ramcfg;
4408 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4411 switch (adev->asic_type) {
4413 adev->gfx.config.max_shader_engines = 2;
4414 adev->gfx.config.max_tile_pipes = 4;
4415 adev->gfx.config.max_cu_per_sh = 7;
4416 adev->gfx.config.max_sh_per_se = 1;
4417 adev->gfx.config.max_backends_per_se = 2;
4418 adev->gfx.config.max_texture_channel_caches = 4;
4419 adev->gfx.config.max_gprs = 256;
4420 adev->gfx.config.max_gs_threads = 32;
4421 adev->gfx.config.max_hw_contexts = 8;
4423 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4424 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4425 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4426 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4427 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4430 adev->gfx.config.max_shader_engines = 4;
4431 adev->gfx.config.max_tile_pipes = 16;
4432 adev->gfx.config.max_cu_per_sh = 11;
4433 adev->gfx.config.max_sh_per_se = 1;
4434 adev->gfx.config.max_backends_per_se = 4;
4435 adev->gfx.config.max_texture_channel_caches = 16;
4436 adev->gfx.config.max_gprs = 256;
4437 adev->gfx.config.max_gs_threads = 32;
4438 adev->gfx.config.max_hw_contexts = 8;
4440 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4441 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4442 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4443 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4444 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4447 adev->gfx.config.max_shader_engines = 1;
4448 adev->gfx.config.max_tile_pipes = 4;
4449 adev->gfx.config.max_cu_per_sh = 8;
4450 adev->gfx.config.max_backends_per_se = 2;
4451 adev->gfx.config.max_sh_per_se = 1;
4452 adev->gfx.config.max_texture_channel_caches = 4;
4453 adev->gfx.config.max_gprs = 256;
4454 adev->gfx.config.max_gs_threads = 16;
4455 adev->gfx.config.max_hw_contexts = 8;
4457 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4458 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4459 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4460 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4461 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4466 adev->gfx.config.max_shader_engines = 1;
4467 adev->gfx.config.max_tile_pipes = 2;
4468 adev->gfx.config.max_cu_per_sh = 2;
4469 adev->gfx.config.max_sh_per_se = 1;
4470 adev->gfx.config.max_backends_per_se = 1;
4471 adev->gfx.config.max_texture_channel_caches = 2;
4472 adev->gfx.config.max_gprs = 256;
4473 adev->gfx.config.max_gs_threads = 16;
4474 adev->gfx.config.max_hw_contexts = 8;
4476 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4477 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4478 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4479 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4480 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4484 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4485 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4486 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4488 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4489 adev->gfx.config.mem_max_burst_length_bytes = 256;
4490 if (adev->flags & AMD_IS_APU) {
4491 /* Get memory bank mapping mode. */
4492 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4493 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4494 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4496 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4497 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4498 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4500 /* Validate settings in case only one DIMM installed. */
4501 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4502 dimm00_addr_map = 0;
4503 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4504 dimm01_addr_map = 0;
4505 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4506 dimm10_addr_map = 0;
4507 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4508 dimm11_addr_map = 0;
4510 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4511 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4512 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4513 adev->gfx.config.mem_row_size_in_kb = 2;
4515 adev->gfx.config.mem_row_size_in_kb = 1;
4517 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4518 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4519 if (adev->gfx.config.mem_row_size_in_kb > 4)
4520 adev->gfx.config.mem_row_size_in_kb = 4;
4522 /* XXX use MC settings? */
4523 adev->gfx.config.shader_engine_tile_size = 32;
4524 adev->gfx.config.num_gpus = 1;
4525 adev->gfx.config.multi_gpu_tile_size = 64;
4527 /* fix up row size */
4528 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4529 switch (adev->gfx.config.mem_row_size_in_kb) {
4532 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4535 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4538 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4541 adev->gfx.config.gb_addr_config = gb_addr_config;
4544 static int gfx_v7_0_sw_init(void *handle)
4546 struct amdgpu_ring *ring;
4547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4551 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4555 /* Privileged reg */
4556 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4560 /* Privileged inst */
4561 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4565 gfx_v7_0_scratch_init(adev);
4567 r = gfx_v7_0_init_microcode(adev);
4569 DRM_ERROR("Failed to load gfx firmware!\n");
4573 r = gfx_v7_0_rlc_init(adev);
4575 DRM_ERROR("Failed to init rlc BOs!\n");
4579 /* allocate mec buffers */
4580 r = gfx_v7_0_mec_init(adev);
4582 DRM_ERROR("Failed to init MEC BOs!\n");
4586 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4587 ring = &adev->gfx.gfx_ring[i];
4588 ring->ring_obj = NULL;
4589 sprintf(ring->name, "gfx");
4590 r = amdgpu_ring_init(adev, ring, 1024,
4591 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4592 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4593 AMDGPU_RING_TYPE_GFX);
4598 /* set up the compute queues */
4599 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4602 /* max 32 queues per MEC */
4603 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4604 DRM_ERROR("Too many (%d) compute rings!\n", i);
4607 ring = &adev->gfx.compute_ring[i];
4608 ring->ring_obj = NULL;
4609 ring->use_doorbell = true;
4610 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4611 ring->me = 1; /* first MEC */
4613 ring->queue = i % 8;
4614 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4615 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4616 /* type-2 packets are deprecated on MEC, use type-3 instead */
4617 r = amdgpu_ring_init(adev, ring, 1024,
4618 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4619 &adev->gfx.eop_irq, irq_type,
4620 AMDGPU_RING_TYPE_COMPUTE);
4625 /* reserve GDS, GWS and OA resource for gfx */
4626 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4627 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4628 &adev->gds.gds_gfx_bo, NULL, NULL);
4632 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4633 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4634 &adev->gds.gws_gfx_bo, NULL, NULL);
4638 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4639 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4640 &adev->gds.oa_gfx_bo, NULL, NULL);
4644 adev->gfx.ce_ram_size = 0x8000;
4646 gfx_v7_0_gpu_early_init(adev);
4651 static int gfx_v7_0_sw_fini(void *handle)
4654 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4656 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4657 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4658 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4660 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4661 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4662 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4663 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4665 gfx_v7_0_cp_compute_fini(adev);
4666 gfx_v7_0_rlc_fini(adev);
4667 gfx_v7_0_mec_fini(adev);
4668 gfx_v7_0_free_microcode(adev);
4673 static int gfx_v7_0_hw_init(void *handle)
4676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4678 gfx_v7_0_gpu_init(adev);
4681 r = gfx_v7_0_rlc_resume(adev);
4685 r = gfx_v7_0_cp_resume(adev);
4692 static int gfx_v7_0_hw_fini(void *handle)
4694 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4696 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4697 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4698 gfx_v7_0_cp_enable(adev, false);
4699 gfx_v7_0_rlc_stop(adev);
4700 gfx_v7_0_fini_pg(adev);
4705 static int gfx_v7_0_suspend(void *handle)
4707 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4709 return gfx_v7_0_hw_fini(adev);
4712 static int gfx_v7_0_resume(void *handle)
4714 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4716 return gfx_v7_0_hw_init(adev);
4719 static bool gfx_v7_0_is_idle(void *handle)
4721 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4723 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4729 static int gfx_v7_0_wait_for_idle(void *handle)
4733 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4735 for (i = 0; i < adev->usec_timeout; i++) {
4736 /* read MC_STATUS */
4737 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4746 static int gfx_v7_0_soft_reset(void *handle)
4748 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4750 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4753 tmp = RREG32(mmGRBM_STATUS);
4754 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4755 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4756 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4757 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4758 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4759 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4760 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4761 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4763 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4764 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4765 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4769 tmp = RREG32(mmGRBM_STATUS2);
4770 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4771 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4774 tmp = RREG32(mmSRBM_STATUS);
4775 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4776 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4778 if (grbm_soft_reset || srbm_soft_reset) {
4780 gfx_v7_0_fini_pg(adev);
4781 gfx_v7_0_update_cg(adev, false);
4784 gfx_v7_0_rlc_stop(adev);
4786 /* Disable GFX parsing/prefetching */
4787 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4789 /* Disable MEC parsing/prefetching */
4790 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4792 if (grbm_soft_reset) {
4793 tmp = RREG32(mmGRBM_SOFT_RESET);
4794 tmp |= grbm_soft_reset;
4795 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4796 WREG32(mmGRBM_SOFT_RESET, tmp);
4797 tmp = RREG32(mmGRBM_SOFT_RESET);
4801 tmp &= ~grbm_soft_reset;
4802 WREG32(mmGRBM_SOFT_RESET, tmp);
4803 tmp = RREG32(mmGRBM_SOFT_RESET);
4806 if (srbm_soft_reset) {
4807 tmp = RREG32(mmSRBM_SOFT_RESET);
4808 tmp |= srbm_soft_reset;
4809 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4810 WREG32(mmSRBM_SOFT_RESET, tmp);
4811 tmp = RREG32(mmSRBM_SOFT_RESET);
4815 tmp &= ~srbm_soft_reset;
4816 WREG32(mmSRBM_SOFT_RESET, tmp);
4817 tmp = RREG32(mmSRBM_SOFT_RESET);
4819 /* Wait a little for things to settle down */
4825 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4826 enum amdgpu_interrupt_state state)
4831 case AMDGPU_IRQ_STATE_DISABLE:
4832 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4833 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4834 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4836 case AMDGPU_IRQ_STATE_ENABLE:
4837 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4838 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4839 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4846 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4848 enum amdgpu_interrupt_state state)
4850 u32 mec_int_cntl, mec_int_cntl_reg;
4853 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4854 * handles the setting of interrupts for this specific pipe. All other
4855 * pipes' interrupts are set by amdkfd.
4861 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4864 DRM_DEBUG("invalid pipe %d\n", pipe);
4868 DRM_DEBUG("invalid me %d\n", me);
4873 case AMDGPU_IRQ_STATE_DISABLE:
4874 mec_int_cntl = RREG32(mec_int_cntl_reg);
4875 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4876 WREG32(mec_int_cntl_reg, mec_int_cntl);
4878 case AMDGPU_IRQ_STATE_ENABLE:
4879 mec_int_cntl = RREG32(mec_int_cntl_reg);
4880 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4881 WREG32(mec_int_cntl_reg, mec_int_cntl);
4888 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4889 struct amdgpu_irq_src *src,
4891 enum amdgpu_interrupt_state state)
4896 case AMDGPU_IRQ_STATE_DISABLE:
4897 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4898 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4899 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4901 case AMDGPU_IRQ_STATE_ENABLE:
4902 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4903 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4904 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4913 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4914 struct amdgpu_irq_src *src,
4916 enum amdgpu_interrupt_state state)
4921 case AMDGPU_IRQ_STATE_DISABLE:
4922 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4923 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4924 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4926 case AMDGPU_IRQ_STATE_ENABLE:
4927 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4928 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4929 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4938 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4939 struct amdgpu_irq_src *src,
4941 enum amdgpu_interrupt_state state)
4944 case AMDGPU_CP_IRQ_GFX_EOP:
4945 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4947 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4948 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4950 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4951 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4953 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4954 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4956 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4957 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4959 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4960 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4962 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4963 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4965 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4966 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4968 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4969 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4977 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4978 struct amdgpu_irq_src *source,
4979 struct amdgpu_iv_entry *entry)
4982 struct amdgpu_ring *ring;
4985 DRM_DEBUG("IH: CP EOP\n");
4986 me_id = (entry->ring_id & 0x0c) >> 2;
4987 pipe_id = (entry->ring_id & 0x03) >> 0;
4990 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4994 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4995 ring = &adev->gfx.compute_ring[i];
4996 if ((ring->me == me_id) && (ring->pipe == pipe_id))
4997 amdgpu_fence_process(ring);
5004 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5005 struct amdgpu_irq_src *source,
5006 struct amdgpu_iv_entry *entry)
5008 DRM_ERROR("Illegal register access in command stream\n");
5009 schedule_work(&adev->reset_work);
5013 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5014 struct amdgpu_irq_src *source,
5015 struct amdgpu_iv_entry *entry)
5017 DRM_ERROR("Illegal instruction in command stream\n");
5018 // XXX soft reset the gfx block only
5019 schedule_work(&adev->reset_work);
5023 static int gfx_v7_0_set_clockgating_state(void *handle,
5024 enum amd_clockgating_state state)
5027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5029 if (state == AMD_CG_STATE_GATE)
5032 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5033 /* order matters! */
5035 gfx_v7_0_enable_mgcg(adev, true);
5036 gfx_v7_0_enable_cgcg(adev, true);
5038 gfx_v7_0_enable_cgcg(adev, false);
5039 gfx_v7_0_enable_mgcg(adev, false);
5041 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5046 static int gfx_v7_0_set_powergating_state(void *handle,
5047 enum amd_powergating_state state)
5050 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5052 if (state == AMD_PG_STATE_GATE)
5055 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5056 AMD_PG_SUPPORT_GFX_SMG |
5057 AMD_PG_SUPPORT_GFX_DMG |
5059 AMD_PG_SUPPORT_GDS |
5060 AMD_PG_SUPPORT_RLC_SMU_HS)) {
5061 gfx_v7_0_update_gfx_pg(adev, gate);
5062 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5063 gfx_v7_0_enable_cp_pg(adev, gate);
5064 gfx_v7_0_enable_gds_pg(adev, gate);
5071 const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5073 .early_init = gfx_v7_0_early_init,
5074 .late_init = gfx_v7_0_late_init,
5075 .sw_init = gfx_v7_0_sw_init,
5076 .sw_fini = gfx_v7_0_sw_fini,
5077 .hw_init = gfx_v7_0_hw_init,
5078 .hw_fini = gfx_v7_0_hw_fini,
5079 .suspend = gfx_v7_0_suspend,
5080 .resume = gfx_v7_0_resume,
5081 .is_idle = gfx_v7_0_is_idle,
5082 .wait_for_idle = gfx_v7_0_wait_for_idle,
5083 .soft_reset = gfx_v7_0_soft_reset,
5084 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5085 .set_powergating_state = gfx_v7_0_set_powergating_state,
5088 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5089 .get_rptr = gfx_v7_0_ring_get_rptr,
5090 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5091 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5093 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5094 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5095 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5096 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5097 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5098 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5099 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5100 .test_ring = gfx_v7_0_ring_test_ring,
5101 .test_ib = gfx_v7_0_ring_test_ib,
5102 .insert_nop = amdgpu_ring_insert_nop,
5103 .pad_ib = amdgpu_ring_generic_pad_ib,
5104 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5105 .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_gfx,
5106 .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_gfx,
5109 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5110 .get_rptr = gfx_v7_0_ring_get_rptr,
5111 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5112 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5114 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5115 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5116 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5117 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5118 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5119 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5120 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5121 .test_ring = gfx_v7_0_ring_test_ring,
5122 .test_ib = gfx_v7_0_ring_test_ib,
5123 .insert_nop = amdgpu_ring_insert_nop,
5124 .pad_ib = amdgpu_ring_generic_pad_ib,
5125 .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_compute,
5126 .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_compute,
5129 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5133 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5134 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5135 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5136 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5139 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5140 .set = gfx_v7_0_set_eop_interrupt_state,
5141 .process = gfx_v7_0_eop_irq,
5144 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5145 .set = gfx_v7_0_set_priv_reg_fault_state,
5146 .process = gfx_v7_0_priv_reg_irq,
5149 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5150 .set = gfx_v7_0_set_priv_inst_fault_state,
5151 .process = gfx_v7_0_priv_inst_irq,
5154 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5156 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5157 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5159 adev->gfx.priv_reg_irq.num_types = 1;
5160 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5162 adev->gfx.priv_inst_irq.num_types = 1;
5163 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5166 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5168 /* init asci gds info */
5169 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5170 adev->gds.gws.total_size = 64;
5171 adev->gds.oa.total_size = 16;
5173 if (adev->gds.mem.total_size == 64 * 1024) {
5174 adev->gds.mem.gfx_partition_size = 4096;
5175 adev->gds.mem.cs_partition_size = 4096;
5177 adev->gds.gws.gfx_partition_size = 4;
5178 adev->gds.gws.cs_partition_size = 4;
5180 adev->gds.oa.gfx_partition_size = 4;
5181 adev->gds.oa.cs_partition_size = 1;
5183 adev->gds.mem.gfx_partition_size = 1024;
5184 adev->gds.mem.cs_partition_size = 1024;
5186 adev->gds.gws.gfx_partition_size = 16;
5187 adev->gds.gws.cs_partition_size = 16;
5189 adev->gds.oa.gfx_partition_size = 4;
5190 adev->gds.oa.cs_partition_size = 4;
5195 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5197 int i, j, k, counter, active_cu_number = 0;
5198 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5199 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5200 unsigned disable_masks[4 * 2];
5202 memset(cu_info, 0, sizeof(*cu_info));
5204 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5206 mutex_lock(&adev->grbm_idx_mutex);
5207 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5208 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5212 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5214 gfx_v7_0_set_user_cu_inactive_bitmap(
5215 adev, disable_masks[i * 2 + j]);
5216 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5217 cu_info->bitmap[i][j] = bitmap;
5219 for (k = 0; k < 16; k ++) {
5220 if (bitmap & mask) {
5227 active_cu_number += counter;
5228 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5231 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5232 mutex_unlock(&adev->grbm_idx_mutex);
5234 cu_info->number = active_cu_number;
5235 cu_info->ao_cu_mask = ao_cu_mask;