drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "amdgpu_gfx.h"
  27 #include "amdgpu_ucode.h"
  28 #include "si/clearstate_si.h"
  29 #include "si/sid.h"
  30
  31 #define GFX6_NUM_GFX_RINGS     1
  32 #define GFX6_NUM_COMPUTE_RINGS 2
  33 #define STATIC_PER_CU_PG_ENABLE                    (1 << 3)
  34 #define DYN_PER_CU_PG_ENABLE                       (1 << 2)
  35 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
  36 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
  37
  38
  39 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  40 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
  42
  43 /*(DEBLOBBED)*/
  44
  45 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
  46 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
  47 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
  48 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
  49
  50
  51 static const u32 verde_rlc_save_restore_register_list[] =
  52 {
  53         (0x8000 << 16) | (0x98f4 >> 2),
  54         0x00000000,
  55         (0x8040 << 16) | (0x98f4 >> 2),
  56         0x00000000,
  57         (0x8000 << 16) | (0xe80 >> 2),
  58         0x00000000,
  59         (0x8040 << 16) | (0xe80 >> 2),
  60         0x00000000,
  61         (0x8000 << 16) | (0x89bc >> 2),
  62         0x00000000,
  63         (0x8040 << 16) | (0x89bc >> 2),
  64         0x00000000,
  65         (0x8000 << 16) | (0x8c1c >> 2),
  66         0x00000000,
  67         (0x8040 << 16) | (0x8c1c >> 2),
  68         0x00000000,
  69         (0x9c00 << 16) | (0x98f0 >> 2),
  70         0x00000000,
  71         (0x9c00 << 16) | (0xe7c >> 2),
  72         0x00000000,
  73         (0x8000 << 16) | (0x9148 >> 2),
  74         0x00000000,
  75         (0x8040 << 16) | (0x9148 >> 2),
  76         0x00000000,
  77         (0x9c00 << 16) | (0x9150 >> 2),
  78         0x00000000,
  79         (0x9c00 << 16) | (0x897c >> 2),
  80         0x00000000,
  81         (0x9c00 << 16) | (0x8d8c >> 2),
  82         0x00000000,
  83         (0x9c00 << 16) | (0xac54 >> 2),
  84         0X00000000,
  85         0x3,
  86         (0x9c00 << 16) | (0x98f8 >> 2),
  87         0x00000000,
  88         (0x9c00 << 16) | (0x9910 >> 2),
  89         0x00000000,
  90         (0x9c00 << 16) | (0x9914 >> 2),
  91         0x00000000,
  92         (0x9c00 << 16) | (0x9918 >> 2),
  93         0x00000000,
  94         (0x9c00 << 16) | (0x991c >> 2),
  95         0x00000000,
  96         (0x9c00 << 16) | (0x9920 >> 2),
  97         0x00000000,
  98         (0x9c00 << 16) | (0x9924 >> 2),
  99         0x00000000,
 100         (0x9c00 << 16) | (0x9928 >> 2),
 101         0x00000000,
 102         (0x9c00 << 16) | (0x992c >> 2),
 103         0x00000000,
 104         (0x9c00 << 16) | (0x9930 >> 2),
 105         0x00000000,
 106         (0x9c00 << 16) | (0x9934 >> 2),
 107         0x00000000,
 108         (0x9c00 << 16) | (0x9938 >> 2),
 109         0x00000000,
 110         (0x9c00 << 16) | (0x993c >> 2),
 111         0x00000000,
 112         (0x9c00 << 16) | (0x9940 >> 2),
 113         0x00000000,
 114         (0x9c00 << 16) | (0x9944 >> 2),
 115         0x00000000,
 116         (0x9c00 << 16) | (0x9948 >> 2),
 117         0x00000000,
 118         (0x9c00 << 16) | (0x994c >> 2),
 119         0x00000000,
 120         (0x9c00 << 16) | (0x9950 >> 2),
 121         0x00000000,
 122         (0x9c00 << 16) | (0x9954 >> 2),
 123         0x00000000,
 124         (0x9c00 << 16) | (0x9958 >> 2),
 125         0x00000000,
 126         (0x9c00 << 16) | (0x995c >> 2),
 127         0x00000000,
 128         (0x9c00 << 16) | (0x9960 >> 2),
 129         0x00000000,
 130         (0x9c00 << 16) | (0x9964 >> 2),
 131         0x00000000,
 132         (0x9c00 << 16) | (0x9968 >> 2),
 133         0x00000000,
 134         (0x9c00 << 16) | (0x996c >> 2),
 135         0x00000000,
 136         (0x9c00 << 16) | (0x9970 >> 2),
 137         0x00000000,
 138         (0x9c00 << 16) | (0x9974 >> 2),
 139         0x00000000,
 140         (0x9c00 << 16) | (0x9978 >> 2),
 141         0x00000000,
 142         (0x9c00 << 16) | (0x997c >> 2),
 143         0x00000000,
 144         (0x9c00 << 16) | (0x9980 >> 2),
 145         0x00000000,
 146         (0x9c00 << 16) | (0x9984 >> 2),
 147         0x00000000,
 148         (0x9c00 << 16) | (0x9988 >> 2),
 149         0x00000000,
 150         (0x9c00 << 16) | (0x998c >> 2),
 151         0x00000000,
 152         (0x9c00 << 16) | (0x8c00 >> 2),
 153         0x00000000,
 154         (0x9c00 << 16) | (0x8c14 >> 2),
 155         0x00000000,
 156         (0x9c00 << 16) | (0x8c04 >> 2),
 157         0x00000000,
 158         (0x9c00 << 16) | (0x8c08 >> 2),
 159         0x00000000,
 160         (0x8000 << 16) | (0x9b7c >> 2),
 161         0x00000000,
 162         (0x8040 << 16) | (0x9b7c >> 2),
 163         0x00000000,
 164         (0x8000 << 16) | (0xe84 >> 2),
 165         0x00000000,
 166         (0x8040 << 16) | (0xe84 >> 2),
 167         0x00000000,
 168         (0x8000 << 16) | (0x89c0 >> 2),
 169         0x00000000,
 170         (0x8040 << 16) | (0x89c0 >> 2),
 171         0x00000000,
 172         (0x8000 << 16) | (0x914c >> 2),
 173         0x00000000,
 174         (0x8040 << 16) | (0x914c >> 2),
 175         0x00000000,
 176         (0x8000 << 16) | (0x8c20 >> 2),
 177         0x00000000,
 178         (0x8040 << 16) | (0x8c20 >> 2),
 179         0x00000000,
 180         (0x8000 << 16) | (0x9354 >> 2),
 181         0x00000000,
 182         (0x8040 << 16) | (0x9354 >> 2),
 183         0x00000000,
 184         (0x9c00 << 16) | (0x9060 >> 2),
 185         0x00000000,
 186         (0x9c00 << 16) | (0x9364 >> 2),
 187         0x00000000,
 188         (0x9c00 << 16) | (0x9100 >> 2),
 189         0x00000000,
 190         (0x9c00 << 16) | (0x913c >> 2),
 191         0x00000000,
 192         (0x8000 << 16) | (0x90e0 >> 2),
 193         0x00000000,
 194         (0x8000 << 16) | (0x90e4 >> 2),
 195         0x00000000,
 196         (0x8000 << 16) | (0x90e8 >> 2),
 197         0x00000000,
 198         (0x8040 << 16) | (0x90e0 >> 2),
 199         0x00000000,
 200         (0x8040 << 16) | (0x90e4 >> 2),
 201         0x00000000,
 202         (0x8040 << 16) | (0x90e8 >> 2),
 203         0x00000000,
 204         (0x9c00 << 16) | (0x8bcc >> 2),
 205         0x00000000,
 206         (0x9c00 << 16) | (0x8b24 >> 2),
 207         0x00000000,
 208         (0x9c00 << 16) | (0x88c4 >> 2),
 209         0x00000000,
 210         (0x9c00 << 16) | (0x8e50 >> 2),
 211         0x00000000,
 212         (0x9c00 << 16) | (0x8c0c >> 2),
 213         0x00000000,
 214         (0x9c00 << 16) | (0x8e58 >> 2),
 215         0x00000000,
 216         (0x9c00 << 16) | (0x8e5c >> 2),
 217         0x00000000,
 218         (0x9c00 << 16) | (0x9508 >> 2),
 219         0x00000000,
 220         (0x9c00 << 16) | (0x950c >> 2),
 221         0x00000000,
 222         (0x9c00 << 16) | (0x9494 >> 2),
 223         0x00000000,
 224         (0x9c00 << 16) | (0xac0c >> 2),
 225         0x00000000,
 226         (0x9c00 << 16) | (0xac10 >> 2),
 227         0x00000000,
 228         (0x9c00 << 16) | (0xac14 >> 2),
 229         0x00000000,
 230         (0x9c00 << 16) | (0xae00 >> 2),
 231         0x00000000,
 232         (0x9c00 << 16) | (0xac08 >> 2),
 233         0x00000000,
 234         (0x9c00 << 16) | (0x88d4 >> 2),
 235         0x00000000,
 236         (0x9c00 << 16) | (0x88c8 >> 2),
 237         0x00000000,
 238         (0x9c00 << 16) | (0x88cc >> 2),
 239         0x00000000,
 240         (0x9c00 << 16) | (0x89b0 >> 2),
 241         0x00000000,
 242         (0x9c00 << 16) | (0x8b10 >> 2),
 243         0x00000000,
 244         (0x9c00 << 16) | (0x8a14 >> 2),
 245         0x00000000,
 246         (0x9c00 << 16) | (0x9830 >> 2),
 247         0x00000000,
 248         (0x9c00 << 16) | (0x9834 >> 2),
 249         0x00000000,
 250         (0x9c00 << 16) | (0x9838 >> 2),
 251         0x00000000,
 252         (0x9c00 << 16) | (0x9a10 >> 2),
 253         0x00000000,
 254         (0x8000 << 16) | (0x9870 >> 2),
 255         0x00000000,
 256         (0x8000 << 16) | (0x9874 >> 2),
 257         0x00000000,
 258         (0x8001 << 16) | (0x9870 >> 2),
 259         0x00000000,
 260         (0x8001 << 16) | (0x9874 >> 2),
 261         0x00000000,
 262         (0x8040 << 16) | (0x9870 >> 2),
 263         0x00000000,
 264         (0x8040 << 16) | (0x9874 >> 2),
 265         0x00000000,
 266         (0x8041 << 16) | (0x9870 >> 2),
 267         0x00000000,
 268         (0x8041 << 16) | (0x9874 >> 2),
 269         0x00000000,
 270         0x00000000
 271 };
 272
 273 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 274 {
 275         const char *chip_name;
 276         char fw_name[30];
 277         int err;
 278         const struct gfx_firmware_header_v1_0 *cp_hdr;
 279         const struct rlc_firmware_header_v1_0 *rlc_hdr;
 280
 281         DRM_DEBUG("\n");
 282
 283         switch (adev->asic_type) {
 284         case CHIP_TAHITI:
 285                 chip_name = "tahiti";
 286                 break;
 287         case CHIP_PITCAIRN:
 288                 chip_name = "pitcairn";
 289                 break;
 290         case CHIP_VERDE:
 291                 chip_name = "verde";
 292                 break;
 293         case CHIP_OLAND:
 294                 chip_name = "oland";
 295                 break;
 296         case CHIP_HAINAN:
 297                 chip_name = "hainan";
 298                 break;
 299         default: BUG();
 300         }
 301
 302         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 303         err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 304         if (err)
 305                 goto out;
 306         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 307         if (err)
 308                 goto out;
 309         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 310         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 311         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 312
 313         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 314         err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 315         if (err)
 316                 goto out;
 317         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 318         if (err)
 319                 goto out;
 320         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 321         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 322         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 323
 324         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 325         err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 326         if (err)
 327                 goto out;
 328         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 329         if (err)
 330                 goto out;
 331         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 332         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 333         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 334
 335         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 336         err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 337         if (err)
 338                 goto out;
 339         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 340         rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 341         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 342         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 343
 344 out:
 345         if (err) {
 346                 printk(KERN_ERR
 347                        "gfx6: Failed to load firmware \"%s\"\n",
 348                        fw_name);
 349                 release_firmware(adev->gfx.pfp_fw);
 350                 adev->gfx.pfp_fw = NULL;
 351                 release_firmware(adev->gfx.me_fw);
 352                 adev->gfx.me_fw = NULL;
 353                 release_firmware(adev->gfx.ce_fw);
 354                 adev->gfx.ce_fw = NULL;
 355                 release_firmware(adev->gfx.rlc_fw);
 356                 adev->gfx.rlc_fw = NULL;
 357         }
 358         return err;
 359 }
 360
 361 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
 362 {
 363         const u32 num_tile_mode_states = 32;
 364         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 365
 366         switch (adev->gfx.config.mem_row_size_in_kb) {
 367         case 1:
 368                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 369                 break;
 370         case 2:
 371         default:
 372                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 373                 break;
 374         case 4:
 375                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 376                 break;
 377         }
 378
 379         if (adev->asic_type == CHIP_VERDE ||
 380                 adev->asic_type == CHIP_OLAND ||
 381                 adev->asic_type == CHIP_HAINAN) {
 382                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 383                         switch (reg_offset) {
 384                         case 0:
 385                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 386                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 387                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 388                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 389                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 390                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 391                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 392                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 393                                 break;
 394                         case 1:
 395                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 396                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 397                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 398                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 399                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 400                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 401                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 402                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 403                                 break;
 404                         case 2:
 405                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 406                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 407                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 408                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 409                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 410                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 411                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 412                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 413                                 break;
 414                         case 3:
 415                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 416                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 417                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 418                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 419                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 420                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 421                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 422                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 423                                 break;
 424                         case 4:
 425                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 426                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 427                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 428                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 429                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 430                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 431                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 432                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 433                                 break;
 434                         case 5:
 435                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 436                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 437                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 438                                                  TILE_SPLIT(split_equal_to_row_size) |
 439                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 440                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 441                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 442                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 443                                 break;
 444                         case 6:
 445                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 446                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 447                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 448                                                  TILE_SPLIT(split_equal_to_row_size) |
 449                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 450                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 451                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 452                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 453                                 break;
 454                         case 7:
 455                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 456                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 457                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 458                                                  TILE_SPLIT(split_equal_to_row_size) |
 459                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 460                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 461                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 462                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 463                                 break;
 464                         case 8:
 465                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 466                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 467                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 468                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 469                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 470                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 471                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 472                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 473                                 break;
 474                         case 9:
 475                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 476                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 477                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 478                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 479                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 480                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 481                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 482                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 483                                 break;
 484                         case 10:
 485                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 486                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 487                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 488                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 489                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 490                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 491                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 492                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 493                                 break;
 494                         case 11:
 495                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 496                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 497                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 498                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 499                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 500                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 501                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 502                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 503                                 break;
 504                         case 12:
 505                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 506                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 507                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 508                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 509                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 510                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 511                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 512                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 513                                 break;
 514                         case 13:
 515                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 516                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 517                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 518                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 519                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 520                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 521                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 522                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 523                                 break;
 524                         case 14:
 525                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 526                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 527                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 528                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 529                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 530                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 531                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 532                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 533                                 break;
 534                         case 15:
 535                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 536                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 537                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 538                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 539                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 540                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 541                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 542                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 543                                 break;
 544                         case 16:
 545                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 546                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 547                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 548                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 549                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 550                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 551                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 552                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 553                                 break;
 554                         case 17:
 555                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 556                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 557                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 558                                                  TILE_SPLIT(split_equal_to_row_size) |
 559                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 560                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 561                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 562                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 563                                 break;
 564                         case 21:
 565                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 566                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 567                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 568                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 569                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 570                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 571                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 572                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 573                                 break;
 574                         case 22:
 575                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 576                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 577                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 578                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 579                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 580                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 581                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 582                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 583                                 break;
 584                         case 23:
 585                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 586                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 587                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 588                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 589                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 590                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 591                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 592                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 593                                 break;
 594                         case 24:
 595                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 596                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 597                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 598                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 599                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 600                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 601                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 602                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 603                                 break;
 604                         case 25:
 605                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 606                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 607                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 608                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 609                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
 610                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 611                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 612                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 613                                 break;
 614                         default:
 615                                 gb_tile_moden = 0;
 616                                 break;
 617                         }
 618                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
 619                         WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
 620                 }
 621         } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
 622                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 623                         switch (reg_offset) {
 624                         case 0:  /* non-AA compressed depth or any compressed stencil */
 625                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 626                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 627                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 628                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 629                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 630                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 631                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 632                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 633                                 break;
 634                         case 1:  /* 2xAA/4xAA compressed depth only */
 635                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 636                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 637                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 638                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 639                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 640                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 641                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 642                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 643                                 break;
 644                         case 2:  /* 8xAA compressed depth only */
 645                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 646                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 647                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 648                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 649                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 650                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 651                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 652                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 653                                 break;
 654                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
 655                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 656                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 657                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 658                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 659                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 660                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 661                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 662                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 663                                 break;
 664                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
 665                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 666                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 667                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 668                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 669                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 670                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 671                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 672                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 673                                 break;
 674                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
 675                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 676                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 677                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 678                                                  TILE_SPLIT(split_equal_to_row_size) |
 679                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 680                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 681                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 682                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 683                                 break;
 684                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
 685                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 686                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 687                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 688                                                  TILE_SPLIT(split_equal_to_row_size) |
 689                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 690                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 691                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 692                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 693                                 break;
 694                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
 695                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 696                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 697                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 698                                                  TILE_SPLIT(split_equal_to_row_size) |
 699                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 700                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 701                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 702                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 703                                 break;
 704                         case 8:  /* 1D and 1D Array Surfaces */
 705                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 706                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 707                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 708                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 709                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 710                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 711                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 712                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 713                                 break;
 714                         case 9:  /* Displayable maps. */
 715                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 716                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 717                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 718                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 719                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 720                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 721                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 722                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 723                                 break;
 724                         case 10:  /* Display 8bpp. */
 725                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 726                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 727                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 728                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 729                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 730                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 731                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 732                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 733                                 break;
 734                         case 11:  /* Display 16bpp. */
 735                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 736                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 737                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 738                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 739                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 740                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 741                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 742                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 743                                 break;
 744                         case 12:  /* Display 32bpp. */
 745                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 746                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 747                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 748                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 749                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 750                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 751                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 752                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 753                                 break;
 754                         case 13:  /* Thin. */
 755                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 756                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 757                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 758                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 759                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 760                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 761                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 762                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 763                                 break;
 764                         case 14:  /* Thin 8 bpp. */
 765                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 766                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 767                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 768                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 769                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 770                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 771                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 772                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 773                                 break;
 774                         case 15:  /* Thin 16 bpp. */
 775                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 776                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 777                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 778                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 779                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 780                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 781                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 782                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 783                                 break;
 784                         case 16:  /* Thin 32 bpp. */
 785                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 786                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 787                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 788                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 789                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 790                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 791                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 792                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 793                                 break;
 794                         case 17:  /* Thin 64 bpp. */
 795                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 796                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 797                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 798                                                  TILE_SPLIT(split_equal_to_row_size) |
 799                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 800                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 801                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 802                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 803                                 break;
 804                         case 21:  /* 8 bpp PRT. */
 805                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 806                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 807                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 808                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 809                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 810                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 811                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 812                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 813                                 break;
 814                         case 22:  /* 16 bpp PRT */
 815                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 816                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 817                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 818                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 819                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 820                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 821                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 822                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 823                                 break;
 824                         case 23:  /* 32 bpp PRT */
 825                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 826                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 827                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 828                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 829                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 830                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 831                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 832                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 833                                 break;
 834                         case 24:  /* 64 bpp PRT */
 835                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 836                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 837                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 838                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 839                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 840                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 841                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 842                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 843                                 break;
 844                         case 25:  /* 128 bpp PRT */
 845                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 846                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 847                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 848                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 849                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
 850                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 851                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 852                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 853                                 break;
 854                         default:
 855                                 gb_tile_moden = 0;
 856                                 break;
 857                         }
 858                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
 859                         WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
 860                 }
 861         } else{
 862
 863                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
 864         }
 865
 866 }
 867
 868 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 869                                   u32 sh_num, u32 instance)
 870 {
 871         u32 data;
 872
 873         if (instance == 0xffffffff)
 874                 data = INSTANCE_BROADCAST_WRITES;
 875         else
 876                 data = INSTANCE_INDEX(instance);
 877
 878         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
 879                 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
 880         else if (se_num == 0xffffffff)
 881                 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
 882         else if (sh_num == 0xffffffff)
 883                 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
 884         else
 885                 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
 886         WREG32(GRBM_GFX_INDEX, data);
 887 }
 888
 889 static u32 gfx_v6_0_create_bitmask(u32 bit_width)
 890 {
 891         return (u32)(((u64)1 << bit_width) - 1);
 892 }
 893
 894 static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
 895                                     u32 max_rb_num_per_se,
 896                                     u32 sh_per_se)
 897 {
 898         u32 data, mask;
 899
 900         data = RREG32(CC_RB_BACKEND_DISABLE);
 901         data &= BACKEND_DISABLE_MASK;
 902         data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
 903
 904         data >>= BACKEND_DISABLE_SHIFT;
 905
 906         mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
 907
 908         return data & mask;
 909 }
 910
 911 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
 912 {
 913         switch (adev->asic_type) {
 914         case CHIP_TAHITI:
 915         case CHIP_PITCAIRN:
 916                 *rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) |
 917                           SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2);
 918                 break;
 919         case CHIP_VERDE:
 920                 *rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1);
 921                 break;
 922         case CHIP_OLAND:
 923                 *rconf |= RB_YSEL;
 924                 break;
 925         case CHIP_HAINAN:
 926                 *rconf |= 0x0;
 927                 break;
 928         default:
 929                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
 930                 break;
 931         }
 932 }
 933
 934 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
 935                                                     u32 raster_config, unsigned rb_mask,
 936                                                     unsigned num_rb)
 937 {
 938         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
 939         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
 940         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
 941         unsigned rb_per_se = num_rb / num_se;
 942         unsigned se_mask[4];
 943         unsigned se;
 944
 945         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
 946         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
 947         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
 948         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
 949
 950         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
 951         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
 952         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
 953
 954         for (se = 0; se < num_se; se++) {
 955                 unsigned raster_config_se = raster_config;
 956                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
 957                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
 958                 int idx = (se / 2) * 2;
 959
 960                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
 961                         raster_config_se &= ~SE_MAP_MASK;
 962
 963                         if (!se_mask[idx]) {
 964                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
 965                         } else {
 966                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
 967                         }
 968                 }
 969
 970                 pkr0_mask &= rb_mask;
 971                 pkr1_mask &= rb_mask;
 972                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
 973                         raster_config_se &= ~PKR_MAP_MASK;
 974
 975                         if (!pkr0_mask) {
 976                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
 977                         } else {
 978                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
 979                         }
 980                 }
 981
 982                 if (rb_per_se >= 2) {
 983                         unsigned rb0_mask = 1 << (se * rb_per_se);
 984                         unsigned rb1_mask = rb0_mask << 1;
 985
 986                         rb0_mask &= rb_mask;
 987                         rb1_mask &= rb_mask;
 988                         if (!rb0_mask || !rb1_mask) {
 989                                 raster_config_se &= ~RB_MAP_PKR0_MASK;
 990
 991                                 if (!rb0_mask) {
 992                                         raster_config_se |=
 993                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
 994                                 } else {
 995                                         raster_config_se |=
 996                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
 997                                 }
 998                         }
 999
1000                         if (rb_per_se > 2) {
1001                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1002                                 rb1_mask = rb0_mask << 1;
1003                                 rb0_mask &= rb_mask;
1004                                 rb1_mask &= rb_mask;
1005                                 if (!rb0_mask || !rb1_mask) {
1006                                         raster_config_se &= ~RB_MAP_PKR1_MASK;
1007
1008                                         if (!rb0_mask) {
1009                                                 raster_config_se |=
1010                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1011                                         } else {
1012                                                 raster_config_se |=
1013                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1014                                         }
1015                                 }
1016                         }
1017                 }
1018
1019                 /* GRBM_GFX_INDEX has a different offset on SI */
1020                 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1021                 WREG32(PA_SC_RASTER_CONFIG, raster_config_se);
1022         }
1023
1024         /* GRBM_GFX_INDEX has a different offset on SI */
1025         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1026 }
1027
1028 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1029                               u32 se_num, u32 sh_per_se,
1030                               u32 max_rb_num_per_se)
1031 {
1032         int i, j;
1033         u32 data, mask;
1034         u32 disabled_rbs = 0;
1035         u32 enabled_rbs = 0;
1036         unsigned num_rb_pipes;
1037
1038         mutex_lock(&adev->grbm_idx_mutex);
1039         for (i = 0; i < se_num; i++) {
1040                 for (j = 0; j < sh_per_se; j++) {
1041                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1042                         data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1043                         disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1044                 }
1045         }
1046         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1047         mutex_unlock(&adev->grbm_idx_mutex);
1048
1049         mask = 1;
1050         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1051                 if (!(disabled_rbs & mask))
1052                         enabled_rbs |= mask;
1053                 mask <<= 1;
1054         }
1055
1056         adev->gfx.config.backend_enable_mask = enabled_rbs;
1057         adev->gfx.config.num_rbs = hweight32(enabled_rbs);
1058
1059         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1060                              adev->gfx.config.max_shader_engines, 16);
1061
1062         mutex_lock(&adev->grbm_idx_mutex);
1063         for (i = 0; i < se_num; i++) {
1064                 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1065                 data = 0;
1066                 for (j = 0; j < sh_per_se; j++) {
1067                         switch (enabled_rbs & 3) {
1068                         case 1:
1069                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1070                                 break;
1071                         case 2:
1072                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1073                                 break;
1074                         case 3:
1075                         default:
1076                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1077                                 break;
1078                         }
1079                         enabled_rbs >>= 2;
1080                 }
1081                 gfx_v6_0_raster_config(adev, &data);
1082
1083                 if (!adev->gfx.config.backend_enable_mask ||
1084                                 adev->gfx.config.num_rbs >= num_rb_pipes)
1085                         WREG32(PA_SC_RASTER_CONFIG, data);
1086                 else
1087                         gfx_v6_0_write_harvested_raster_configs(adev, data,
1088                                                                 adev->gfx.config.backend_enable_mask,
1089                                                                 num_rb_pipes);
1090         }
1091         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1092         mutex_unlock(&adev->grbm_idx_mutex);
1093 }
1094 /*
1095 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
1096 {
1097 }
1098 */
1099
1100 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
1101 {
1102         u32 data, mask;
1103
1104         data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1105         data &= INACTIVE_CUS_MASK;
1106         data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1107
1108         data >>= INACTIVE_CUS_SHIFT;
1109
1110         mask = gfx_v6_0_create_bitmask(cu_per_sh);
1111
1112         return ~data & mask;
1113 }
1114
1115
1116 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1117                          u32 se_num, u32 sh_per_se,
1118                          u32 cu_per_sh)
1119 {
1120         int i, j, k;
1121         u32 data, mask;
1122         u32 active_cu = 0;
1123
1124         mutex_lock(&adev->grbm_idx_mutex);
1125         for (i = 0; i < se_num; i++) {
1126                 for (j = 0; j < sh_per_se; j++) {
1127                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1128                         data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1129                         active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1130
1131                         mask = 1;
1132                         for (k = 0; k < 16; k++) {
1133                                 mask <<= k;
1134                                 if (active_cu & mask) {
1135                                         data &= ~mask;
1136                                         WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1137                                         break;
1138                                 }
1139                         }
1140                 }
1141         }
1142         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1143         mutex_unlock(&adev->grbm_idx_mutex);
1144 }
1145
1146 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1147 {
1148         u32 gb_addr_config = 0;
1149         u32 mc_shared_chmap, mc_arb_ramcfg;
1150         u32 sx_debug_1;
1151         u32 hdp_host_path_cntl;
1152         u32 tmp;
1153
1154         switch (adev->asic_type) {
1155         case CHIP_TAHITI:
1156                 adev->gfx.config.max_shader_engines = 2;
1157                 adev->gfx.config.max_tile_pipes = 12;
1158                 adev->gfx.config.max_cu_per_sh = 8;
1159                 adev->gfx.config.max_sh_per_se = 2;
1160                 adev->gfx.config.max_backends_per_se = 4;
1161                 adev->gfx.config.max_texture_channel_caches = 12;
1162                 adev->gfx.config.max_gprs = 256;
1163                 adev->gfx.config.max_gs_threads = 32;
1164                 adev->gfx.config.max_hw_contexts = 8;
1165
1166                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1167                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1168                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1169                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1170                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1171                 break;
1172         case CHIP_PITCAIRN:
1173                 adev->gfx.config.max_shader_engines = 2;
1174                 adev->gfx.config.max_tile_pipes = 8;
1175                 adev->gfx.config.max_cu_per_sh = 5;
1176                 adev->gfx.config.max_sh_per_se = 2;
1177                 adev->gfx.config.max_backends_per_se = 4;
1178                 adev->gfx.config.max_texture_channel_caches = 8;
1179                 adev->gfx.config.max_gprs = 256;
1180                 adev->gfx.config.max_gs_threads = 32;
1181                 adev->gfx.config.max_hw_contexts = 8;
1182
1183                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1184                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1185                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1186                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1187                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1188                 break;
1189
1190         case CHIP_VERDE:
1191                 adev->gfx.config.max_shader_engines = 1;
1192                 adev->gfx.config.max_tile_pipes = 4;
1193                 adev->gfx.config.max_cu_per_sh = 5;
1194                 adev->gfx.config.max_sh_per_se = 2;
1195                 adev->gfx.config.max_backends_per_se = 4;
1196                 adev->gfx.config.max_texture_channel_caches = 4;
1197                 adev->gfx.config.max_gprs = 256;
1198                 adev->gfx.config.max_gs_threads = 32;
1199                 adev->gfx.config.max_hw_contexts = 8;
1200
1201                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1202                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1203                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1204                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1205                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1206                 break;
1207         case CHIP_OLAND:
1208                 adev->gfx.config.max_shader_engines = 1;
1209                 adev->gfx.config.max_tile_pipes = 4;
1210                 adev->gfx.config.max_cu_per_sh = 6;
1211                 adev->gfx.config.max_sh_per_se = 1;
1212                 adev->gfx.config.max_backends_per_se = 2;
1213                 adev->gfx.config.max_texture_channel_caches = 4;
1214                 adev->gfx.config.max_gprs = 256;
1215                 adev->gfx.config.max_gs_threads = 16;
1216                 adev->gfx.config.max_hw_contexts = 8;
1217
1218                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1219                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1220                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1221                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1222                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1223                 break;
1224         case CHIP_HAINAN:
1225                 adev->gfx.config.max_shader_engines = 1;
1226                 adev->gfx.config.max_tile_pipes = 4;
1227                 adev->gfx.config.max_cu_per_sh = 5;
1228                 adev->gfx.config.max_sh_per_se = 1;
1229                 adev->gfx.config.max_backends_per_se = 1;
1230                 adev->gfx.config.max_texture_channel_caches = 2;
1231                 adev->gfx.config.max_gprs = 256;
1232                 adev->gfx.config.max_gs_threads = 16;
1233                 adev->gfx.config.max_hw_contexts = 8;
1234
1235                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1236                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1237                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1238                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1239                 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1240                 break;
1241         default:
1242                 BUG();
1243                 break;
1244         }
1245
1246         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1247         WREG32(SRBM_INT_CNTL, 1);
1248         WREG32(SRBM_INT_ACK, 1);
1249
1250         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1251
1252         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1253         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1254
1255         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1256         adev->gfx.config.mem_max_burst_length_bytes = 256;
1257         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1258         adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1259         if (adev->gfx.config.mem_row_size_in_kb > 4)
1260                 adev->gfx.config.mem_row_size_in_kb = 4;
1261         adev->gfx.config.shader_engine_tile_size = 32;
1262         adev->gfx.config.num_gpus = 1;
1263         adev->gfx.config.multi_gpu_tile_size = 64;
1264
1265         gb_addr_config &= ~ROW_SIZE_MASK;
1266         switch (adev->gfx.config.mem_row_size_in_kb) {
1267         case 1:
1268         default:
1269                 gb_addr_config |= ROW_SIZE(0);
1270                 break;
1271         case 2:
1272                 gb_addr_config |= ROW_SIZE(1);
1273                 break;
1274         case 4:
1275                 gb_addr_config |= ROW_SIZE(2);
1276                 break;
1277         }
1278         adev->gfx.config.gb_addr_config = gb_addr_config;
1279
1280         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1281         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1282         WREG32(DMIF_ADDR_CALC, gb_addr_config);
1283         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1284         WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1285         WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1286 #if 0
1287         if (adev->has_uvd) {
1288                 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1289                 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1290                 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1291         }
1292 #endif
1293         gfx_v6_0_tiling_mode_table_init(adev);
1294
1295         gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1296                     adev->gfx.config.max_sh_per_se,
1297                     adev->gfx.config.max_backends_per_se);
1298
1299         gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1300                      adev->gfx.config.max_sh_per_se,
1301                      adev->gfx.config.max_cu_per_sh);
1302
1303         gfx_v6_0_get_cu_info(adev);
1304
1305         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1306                                      ROQ_IB2_START(0x2b)));
1307         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1308
1309         sx_debug_1 = RREG32(SX_DEBUG_1);
1310         WREG32(SX_DEBUG_1, sx_debug_1);
1311
1312         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1313
1314         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) |
1315                                  SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) |
1316                                  SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) |
1317                                  SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
1318
1319         WREG32(VGT_NUM_INSTANCES, 1);
1320         WREG32(CP_PERFMON_CNTL, 0);
1321         WREG32(SQ_CONFIG, 0);
1322         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1323                                           FORCE_EOV_MAX_REZ_CNT(255)));
1324
1325         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1326                AUTO_INVLD_EN(ES_AND_GS_AUTO));
1327
1328         WREG32(VGT_GS_VERTEX_REUSE, 16);
1329         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1330
1331         WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1332         WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1333         WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1334         WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1335         WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1336         WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1337         WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1338         WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1339
1340         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1341         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1342
1343         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1344
1345         udelay(50);
1346 }
1347
1348
1349 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1350 {
1351         int i;
1352
1353         adev->gfx.scratch.num_reg = 7;
1354         adev->gfx.scratch.reg_base = SCRATCH_REG0;
1355         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1356                 adev->gfx.scratch.free[i] = true;
1357                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1358         }
1359 }
1360
1361 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1362 {
1363         struct amdgpu_device *adev = ring->adev;
1364         uint32_t scratch;
1365         uint32_t tmp = 0;
1366         unsigned i;
1367         int r;
1368
1369         r = amdgpu_gfx_scratch_get(adev, &scratch);
1370         if (r) {
1371                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1372                 return r;
1373         }
1374         WREG32(scratch, 0xCAFEDEAD);
1375
1376         r = amdgpu_ring_alloc(ring, 3);
1377         if (r) {
1378                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1379                 amdgpu_gfx_scratch_free(adev, scratch);
1380                 return r;
1381         }
1382         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1383         amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1384         amdgpu_ring_write(ring, 0xDEADBEEF);
1385         amdgpu_ring_commit(ring);
1386
1387         for (i = 0; i < adev->usec_timeout; i++) {
1388                 tmp = RREG32(scratch);
1389                 if (tmp == 0xDEADBEEF)
1390                         break;
1391                 DRM_UDELAY(1);
1392         }
1393         if (i < adev->usec_timeout) {
1394                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1395         } else {
1396                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1397                           ring->idx, scratch, tmp);
1398                 r = -EINVAL;
1399         }
1400         amdgpu_gfx_scratch_free(adev, scratch);
1401         return r;
1402 }
1403
1404 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1405 {
1406         /* flush hdp cache */
1407         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1408         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1409                                  WRITE_DATA_DST_SEL(0)));
1410         amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL);
1411         amdgpu_ring_write(ring, 0);
1412         amdgpu_ring_write(ring, 0x1);
1413 }
1414
1415 /**
1416  * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1417  *
1418  * @adev: amdgpu_device pointer
1419  * @ridx: amdgpu ring index
1420  *
1421  * Emits an hdp invalidate on the cp.
1422  */
1423 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1424 {
1425         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1426         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1427                                  WRITE_DATA_DST_SEL(0)));
1428         amdgpu_ring_write(ring, HDP_DEBUG0);
1429         amdgpu_ring_write(ring, 0);
1430         amdgpu_ring_write(ring, 0x1);
1431 }
1432
1433 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1434                                      u64 seq, unsigned flags)
1435 {
1436         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1437         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1438         /* flush read cache over gart */
1439         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1440         amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1441         amdgpu_ring_write(ring, 0);
1442         amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1443         amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1444                           PACKET3_TC_ACTION_ENA |
1445                           PACKET3_SH_KCACHE_ACTION_ENA |
1446                           PACKET3_SH_ICACHE_ACTION_ENA);
1447         amdgpu_ring_write(ring, 0xFFFFFFFF);
1448         amdgpu_ring_write(ring, 0);
1449         amdgpu_ring_write(ring, 10); /* poll interval */
1450         /* EVENT_WRITE_EOP - flush caches, send int */
1451         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1452         amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1453         amdgpu_ring_write(ring, addr & 0xfffffffc);
1454         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1455                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1456         amdgpu_ring_write(ring, lower_32_bits(seq));
1457         amdgpu_ring_write(ring, upper_32_bits(seq));
1458 }
1459
1460 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1461                                   struct amdgpu_ib *ib,
1462                                   unsigned vm_id, bool ctx_switch)
1463 {
1464         u32 header, control = 0;
1465
1466         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1467         if (ctx_switch) {
1468                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1469                 amdgpu_ring_write(ring, 0);
1470         }
1471
1472         if (ib->flags & AMDGPU_IB_FLAG_CE)
1473                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1474         else
1475                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1476
1477         control |= ib->length_dw | (vm_id << 24);
1478
1479         amdgpu_ring_write(ring, header);
1480         amdgpu_ring_write(ring,
1481 #ifdef __BIG_ENDIAN
1482                           (2 << 0) |
1483 #endif
1484                           (ib->gpu_addr & 0xFFFFFFFC));
1485         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1486         amdgpu_ring_write(ring, control);
1487 }
1488
1489 /**
1490  * gfx_v6_0_ring_test_ib - basic ring IB test
1491  *
1492  * @ring: amdgpu_ring structure holding ring information
1493  *
1494  * Allocate an IB and execute it on the gfx ring (SI).
1495  * Provides a basic gfx ring test to verify that IBs are working.
1496  * Returns 0 on success, error on failure.
1497  */
1498 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1499 {
1500         struct amdgpu_device *adev = ring->adev;
1501         struct amdgpu_ib ib;
1502         struct fence *f = NULL;
1503         uint32_t scratch;
1504         uint32_t tmp = 0;
1505         long r;
1506
1507         r = amdgpu_gfx_scratch_get(adev, &scratch);
1508         if (r) {
1509                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1510                 return r;
1511         }
1512         WREG32(scratch, 0xCAFEDEAD);
1513         memset(&ib, 0, sizeof(ib));
1514         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1515         if (r) {
1516                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1517                 goto err1;
1518         }
1519         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1520         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1521         ib.ptr[2] = 0xDEADBEEF;
1522         ib.length_dw = 3;
1523
1524         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1525         if (r)
1526                 goto err2;
1527
1528         r = fence_wait_timeout(f, false, timeout);
1529         if (r == 0) {
1530                 DRM_ERROR("amdgpu: IB test timed out\n");
1531                 r = -ETIMEDOUT;
1532                 goto err2;
1533         } else if (r < 0) {
1534                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1535                 goto err2;
1536         }
1537         tmp = RREG32(scratch);
1538         if (tmp == 0xDEADBEEF) {
1539                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1540                 r = 0;
1541         } else {
1542                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1543                           scratch, tmp);
1544                 r = -EINVAL;
1545         }
1546
1547 err2:
1548         amdgpu_ib_free(adev, &ib, NULL);
1549         fence_put(f);
1550 err1:
1551         amdgpu_gfx_scratch_free(adev, scratch);
1552         return r;
1553 }
1554
1555 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1556 {
1557         int i;
1558         if (enable)
1559                 WREG32(CP_ME_CNTL, 0);
1560         else {
1561                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1562                 WREG32(SCRATCH_UMSK, 0);
1563                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1564                         adev->gfx.gfx_ring[i].ready = false;
1565                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1566                         adev->gfx.compute_ring[i].ready = false;
1567         }
1568         udelay(50);
1569 }
1570
1571 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1572 {
1573         unsigned i;
1574         const struct gfx_firmware_header_v1_0 *pfp_hdr;
1575         const struct gfx_firmware_header_v1_0 *ce_hdr;
1576         const struct gfx_firmware_header_v1_0 *me_hdr;
1577         const __le32 *fw_data;
1578         u32 fw_size;
1579
1580         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1581                 return -EINVAL;
1582
1583         gfx_v6_0_cp_gfx_enable(adev, false);
1584         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1585         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1586         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1587
1588         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1589         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1590         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1591
1592         /* PFP */
1593         fw_data = (const __le32 *)
1594                 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1595         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1596         WREG32(CP_PFP_UCODE_ADDR, 0);
1597         for (i = 0; i < fw_size; i++)
1598                 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1599         WREG32(CP_PFP_UCODE_ADDR, 0);
1600
1601         /* CE */
1602         fw_data = (const __le32 *)
1603                 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1604         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1605         WREG32(CP_CE_UCODE_ADDR, 0);
1606         for (i = 0; i < fw_size; i++)
1607                 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1608         WREG32(CP_CE_UCODE_ADDR, 0);
1609
1610         /* ME */
1611         fw_data = (const __be32 *)
1612                 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1613         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1614         WREG32(CP_ME_RAM_WADDR, 0);
1615         for (i = 0; i < fw_size; i++)
1616                 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1617         WREG32(CP_ME_RAM_WADDR, 0);
1618
1619
1620         WREG32(CP_PFP_UCODE_ADDR, 0);
1621         WREG32(CP_CE_UCODE_ADDR, 0);
1622         WREG32(CP_ME_RAM_WADDR, 0);
1623         WREG32(CP_ME_RAM_RADDR, 0);
1624         return 0;
1625 }
1626
1627 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1628 {
1629         const struct cs_section_def *sect = NULL;
1630         const struct cs_extent_def *ext = NULL;
1631         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1632         int r, i;
1633
1634         r = amdgpu_ring_alloc(ring, 7 + 4);
1635         if (r) {
1636                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1637                 return r;
1638         }
1639         amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1640         amdgpu_ring_write(ring, 0x1);
1641         amdgpu_ring_write(ring, 0x0);
1642         amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1643         amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1644         amdgpu_ring_write(ring, 0);
1645         amdgpu_ring_write(ring, 0);
1646
1647         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1648         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1649         amdgpu_ring_write(ring, 0xc000);
1650         amdgpu_ring_write(ring, 0xe000);
1651         amdgpu_ring_commit(ring);
1652
1653         gfx_v6_0_cp_gfx_enable(adev, true);
1654
1655         r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
1656         if (r) {
1657                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1658                 return r;
1659         }
1660
1661         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1662         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1663
1664         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1665                 for (ext = sect->section; ext->extent != NULL; ++ext) {
1666                         if (sect->id == SECT_CONTEXT) {
1667                                 amdgpu_ring_write(ring,
1668                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1669                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1670                                 for (i = 0; i < ext->reg_count; i++)
1671                                         amdgpu_ring_write(ring, ext->extent[i]);
1672                         }
1673                 }
1674         }
1675
1676         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1677         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1678
1679         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1680         amdgpu_ring_write(ring, 0);
1681
1682         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1683         amdgpu_ring_write(ring, 0x00000316);
1684         amdgpu_ring_write(ring, 0x0000000e);
1685         amdgpu_ring_write(ring, 0x00000010);
1686
1687         amdgpu_ring_commit(ring);
1688
1689         return 0;
1690 }
1691
1692 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1693 {
1694         struct amdgpu_ring *ring;
1695         u32 tmp;
1696         u32 rb_bufsz;
1697         int r;
1698         u64 rptr_addr;
1699
1700         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1701         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1702
1703         /* Set the write pointer delay */
1704         WREG32(CP_RB_WPTR_DELAY, 0);
1705
1706         WREG32(CP_DEBUG, 0);
1707         WREG32(SCRATCH_ADDR, 0);
1708
1709         /* ring 0 - compute and gfx */
1710         /* Set ring buffer size */
1711         ring = &adev->gfx.gfx_ring[0];
1712         rb_bufsz = order_base_2(ring->ring_size / 8);
1713         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1714
1715 #ifdef __BIG_ENDIAN
1716         tmp |= BUF_SWAP_32BIT;
1717 #endif
1718         WREG32(CP_RB0_CNTL, tmp);
1719
1720         /* Initialize the ring buffer's read and write pointers */
1721         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1722         ring->wptr = 0;
1723         WREG32(CP_RB0_WPTR, ring->wptr);
1724
1725         /* set the wb address whether it's enabled or not */
1726         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1727         WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1728         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1729
1730         WREG32(SCRATCH_UMSK, 0);
1731
1732         mdelay(1);
1733         WREG32(CP_RB0_CNTL, tmp);
1734
1735         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1736
1737         /* start the rings */
1738         gfx_v6_0_cp_gfx_start(adev);
1739         ring->ready = true;
1740         r = amdgpu_ring_test_ring(ring);
1741         if (r) {
1742                 ring->ready = false;
1743                 return r;
1744         }
1745
1746         return 0;
1747 }
1748
1749 static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
1750 {
1751         return ring->adev->wb.wb[ring->rptr_offs];
1752 }
1753
1754 static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
1755 {
1756         struct amdgpu_device *adev = ring->adev;
1757
1758         if (ring == &adev->gfx.gfx_ring[0])
1759                 return RREG32(CP_RB0_WPTR);
1760         else if (ring == &adev->gfx.compute_ring[0])
1761                 return RREG32(CP_RB1_WPTR);
1762         else if (ring == &adev->gfx.compute_ring[1])
1763                 return RREG32(CP_RB2_WPTR);
1764         else
1765                 BUG();
1766 }
1767
1768 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1769 {
1770         struct amdgpu_device *adev = ring->adev;
1771
1772         WREG32(CP_RB0_WPTR, ring->wptr);
1773         (void)RREG32(CP_RB0_WPTR);
1774 }
1775
1776 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1777 {
1778         struct amdgpu_device *adev = ring->adev;
1779
1780         if (ring == &adev->gfx.compute_ring[0]) {
1781                 WREG32(CP_RB1_WPTR, ring->wptr);
1782                 (void)RREG32(CP_RB1_WPTR);
1783         } else if (ring == &adev->gfx.compute_ring[1]) {
1784                 WREG32(CP_RB2_WPTR, ring->wptr);
1785                 (void)RREG32(CP_RB2_WPTR);
1786         } else {
1787                 BUG();
1788         }
1789
1790 }
1791
1792 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1793 {
1794         struct amdgpu_ring *ring;
1795         u32 tmp;
1796         u32 rb_bufsz;
1797         int r;
1798         u64 rptr_addr;
1799
1800         /* ring1  - compute only */
1801         /* Set ring buffer size */
1802
1803         ring = &adev->gfx.compute_ring[0];
1804         rb_bufsz = order_base_2(ring->ring_size / 8);
1805         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1806 #ifdef __BIG_ENDIAN
1807         tmp |= BUF_SWAP_32BIT;
1808 #endif
1809         WREG32(CP_RB1_CNTL, tmp);
1810
1811         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1812         ring->wptr = 0;
1813         WREG32(CP_RB1_WPTR, ring->wptr);
1814
1815         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1816         WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1817         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1818
1819         mdelay(1);
1820         WREG32(CP_RB1_CNTL, tmp);
1821         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1822
1823         ring = &adev->gfx.compute_ring[1];
1824         rb_bufsz = order_base_2(ring->ring_size / 8);
1825         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1826 #ifdef __BIG_ENDIAN
1827         tmp |= BUF_SWAP_32BIT;
1828 #endif
1829         WREG32(CP_RB2_CNTL, tmp);
1830
1831         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1832         ring->wptr = 0;
1833         WREG32(CP_RB2_WPTR, ring->wptr);
1834         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1835         WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1836         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1837
1838         mdelay(1);
1839         WREG32(CP_RB2_CNTL, tmp);
1840         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1841
1842         adev->gfx.compute_ring[0].ready = true;
1843         adev->gfx.compute_ring[1].ready = true;
1844
1845         r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]);
1846         if (r) {
1847                 adev->gfx.compute_ring[0].ready = false;
1848                 return r;
1849         }
1850
1851         r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1852         if (r) {
1853                 adev->gfx.compute_ring[1].ready = false;
1854                 return r;
1855         }
1856
1857         return 0;
1858 }
1859
1860 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
1861 {
1862         gfx_v6_0_cp_gfx_enable(adev, enable);
1863 }
1864
1865 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1866 {
1867         return gfx_v6_0_cp_gfx_load_microcode(adev);
1868 }
1869
1870 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1871                                                bool enable)
1872 {
1873         u32 tmp = RREG32(CP_INT_CNTL_RING0);
1874         u32 mask;
1875         int i;
1876
1877         if (enable)
1878                 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1879         else
1880                 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1881         WREG32(CP_INT_CNTL_RING0, tmp);
1882
1883         if (!enable) {
1884                 /* read a gfx register */
1885                 tmp = RREG32(DB_DEPTH_INFO);
1886
1887                 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1888                 for (i = 0; i < adev->usec_timeout; i++) {
1889                         if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1890                                 break;
1891                         udelay(1);
1892                 }
1893         }
1894 }
1895
1896 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
1897 {
1898         int r;
1899
1900         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
1901
1902         r = gfx_v6_0_cp_load_microcode(adev);
1903         if (r)
1904                 return r;
1905
1906         r = gfx_v6_0_cp_gfx_resume(adev);
1907         if (r)
1908                 return r;
1909         r = gfx_v6_0_cp_compute_resume(adev);
1910         if (r)
1911                 return r;
1912
1913         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
1914
1915         return 0;
1916 }
1917
1918 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1919 {
1920         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1921         uint32_t seq = ring->fence_drv.sync_seq;
1922         uint64_t addr = ring->fence_drv.gpu_addr;
1923
1924         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1925         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
1926                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
1927                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
1928         amdgpu_ring_write(ring, addr & 0xfffffffc);
1929         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1930         amdgpu_ring_write(ring, seq);
1931         amdgpu_ring_write(ring, 0xffffffff);
1932         amdgpu_ring_write(ring, 4); /* poll interval */
1933
1934         if (usepfp) {
1935                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1936                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1937                 amdgpu_ring_write(ring, 0);
1938                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1939                 amdgpu_ring_write(ring, 0);
1940         }
1941 }
1942
1943 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1944                                         unsigned vm_id, uint64_t pd_addr)
1945 {
1946         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1947
1948         /* write new base address */
1949         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1950         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1951                                  WRITE_DATA_DST_SEL(0)));
1952         if (vm_id < 8) {
1953                 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1954         } else {
1955                 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1956         }
1957         amdgpu_ring_write(ring, 0);
1958         amdgpu_ring_write(ring, pd_addr >> 12);
1959
1960         /* bits 0-15 are the VM contexts0-15 */
1961         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1962         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1963                                  WRITE_DATA_DST_SEL(0)));
1964         amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1965         amdgpu_ring_write(ring, 0);
1966         amdgpu_ring_write(ring, 1 << vm_id);
1967
1968         /* wait for the invalidate to complete */
1969         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1970         amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |  /* always */
1971                                  WAIT_REG_MEM_ENGINE(0))); /* me */
1972         amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1973         amdgpu_ring_write(ring, 0);
1974         amdgpu_ring_write(ring, 0); /* ref */
1975         amdgpu_ring_write(ring, 0); /* mask */
1976         amdgpu_ring_write(ring, 0x20); /* poll interval */
1977
1978         if (usepfp) {
1979                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
1980                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1981                 amdgpu_ring_write(ring, 0x0);
1982
1983                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1984                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1985                 amdgpu_ring_write(ring, 0);
1986                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1987                 amdgpu_ring_write(ring, 0);
1988         }
1989 }
1990
1991
1992 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
1993 {
1994         int r;
1995
1996         if (adev->gfx.rlc.save_restore_obj) {
1997                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
1998                 if (unlikely(r != 0))
1999                         dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
2000                 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
2001                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2002
2003                 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
2004                 adev->gfx.rlc.save_restore_obj = NULL;
2005         }
2006
2007         if (adev->gfx.rlc.clear_state_obj) {
2008                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2009                 if (unlikely(r != 0))
2010                         dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
2011                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
2012                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2013
2014                 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2015                 adev->gfx.rlc.clear_state_obj = NULL;
2016         }
2017
2018         if (adev->gfx.rlc.cp_table_obj) {
2019                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
2020                 if (unlikely(r != 0))
2021                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
2022                 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
2023                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
2024
2025                 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
2026                 adev->gfx.rlc.cp_table_obj = NULL;
2027         }
2028 }
2029
2030 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2031 {
2032         const u32 *src_ptr;
2033         volatile u32 *dst_ptr;
2034         u32 dws, i;
2035         u64 reg_list_mc_addr;
2036         const struct cs_section_def *cs_data;
2037         int r;
2038
2039         adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2040         adev->gfx.rlc.reg_list_size =
2041                         (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2042
2043         adev->gfx.rlc.cs_data = si_cs_data;
2044         src_ptr = adev->gfx.rlc.reg_list;
2045         dws = adev->gfx.rlc.reg_list_size;
2046         cs_data = adev->gfx.rlc.cs_data;
2047
2048         if (src_ptr) {
2049                 /* save restore block */
2050                 if (adev->gfx.rlc.save_restore_obj == NULL) {
2051
2052                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2053                                              AMDGPU_GEM_DOMAIN_VRAM,
2054                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2055                                              NULL, NULL,
2056                                              &adev->gfx.rlc.save_restore_obj);
2057
2058                         if (r) {
2059                                 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2060                                 return r;
2061                         }
2062                 }
2063
2064                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2065                 if (unlikely(r != 0)) {
2066                         gfx_v6_0_rlc_fini(adev);
2067                         return r;
2068                 }
2069                 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2070                                   &adev->gfx.rlc.save_restore_gpu_addr);
2071                 if (r) {
2072                         amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2073                         dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2074                         gfx_v6_0_rlc_fini(adev);
2075                         return r;
2076                 }
2077
2078                 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2079                 if (r) {
2080                         dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2081                         gfx_v6_0_rlc_fini(adev);
2082                         return r;
2083                 }
2084                 /* write the sr buffer */
2085                 dst_ptr = adev->gfx.rlc.sr_ptr;
2086                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2087                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2088                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2089                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2090         }
2091
2092         if (cs_data) {
2093                 /* clear state block */
2094                 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2095                 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2096
2097                 if (adev->gfx.rlc.clear_state_obj == NULL) {
2098                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2099                                              AMDGPU_GEM_DOMAIN_VRAM,
2100                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2101                                              NULL, NULL,
2102                                              &adev->gfx.rlc.clear_state_obj);
2103
2104                         if (r) {
2105                                 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2106                                 gfx_v6_0_rlc_fini(adev);
2107                                 return r;
2108                         }
2109                 }
2110                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2111                 if (unlikely(r != 0)) {
2112                         gfx_v6_0_rlc_fini(adev);
2113                         return r;
2114                 }
2115                 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2116                                   &adev->gfx.rlc.clear_state_gpu_addr);
2117                 if (r) {
2118                         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2119                         dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2120                         gfx_v6_0_rlc_fini(adev);
2121                         return r;
2122                 }
2123
2124                 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2125                 if (r) {
2126                         dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2127                         gfx_v6_0_rlc_fini(adev);
2128                         return r;
2129                 }
2130                 /* set up the cs buffer */
2131                 dst_ptr = adev->gfx.rlc.cs_ptr;
2132                 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2133                 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2134                 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2135                 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2136                 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2137                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2138                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2139         }
2140
2141         return 0;
2142 }
2143
2144 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2145 {
2146         u32 tmp;
2147
2148         tmp = RREG32(RLC_LB_CNTL);
2149         if (enable)
2150                 tmp |= LOAD_BALANCE_ENABLE;
2151         else
2152                 tmp &= ~LOAD_BALANCE_ENABLE;
2153         WREG32(RLC_LB_CNTL, tmp);
2154
2155         if (!enable) {
2156                 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2157                 WREG32(SPI_LB_CU_MASK, 0x00ff);
2158         }
2159
2160 }
2161
2162 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2163 {
2164         int i;
2165
2166         for (i = 0; i < adev->usec_timeout; i++) {
2167                 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
2168                         break;
2169                 udelay(1);
2170         }
2171
2172         for (i = 0; i < adev->usec_timeout; i++) {
2173                 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
2174                         break;
2175                 udelay(1);
2176         }
2177 }
2178
2179 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2180 {
2181         u32 tmp;
2182
2183         tmp = RREG32(RLC_CNTL);
2184         if (tmp != rlc)
2185                 WREG32(RLC_CNTL, rlc);
2186 }
2187
2188 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2189 {
2190         u32 data, orig;
2191
2192         orig = data = RREG32(RLC_CNTL);
2193
2194         if (data & RLC_ENABLE) {
2195                 data &= ~RLC_ENABLE;
2196                 WREG32(RLC_CNTL, data);
2197
2198                 gfx_v6_0_wait_for_rlc_serdes(adev);
2199         }
2200
2201         return orig;
2202 }
2203
2204 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2205 {
2206         WREG32(RLC_CNTL, 0);
2207
2208         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2209         gfx_v6_0_wait_for_rlc_serdes(adev);
2210 }
2211
2212 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2213 {
2214         WREG32(RLC_CNTL, RLC_ENABLE);
2215
2216         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2217
2218         udelay(50);
2219 }
2220
2221 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2222 {
2223         u32 tmp = RREG32(GRBM_SOFT_RESET);
2224
2225         tmp |= SOFT_RESET_RLC;
2226         WREG32(GRBM_SOFT_RESET, tmp);
2227         udelay(50);
2228         tmp &= ~SOFT_RESET_RLC;
2229         WREG32(GRBM_SOFT_RESET, tmp);
2230         udelay(50);
2231 }
2232
2233 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2234 {
2235         u32 tmp;
2236
2237         /* Enable LBPW only for DDR3 */
2238         tmp = RREG32(MC_SEQ_MISC0);
2239         if ((tmp & 0xF0000000) == 0xB0000000)
2240                 return true;
2241         return false;
2242 }
2243 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2244 {
2245 }
2246
2247 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2248 {
2249         u32 i;
2250         const struct rlc_firmware_header_v1_0 *hdr;
2251         const __le32 *fw_data;
2252         u32 fw_size;
2253
2254
2255         if (!adev->gfx.rlc_fw)
2256                 return -EINVAL;
2257
2258         gfx_v6_0_rlc_stop(adev);
2259         gfx_v6_0_rlc_reset(adev);
2260         gfx_v6_0_init_pg(adev);
2261         gfx_v6_0_init_cg(adev);
2262
2263         WREG32(RLC_RL_BASE, 0);
2264         WREG32(RLC_RL_SIZE, 0);
2265         WREG32(RLC_LB_CNTL, 0);
2266         WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2267         WREG32(RLC_LB_CNTR_INIT, 0);
2268         WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
2269
2270         WREG32(RLC_MC_CNTL, 0);
2271         WREG32(RLC_UCODE_CNTL, 0);
2272
2273         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2274         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2275         fw_data = (const __le32 *)
2276                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2277
2278         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2279
2280         for (i = 0; i < fw_size; i++) {
2281                 WREG32(RLC_UCODE_ADDR, i);
2282                 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
2283         }
2284         WREG32(RLC_UCODE_ADDR, 0);
2285
2286         gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2287         gfx_v6_0_rlc_start(adev);
2288
2289         return 0;
2290 }
2291
2292 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2293 {
2294         u32 data, orig, tmp;
2295
2296         orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
2297
2298         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2299                 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2300
2301                 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
2302
2303                 tmp = gfx_v6_0_halt_rlc(adev);
2304
2305                 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2306                 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2307                 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
2308
2309                 gfx_v6_0_wait_for_rlc_serdes(adev);
2310                 gfx_v6_0_update_rlc(adev, tmp);
2311
2312                 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
2313
2314                 data |= CGCG_EN | CGLS_EN;
2315         } else {
2316                 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2317
2318                 RREG32(CB_CGTT_SCLK_CTRL);
2319                 RREG32(CB_CGTT_SCLK_CTRL);
2320                 RREG32(CB_CGTT_SCLK_CTRL);
2321                 RREG32(CB_CGTT_SCLK_CTRL);
2322
2323                 data &= ~(CGCG_EN | CGLS_EN);
2324         }
2325
2326         if (orig != data)
2327                 WREG32(RLC_CGCG_CGLS_CTRL, data);
2328
2329 }
2330
2331 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2332 {
2333
2334         u32 data, orig, tmp = 0;
2335
2336         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2337                 orig = data = RREG32(CGTS_SM_CTRL_REG);
2338                 data = 0x96940200;
2339                 if (orig != data)
2340                         WREG32(CGTS_SM_CTRL_REG, data);
2341
2342                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2343                         orig = data = RREG32(CP_MEM_SLP_CNTL);
2344                         data |= CP_MEM_LS_EN;
2345                         if (orig != data)
2346                                 WREG32(CP_MEM_SLP_CNTL, data);
2347                 }
2348
2349                 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2350                 data &= 0xffffffc0;
2351                 if (orig != data)
2352                         WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2353
2354                 tmp = gfx_v6_0_halt_rlc(adev);
2355
2356                 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2357                 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2358                 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
2359
2360                 gfx_v6_0_update_rlc(adev, tmp);
2361         } else {
2362                 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2363                 data |= 0x00000003;
2364                 if (orig != data)
2365                         WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2366
2367                 data = RREG32(CP_MEM_SLP_CNTL);
2368                 if (data & CP_MEM_LS_EN) {
2369                         data &= ~CP_MEM_LS_EN;
2370                         WREG32(CP_MEM_SLP_CNTL, data);
2371                 }
2372                 orig = data = RREG32(CGTS_SM_CTRL_REG);
2373                 data |= LS_OVERRIDE | OVERRIDE;
2374                 if (orig != data)
2375                         WREG32(CGTS_SM_CTRL_REG, data);
2376
2377                 tmp = gfx_v6_0_halt_rlc(adev);
2378
2379                 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2380                 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2381                 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
2382
2383                 gfx_v6_0_update_rlc(adev, tmp);
2384         }
2385 }
2386 /*
2387 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2388                                bool enable)
2389 {
2390         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2391         if (enable) {
2392                 gfx_v6_0_enable_mgcg(adev, true);
2393                 gfx_v6_0_enable_cgcg(adev, true);
2394         } else {
2395                 gfx_v6_0_enable_cgcg(adev, false);
2396                 gfx_v6_0_enable_mgcg(adev, false);
2397         }
2398         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2399 }
2400 */
2401 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2402                                                 bool enable)
2403 {
2404 }
2405
2406 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2407                                                 bool enable)
2408 {
2409 }
2410
2411 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2412 {
2413         u32 data, orig;
2414
2415         orig = data = RREG32(RLC_PG_CNTL);
2416         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2417                 data &= ~0x8000;
2418         else
2419                 data |= 0x8000;
2420         if (orig != data)
2421                 WREG32(RLC_PG_CNTL, data);
2422 }
2423
2424 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2425 {
2426 }
2427 /*
2428 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2429 {
2430         const __le32 *fw_data;
2431         volatile u32 *dst_ptr;
2432         int me, i, max_me = 4;
2433         u32 bo_offset = 0;
2434         u32 table_offset, table_size;
2435
2436         if (adev->asic_type == CHIP_KAVERI)
2437                 max_me = 5;
2438
2439         if (adev->gfx.rlc.cp_table_ptr == NULL)
2440                 return;
2441
2442         dst_ptr = adev->gfx.rlc.cp_table_ptr;
2443         for (me = 0; me < max_me; me++) {
2444                 if (me == 0) {
2445                         const struct gfx_firmware_header_v1_0 *hdr =
2446                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2447                         fw_data = (const __le32 *)
2448                                 (adev->gfx.ce_fw->data +
2449                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2450                         table_offset = le32_to_cpu(hdr->jt_offset);
2451                         table_size = le32_to_cpu(hdr->jt_size);
2452                 } else if (me == 1) {
2453                         const struct gfx_firmware_header_v1_0 *hdr =
2454                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2455                         fw_data = (const __le32 *)
2456                                 (adev->gfx.pfp_fw->data +
2457                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2458                         table_offset = le32_to_cpu(hdr->jt_offset);
2459                         table_size = le32_to_cpu(hdr->jt_size);
2460                 } else if (me == 2) {
2461                         const struct gfx_firmware_header_v1_0 *hdr =
2462                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2463                         fw_data = (const __le32 *)
2464                                 (adev->gfx.me_fw->data +
2465                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2466                         table_offset = le32_to_cpu(hdr->jt_offset);
2467                         table_size = le32_to_cpu(hdr->jt_size);
2468                 } else if (me == 3) {
2469                         const struct gfx_firmware_header_v1_0 *hdr =
2470                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2471                         fw_data = (const __le32 *)
2472                                 (adev->gfx.mec_fw->data +
2473                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2474                         table_offset = le32_to_cpu(hdr->jt_offset);
2475                         table_size = le32_to_cpu(hdr->jt_size);
2476                 } else {
2477                         const struct gfx_firmware_header_v1_0 *hdr =
2478                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2479                         fw_data = (const __le32 *)
2480                                 (adev->gfx.mec2_fw->data +
2481                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2482                         table_offset = le32_to_cpu(hdr->jt_offset);
2483                         table_size = le32_to_cpu(hdr->jt_size);
2484                 }
2485
2486                 for (i = 0; i < table_size; i ++) {
2487                         dst_ptr[bo_offset + i] =
2488                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2489                 }
2490
2491                 bo_offset += table_size;
2492         }
2493 }
2494 */
2495 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2496                                      bool enable)
2497 {
2498
2499         u32 tmp;
2500
2501         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2502                 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
2503                 WREG32(RLC_TTOP_D, tmp);
2504
2505                 tmp = RREG32(RLC_PG_CNTL);
2506                 tmp |= GFX_PG_ENABLE;
2507                 WREG32(RLC_PG_CNTL, tmp);
2508
2509                 tmp = RREG32(RLC_AUTO_PG_CTRL);
2510                 tmp |= AUTO_PG_EN;
2511                 WREG32(RLC_AUTO_PG_CTRL, tmp);
2512         } else {
2513                 tmp = RREG32(RLC_AUTO_PG_CTRL);
2514                 tmp &= ~AUTO_PG_EN;
2515                 WREG32(RLC_AUTO_PG_CTRL, tmp);
2516
2517                 tmp = RREG32(DB_RENDER_CONTROL);
2518         }
2519 }
2520
2521 static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2522                                          u32 se, u32 sh)
2523 {
2524
2525         u32 mask = 0, tmp, tmp1;
2526         int i;
2527
2528         mutex_lock(&adev->grbm_idx_mutex);
2529         gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2530         tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2531         tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2532         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2533         mutex_unlock(&adev->grbm_idx_mutex);
2534
2535         tmp &= 0xffff0000;
2536
2537         tmp |= tmp1;
2538         tmp >>= 16;
2539
2540         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2541                 mask <<= 1;
2542                 mask |= 1;
2543         }
2544
2545         return (~tmp) & mask;
2546 }
2547
2548 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2549 {
2550         u32 i, j, k, active_cu_number = 0;
2551
2552         u32 mask, counter, cu_bitmap;
2553         u32 tmp = 0;
2554
2555         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2556                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2557                         mask = 1;
2558                         cu_bitmap = 0;
2559                         counter  = 0;
2560                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2561                                 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2562                                         if (counter < 2)
2563                                                 cu_bitmap |= mask;
2564                                         counter++;
2565                                 }
2566                                 mask <<= 1;
2567                         }
2568
2569                         active_cu_number += counter;
2570                         tmp |= (cu_bitmap << (i * 16 + j * 8));
2571                 }
2572         }
2573
2574         WREG32(RLC_PG_AO_CU_MASK, tmp);
2575
2576         tmp = RREG32(RLC_MAX_PG_CU);
2577         tmp &= ~MAX_PU_CU_MASK;
2578         tmp |= MAX_PU_CU(active_cu_number);
2579         WREG32(RLC_MAX_PG_CU, tmp);
2580 }
2581
2582 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2583                                             bool enable)
2584 {
2585         u32 data, orig;
2586
2587         orig = data = RREG32(RLC_PG_CNTL);
2588         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2589                 data |= STATIC_PER_CU_PG_ENABLE;
2590         else
2591                 data &= ~STATIC_PER_CU_PG_ENABLE;
2592         if (orig != data)
2593                 WREG32(RLC_PG_CNTL, data);
2594 }
2595
2596 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2597                                              bool enable)
2598 {
2599         u32 data, orig;
2600
2601         orig = data = RREG32(RLC_PG_CNTL);
2602         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2603                 data |= DYN_PER_CU_PG_ENABLE;
2604         else
2605                 data &= ~DYN_PER_CU_PG_ENABLE;
2606         if (orig != data)
2607                 WREG32(RLC_PG_CNTL, data);
2608 }
2609
2610 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2611 {
2612         u32 tmp;
2613
2614         WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2615
2616         tmp = RREG32(RLC_PG_CNTL);
2617         tmp |= GFX_PG_SRC;
2618         WREG32(RLC_PG_CNTL, tmp);
2619
2620         WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2621
2622         tmp = RREG32(RLC_AUTO_PG_CTRL);
2623
2624         tmp &= ~GRBM_REG_SGIT_MASK;
2625         tmp |= GRBM_REG_SGIT(0x700);
2626         tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
2627         WREG32(RLC_AUTO_PG_CTRL, tmp);
2628 }
2629
2630 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2631 {
2632         gfx_v6_0_enable_gfx_cgpg(adev, enable);
2633         gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2634         gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2635 }
2636
2637 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2638 {
2639         u32 count = 0;
2640         const struct cs_section_def *sect = NULL;
2641         const struct cs_extent_def *ext = NULL;
2642
2643         if (adev->gfx.rlc.cs_data == NULL)
2644                 return 0;
2645
2646         /* begin clear state */
2647         count += 2;
2648         /* context control state */
2649         count += 3;
2650
2651         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2652                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2653                         if (sect->id == SECT_CONTEXT)
2654                                 count += 2 + ext->reg_count;
2655                         else
2656                                 return 0;
2657                 }
2658         }
2659         /* pa_sc_raster_config */
2660         count += 3;
2661         /* end clear state */
2662         count += 2;
2663         /* clear state */
2664         count += 2;
2665
2666         return count;
2667 }
2668
2669 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2670                                     volatile u32 *buffer)
2671 {
2672         u32 count = 0, i;
2673         const struct cs_section_def *sect = NULL;
2674         const struct cs_extent_def *ext = NULL;
2675
2676         if (adev->gfx.rlc.cs_data == NULL)
2677                 return;
2678         if (buffer == NULL)
2679                 return;
2680
2681         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2682         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2683
2684         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2685         buffer[count++] = cpu_to_le32(0x80000000);
2686         buffer[count++] = cpu_to_le32(0x80000000);
2687
2688         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2689                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2690                         if (sect->id == SECT_CONTEXT) {
2691                                 buffer[count++] =
2692                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2693                                 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2694                                 for (i = 0; i < ext->reg_count; i++)
2695                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
2696                         } else {
2697                                 return;
2698                         }
2699                 }
2700         }
2701
2702         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2703         buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2704
2705         switch (adev->asic_type) {
2706         case CHIP_TAHITI:
2707         case CHIP_PITCAIRN:
2708                 buffer[count++] = cpu_to_le32(0x2a00126a);
2709                 break;
2710         case CHIP_VERDE:
2711                 buffer[count++] = cpu_to_le32(0x0000124a);
2712                 break;
2713         case CHIP_OLAND:
2714                 buffer[count++] = cpu_to_le32(0x00000082);
2715                 break;
2716         case CHIP_HAINAN:
2717                 buffer[count++] = cpu_to_le32(0x00000000);
2718                 break;
2719         default:
2720                 buffer[count++] = cpu_to_le32(0x00000000);
2721                 break;
2722         }
2723
2724         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2725         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2726
2727         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2728         buffer[count++] = cpu_to_le32(0);
2729 }
2730
2731 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2732 {
2733         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2734                               AMD_PG_SUPPORT_GFX_SMG |
2735                               AMD_PG_SUPPORT_GFX_DMG |
2736                               AMD_PG_SUPPORT_CP |
2737                               AMD_PG_SUPPORT_GDS |
2738                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2739                 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2740                 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2741                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2742                         gfx_v6_0_init_gfx_cgpg(adev);
2743                         gfx_v6_0_enable_cp_pg(adev, true);
2744                         gfx_v6_0_enable_gds_pg(adev, true);
2745                 } else {
2746                         WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2747                         WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2748
2749                 }
2750                 gfx_v6_0_init_ao_cu_mask(adev);
2751                 gfx_v6_0_update_gfx_pg(adev, true);
2752         } else {
2753
2754                 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2755                 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2756         }
2757 }
2758
2759 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2760 {
2761         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2762                               AMD_PG_SUPPORT_GFX_SMG |
2763                               AMD_PG_SUPPORT_GFX_DMG |
2764                               AMD_PG_SUPPORT_CP |
2765                               AMD_PG_SUPPORT_GDS |
2766                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2767                 gfx_v6_0_update_gfx_pg(adev, false);
2768                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2769                         gfx_v6_0_enable_cp_pg(adev, false);
2770                         gfx_v6_0_enable_gds_pg(adev, false);
2771                 }
2772         }
2773 }
2774
2775 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2776 {
2777         uint64_t clock;
2778
2779         mutex_lock(&adev->gfx.gpu_clock_mutex);
2780         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2781         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
2782                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2783         mutex_unlock(&adev->gfx.gpu_clock_mutex);
2784         return clock;
2785 }
2786
2787 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2788 {
2789         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2790         amdgpu_ring_write(ring, 0x80000000);
2791         amdgpu_ring_write(ring, 0);
2792 }
2793
2794 static unsigned gfx_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
2795 {
2796         return
2797                 6; /* gfx_v6_0_ring_emit_ib */
2798 }
2799
2800 static unsigned gfx_v6_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
2801 {
2802         return
2803                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2804                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2805                 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2806                 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
2807                 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
2808                 3; /* gfx_v6_ring_emit_cntxcntl */
2809 }
2810
2811 static unsigned gfx_v6_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring)
2812 {
2813         return
2814                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2815                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2816                 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
2817                 17 + /* gfx_v6_0_ring_emit_vm_flush */
2818                 14 + 14 + 14; /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2819 }
2820
2821 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2822         .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2823         .select_se_sh = &gfx_v6_0_select_se_sh,
2824 };
2825
2826 static int gfx_v6_0_early_init(void *handle)
2827 {
2828         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2829
2830         adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
2831         adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
2832         adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
2833         gfx_v6_0_set_ring_funcs(adev);
2834         gfx_v6_0_set_irq_funcs(adev);
2835
2836         return 0;
2837 }
2838
2839 static int gfx_v6_0_sw_init(void *handle)
2840 {
2841         struct amdgpu_ring *ring;
2842         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2843         int i, r;
2844
2845         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
2846         if (r)
2847                 return r;
2848
2849         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
2850         if (r)
2851                 return r;
2852
2853         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2854         if (r)
2855                 return r;
2856
2857         gfx_v6_0_scratch_init(adev);
2858
2859         r = gfx_v6_0_init_microcode(adev);
2860         if (r) {
2861                 DRM_ERROR("Failed to load gfx firmware!\n");
2862                 return r;
2863         }
2864
2865         r = gfx_v6_0_rlc_init(adev);
2866         if (r) {
2867                 DRM_ERROR("Failed to init rlc BOs!\n");
2868                 return r;
2869         }
2870
2871         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2872                 ring = &adev->gfx.gfx_ring[i];
2873                 ring->ring_obj = NULL;
2874                 sprintf(ring->name, "gfx");
2875                 r = amdgpu_ring_init(adev, ring, 1024,
2876                                      0x80000000, 0xf,
2877                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
2878                                      AMDGPU_RING_TYPE_GFX);
2879                 if (r)
2880                         return r;
2881         }
2882
2883         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2884                 unsigned irq_type;
2885
2886                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2887                         DRM_ERROR("Too many (%d) compute rings!\n", i);
2888                         break;
2889                 }
2890                 ring = &adev->gfx.compute_ring[i];
2891                 ring->ring_obj = NULL;
2892                 ring->use_doorbell = false;
2893                 ring->doorbell_index = 0;
2894                 ring->me = 1;
2895                 ring->pipe = i;
2896                 ring->queue = i;
2897                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
2898                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2899                 r = amdgpu_ring_init(adev, ring, 1024,
2900                                      0x80000000, 0xf,
2901                                      &adev->gfx.eop_irq, irq_type,
2902                                      AMDGPU_RING_TYPE_COMPUTE);
2903                 if (r)
2904                         return r;
2905         }
2906
2907         return r;
2908 }
2909
2910 static int gfx_v6_0_sw_fini(void *handle)
2911 {
2912         int i;
2913         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2914
2915         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
2916         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
2917         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
2918
2919         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2920                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2921         for (i = 0; i < adev->gfx.num_compute_rings; i++)
2922                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2923
2924         gfx_v6_0_rlc_fini(adev);
2925
2926         return 0;
2927 }
2928
2929 static int gfx_v6_0_hw_init(void *handle)
2930 {
2931         int r;
2932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2933
2934         gfx_v6_0_gpu_init(adev);
2935
2936         r = gfx_v6_0_rlc_resume(adev);
2937         if (r)
2938                 return r;
2939
2940         r = gfx_v6_0_cp_resume(adev);
2941         if (r)
2942                 return r;
2943
2944         adev->gfx.ce_ram_size = 0x8000;
2945
2946         return r;
2947 }
2948
2949 static int gfx_v6_0_hw_fini(void *handle)
2950 {
2951         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2952
2953         gfx_v6_0_cp_enable(adev, false);
2954         gfx_v6_0_rlc_stop(adev);
2955         gfx_v6_0_fini_pg(adev);
2956
2957         return 0;
2958 }
2959
2960 static int gfx_v6_0_suspend(void *handle)
2961 {
2962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2963
2964         return gfx_v6_0_hw_fini(adev);
2965 }
2966
2967 static int gfx_v6_0_resume(void *handle)
2968 {
2969         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2970
2971         return gfx_v6_0_hw_init(adev);
2972 }
2973
2974 static bool gfx_v6_0_is_idle(void *handle)
2975 {
2976         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2977
2978         if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2979                 return false;
2980         else
2981                 return true;
2982 }
2983
2984 static int gfx_v6_0_wait_for_idle(void *handle)
2985 {
2986         unsigned i;
2987         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2988
2989         for (i = 0; i < adev->usec_timeout; i++) {
2990                 if (gfx_v6_0_is_idle(handle))
2991                         return 0;
2992                 udelay(1);
2993         }
2994         return -ETIMEDOUT;
2995 }
2996
2997 static int gfx_v6_0_soft_reset(void *handle)
2998 {
2999         return 0;
3000 }
3001
3002 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3003                                                  enum amdgpu_interrupt_state state)
3004 {
3005         u32 cp_int_cntl;
3006
3007         switch (state) {
3008         case AMDGPU_IRQ_STATE_DISABLE:
3009                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3010                 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3011                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3012                 break;
3013         case AMDGPU_IRQ_STATE_ENABLE:
3014                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3015                 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3016                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3017                 break;
3018         default:
3019                 break;
3020         }
3021 }
3022
3023 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3024                                                      int ring,
3025                                                      enum amdgpu_interrupt_state state)
3026 {
3027         u32 cp_int_cntl;
3028         switch (state){
3029         case AMDGPU_IRQ_STATE_DISABLE:
3030                 if (ring == 0) {
3031                         cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
3032                         cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3033                         WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
3034                         break;
3035                 } else {
3036                         cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
3037                         cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3038                         WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
3039                         break;
3040
3041                 }
3042         case AMDGPU_IRQ_STATE_ENABLE:
3043                 if (ring == 0) {
3044                         cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
3045                         cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3046                         WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
3047                         break;
3048                 } else {
3049                         cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
3050                         cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3051                         WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
3052                         break;
3053
3054                 }
3055
3056         default:
3057                 BUG();
3058                 break;
3059
3060         }
3061 }
3062
3063 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3064                                              struct amdgpu_irq_src *src,
3065                                              unsigned type,
3066                                              enum amdgpu_interrupt_state state)
3067 {
3068         u32 cp_int_cntl;
3069
3070         switch (state) {
3071         case AMDGPU_IRQ_STATE_DISABLE:
3072                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3073                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3074                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3075                 break;
3076         case AMDGPU_IRQ_STATE_ENABLE:
3077                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3078                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3079                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3080                 break;
3081         default:
3082                 break;
3083         }
3084
3085         return 0;
3086 }
3087
3088 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3089                                               struct amdgpu_irq_src *src,
3090                                               unsigned type,
3091                                               enum amdgpu_interrupt_state state)
3092 {
3093         u32 cp_int_cntl;
3094
3095         switch (state) {
3096         case AMDGPU_IRQ_STATE_DISABLE:
3097                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3098                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3099                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3100                 break;
3101         case AMDGPU_IRQ_STATE_ENABLE:
3102                 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3103                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3104                 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3105                 break;
3106         default:
3107                 break;
3108         }
3109
3110         return 0;
3111 }
3112
3113 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3114                                             struct amdgpu_irq_src *src,
3115                                             unsigned type,
3116                                             enum amdgpu_interrupt_state state)
3117 {
3118         switch (type) {
3119         case AMDGPU_CP_IRQ_GFX_EOP:
3120                 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3121                 break;
3122         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3123                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3124                 break;
3125         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3126                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3127                 break;
3128         default:
3129                 break;
3130         }
3131         return 0;
3132 }
3133
3134 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3135                             struct amdgpu_irq_src *source,
3136                             struct amdgpu_iv_entry *entry)
3137 {
3138         switch (entry->ring_id) {
3139         case 0:
3140                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3141                 break;
3142         case 1:
3143         case 2:
3144                 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]);
3145                 break;
3146         default:
3147                 break;
3148         }
3149         return 0;
3150 }
3151
3152 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3153                                  struct amdgpu_irq_src *source,
3154                                  struct amdgpu_iv_entry *entry)
3155 {
3156         DRM_ERROR("Illegal register access in command stream\n");
3157         schedule_work(&adev->reset_work);
3158         return 0;
3159 }
3160
3161 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3162                                   struct amdgpu_irq_src *source,
3163                                   struct amdgpu_iv_entry *entry)
3164 {
3165         DRM_ERROR("Illegal instruction in command stream\n");
3166         schedule_work(&adev->reset_work);
3167         return 0;
3168 }
3169
3170 static int gfx_v6_0_set_clockgating_state(void *handle,
3171                                           enum amd_clockgating_state state)
3172 {
3173         bool gate = false;
3174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3175
3176         if (state == AMD_CG_STATE_GATE)
3177                 gate = true;
3178
3179         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3180         if (gate) {
3181                 gfx_v6_0_enable_mgcg(adev, true);
3182                 gfx_v6_0_enable_cgcg(adev, true);
3183         } else {
3184                 gfx_v6_0_enable_cgcg(adev, false);
3185                 gfx_v6_0_enable_mgcg(adev, false);
3186         }
3187         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3188
3189         return 0;
3190 }
3191
3192 static int gfx_v6_0_set_powergating_state(void *handle,
3193                                           enum amd_powergating_state state)
3194 {
3195         bool gate = false;
3196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3197
3198         if (state == AMD_PG_STATE_GATE)
3199                 gate = true;
3200
3201         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3202                               AMD_PG_SUPPORT_GFX_SMG |
3203                               AMD_PG_SUPPORT_GFX_DMG |
3204                               AMD_PG_SUPPORT_CP |
3205                               AMD_PG_SUPPORT_GDS |
3206                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3207                 gfx_v6_0_update_gfx_pg(adev, gate);
3208                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3209                         gfx_v6_0_enable_cp_pg(adev, gate);
3210                         gfx_v6_0_enable_gds_pg(adev, gate);
3211                 }
3212         }
3213
3214         return 0;
3215 }
3216
3217 const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3218         .name = "gfx_v6_0",
3219         .early_init = gfx_v6_0_early_init,
3220         .late_init = NULL,
3221         .sw_init = gfx_v6_0_sw_init,
3222         .sw_fini = gfx_v6_0_sw_fini,
3223         .hw_init = gfx_v6_0_hw_init,
3224         .hw_fini = gfx_v6_0_hw_fini,
3225         .suspend = gfx_v6_0_suspend,
3226         .resume = gfx_v6_0_resume,
3227         .is_idle = gfx_v6_0_is_idle,
3228         .wait_for_idle = gfx_v6_0_wait_for_idle,
3229         .soft_reset = gfx_v6_0_soft_reset,
3230         .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3231         .set_powergating_state = gfx_v6_0_set_powergating_state,
3232 };
3233
3234 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3235         .get_rptr = gfx_v6_0_ring_get_rptr,
3236         .get_wptr = gfx_v6_0_ring_get_wptr,
3237         .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3238         .parse_cs = NULL,
3239         .emit_ib = gfx_v6_0_ring_emit_ib,
3240         .emit_fence = gfx_v6_0_ring_emit_fence,
3241         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3242         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3243         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3244         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3245         .test_ring = gfx_v6_0_ring_test_ring,
3246         .test_ib = gfx_v6_0_ring_test_ib,
3247         .insert_nop = amdgpu_ring_insert_nop,
3248         .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3249         .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3250         .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_gfx,
3251 };
3252
3253 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3254         .get_rptr = gfx_v6_0_ring_get_rptr,
3255         .get_wptr = gfx_v6_0_ring_get_wptr,
3256         .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3257         .parse_cs = NULL,
3258         .emit_ib = gfx_v6_0_ring_emit_ib,
3259         .emit_fence = gfx_v6_0_ring_emit_fence,
3260         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3261         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3262         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3263         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3264         .test_ring = gfx_v6_0_ring_test_ring,
3265         .test_ib = gfx_v6_0_ring_test_ib,
3266         .insert_nop = amdgpu_ring_insert_nop,
3267         .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3268         .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_compute,
3269 };
3270
3271 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3272 {
3273         int i;
3274
3275         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3276                 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3277         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3278                 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3279 }
3280
3281 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3282         .set = gfx_v6_0_set_eop_interrupt_state,
3283         .process = gfx_v6_0_eop_irq,
3284 };
3285
3286 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3287         .set = gfx_v6_0_set_priv_reg_fault_state,
3288         .process = gfx_v6_0_priv_reg_irq,
3289 };
3290
3291 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3292         .set = gfx_v6_0_set_priv_inst_fault_state,
3293         .process = gfx_v6_0_priv_inst_irq,
3294 };
3295
3296 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3297 {
3298         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3299         adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3300
3301         adev->gfx.priv_reg_irq.num_types = 1;
3302         adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3303
3304         adev->gfx.priv_inst_irq.num_types = 1;
3305         adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3306 }
3307
3308 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3309 {
3310         int i, j, k, counter, active_cu_number = 0;
3311         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3312         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3313
3314         memset(cu_info, 0, sizeof(*cu_info));
3315
3316         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3317                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3318                         mask = 1;
3319                         ao_bitmap = 0;
3320                         counter = 0;
3321                         bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3322                         cu_info->bitmap[i][j] = bitmap;
3323
3324                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3325                                 if (bitmap & mask) {
3326                                         if (counter < 2)
3327                                                 ao_bitmap |= mask;
3328                                         counter ++;
3329                                 }
3330                                 mask <<= 1;
3331                         }
3332                         active_cu_number += counter;
3333                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3334                 }
3335         }
3336
3337         cu_info->number = active_cu_number;
3338         cu_info->ao_cu_mask = ao_cu_mask;
3339 }