2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_ih.h"
26 #include "amdgpu_gfx.h"
27 #include "amdgpu_ucode.h"
28 #include "si/clearstate_si.h"
31 #define GFX6_NUM_GFX_RINGS 1
32 #define GFX6_NUM_COMPUTE_RINGS 2
33 #define STATIC_PER_CU_PG_ENABLE (1 << 3)
34 #define DYN_PER_CU_PG_ENABLE (1 << 2)
35 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
36 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
39 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
40 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
45 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
46 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
47 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
48 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
51 static const u32 verde_rlc_save_restore_register_list[] =
53 (0x8000 << 16) | (0x98f4 >> 2),
55 (0x8040 << 16) | (0x98f4 >> 2),
57 (0x8000 << 16) | (0xe80 >> 2),
59 (0x8040 << 16) | (0xe80 >> 2),
61 (0x8000 << 16) | (0x89bc >> 2),
63 (0x8040 << 16) | (0x89bc >> 2),
65 (0x8000 << 16) | (0x8c1c >> 2),
67 (0x8040 << 16) | (0x8c1c >> 2),
69 (0x9c00 << 16) | (0x98f0 >> 2),
71 (0x9c00 << 16) | (0xe7c >> 2),
73 (0x8000 << 16) | (0x9148 >> 2),
75 (0x8040 << 16) | (0x9148 >> 2),
77 (0x9c00 << 16) | (0x9150 >> 2),
79 (0x9c00 << 16) | (0x897c >> 2),
81 (0x9c00 << 16) | (0x8d8c >> 2),
83 (0x9c00 << 16) | (0xac54 >> 2),
86 (0x9c00 << 16) | (0x98f8 >> 2),
88 (0x9c00 << 16) | (0x9910 >> 2),
90 (0x9c00 << 16) | (0x9914 >> 2),
92 (0x9c00 << 16) | (0x9918 >> 2),
94 (0x9c00 << 16) | (0x991c >> 2),
96 (0x9c00 << 16) | (0x9920 >> 2),
98 (0x9c00 << 16) | (0x9924 >> 2),
100 (0x9c00 << 16) | (0x9928 >> 2),
102 (0x9c00 << 16) | (0x992c >> 2),
104 (0x9c00 << 16) | (0x9930 >> 2),
106 (0x9c00 << 16) | (0x9934 >> 2),
108 (0x9c00 << 16) | (0x9938 >> 2),
110 (0x9c00 << 16) | (0x993c >> 2),
112 (0x9c00 << 16) | (0x9940 >> 2),
114 (0x9c00 << 16) | (0x9944 >> 2),
116 (0x9c00 << 16) | (0x9948 >> 2),
118 (0x9c00 << 16) | (0x994c >> 2),
120 (0x9c00 << 16) | (0x9950 >> 2),
122 (0x9c00 << 16) | (0x9954 >> 2),
124 (0x9c00 << 16) | (0x9958 >> 2),
126 (0x9c00 << 16) | (0x995c >> 2),
128 (0x9c00 << 16) | (0x9960 >> 2),
130 (0x9c00 << 16) | (0x9964 >> 2),
132 (0x9c00 << 16) | (0x9968 >> 2),
134 (0x9c00 << 16) | (0x996c >> 2),
136 (0x9c00 << 16) | (0x9970 >> 2),
138 (0x9c00 << 16) | (0x9974 >> 2),
140 (0x9c00 << 16) | (0x9978 >> 2),
142 (0x9c00 << 16) | (0x997c >> 2),
144 (0x9c00 << 16) | (0x9980 >> 2),
146 (0x9c00 << 16) | (0x9984 >> 2),
148 (0x9c00 << 16) | (0x9988 >> 2),
150 (0x9c00 << 16) | (0x998c >> 2),
152 (0x9c00 << 16) | (0x8c00 >> 2),
154 (0x9c00 << 16) | (0x8c14 >> 2),
156 (0x9c00 << 16) | (0x8c04 >> 2),
158 (0x9c00 << 16) | (0x8c08 >> 2),
160 (0x8000 << 16) | (0x9b7c >> 2),
162 (0x8040 << 16) | (0x9b7c >> 2),
164 (0x8000 << 16) | (0xe84 >> 2),
166 (0x8040 << 16) | (0xe84 >> 2),
168 (0x8000 << 16) | (0x89c0 >> 2),
170 (0x8040 << 16) | (0x89c0 >> 2),
172 (0x8000 << 16) | (0x914c >> 2),
174 (0x8040 << 16) | (0x914c >> 2),
176 (0x8000 << 16) | (0x8c20 >> 2),
178 (0x8040 << 16) | (0x8c20 >> 2),
180 (0x8000 << 16) | (0x9354 >> 2),
182 (0x8040 << 16) | (0x9354 >> 2),
184 (0x9c00 << 16) | (0x9060 >> 2),
186 (0x9c00 << 16) | (0x9364 >> 2),
188 (0x9c00 << 16) | (0x9100 >> 2),
190 (0x9c00 << 16) | (0x913c >> 2),
192 (0x8000 << 16) | (0x90e0 >> 2),
194 (0x8000 << 16) | (0x90e4 >> 2),
196 (0x8000 << 16) | (0x90e8 >> 2),
198 (0x8040 << 16) | (0x90e0 >> 2),
200 (0x8040 << 16) | (0x90e4 >> 2),
202 (0x8040 << 16) | (0x90e8 >> 2),
204 (0x9c00 << 16) | (0x8bcc >> 2),
206 (0x9c00 << 16) | (0x8b24 >> 2),
208 (0x9c00 << 16) | (0x88c4 >> 2),
210 (0x9c00 << 16) | (0x8e50 >> 2),
212 (0x9c00 << 16) | (0x8c0c >> 2),
214 (0x9c00 << 16) | (0x8e58 >> 2),
216 (0x9c00 << 16) | (0x8e5c >> 2),
218 (0x9c00 << 16) | (0x9508 >> 2),
220 (0x9c00 << 16) | (0x950c >> 2),
222 (0x9c00 << 16) | (0x9494 >> 2),
224 (0x9c00 << 16) | (0xac0c >> 2),
226 (0x9c00 << 16) | (0xac10 >> 2),
228 (0x9c00 << 16) | (0xac14 >> 2),
230 (0x9c00 << 16) | (0xae00 >> 2),
232 (0x9c00 << 16) | (0xac08 >> 2),
234 (0x9c00 << 16) | (0x88d4 >> 2),
236 (0x9c00 << 16) | (0x88c8 >> 2),
238 (0x9c00 << 16) | (0x88cc >> 2),
240 (0x9c00 << 16) | (0x89b0 >> 2),
242 (0x9c00 << 16) | (0x8b10 >> 2),
244 (0x9c00 << 16) | (0x8a14 >> 2),
246 (0x9c00 << 16) | (0x9830 >> 2),
248 (0x9c00 << 16) | (0x9834 >> 2),
250 (0x9c00 << 16) | (0x9838 >> 2),
252 (0x9c00 << 16) | (0x9a10 >> 2),
254 (0x8000 << 16) | (0x9870 >> 2),
256 (0x8000 << 16) | (0x9874 >> 2),
258 (0x8001 << 16) | (0x9870 >> 2),
260 (0x8001 << 16) | (0x9874 >> 2),
262 (0x8040 << 16) | (0x9870 >> 2),
264 (0x8040 << 16) | (0x9874 >> 2),
266 (0x8041 << 16) | (0x9870 >> 2),
268 (0x8041 << 16) | (0x9874 >> 2),
273 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
275 const char *chip_name;
278 const struct gfx_firmware_header_v1_0 *cp_hdr;
279 const struct rlc_firmware_header_v1_0 *rlc_hdr;
283 switch (adev->asic_type) {
285 chip_name = "tahiti";
288 chip_name = "pitcairn";
297 chip_name = "hainan";
302 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
303 err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
306 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
309 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
310 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
311 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
313 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
314 err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
317 err = amdgpu_ucode_validate(adev->gfx.me_fw);
320 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
321 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
322 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
324 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
325 err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
328 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
331 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
332 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
333 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
335 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
336 err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
339 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
340 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
341 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
342 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
347 "gfx6: Failed to load firmware \"%s\"\n",
349 release_firmware(adev->gfx.pfp_fw);
350 adev->gfx.pfp_fw = NULL;
351 release_firmware(adev->gfx.me_fw);
352 adev->gfx.me_fw = NULL;
353 release_firmware(adev->gfx.ce_fw);
354 adev->gfx.ce_fw = NULL;
355 release_firmware(adev->gfx.rlc_fw);
356 adev->gfx.rlc_fw = NULL;
361 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
363 const u32 num_tile_mode_states = 32;
364 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
366 switch (adev->gfx.config.mem_row_size_in_kb) {
368 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
372 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
375 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
379 if (adev->asic_type == CHIP_VERDE ||
380 adev->asic_type == CHIP_OLAND ||
381 adev->asic_type == CHIP_HAINAN) {
382 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
383 switch (reg_offset) {
385 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
386 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
387 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
388 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
389 NUM_BANKS(ADDR_SURF_16_BANK) |
390 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
391 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
392 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
395 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
396 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
397 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
398 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
399 NUM_BANKS(ADDR_SURF_16_BANK) |
400 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
401 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
402 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
405 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
406 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
407 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
409 NUM_BANKS(ADDR_SURF_16_BANK) |
410 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
411 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
412 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
415 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
416 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
417 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
418 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
419 NUM_BANKS(ADDR_SURF_16_BANK) |
420 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
425 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
426 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
427 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
429 NUM_BANKS(ADDR_SURF_16_BANK) |
430 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
431 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
432 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
435 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
436 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
437 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
438 TILE_SPLIT(split_equal_to_row_size) |
439 NUM_BANKS(ADDR_SURF_16_BANK) |
440 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
441 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
442 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
445 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
446 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
447 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
448 TILE_SPLIT(split_equal_to_row_size) |
449 NUM_BANKS(ADDR_SURF_16_BANK) |
450 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
451 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
452 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
455 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
456 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
457 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
458 TILE_SPLIT(split_equal_to_row_size) |
459 NUM_BANKS(ADDR_SURF_16_BANK) |
460 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
462 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
465 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
466 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
467 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
468 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
469 NUM_BANKS(ADDR_SURF_16_BANK) |
470 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
471 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
472 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
475 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
476 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
477 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
478 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
479 NUM_BANKS(ADDR_SURF_16_BANK) |
480 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
485 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
486 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
487 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
488 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
489 NUM_BANKS(ADDR_SURF_16_BANK) |
490 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
495 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
496 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
499 NUM_BANKS(ADDR_SURF_16_BANK) |
500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
505 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
506 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
507 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
508 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
509 NUM_BANKS(ADDR_SURF_16_BANK) |
510 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
515 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
516 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
517 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
519 NUM_BANKS(ADDR_SURF_16_BANK) |
520 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
525 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
526 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
527 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
528 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
529 NUM_BANKS(ADDR_SURF_16_BANK) |
530 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
535 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
536 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
537 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
538 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
539 NUM_BANKS(ADDR_SURF_16_BANK) |
540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
545 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
546 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
547 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
548 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
549 NUM_BANKS(ADDR_SURF_16_BANK) |
550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
555 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
556 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
557 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
558 TILE_SPLIT(split_equal_to_row_size) |
559 NUM_BANKS(ADDR_SURF_16_BANK) |
560 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
565 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
566 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
568 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
569 NUM_BANKS(ADDR_SURF_16_BANK) |
570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
575 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
576 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
577 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
578 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
579 NUM_BANKS(ADDR_SURF_16_BANK) |
580 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
581 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
582 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
585 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
586 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
587 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
588 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
589 NUM_BANKS(ADDR_SURF_16_BANK) |
590 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
591 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
592 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
595 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
596 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
597 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
598 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
599 NUM_BANKS(ADDR_SURF_16_BANK) |
600 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
601 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
602 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
605 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
606 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
607 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
609 NUM_BANKS(ADDR_SURF_8_BANK) |
610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
618 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
619 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
621 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
622 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
623 switch (reg_offset) {
624 case 0: /* non-AA compressed depth or any compressed stencil */
625 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
626 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
627 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
628 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
629 NUM_BANKS(ADDR_SURF_16_BANK) |
630 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
634 case 1: /* 2xAA/4xAA compressed depth only */
635 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
636 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
637 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
638 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
639 NUM_BANKS(ADDR_SURF_16_BANK) |
640 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
641 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
642 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
644 case 2: /* 8xAA compressed depth only */
645 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
646 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
647 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
648 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
649 NUM_BANKS(ADDR_SURF_16_BANK) |
650 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
654 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
655 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
656 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
657 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
658 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
659 NUM_BANKS(ADDR_SURF_16_BANK) |
660 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
661 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
662 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
664 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
665 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
666 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
667 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
669 NUM_BANKS(ADDR_SURF_16_BANK) |
670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
674 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
675 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
676 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
677 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
678 TILE_SPLIT(split_equal_to_row_size) |
679 NUM_BANKS(ADDR_SURF_16_BANK) |
680 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
681 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
682 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
684 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
685 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
686 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
687 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
688 TILE_SPLIT(split_equal_to_row_size) |
689 NUM_BANKS(ADDR_SURF_16_BANK) |
690 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
694 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
695 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
696 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
697 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
698 TILE_SPLIT(split_equal_to_row_size) |
699 NUM_BANKS(ADDR_SURF_16_BANK) |
700 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
704 case 8: /* 1D and 1D Array Surfaces */
705 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
706 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
707 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
709 NUM_BANKS(ADDR_SURF_16_BANK) |
710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
714 case 9: /* Displayable maps. */
715 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
716 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
717 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
718 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
719 NUM_BANKS(ADDR_SURF_16_BANK) |
720 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
721 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
722 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
724 case 10: /* Display 8bpp. */
725 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
726 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
727 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
728 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
729 NUM_BANKS(ADDR_SURF_16_BANK) |
730 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
734 case 11: /* Display 16bpp. */
735 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
736 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
737 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
738 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
739 NUM_BANKS(ADDR_SURF_16_BANK) |
740 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
741 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
742 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
744 case 12: /* Display 32bpp. */
745 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
746 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
747 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
749 NUM_BANKS(ADDR_SURF_16_BANK) |
750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
755 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
756 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
757 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
758 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
759 NUM_BANKS(ADDR_SURF_16_BANK) |
760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
764 case 14: /* Thin 8 bpp. */
765 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
766 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
767 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
768 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
769 NUM_BANKS(ADDR_SURF_16_BANK) |
770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
774 case 15: /* Thin 16 bpp. */
775 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
776 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
777 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
778 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
779 NUM_BANKS(ADDR_SURF_16_BANK) |
780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
784 case 16: /* Thin 32 bpp. */
785 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
786 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
787 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
789 NUM_BANKS(ADDR_SURF_16_BANK) |
790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
794 case 17: /* Thin 64 bpp. */
795 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
796 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
797 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
798 TILE_SPLIT(split_equal_to_row_size) |
799 NUM_BANKS(ADDR_SURF_16_BANK) |
800 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
801 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
802 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
804 case 21: /* 8 bpp PRT. */
805 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
806 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
807 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
808 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
809 NUM_BANKS(ADDR_SURF_16_BANK) |
810 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
811 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
812 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
814 case 22: /* 16 bpp PRT */
815 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
816 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
817 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
818 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
819 NUM_BANKS(ADDR_SURF_16_BANK) |
820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
824 case 23: /* 32 bpp PRT */
825 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
826 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
827 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
828 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
829 NUM_BANKS(ADDR_SURF_16_BANK) |
830 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
831 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
832 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
834 case 24: /* 64 bpp PRT */
835 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
836 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
837 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
838 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
839 NUM_BANKS(ADDR_SURF_16_BANK) |
840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
844 case 25: /* 128 bpp PRT */
845 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
846 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
847 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
848 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
849 NUM_BANKS(ADDR_SURF_8_BANK) |
850 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
851 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
852 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
858 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
859 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
863 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
868 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
869 u32 sh_num, u32 instance)
873 if (instance == 0xffffffff)
874 data = INSTANCE_BROADCAST_WRITES;
876 data = INSTANCE_INDEX(instance);
878 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
879 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
880 else if (se_num == 0xffffffff)
881 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
882 else if (sh_num == 0xffffffff)
883 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
885 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
886 WREG32(GRBM_GFX_INDEX, data);
889 static u32 gfx_v6_0_create_bitmask(u32 bit_width)
891 return (u32)(((u64)1 << bit_width) - 1);
894 static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
895 u32 max_rb_num_per_se,
900 data = RREG32(CC_RB_BACKEND_DISABLE);
901 data &= BACKEND_DISABLE_MASK;
902 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
904 data >>= BACKEND_DISABLE_SHIFT;
906 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
911 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
913 switch (adev->asic_type) {
916 *rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) |
917 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2);
920 *rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1);
929 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
934 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
935 u32 raster_config, unsigned rb_mask,
938 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
939 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
940 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
941 unsigned rb_per_se = num_rb / num_se;
945 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
946 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
947 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
948 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
950 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
951 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
952 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
954 for (se = 0; se < num_se; se++) {
955 unsigned raster_config_se = raster_config;
956 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
957 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
958 int idx = (se / 2) * 2;
960 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
961 raster_config_se &= ~SE_MAP_MASK;
964 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
966 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
970 pkr0_mask &= rb_mask;
971 pkr1_mask &= rb_mask;
972 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
973 raster_config_se &= ~PKR_MAP_MASK;
976 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
978 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
982 if (rb_per_se >= 2) {
983 unsigned rb0_mask = 1 << (se * rb_per_se);
984 unsigned rb1_mask = rb0_mask << 1;
988 if (!rb0_mask || !rb1_mask) {
989 raster_config_se &= ~RB_MAP_PKR0_MASK;
993 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
996 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1000 if (rb_per_se > 2) {
1001 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1002 rb1_mask = rb0_mask << 1;
1003 rb0_mask &= rb_mask;
1004 rb1_mask &= rb_mask;
1005 if (!rb0_mask || !rb1_mask) {
1006 raster_config_se &= ~RB_MAP_PKR1_MASK;
1010 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1013 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1019 /* GRBM_GFX_INDEX has a different offset on SI */
1020 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1021 WREG32(PA_SC_RASTER_CONFIG, raster_config_se);
1024 /* GRBM_GFX_INDEX has a different offset on SI */
1025 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1028 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1029 u32 se_num, u32 sh_per_se,
1030 u32 max_rb_num_per_se)
1034 u32 disabled_rbs = 0;
1035 u32 enabled_rbs = 0;
1036 unsigned num_rb_pipes;
1038 mutex_lock(&adev->grbm_idx_mutex);
1039 for (i = 0; i < se_num; i++) {
1040 for (j = 0; j < sh_per_se; j++) {
1041 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1042 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1043 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1046 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1047 mutex_unlock(&adev->grbm_idx_mutex);
1050 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1051 if (!(disabled_rbs & mask))
1052 enabled_rbs |= mask;
1056 adev->gfx.config.backend_enable_mask = enabled_rbs;
1057 adev->gfx.config.num_rbs = hweight32(enabled_rbs);
1059 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1060 adev->gfx.config.max_shader_engines, 16);
1062 mutex_lock(&adev->grbm_idx_mutex);
1063 for (i = 0; i < se_num; i++) {
1064 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1066 for (j = 0; j < sh_per_se; j++) {
1067 switch (enabled_rbs & 3) {
1069 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1072 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1076 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1081 gfx_v6_0_raster_config(adev, &data);
1083 if (!adev->gfx.config.backend_enable_mask ||
1084 adev->gfx.config.num_rbs >= num_rb_pipes)
1085 WREG32(PA_SC_RASTER_CONFIG, data);
1087 gfx_v6_0_write_harvested_raster_configs(adev, data,
1088 adev->gfx.config.backend_enable_mask,
1091 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1092 mutex_unlock(&adev->grbm_idx_mutex);
1095 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
1100 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
1104 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1105 data &= INACTIVE_CUS_MASK;
1106 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1108 data >>= INACTIVE_CUS_SHIFT;
1110 mask = gfx_v6_0_create_bitmask(cu_per_sh);
1112 return ~data & mask;
1116 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1117 u32 se_num, u32 sh_per_se,
1124 mutex_lock(&adev->grbm_idx_mutex);
1125 for (i = 0; i < se_num; i++) {
1126 for (j = 0; j < sh_per_se; j++) {
1127 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1128 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1129 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1132 for (k = 0; k < 16; k++) {
1134 if (active_cu & mask) {
1136 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1142 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1143 mutex_unlock(&adev->grbm_idx_mutex);
1146 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1148 u32 gb_addr_config = 0;
1149 u32 mc_shared_chmap, mc_arb_ramcfg;
1151 u32 hdp_host_path_cntl;
1154 switch (adev->asic_type) {
1156 adev->gfx.config.max_shader_engines = 2;
1157 adev->gfx.config.max_tile_pipes = 12;
1158 adev->gfx.config.max_cu_per_sh = 8;
1159 adev->gfx.config.max_sh_per_se = 2;
1160 adev->gfx.config.max_backends_per_se = 4;
1161 adev->gfx.config.max_texture_channel_caches = 12;
1162 adev->gfx.config.max_gprs = 256;
1163 adev->gfx.config.max_gs_threads = 32;
1164 adev->gfx.config.max_hw_contexts = 8;
1166 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1167 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1168 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1169 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1170 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1173 adev->gfx.config.max_shader_engines = 2;
1174 adev->gfx.config.max_tile_pipes = 8;
1175 adev->gfx.config.max_cu_per_sh = 5;
1176 adev->gfx.config.max_sh_per_se = 2;
1177 adev->gfx.config.max_backends_per_se = 4;
1178 adev->gfx.config.max_texture_channel_caches = 8;
1179 adev->gfx.config.max_gprs = 256;
1180 adev->gfx.config.max_gs_threads = 32;
1181 adev->gfx.config.max_hw_contexts = 8;
1183 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1184 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1185 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1186 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1187 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1191 adev->gfx.config.max_shader_engines = 1;
1192 adev->gfx.config.max_tile_pipes = 4;
1193 adev->gfx.config.max_cu_per_sh = 5;
1194 adev->gfx.config.max_sh_per_se = 2;
1195 adev->gfx.config.max_backends_per_se = 4;
1196 adev->gfx.config.max_texture_channel_caches = 4;
1197 adev->gfx.config.max_gprs = 256;
1198 adev->gfx.config.max_gs_threads = 32;
1199 adev->gfx.config.max_hw_contexts = 8;
1201 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1202 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1203 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1204 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1205 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1208 adev->gfx.config.max_shader_engines = 1;
1209 adev->gfx.config.max_tile_pipes = 4;
1210 adev->gfx.config.max_cu_per_sh = 6;
1211 adev->gfx.config.max_sh_per_se = 1;
1212 adev->gfx.config.max_backends_per_se = 2;
1213 adev->gfx.config.max_texture_channel_caches = 4;
1214 adev->gfx.config.max_gprs = 256;
1215 adev->gfx.config.max_gs_threads = 16;
1216 adev->gfx.config.max_hw_contexts = 8;
1218 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1219 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1220 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1221 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1222 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1225 adev->gfx.config.max_shader_engines = 1;
1226 adev->gfx.config.max_tile_pipes = 4;
1227 adev->gfx.config.max_cu_per_sh = 5;
1228 adev->gfx.config.max_sh_per_se = 1;
1229 adev->gfx.config.max_backends_per_se = 1;
1230 adev->gfx.config.max_texture_channel_caches = 2;
1231 adev->gfx.config.max_gprs = 256;
1232 adev->gfx.config.max_gs_threads = 16;
1233 adev->gfx.config.max_hw_contexts = 8;
1235 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1236 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1237 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1238 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1239 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1246 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1247 WREG32(SRBM_INT_CNTL, 1);
1248 WREG32(SRBM_INT_ACK, 1);
1250 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1252 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1253 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1255 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1256 adev->gfx.config.mem_max_burst_length_bytes = 256;
1257 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1258 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1259 if (adev->gfx.config.mem_row_size_in_kb > 4)
1260 adev->gfx.config.mem_row_size_in_kb = 4;
1261 adev->gfx.config.shader_engine_tile_size = 32;
1262 adev->gfx.config.num_gpus = 1;
1263 adev->gfx.config.multi_gpu_tile_size = 64;
1265 gb_addr_config &= ~ROW_SIZE_MASK;
1266 switch (adev->gfx.config.mem_row_size_in_kb) {
1269 gb_addr_config |= ROW_SIZE(0);
1272 gb_addr_config |= ROW_SIZE(1);
1275 gb_addr_config |= ROW_SIZE(2);
1278 adev->gfx.config.gb_addr_config = gb_addr_config;
1280 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1281 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1282 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1283 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1284 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1285 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1287 if (adev->has_uvd) {
1288 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1289 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1290 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1293 gfx_v6_0_tiling_mode_table_init(adev);
1295 gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1296 adev->gfx.config.max_sh_per_se,
1297 adev->gfx.config.max_backends_per_se);
1299 gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1300 adev->gfx.config.max_sh_per_se,
1301 adev->gfx.config.max_cu_per_sh);
1303 gfx_v6_0_get_cu_info(adev);
1305 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1306 ROQ_IB2_START(0x2b)));
1307 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1309 sx_debug_1 = RREG32(SX_DEBUG_1);
1310 WREG32(SX_DEBUG_1, sx_debug_1);
1312 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1314 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) |
1315 SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) |
1316 SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) |
1317 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
1319 WREG32(VGT_NUM_INSTANCES, 1);
1320 WREG32(CP_PERFMON_CNTL, 0);
1321 WREG32(SQ_CONFIG, 0);
1322 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1323 FORCE_EOV_MAX_REZ_CNT(255)));
1325 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1326 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1328 WREG32(VGT_GS_VERTEX_REUSE, 16);
1329 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1331 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1332 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1333 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1334 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1335 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1336 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1337 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1338 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1340 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1341 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1343 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1349 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1353 adev->gfx.scratch.num_reg = 7;
1354 adev->gfx.scratch.reg_base = SCRATCH_REG0;
1355 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1356 adev->gfx.scratch.free[i] = true;
1357 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1361 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1363 struct amdgpu_device *adev = ring->adev;
1369 r = amdgpu_gfx_scratch_get(adev, &scratch);
1371 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1374 WREG32(scratch, 0xCAFEDEAD);
1376 r = amdgpu_ring_alloc(ring, 3);
1378 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1379 amdgpu_gfx_scratch_free(adev, scratch);
1382 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1383 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1384 amdgpu_ring_write(ring, 0xDEADBEEF);
1385 amdgpu_ring_commit(ring);
1387 for (i = 0; i < adev->usec_timeout; i++) {
1388 tmp = RREG32(scratch);
1389 if (tmp == 0xDEADBEEF)
1393 if (i < adev->usec_timeout) {
1394 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1396 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1397 ring->idx, scratch, tmp);
1400 amdgpu_gfx_scratch_free(adev, scratch);
1404 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1406 /* flush hdp cache */
1407 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1408 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1409 WRITE_DATA_DST_SEL(0)));
1410 amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL);
1411 amdgpu_ring_write(ring, 0);
1412 amdgpu_ring_write(ring, 0x1);
1416 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1418 * @adev: amdgpu_device pointer
1419 * @ridx: amdgpu ring index
1421 * Emits an hdp invalidate on the cp.
1423 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1425 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1426 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1427 WRITE_DATA_DST_SEL(0)));
1428 amdgpu_ring_write(ring, HDP_DEBUG0);
1429 amdgpu_ring_write(ring, 0);
1430 amdgpu_ring_write(ring, 0x1);
1433 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1434 u64 seq, unsigned flags)
1436 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1437 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1438 /* flush read cache over gart */
1439 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1440 amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1441 amdgpu_ring_write(ring, 0);
1442 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1443 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1444 PACKET3_TC_ACTION_ENA |
1445 PACKET3_SH_KCACHE_ACTION_ENA |
1446 PACKET3_SH_ICACHE_ACTION_ENA);
1447 amdgpu_ring_write(ring, 0xFFFFFFFF);
1448 amdgpu_ring_write(ring, 0);
1449 amdgpu_ring_write(ring, 10); /* poll interval */
1450 /* EVENT_WRITE_EOP - flush caches, send int */
1451 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1452 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1453 amdgpu_ring_write(ring, addr & 0xfffffffc);
1454 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1455 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1456 amdgpu_ring_write(ring, lower_32_bits(seq));
1457 amdgpu_ring_write(ring, upper_32_bits(seq));
1460 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1461 struct amdgpu_ib *ib,
1462 unsigned vm_id, bool ctx_switch)
1464 u32 header, control = 0;
1466 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1468 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1469 amdgpu_ring_write(ring, 0);
1472 if (ib->flags & AMDGPU_IB_FLAG_CE)
1473 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1475 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1477 control |= ib->length_dw | (vm_id << 24);
1479 amdgpu_ring_write(ring, header);
1480 amdgpu_ring_write(ring,
1484 (ib->gpu_addr & 0xFFFFFFFC));
1485 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1486 amdgpu_ring_write(ring, control);
1490 * gfx_v6_0_ring_test_ib - basic ring IB test
1492 * @ring: amdgpu_ring structure holding ring information
1494 * Allocate an IB and execute it on the gfx ring (SI).
1495 * Provides a basic gfx ring test to verify that IBs are working.
1496 * Returns 0 on success, error on failure.
1498 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1500 struct amdgpu_device *adev = ring->adev;
1501 struct amdgpu_ib ib;
1502 struct fence *f = NULL;
1507 r = amdgpu_gfx_scratch_get(adev, &scratch);
1509 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1512 WREG32(scratch, 0xCAFEDEAD);
1513 memset(&ib, 0, sizeof(ib));
1514 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1516 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1519 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1520 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1521 ib.ptr[2] = 0xDEADBEEF;
1524 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1528 r = fence_wait_timeout(f, false, timeout);
1530 DRM_ERROR("amdgpu: IB test timed out\n");
1534 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1537 tmp = RREG32(scratch);
1538 if (tmp == 0xDEADBEEF) {
1539 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1542 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1548 amdgpu_ib_free(adev, &ib, NULL);
1551 amdgpu_gfx_scratch_free(adev, scratch);
1555 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1559 WREG32(CP_ME_CNTL, 0);
1561 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1562 WREG32(SCRATCH_UMSK, 0);
1563 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1564 adev->gfx.gfx_ring[i].ready = false;
1565 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1566 adev->gfx.compute_ring[i].ready = false;
1571 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1574 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1575 const struct gfx_firmware_header_v1_0 *ce_hdr;
1576 const struct gfx_firmware_header_v1_0 *me_hdr;
1577 const __le32 *fw_data;
1580 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1583 gfx_v6_0_cp_gfx_enable(adev, false);
1584 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1585 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1586 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1588 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1589 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1590 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1593 fw_data = (const __le32 *)
1594 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1595 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1596 WREG32(CP_PFP_UCODE_ADDR, 0);
1597 for (i = 0; i < fw_size; i++)
1598 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1599 WREG32(CP_PFP_UCODE_ADDR, 0);
1602 fw_data = (const __le32 *)
1603 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1604 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1605 WREG32(CP_CE_UCODE_ADDR, 0);
1606 for (i = 0; i < fw_size; i++)
1607 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1608 WREG32(CP_CE_UCODE_ADDR, 0);
1611 fw_data = (const __be32 *)
1612 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1613 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1614 WREG32(CP_ME_RAM_WADDR, 0);
1615 for (i = 0; i < fw_size; i++)
1616 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1617 WREG32(CP_ME_RAM_WADDR, 0);
1620 WREG32(CP_PFP_UCODE_ADDR, 0);
1621 WREG32(CP_CE_UCODE_ADDR, 0);
1622 WREG32(CP_ME_RAM_WADDR, 0);
1623 WREG32(CP_ME_RAM_RADDR, 0);
1627 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1629 const struct cs_section_def *sect = NULL;
1630 const struct cs_extent_def *ext = NULL;
1631 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1634 r = amdgpu_ring_alloc(ring, 7 + 4);
1636 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1639 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1640 amdgpu_ring_write(ring, 0x1);
1641 amdgpu_ring_write(ring, 0x0);
1642 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1643 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1644 amdgpu_ring_write(ring, 0);
1645 amdgpu_ring_write(ring, 0);
1647 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1648 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1649 amdgpu_ring_write(ring, 0xc000);
1650 amdgpu_ring_write(ring, 0xe000);
1651 amdgpu_ring_commit(ring);
1653 gfx_v6_0_cp_gfx_enable(adev, true);
1655 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
1657 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1661 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1662 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1664 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1665 for (ext = sect->section; ext->extent != NULL; ++ext) {
1666 if (sect->id == SECT_CONTEXT) {
1667 amdgpu_ring_write(ring,
1668 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1669 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1670 for (i = 0; i < ext->reg_count; i++)
1671 amdgpu_ring_write(ring, ext->extent[i]);
1676 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1677 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1679 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1680 amdgpu_ring_write(ring, 0);
1682 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1683 amdgpu_ring_write(ring, 0x00000316);
1684 amdgpu_ring_write(ring, 0x0000000e);
1685 amdgpu_ring_write(ring, 0x00000010);
1687 amdgpu_ring_commit(ring);
1692 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1694 struct amdgpu_ring *ring;
1700 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1701 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1703 /* Set the write pointer delay */
1704 WREG32(CP_RB_WPTR_DELAY, 0);
1706 WREG32(CP_DEBUG, 0);
1707 WREG32(SCRATCH_ADDR, 0);
1709 /* ring 0 - compute and gfx */
1710 /* Set ring buffer size */
1711 ring = &adev->gfx.gfx_ring[0];
1712 rb_bufsz = order_base_2(ring->ring_size / 8);
1713 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1716 tmp |= BUF_SWAP_32BIT;
1718 WREG32(CP_RB0_CNTL, tmp);
1720 /* Initialize the ring buffer's read and write pointers */
1721 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1723 WREG32(CP_RB0_WPTR, ring->wptr);
1725 /* set the wb address whether it's enabled or not */
1726 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1727 WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1728 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1730 WREG32(SCRATCH_UMSK, 0);
1733 WREG32(CP_RB0_CNTL, tmp);
1735 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1737 /* start the rings */
1738 gfx_v6_0_cp_gfx_start(adev);
1740 r = amdgpu_ring_test_ring(ring);
1742 ring->ready = false;
1749 static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
1751 return ring->adev->wb.wb[ring->rptr_offs];
1754 static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
1756 struct amdgpu_device *adev = ring->adev;
1758 if (ring == &adev->gfx.gfx_ring[0])
1759 return RREG32(CP_RB0_WPTR);
1760 else if (ring == &adev->gfx.compute_ring[0])
1761 return RREG32(CP_RB1_WPTR);
1762 else if (ring == &adev->gfx.compute_ring[1])
1763 return RREG32(CP_RB2_WPTR);
1768 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1770 struct amdgpu_device *adev = ring->adev;
1772 WREG32(CP_RB0_WPTR, ring->wptr);
1773 (void)RREG32(CP_RB0_WPTR);
1776 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1778 struct amdgpu_device *adev = ring->adev;
1780 if (ring == &adev->gfx.compute_ring[0]) {
1781 WREG32(CP_RB1_WPTR, ring->wptr);
1782 (void)RREG32(CP_RB1_WPTR);
1783 } else if (ring == &adev->gfx.compute_ring[1]) {
1784 WREG32(CP_RB2_WPTR, ring->wptr);
1785 (void)RREG32(CP_RB2_WPTR);
1792 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1794 struct amdgpu_ring *ring;
1800 /* ring1 - compute only */
1801 /* Set ring buffer size */
1803 ring = &adev->gfx.compute_ring[0];
1804 rb_bufsz = order_base_2(ring->ring_size / 8);
1805 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1807 tmp |= BUF_SWAP_32BIT;
1809 WREG32(CP_RB1_CNTL, tmp);
1811 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1813 WREG32(CP_RB1_WPTR, ring->wptr);
1815 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1816 WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1817 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1820 WREG32(CP_RB1_CNTL, tmp);
1821 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1823 ring = &adev->gfx.compute_ring[1];
1824 rb_bufsz = order_base_2(ring->ring_size / 8);
1825 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1827 tmp |= BUF_SWAP_32BIT;
1829 WREG32(CP_RB2_CNTL, tmp);
1831 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1833 WREG32(CP_RB2_WPTR, ring->wptr);
1834 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1835 WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1836 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1839 WREG32(CP_RB2_CNTL, tmp);
1840 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1842 adev->gfx.compute_ring[0].ready = true;
1843 adev->gfx.compute_ring[1].ready = true;
1845 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]);
1847 adev->gfx.compute_ring[0].ready = false;
1851 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1853 adev->gfx.compute_ring[1].ready = false;
1860 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
1862 gfx_v6_0_cp_gfx_enable(adev, enable);
1865 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1867 return gfx_v6_0_cp_gfx_load_microcode(adev);
1870 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1873 u32 tmp = RREG32(CP_INT_CNTL_RING0);
1878 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1880 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1881 WREG32(CP_INT_CNTL_RING0, tmp);
1884 /* read a gfx register */
1885 tmp = RREG32(DB_DEPTH_INFO);
1887 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1888 for (i = 0; i < adev->usec_timeout; i++) {
1889 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1896 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
1900 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
1902 r = gfx_v6_0_cp_load_microcode(adev);
1906 r = gfx_v6_0_cp_gfx_resume(adev);
1909 r = gfx_v6_0_cp_compute_resume(adev);
1913 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
1918 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1920 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1921 uint32_t seq = ring->fence_drv.sync_seq;
1922 uint64_t addr = ring->fence_drv.gpu_addr;
1924 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1925 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
1926 WAIT_REG_MEM_FUNCTION(3) | /* equal */
1927 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
1928 amdgpu_ring_write(ring, addr & 0xfffffffc);
1929 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1930 amdgpu_ring_write(ring, seq);
1931 amdgpu_ring_write(ring, 0xffffffff);
1932 amdgpu_ring_write(ring, 4); /* poll interval */
1935 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1936 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1937 amdgpu_ring_write(ring, 0);
1938 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1939 amdgpu_ring_write(ring, 0);
1943 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1944 unsigned vm_id, uint64_t pd_addr)
1946 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1948 /* write new base address */
1949 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1950 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1951 WRITE_DATA_DST_SEL(0)));
1953 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1955 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1957 amdgpu_ring_write(ring, 0);
1958 amdgpu_ring_write(ring, pd_addr >> 12);
1960 /* bits 0-15 are the VM contexts0-15 */
1961 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1962 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1963 WRITE_DATA_DST_SEL(0)));
1964 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1965 amdgpu_ring_write(ring, 0);
1966 amdgpu_ring_write(ring, 1 << vm_id);
1968 /* wait for the invalidate to complete */
1969 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1970 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
1971 WAIT_REG_MEM_ENGINE(0))); /* me */
1972 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1973 amdgpu_ring_write(ring, 0);
1974 amdgpu_ring_write(ring, 0); /* ref */
1975 amdgpu_ring_write(ring, 0); /* mask */
1976 amdgpu_ring_write(ring, 0x20); /* poll interval */
1979 /* sync PFP to ME, otherwise we might get invalid PFP reads */
1980 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1981 amdgpu_ring_write(ring, 0x0);
1983 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1984 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1985 amdgpu_ring_write(ring, 0);
1986 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1987 amdgpu_ring_write(ring, 0);
1992 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
1996 if (adev->gfx.rlc.save_restore_obj) {
1997 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
1998 if (unlikely(r != 0))
1999 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
2000 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
2001 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2003 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
2004 adev->gfx.rlc.save_restore_obj = NULL;
2007 if (adev->gfx.rlc.clear_state_obj) {
2008 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2009 if (unlikely(r != 0))
2010 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
2011 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
2012 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2014 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2015 adev->gfx.rlc.clear_state_obj = NULL;
2018 if (adev->gfx.rlc.cp_table_obj) {
2019 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
2020 if (unlikely(r != 0))
2021 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
2022 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
2023 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
2025 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
2026 adev->gfx.rlc.cp_table_obj = NULL;
2030 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2033 volatile u32 *dst_ptr;
2035 u64 reg_list_mc_addr;
2036 const struct cs_section_def *cs_data;
2039 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2040 adev->gfx.rlc.reg_list_size =
2041 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2043 adev->gfx.rlc.cs_data = si_cs_data;
2044 src_ptr = adev->gfx.rlc.reg_list;
2045 dws = adev->gfx.rlc.reg_list_size;
2046 cs_data = adev->gfx.rlc.cs_data;
2049 /* save restore block */
2050 if (adev->gfx.rlc.save_restore_obj == NULL) {
2052 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2053 AMDGPU_GEM_DOMAIN_VRAM,
2054 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2056 &adev->gfx.rlc.save_restore_obj);
2059 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2064 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2065 if (unlikely(r != 0)) {
2066 gfx_v6_0_rlc_fini(adev);
2069 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2070 &adev->gfx.rlc.save_restore_gpu_addr);
2072 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2073 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2074 gfx_v6_0_rlc_fini(adev);
2078 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2080 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2081 gfx_v6_0_rlc_fini(adev);
2084 /* write the sr buffer */
2085 dst_ptr = adev->gfx.rlc.sr_ptr;
2086 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2087 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2088 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2089 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2093 /* clear state block */
2094 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2095 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2097 if (adev->gfx.rlc.clear_state_obj == NULL) {
2098 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2099 AMDGPU_GEM_DOMAIN_VRAM,
2100 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2102 &adev->gfx.rlc.clear_state_obj);
2105 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2106 gfx_v6_0_rlc_fini(adev);
2110 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2111 if (unlikely(r != 0)) {
2112 gfx_v6_0_rlc_fini(adev);
2115 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2116 &adev->gfx.rlc.clear_state_gpu_addr);
2118 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2119 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2120 gfx_v6_0_rlc_fini(adev);
2124 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2126 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2127 gfx_v6_0_rlc_fini(adev);
2130 /* set up the cs buffer */
2131 dst_ptr = adev->gfx.rlc.cs_ptr;
2132 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2133 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2134 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2135 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2136 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2137 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2138 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2144 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2148 tmp = RREG32(RLC_LB_CNTL);
2150 tmp |= LOAD_BALANCE_ENABLE;
2152 tmp &= ~LOAD_BALANCE_ENABLE;
2153 WREG32(RLC_LB_CNTL, tmp);
2156 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2157 WREG32(SPI_LB_CU_MASK, 0x00ff);
2162 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2166 for (i = 0; i < adev->usec_timeout; i++) {
2167 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
2172 for (i = 0; i < adev->usec_timeout; i++) {
2173 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
2179 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2183 tmp = RREG32(RLC_CNTL);
2185 WREG32(RLC_CNTL, rlc);
2188 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2192 orig = data = RREG32(RLC_CNTL);
2194 if (data & RLC_ENABLE) {
2195 data &= ~RLC_ENABLE;
2196 WREG32(RLC_CNTL, data);
2198 gfx_v6_0_wait_for_rlc_serdes(adev);
2204 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2206 WREG32(RLC_CNTL, 0);
2208 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2209 gfx_v6_0_wait_for_rlc_serdes(adev);
2212 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2214 WREG32(RLC_CNTL, RLC_ENABLE);
2216 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2221 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2223 u32 tmp = RREG32(GRBM_SOFT_RESET);
2225 tmp |= SOFT_RESET_RLC;
2226 WREG32(GRBM_SOFT_RESET, tmp);
2228 tmp &= ~SOFT_RESET_RLC;
2229 WREG32(GRBM_SOFT_RESET, tmp);
2233 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2237 /* Enable LBPW only for DDR3 */
2238 tmp = RREG32(MC_SEQ_MISC0);
2239 if ((tmp & 0xF0000000) == 0xB0000000)
2243 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2247 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2250 const struct rlc_firmware_header_v1_0 *hdr;
2251 const __le32 *fw_data;
2255 if (!adev->gfx.rlc_fw)
2258 gfx_v6_0_rlc_stop(adev);
2259 gfx_v6_0_rlc_reset(adev);
2260 gfx_v6_0_init_pg(adev);
2261 gfx_v6_0_init_cg(adev);
2263 WREG32(RLC_RL_BASE, 0);
2264 WREG32(RLC_RL_SIZE, 0);
2265 WREG32(RLC_LB_CNTL, 0);
2266 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2267 WREG32(RLC_LB_CNTR_INIT, 0);
2268 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
2270 WREG32(RLC_MC_CNTL, 0);
2271 WREG32(RLC_UCODE_CNTL, 0);
2273 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2274 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2275 fw_data = (const __le32 *)
2276 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2278 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2280 for (i = 0; i < fw_size; i++) {
2281 WREG32(RLC_UCODE_ADDR, i);
2282 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
2284 WREG32(RLC_UCODE_ADDR, 0);
2286 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2287 gfx_v6_0_rlc_start(adev);
2292 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2294 u32 data, orig, tmp;
2296 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
2298 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2299 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2301 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
2303 tmp = gfx_v6_0_halt_rlc(adev);
2305 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2306 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2307 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
2309 gfx_v6_0_wait_for_rlc_serdes(adev);
2310 gfx_v6_0_update_rlc(adev, tmp);
2312 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
2314 data |= CGCG_EN | CGLS_EN;
2316 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2318 RREG32(CB_CGTT_SCLK_CTRL);
2319 RREG32(CB_CGTT_SCLK_CTRL);
2320 RREG32(CB_CGTT_SCLK_CTRL);
2321 RREG32(CB_CGTT_SCLK_CTRL);
2323 data &= ~(CGCG_EN | CGLS_EN);
2327 WREG32(RLC_CGCG_CGLS_CTRL, data);
2331 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2334 u32 data, orig, tmp = 0;
2336 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2337 orig = data = RREG32(CGTS_SM_CTRL_REG);
2340 WREG32(CGTS_SM_CTRL_REG, data);
2342 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2343 orig = data = RREG32(CP_MEM_SLP_CNTL);
2344 data |= CP_MEM_LS_EN;
2346 WREG32(CP_MEM_SLP_CNTL, data);
2349 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2352 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2354 tmp = gfx_v6_0_halt_rlc(adev);
2356 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2357 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2358 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
2360 gfx_v6_0_update_rlc(adev, tmp);
2362 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2365 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2367 data = RREG32(CP_MEM_SLP_CNTL);
2368 if (data & CP_MEM_LS_EN) {
2369 data &= ~CP_MEM_LS_EN;
2370 WREG32(CP_MEM_SLP_CNTL, data);
2372 orig = data = RREG32(CGTS_SM_CTRL_REG);
2373 data |= LS_OVERRIDE | OVERRIDE;
2375 WREG32(CGTS_SM_CTRL_REG, data);
2377 tmp = gfx_v6_0_halt_rlc(adev);
2379 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2380 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2381 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
2383 gfx_v6_0_update_rlc(adev, tmp);
2387 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2390 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2392 gfx_v6_0_enable_mgcg(adev, true);
2393 gfx_v6_0_enable_cgcg(adev, true);
2395 gfx_v6_0_enable_cgcg(adev, false);
2396 gfx_v6_0_enable_mgcg(adev, false);
2398 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2401 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2406 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2411 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2415 orig = data = RREG32(RLC_PG_CNTL);
2416 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2421 WREG32(RLC_PG_CNTL, data);
2424 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2428 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2430 const __le32 *fw_data;
2431 volatile u32 *dst_ptr;
2432 int me, i, max_me = 4;
2434 u32 table_offset, table_size;
2436 if (adev->asic_type == CHIP_KAVERI)
2439 if (adev->gfx.rlc.cp_table_ptr == NULL)
2442 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2443 for (me = 0; me < max_me; me++) {
2445 const struct gfx_firmware_header_v1_0 *hdr =
2446 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2447 fw_data = (const __le32 *)
2448 (adev->gfx.ce_fw->data +
2449 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2450 table_offset = le32_to_cpu(hdr->jt_offset);
2451 table_size = le32_to_cpu(hdr->jt_size);
2452 } else if (me == 1) {
2453 const struct gfx_firmware_header_v1_0 *hdr =
2454 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2455 fw_data = (const __le32 *)
2456 (adev->gfx.pfp_fw->data +
2457 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2458 table_offset = le32_to_cpu(hdr->jt_offset);
2459 table_size = le32_to_cpu(hdr->jt_size);
2460 } else if (me == 2) {
2461 const struct gfx_firmware_header_v1_0 *hdr =
2462 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2463 fw_data = (const __le32 *)
2464 (adev->gfx.me_fw->data +
2465 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2466 table_offset = le32_to_cpu(hdr->jt_offset);
2467 table_size = le32_to_cpu(hdr->jt_size);
2468 } else if (me == 3) {
2469 const struct gfx_firmware_header_v1_0 *hdr =
2470 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2471 fw_data = (const __le32 *)
2472 (adev->gfx.mec_fw->data +
2473 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2474 table_offset = le32_to_cpu(hdr->jt_offset);
2475 table_size = le32_to_cpu(hdr->jt_size);
2477 const struct gfx_firmware_header_v1_0 *hdr =
2478 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2479 fw_data = (const __le32 *)
2480 (adev->gfx.mec2_fw->data +
2481 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2482 table_offset = le32_to_cpu(hdr->jt_offset);
2483 table_size = le32_to_cpu(hdr->jt_size);
2486 for (i = 0; i < table_size; i ++) {
2487 dst_ptr[bo_offset + i] =
2488 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2491 bo_offset += table_size;
2495 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2501 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2502 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
2503 WREG32(RLC_TTOP_D, tmp);
2505 tmp = RREG32(RLC_PG_CNTL);
2506 tmp |= GFX_PG_ENABLE;
2507 WREG32(RLC_PG_CNTL, tmp);
2509 tmp = RREG32(RLC_AUTO_PG_CTRL);
2511 WREG32(RLC_AUTO_PG_CTRL, tmp);
2513 tmp = RREG32(RLC_AUTO_PG_CTRL);
2515 WREG32(RLC_AUTO_PG_CTRL, tmp);
2517 tmp = RREG32(DB_RENDER_CONTROL);
2521 static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2525 u32 mask = 0, tmp, tmp1;
2528 mutex_lock(&adev->grbm_idx_mutex);
2529 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2530 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2531 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2532 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2533 mutex_unlock(&adev->grbm_idx_mutex);
2540 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2545 return (~tmp) & mask;
2548 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2550 u32 i, j, k, active_cu_number = 0;
2552 u32 mask, counter, cu_bitmap;
2555 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2556 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2560 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2561 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2569 active_cu_number += counter;
2570 tmp |= (cu_bitmap << (i * 16 + j * 8));
2574 WREG32(RLC_PG_AO_CU_MASK, tmp);
2576 tmp = RREG32(RLC_MAX_PG_CU);
2577 tmp &= ~MAX_PU_CU_MASK;
2578 tmp |= MAX_PU_CU(active_cu_number);
2579 WREG32(RLC_MAX_PG_CU, tmp);
2582 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2587 orig = data = RREG32(RLC_PG_CNTL);
2588 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2589 data |= STATIC_PER_CU_PG_ENABLE;
2591 data &= ~STATIC_PER_CU_PG_ENABLE;
2593 WREG32(RLC_PG_CNTL, data);
2596 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2601 orig = data = RREG32(RLC_PG_CNTL);
2602 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2603 data |= DYN_PER_CU_PG_ENABLE;
2605 data &= ~DYN_PER_CU_PG_ENABLE;
2607 WREG32(RLC_PG_CNTL, data);
2610 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2614 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2616 tmp = RREG32(RLC_PG_CNTL);
2618 WREG32(RLC_PG_CNTL, tmp);
2620 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2622 tmp = RREG32(RLC_AUTO_PG_CTRL);
2624 tmp &= ~GRBM_REG_SGIT_MASK;
2625 tmp |= GRBM_REG_SGIT(0x700);
2626 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
2627 WREG32(RLC_AUTO_PG_CTRL, tmp);
2630 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2632 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2633 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2634 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2637 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2640 const struct cs_section_def *sect = NULL;
2641 const struct cs_extent_def *ext = NULL;
2643 if (adev->gfx.rlc.cs_data == NULL)
2646 /* begin clear state */
2648 /* context control state */
2651 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2652 for (ext = sect->section; ext->extent != NULL; ++ext) {
2653 if (sect->id == SECT_CONTEXT)
2654 count += 2 + ext->reg_count;
2659 /* pa_sc_raster_config */
2661 /* end clear state */
2669 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2670 volatile u32 *buffer)
2673 const struct cs_section_def *sect = NULL;
2674 const struct cs_extent_def *ext = NULL;
2676 if (adev->gfx.rlc.cs_data == NULL)
2681 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2682 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2684 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2685 buffer[count++] = cpu_to_le32(0x80000000);
2686 buffer[count++] = cpu_to_le32(0x80000000);
2688 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2689 for (ext = sect->section; ext->extent != NULL; ++ext) {
2690 if (sect->id == SECT_CONTEXT) {
2692 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2693 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2694 for (i = 0; i < ext->reg_count; i++)
2695 buffer[count++] = cpu_to_le32(ext->extent[i]);
2702 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2703 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2705 switch (adev->asic_type) {
2708 buffer[count++] = cpu_to_le32(0x2a00126a);
2711 buffer[count++] = cpu_to_le32(0x0000124a);
2714 buffer[count++] = cpu_to_le32(0x00000082);
2717 buffer[count++] = cpu_to_le32(0x00000000);
2720 buffer[count++] = cpu_to_le32(0x00000000);
2724 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2725 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2727 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2728 buffer[count++] = cpu_to_le32(0);
2731 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2733 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2734 AMD_PG_SUPPORT_GFX_SMG |
2735 AMD_PG_SUPPORT_GFX_DMG |
2737 AMD_PG_SUPPORT_GDS |
2738 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2739 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2740 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2741 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2742 gfx_v6_0_init_gfx_cgpg(adev);
2743 gfx_v6_0_enable_cp_pg(adev, true);
2744 gfx_v6_0_enable_gds_pg(adev, true);
2746 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2747 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2750 gfx_v6_0_init_ao_cu_mask(adev);
2751 gfx_v6_0_update_gfx_pg(adev, true);
2754 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2755 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2759 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2761 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2762 AMD_PG_SUPPORT_GFX_SMG |
2763 AMD_PG_SUPPORT_GFX_DMG |
2765 AMD_PG_SUPPORT_GDS |
2766 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2767 gfx_v6_0_update_gfx_pg(adev, false);
2768 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2769 gfx_v6_0_enable_cp_pg(adev, false);
2770 gfx_v6_0_enable_gds_pg(adev, false);
2775 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2779 mutex_lock(&adev->gfx.gpu_clock_mutex);
2780 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2781 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
2782 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2783 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2787 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2789 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2790 amdgpu_ring_write(ring, 0x80000000);
2791 amdgpu_ring_write(ring, 0);
2794 static unsigned gfx_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
2797 6; /* gfx_v6_0_ring_emit_ib */
2800 static unsigned gfx_v6_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
2803 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2804 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2805 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2806 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
2807 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
2808 3; /* gfx_v6_ring_emit_cntxcntl */
2811 static unsigned gfx_v6_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring)
2814 5 + /* gfx_v6_0_ring_emit_hdp_flush */
2815 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
2816 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
2817 17 + /* gfx_v6_0_ring_emit_vm_flush */
2818 14 + 14 + 14; /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
2821 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2822 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2823 .select_se_sh = &gfx_v6_0_select_se_sh,
2826 static int gfx_v6_0_early_init(void *handle)
2828 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2830 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
2831 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
2832 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
2833 gfx_v6_0_set_ring_funcs(adev);
2834 gfx_v6_0_set_irq_funcs(adev);
2839 static int gfx_v6_0_sw_init(void *handle)
2841 struct amdgpu_ring *ring;
2842 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2845 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
2849 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
2853 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2857 gfx_v6_0_scratch_init(adev);
2859 r = gfx_v6_0_init_microcode(adev);
2861 DRM_ERROR("Failed to load gfx firmware!\n");
2865 r = gfx_v6_0_rlc_init(adev);
2867 DRM_ERROR("Failed to init rlc BOs!\n");
2871 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2872 ring = &adev->gfx.gfx_ring[i];
2873 ring->ring_obj = NULL;
2874 sprintf(ring->name, "gfx");
2875 r = amdgpu_ring_init(adev, ring, 1024,
2877 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
2878 AMDGPU_RING_TYPE_GFX);
2883 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2886 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2887 DRM_ERROR("Too many (%d) compute rings!\n", i);
2890 ring = &adev->gfx.compute_ring[i];
2891 ring->ring_obj = NULL;
2892 ring->use_doorbell = false;
2893 ring->doorbell_index = 0;
2897 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
2898 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2899 r = amdgpu_ring_init(adev, ring, 1024,
2901 &adev->gfx.eop_irq, irq_type,
2902 AMDGPU_RING_TYPE_COMPUTE);
2910 static int gfx_v6_0_sw_fini(void *handle)
2913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2915 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
2916 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
2917 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
2919 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2920 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2921 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2922 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2924 gfx_v6_0_rlc_fini(adev);
2929 static int gfx_v6_0_hw_init(void *handle)
2932 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2934 gfx_v6_0_gpu_init(adev);
2936 r = gfx_v6_0_rlc_resume(adev);
2940 r = gfx_v6_0_cp_resume(adev);
2944 adev->gfx.ce_ram_size = 0x8000;
2949 static int gfx_v6_0_hw_fini(void *handle)
2951 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2953 gfx_v6_0_cp_enable(adev, false);
2954 gfx_v6_0_rlc_stop(adev);
2955 gfx_v6_0_fini_pg(adev);
2960 static int gfx_v6_0_suspend(void *handle)
2962 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2964 return gfx_v6_0_hw_fini(adev);
2967 static int gfx_v6_0_resume(void *handle)
2969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2971 return gfx_v6_0_hw_init(adev);
2974 static bool gfx_v6_0_is_idle(void *handle)
2976 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2978 if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2984 static int gfx_v6_0_wait_for_idle(void *handle)
2987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2989 for (i = 0; i < adev->usec_timeout; i++) {
2990 if (gfx_v6_0_is_idle(handle))
2997 static int gfx_v6_0_soft_reset(void *handle)
3002 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3003 enum amdgpu_interrupt_state state)
3008 case AMDGPU_IRQ_STATE_DISABLE:
3009 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3010 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3011 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3013 case AMDGPU_IRQ_STATE_ENABLE:
3014 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3015 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3016 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3023 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3025 enum amdgpu_interrupt_state state)
3029 case AMDGPU_IRQ_STATE_DISABLE:
3031 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
3032 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3033 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
3036 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
3037 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3038 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
3042 case AMDGPU_IRQ_STATE_ENABLE:
3044 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
3045 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3046 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
3049 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
3050 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
3051 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
3063 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3064 struct amdgpu_irq_src *src,
3066 enum amdgpu_interrupt_state state)
3071 case AMDGPU_IRQ_STATE_DISABLE:
3072 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3073 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3074 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3076 case AMDGPU_IRQ_STATE_ENABLE:
3077 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3078 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3079 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3088 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3089 struct amdgpu_irq_src *src,
3091 enum amdgpu_interrupt_state state)
3096 case AMDGPU_IRQ_STATE_DISABLE:
3097 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3098 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3099 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3101 case AMDGPU_IRQ_STATE_ENABLE:
3102 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3103 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3104 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3113 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3114 struct amdgpu_irq_src *src,
3116 enum amdgpu_interrupt_state state)
3119 case AMDGPU_CP_IRQ_GFX_EOP:
3120 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3122 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3123 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3125 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3126 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3134 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3135 struct amdgpu_irq_src *source,
3136 struct amdgpu_iv_entry *entry)
3138 switch (entry->ring_id) {
3140 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3144 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]);
3152 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3153 struct amdgpu_irq_src *source,
3154 struct amdgpu_iv_entry *entry)
3156 DRM_ERROR("Illegal register access in command stream\n");
3157 schedule_work(&adev->reset_work);
3161 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3162 struct amdgpu_irq_src *source,
3163 struct amdgpu_iv_entry *entry)
3165 DRM_ERROR("Illegal instruction in command stream\n");
3166 schedule_work(&adev->reset_work);
3170 static int gfx_v6_0_set_clockgating_state(void *handle,
3171 enum amd_clockgating_state state)
3174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3176 if (state == AMD_CG_STATE_GATE)
3179 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3181 gfx_v6_0_enable_mgcg(adev, true);
3182 gfx_v6_0_enable_cgcg(adev, true);
3184 gfx_v6_0_enable_cgcg(adev, false);
3185 gfx_v6_0_enable_mgcg(adev, false);
3187 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3192 static int gfx_v6_0_set_powergating_state(void *handle,
3193 enum amd_powergating_state state)
3196 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3198 if (state == AMD_PG_STATE_GATE)
3201 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3202 AMD_PG_SUPPORT_GFX_SMG |
3203 AMD_PG_SUPPORT_GFX_DMG |
3205 AMD_PG_SUPPORT_GDS |
3206 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3207 gfx_v6_0_update_gfx_pg(adev, gate);
3208 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3209 gfx_v6_0_enable_cp_pg(adev, gate);
3210 gfx_v6_0_enable_gds_pg(adev, gate);
3217 const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3219 .early_init = gfx_v6_0_early_init,
3221 .sw_init = gfx_v6_0_sw_init,
3222 .sw_fini = gfx_v6_0_sw_fini,
3223 .hw_init = gfx_v6_0_hw_init,
3224 .hw_fini = gfx_v6_0_hw_fini,
3225 .suspend = gfx_v6_0_suspend,
3226 .resume = gfx_v6_0_resume,
3227 .is_idle = gfx_v6_0_is_idle,
3228 .wait_for_idle = gfx_v6_0_wait_for_idle,
3229 .soft_reset = gfx_v6_0_soft_reset,
3230 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3231 .set_powergating_state = gfx_v6_0_set_powergating_state,
3234 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3235 .get_rptr = gfx_v6_0_ring_get_rptr,
3236 .get_wptr = gfx_v6_0_ring_get_wptr,
3237 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3239 .emit_ib = gfx_v6_0_ring_emit_ib,
3240 .emit_fence = gfx_v6_0_ring_emit_fence,
3241 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3242 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3243 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3244 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3245 .test_ring = gfx_v6_0_ring_test_ring,
3246 .test_ib = gfx_v6_0_ring_test_ib,
3247 .insert_nop = amdgpu_ring_insert_nop,
3248 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3249 .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3250 .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_gfx,
3253 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3254 .get_rptr = gfx_v6_0_ring_get_rptr,
3255 .get_wptr = gfx_v6_0_ring_get_wptr,
3256 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3258 .emit_ib = gfx_v6_0_ring_emit_ib,
3259 .emit_fence = gfx_v6_0_ring_emit_fence,
3260 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3261 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3262 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3263 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3264 .test_ring = gfx_v6_0_ring_test_ring,
3265 .test_ib = gfx_v6_0_ring_test_ib,
3266 .insert_nop = amdgpu_ring_insert_nop,
3267 .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size,
3268 .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_compute,
3271 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3275 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3276 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3277 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3278 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3281 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3282 .set = gfx_v6_0_set_eop_interrupt_state,
3283 .process = gfx_v6_0_eop_irq,
3286 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3287 .set = gfx_v6_0_set_priv_reg_fault_state,
3288 .process = gfx_v6_0_priv_reg_irq,
3291 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3292 .set = gfx_v6_0_set_priv_inst_fault_state,
3293 .process = gfx_v6_0_priv_inst_irq,
3296 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3298 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3299 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3301 adev->gfx.priv_reg_irq.num_types = 1;
3302 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3304 adev->gfx.priv_inst_irq.num_types = 1;
3305 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3308 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3310 int i, j, k, counter, active_cu_number = 0;
3311 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3312 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3314 memset(cu_info, 0, sizeof(*cu_info));
3316 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3317 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3321 bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3322 cu_info->bitmap[i][j] = bitmap;
3324 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3325 if (bitmap & mask) {
3332 active_cu_number += counter;
3333 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3337 cu_info->number = active_cu_number;
3338 cu_info->ao_cu_mask = ao_cu_mask;