drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "amdgpu_gfx.h"
  27 #include "amdgpu_ucode.h"
  28 #include "clearstate_si.h"
  29 #include "bif/bif_3_0_d.h"
  30 #include "bif/bif_3_0_sh_mask.h"
  31 #include "oss/oss_1_0_d.h"
  32 #include "oss/oss_1_0_sh_mask.h"
  33 #include "gca/gfx_6_0_d.h"
  34 #include "gca/gfx_6_0_sh_mask.h"
  35 #include "gmc/gmc_6_0_d.h"
  36 #include "gmc/gmc_6_0_sh_mask.h"
  37 #include "dce/dce_6_0_d.h"
  38 #include "dce/dce_6_0_sh_mask.h"
  39 #include "gca/gfx_7_2_enum.h"
  40 #include "si_enums.h"
  41
  42 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  43 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
  45
  46 /*(DEBLOBBED)*/
  47
  48 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
  49 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
  50 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
  51 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
  52
  53 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  54 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  55 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  56 #define MICRO_TILE_MODE(x)                              ((x) << 0)
  57 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  58 #define BANK_WIDTH(x)                                   ((x) << 14)
  59 #define BANK_HEIGHT(x)                                  ((x) << 16)
  60 #define MACRO_TILE_ASPECT(x)                            ((x) << 18)
  61 #define NUM_BANKS(x)                                    ((x) << 20)
  62
  63 static const u32 verde_rlc_save_restore_register_list[] =
  64 {
  65         (0x8000 << 16) | (0x98f4 >> 2),
  66         0x00000000,
  67         (0x8040 << 16) | (0x98f4 >> 2),
  68         0x00000000,
  69         (0x8000 << 16) | (0xe80 >> 2),
  70         0x00000000,
  71         (0x8040 << 16) | (0xe80 >> 2),
  72         0x00000000,
  73         (0x8000 << 16) | (0x89bc >> 2),
  74         0x00000000,
  75         (0x8040 << 16) | (0x89bc >> 2),
  76         0x00000000,
  77         (0x8000 << 16) | (0x8c1c >> 2),
  78         0x00000000,
  79         (0x8040 << 16) | (0x8c1c >> 2),
  80         0x00000000,
  81         (0x9c00 << 16) | (0x98f0 >> 2),
  82         0x00000000,
  83         (0x9c00 << 16) | (0xe7c >> 2),
  84         0x00000000,
  85         (0x8000 << 16) | (0x9148 >> 2),
  86         0x00000000,
  87         (0x8040 << 16) | (0x9148 >> 2),
  88         0x00000000,
  89         (0x9c00 << 16) | (0x9150 >> 2),
  90         0x00000000,
  91         (0x9c00 << 16) | (0x897c >> 2),
  92         0x00000000,
  93         (0x9c00 << 16) | (0x8d8c >> 2),
  94         0x00000000,
  95         (0x9c00 << 16) | (0xac54 >> 2),
  96         0X00000000,
  97         0x3,
  98         (0x9c00 << 16) | (0x98f8 >> 2),
  99         0x00000000,
 100         (0x9c00 << 16) | (0x9910 >> 2),
 101         0x00000000,
 102         (0x9c00 << 16) | (0x9914 >> 2),
 103         0x00000000,
 104         (0x9c00 << 16) | (0x9918 >> 2),
 105         0x00000000,
 106         (0x9c00 << 16) | (0x991c >> 2),
 107         0x00000000,
 108         (0x9c00 << 16) | (0x9920 >> 2),
 109         0x00000000,
 110         (0x9c00 << 16) | (0x9924 >> 2),
 111         0x00000000,
 112         (0x9c00 << 16) | (0x9928 >> 2),
 113         0x00000000,
 114         (0x9c00 << 16) | (0x992c >> 2),
 115         0x00000000,
 116         (0x9c00 << 16) | (0x9930 >> 2),
 117         0x00000000,
 118         (0x9c00 << 16) | (0x9934 >> 2),
 119         0x00000000,
 120         (0x9c00 << 16) | (0x9938 >> 2),
 121         0x00000000,
 122         (0x9c00 << 16) | (0x993c >> 2),
 123         0x00000000,
 124         (0x9c00 << 16) | (0x9940 >> 2),
 125         0x00000000,
 126         (0x9c00 << 16) | (0x9944 >> 2),
 127         0x00000000,
 128         (0x9c00 << 16) | (0x9948 >> 2),
 129         0x00000000,
 130         (0x9c00 << 16) | (0x994c >> 2),
 131         0x00000000,
 132         (0x9c00 << 16) | (0x9950 >> 2),
 133         0x00000000,
 134         (0x9c00 << 16) | (0x9954 >> 2),
 135         0x00000000,
 136         (0x9c00 << 16) | (0x9958 >> 2),
 137         0x00000000,
 138         (0x9c00 << 16) | (0x995c >> 2),
 139         0x00000000,
 140         (0x9c00 << 16) | (0x9960 >> 2),
 141         0x00000000,
 142         (0x9c00 << 16) | (0x9964 >> 2),
 143         0x00000000,
 144         (0x9c00 << 16) | (0x9968 >> 2),
 145         0x00000000,
 146         (0x9c00 << 16) | (0x996c >> 2),
 147         0x00000000,
 148         (0x9c00 << 16) | (0x9970 >> 2),
 149         0x00000000,
 150         (0x9c00 << 16) | (0x9974 >> 2),
 151         0x00000000,
 152         (0x9c00 << 16) | (0x9978 >> 2),
 153         0x00000000,
 154         (0x9c00 << 16) | (0x997c >> 2),
 155         0x00000000,
 156         (0x9c00 << 16) | (0x9980 >> 2),
 157         0x00000000,
 158         (0x9c00 << 16) | (0x9984 >> 2),
 159         0x00000000,
 160         (0x9c00 << 16) | (0x9988 >> 2),
 161         0x00000000,
 162         (0x9c00 << 16) | (0x998c >> 2),
 163         0x00000000,
 164         (0x9c00 << 16) | (0x8c00 >> 2),
 165         0x00000000,
 166         (0x9c00 << 16) | (0x8c14 >> 2),
 167         0x00000000,
 168         (0x9c00 << 16) | (0x8c04 >> 2),
 169         0x00000000,
 170         (0x9c00 << 16) | (0x8c08 >> 2),
 171         0x00000000,
 172         (0x8000 << 16) | (0x9b7c >> 2),
 173         0x00000000,
 174         (0x8040 << 16) | (0x9b7c >> 2),
 175         0x00000000,
 176         (0x8000 << 16) | (0xe84 >> 2),
 177         0x00000000,
 178         (0x8040 << 16) | (0xe84 >> 2),
 179         0x00000000,
 180         (0x8000 << 16) | (0x89c0 >> 2),
 181         0x00000000,
 182         (0x8040 << 16) | (0x89c0 >> 2),
 183         0x00000000,
 184         (0x8000 << 16) | (0x914c >> 2),
 185         0x00000000,
 186         (0x8040 << 16) | (0x914c >> 2),
 187         0x00000000,
 188         (0x8000 << 16) | (0x8c20 >> 2),
 189         0x00000000,
 190         (0x8040 << 16) | (0x8c20 >> 2),
 191         0x00000000,
 192         (0x8000 << 16) | (0x9354 >> 2),
 193         0x00000000,
 194         (0x8040 << 16) | (0x9354 >> 2),
 195         0x00000000,
 196         (0x9c00 << 16) | (0x9060 >> 2),
 197         0x00000000,
 198         (0x9c00 << 16) | (0x9364 >> 2),
 199         0x00000000,
 200         (0x9c00 << 16) | (0x9100 >> 2),
 201         0x00000000,
 202         (0x9c00 << 16) | (0x913c >> 2),
 203         0x00000000,
 204         (0x8000 << 16) | (0x90e0 >> 2),
 205         0x00000000,
 206         (0x8000 << 16) | (0x90e4 >> 2),
 207         0x00000000,
 208         (0x8000 << 16) | (0x90e8 >> 2),
 209         0x00000000,
 210         (0x8040 << 16) | (0x90e0 >> 2),
 211         0x00000000,
 212         (0x8040 << 16) | (0x90e4 >> 2),
 213         0x00000000,
 214         (0x8040 << 16) | (0x90e8 >> 2),
 215         0x00000000,
 216         (0x9c00 << 16) | (0x8bcc >> 2),
 217         0x00000000,
 218         (0x9c00 << 16) | (0x8b24 >> 2),
 219         0x00000000,
 220         (0x9c00 << 16) | (0x88c4 >> 2),
 221         0x00000000,
 222         (0x9c00 << 16) | (0x8e50 >> 2),
 223         0x00000000,
 224         (0x9c00 << 16) | (0x8c0c >> 2),
 225         0x00000000,
 226         (0x9c00 << 16) | (0x8e58 >> 2),
 227         0x00000000,
 228         (0x9c00 << 16) | (0x8e5c >> 2),
 229         0x00000000,
 230         (0x9c00 << 16) | (0x9508 >> 2),
 231         0x00000000,
 232         (0x9c00 << 16) | (0x950c >> 2),
 233         0x00000000,
 234         (0x9c00 << 16) | (0x9494 >> 2),
 235         0x00000000,
 236         (0x9c00 << 16) | (0xac0c >> 2),
 237         0x00000000,
 238         (0x9c00 << 16) | (0xac10 >> 2),
 239         0x00000000,
 240         (0x9c00 << 16) | (0xac14 >> 2),
 241         0x00000000,
 242         (0x9c00 << 16) | (0xae00 >> 2),
 243         0x00000000,
 244         (0x9c00 << 16) | (0xac08 >> 2),
 245         0x00000000,
 246         (0x9c00 << 16) | (0x88d4 >> 2),
 247         0x00000000,
 248         (0x9c00 << 16) | (0x88c8 >> 2),
 249         0x00000000,
 250         (0x9c00 << 16) | (0x88cc >> 2),
 251         0x00000000,
 252         (0x9c00 << 16) | (0x89b0 >> 2),
 253         0x00000000,
 254         (0x9c00 << 16) | (0x8b10 >> 2),
 255         0x00000000,
 256         (0x9c00 << 16) | (0x8a14 >> 2),
 257         0x00000000,
 258         (0x9c00 << 16) | (0x9830 >> 2),
 259         0x00000000,
 260         (0x9c00 << 16) | (0x9834 >> 2),
 261         0x00000000,
 262         (0x9c00 << 16) | (0x9838 >> 2),
 263         0x00000000,
 264         (0x9c00 << 16) | (0x9a10 >> 2),
 265         0x00000000,
 266         (0x8000 << 16) | (0x9870 >> 2),
 267         0x00000000,
 268         (0x8000 << 16) | (0x9874 >> 2),
 269         0x00000000,
 270         (0x8001 << 16) | (0x9870 >> 2),
 271         0x00000000,
 272         (0x8001 << 16) | (0x9874 >> 2),
 273         0x00000000,
 274         (0x8040 << 16) | (0x9870 >> 2),
 275         0x00000000,
 276         (0x8040 << 16) | (0x9874 >> 2),
 277         0x00000000,
 278         (0x8041 << 16) | (0x9870 >> 2),
 279         0x00000000,
 280         (0x8041 << 16) | (0x9874 >> 2),
 281         0x00000000,
 282         0x00000000
 283 };
 284
 285 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 286 {
 287         const char *chip_name;
 288         char fw_name[30];
 289         int err;
 290         const struct gfx_firmware_header_v1_0 *cp_hdr;
 291         const struct rlc_firmware_header_v1_0 *rlc_hdr;
 292
 293         DRM_DEBUG("\n");
 294
 295         switch (adev->asic_type) {
 296         case CHIP_TAHITI:
 297                 chip_name = "tahiti";
 298                 break;
 299         case CHIP_PITCAIRN:
 300                 chip_name = "pitcairn";
 301                 break;
 302         case CHIP_VERDE:
 303                 chip_name = "verde";
 304                 break;
 305         case CHIP_OLAND:
 306                 chip_name = "oland";
 307                 break;
 308         case CHIP_HAINAN:
 309                 chip_name = "hainan";
 310                 break;
 311         default: BUG();
 312         }
 313
 314         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 315         err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 316         if (err)
 317                 goto out;
 318         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 319         if (err)
 320                 goto out;
 321         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 322         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 323         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 324
 325         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 326         err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 327         if (err)
 328                 goto out;
 329         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 330         if (err)
 331                 goto out;
 332         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 333         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 334         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 335
 336         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 337         err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 338         if (err)
 339                 goto out;
 340         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 341         if (err)
 342                 goto out;
 343         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 344         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 345         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 346
 347         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 348         err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 349         if (err)
 350                 goto out;
 351         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 352         rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 353         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 354         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 355
 356 out:
 357         if (err) {
 358                 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
 359                 release_firmware(adev->gfx.pfp_fw);
 360                 adev->gfx.pfp_fw = NULL;
 361                 release_firmware(adev->gfx.me_fw);
 362                 adev->gfx.me_fw = NULL;
 363                 release_firmware(adev->gfx.ce_fw);
 364                 adev->gfx.ce_fw = NULL;
 365                 release_firmware(adev->gfx.rlc_fw);
 366                 adev->gfx.rlc_fw = NULL;
 367         }
 368         return err;
 369 }
 370
 371 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
 372 {
 373         const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 374         u32 reg_offset, split_equal_to_row_size, *tilemode;
 375
 376         memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
 377         tilemode = adev->gfx.config.tile_mode_array;
 378
 379         switch (adev->gfx.config.mem_row_size_in_kb) {
 380         case 1:
 381                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 382                 break;
 383         case 2:
 384         default:
 385                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 386                 break;
 387         case 4:
 388                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 389                 break;
 390         }
 391
 392         if (adev->asic_type == CHIP_VERDE) {
 393                 tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 394                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 395                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 396                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 397                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 398                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 399                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 400                                 NUM_BANKS(ADDR_SURF_16_BANK);
 401                 tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 402                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 403                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 404                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 405                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 406                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 407                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 408                                 NUM_BANKS(ADDR_SURF_16_BANK);
 409                 tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 410                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 411                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 412                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 413                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 414                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 415                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 416                                 NUM_BANKS(ADDR_SURF_16_BANK);
 417                 tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 418                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 419                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 420                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 421                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 422                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 423                                 NUM_BANKS(ADDR_SURF_8_BANK) |
 424                                 TILE_SPLIT(split_equal_to_row_size);
 425                 tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 426                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 427                                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 428                 tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 429                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 430                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 431                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 432                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 433                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 434                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 435                                 NUM_BANKS(ADDR_SURF_4_BANK);
 436                 tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 437                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 438                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 439                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 440                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 441                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 442                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 443                                 NUM_BANKS(ADDR_SURF_4_BANK);
 444                 tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 445                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 446                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 447                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 448                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 449                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 450                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 451                                 NUM_BANKS(ADDR_SURF_2_BANK);
 452                 tilemode[8] =   ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
 453                 tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 454                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 455                                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 456                 tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 457                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 458                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 459                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 460                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 461                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 462                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 463                                 NUM_BANKS(ADDR_SURF_16_BANK);
 464                 tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 465                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 466                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 467                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 468                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 469                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 470                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 471                                 NUM_BANKS(ADDR_SURF_16_BANK);
 472                 tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 473                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 474                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 475                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 476                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 477                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 478                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 479                                 NUM_BANKS(ADDR_SURF_16_BANK);
 480                 tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 481                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 482                                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 483                 tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 484                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 485                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 486                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 487                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 488                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 489                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 490                                 NUM_BANKS(ADDR_SURF_16_BANK);
 491                 tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 492                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 493                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 494                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 495                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 496                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 497                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 498                                 NUM_BANKS(ADDR_SURF_16_BANK);
 499                 tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 500                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 501                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 502                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 503                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 504                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 505                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 506                                 NUM_BANKS(ADDR_SURF_16_BANK);
 507                 tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 508                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 509                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 510                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 511                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 512                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 513                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 514                                 TILE_SPLIT(split_equal_to_row_size);
 515                 tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 516                                 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
 517                                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 518                 tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 519                                 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
 520                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 521                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 522                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 523                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 524                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 525                                 TILE_SPLIT(split_equal_to_row_size);
 526                 tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 527                                 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
 528                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 529                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 530                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 531                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 532                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 533                                 TILE_SPLIT(split_equal_to_row_size);
 534                 tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 535                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 536                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 537                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 538                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 539                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 540                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 541                                 NUM_BANKS(ADDR_SURF_8_BANK);
 542                 tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 543                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 544                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 545                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 546                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 547                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 548                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 549                                 NUM_BANKS(ADDR_SURF_8_BANK);
 550                 tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 551                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 552                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 553                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 554                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 555                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 556                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 557                                 NUM_BANKS(ADDR_SURF_4_BANK);
 558                 tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 559                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 560                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 561                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 562                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 563                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 564                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 565                                 NUM_BANKS(ADDR_SURF_4_BANK);
 566                 tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 567                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 568                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 569                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 570                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 571                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 572                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 573                                 NUM_BANKS(ADDR_SURF_2_BANK);
 574                 tilemode[26] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 575                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 576                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 577                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 578                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 579                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 580                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 581                                 NUM_BANKS(ADDR_SURF_2_BANK);
 582                 tilemode[27] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 583                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 584                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 585                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 586                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 587                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 588                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 589                                 NUM_BANKS(ADDR_SURF_2_BANK);
 590                 tilemode[28] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 591                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 592                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 593                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 594                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 595                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 596                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 597                                 NUM_BANKS(ADDR_SURF_2_BANK);
 598                 tilemode[29] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 599                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 600                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 601                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 602                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 603                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 604                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 605                                 NUM_BANKS(ADDR_SURF_2_BANK);
 606                 tilemode[30] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 607                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 608                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 609                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 610                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 611                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 612                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 613                                 NUM_BANKS(ADDR_SURF_2_BANK);
 614                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
 615                         WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
 616         } else if (adev->asic_type == CHIP_OLAND) {
 617                 tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 618                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 619                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 620                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 621                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 622                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 623                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 624                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
 625                 tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 626                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 627                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 628                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 629                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 630                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 631                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 632                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
 633                 tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 634                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 635                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 636                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 637                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 638                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 639                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 640                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
 641                 tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 642                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 643                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 644                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 645                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 646                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 647                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 648                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
 649                 tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 650                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 651                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 652                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 653                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 654                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 655                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 656                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 657                 tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 658                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 659                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 660                                 TILE_SPLIT(split_equal_to_row_size) |
 661                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 662                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 663                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 664                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 665                 tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 666                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 667                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 668                                 TILE_SPLIT(split_equal_to_row_size) |
 669                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 670                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 671                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 672                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 673                 tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 674                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 675                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 676                                 TILE_SPLIT(split_equal_to_row_size) |
 677                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 678                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 679                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 680                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
 681                 tilemode[8] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 682                                 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 683                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 684                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 685                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 686                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 687                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 688                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 689                 tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 690                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 691                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 692                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 693                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 694                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 695                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 696                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 697                 tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 698                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 699                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 700                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 701                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 702                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 703                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 704                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
 705                 tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 706                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 707                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 708                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 709                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 710                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 711                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 712                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 713                 tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 714                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 715                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 716                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 717                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 718                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 719                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 720                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 721                 tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 722                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 723                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 724                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 725                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 726                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 727                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 728                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 729                 tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 730                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 731                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 732                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 733                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 734                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 735                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 736                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 737                 tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 738                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 739                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 740                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 741                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 742                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 743                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 744                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 745                 tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 746                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 747                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 748                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 749                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 750                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 751                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 752                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 753                 tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 754                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 755                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 756                                 TILE_SPLIT(split_equal_to_row_size) |
 757                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 758                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 759                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 760                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 761                 tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 762                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 763                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 764                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 765                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 766                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 767                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 768                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 769                 tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 770                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 771                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 772                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 773                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 774                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 775                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 776                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
 777                 tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 778                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 779                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 780                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 781                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 782                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 783                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 784                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 785                 tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 786                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 787                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 788                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 789                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 790                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 791                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 792                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
 793                 tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 794                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 795                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 796                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 797                                 NUM_BANKS(ADDR_SURF_8_BANK) |
 798                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 799                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 800                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
 801                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
 802                         WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
 803         } else if (adev->asic_type == CHIP_HAINAN) {
 804                 tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 805                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 806                                 PIPE_CONFIG(ADDR_SURF_P2) |
 807                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 808                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 809                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 810                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 811                                 NUM_BANKS(ADDR_SURF_16_BANK);
 812                 tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 813                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 814                                 PIPE_CONFIG(ADDR_SURF_P2) |
 815                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 816                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 817                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 818                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 819                                 NUM_BANKS(ADDR_SURF_16_BANK);
 820                 tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 821                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 822                                 PIPE_CONFIG(ADDR_SURF_P2) |
 823                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 824                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 825                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 826                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 827                                 NUM_BANKS(ADDR_SURF_16_BANK);
 828                 tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 829                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 830                                 PIPE_CONFIG(ADDR_SURF_P2) |
 831                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 832                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 833                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 834                                 NUM_BANKS(ADDR_SURF_8_BANK) |
 835                                 TILE_SPLIT(split_equal_to_row_size);
 836                 tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 837                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 838                                 PIPE_CONFIG(ADDR_SURF_P2);
 839                 tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 840                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 841                                 PIPE_CONFIG(ADDR_SURF_P2) |
 842                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 843                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 844                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 845                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 846                                 NUM_BANKS(ADDR_SURF_8_BANK);
 847                 tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 848                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 849                                 PIPE_CONFIG(ADDR_SURF_P2) |
 850                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 851                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 852                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 853                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 854                                 NUM_BANKS(ADDR_SURF_8_BANK);
 855                 tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 856                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 857                                 PIPE_CONFIG(ADDR_SURF_P2) |
 858                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 859                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 860                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 861                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 862                                 NUM_BANKS(ADDR_SURF_4_BANK);
 863                 tilemode[8] =   ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
 864                 tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 865                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 866                                 PIPE_CONFIG(ADDR_SURF_P2);
 867                 tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 868                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 869                                 PIPE_CONFIG(ADDR_SURF_P2) |
 870                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 871                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 872                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 873                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 874                                 NUM_BANKS(ADDR_SURF_16_BANK);
 875                 tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 876                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 877                                 PIPE_CONFIG(ADDR_SURF_P2) |
 878                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 879                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 880                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 881                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 882                                 NUM_BANKS(ADDR_SURF_16_BANK);
 883                 tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 884                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 885                                 PIPE_CONFIG(ADDR_SURF_P2) |
 886                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 887                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 888                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 889                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 890                                 NUM_BANKS(ADDR_SURF_16_BANK);
 891                 tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 892                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 893                                 PIPE_CONFIG(ADDR_SURF_P2);
 894                 tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 895                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 896                                 PIPE_CONFIG(ADDR_SURF_P2) |
 897                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 898                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 899                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 900                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 901                                 NUM_BANKS(ADDR_SURF_16_BANK);
 902                 tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 903                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 904                                 PIPE_CONFIG(ADDR_SURF_P2) |
 905                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 906                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 907                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 908                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 909                                 NUM_BANKS(ADDR_SURF_16_BANK);
 910                 tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 911                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 912                                 PIPE_CONFIG(ADDR_SURF_P2) |
 913                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 914                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 915                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 916                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 917                                 NUM_BANKS(ADDR_SURF_16_BANK);
 918                 tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 919                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 920                                 PIPE_CONFIG(ADDR_SURF_P2) |
 921                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 922                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 923                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 924                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 925                                 TILE_SPLIT(split_equal_to_row_size);
 926                 tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 927                                 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
 928                                 PIPE_CONFIG(ADDR_SURF_P2);
 929                 tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 930                                 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
 931                                 PIPE_CONFIG(ADDR_SURF_P2) |
 932                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 933                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 934                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 935                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 936                                 TILE_SPLIT(split_equal_to_row_size);
 937                 tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 938                                 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
 939                                 PIPE_CONFIG(ADDR_SURF_P2) |
 940                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 941                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 942                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 943                                 NUM_BANKS(ADDR_SURF_16_BANK) |
 944                                 TILE_SPLIT(split_equal_to_row_size);
 945                 tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 946                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 947                                 PIPE_CONFIG(ADDR_SURF_P2) |
 948                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 949                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 950                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 951                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 952                                 NUM_BANKS(ADDR_SURF_8_BANK);
 953                 tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 954                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 955                                 PIPE_CONFIG(ADDR_SURF_P2) |
 956                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 957                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 958                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 959                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 960                                 NUM_BANKS(ADDR_SURF_8_BANK);
 961                 tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 962                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 963                                 PIPE_CONFIG(ADDR_SURF_P2) |
 964                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 965                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 966                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 967                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 968                                 NUM_BANKS(ADDR_SURF_8_BANK);
 969                 tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 970                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 971                                 PIPE_CONFIG(ADDR_SURF_P2) |
 972                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 973                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 974                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 975                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 976                                 NUM_BANKS(ADDR_SURF_8_BANK);
 977                 tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 978                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 979                                 PIPE_CONFIG(ADDR_SURF_P2) |
 980                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 981                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 982                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 983                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 984                                 NUM_BANKS(ADDR_SURF_4_BANK);
 985                 tilemode[26] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 986                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 987                                 PIPE_CONFIG(ADDR_SURF_P2) |
 988                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 989                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 990                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 991                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 992                                 NUM_BANKS(ADDR_SURF_4_BANK);
 993                 tilemode[27] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 994                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 995                                 PIPE_CONFIG(ADDR_SURF_P2) |
 996                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 997                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 998                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 999                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1000                                 NUM_BANKS(ADDR_SURF_4_BANK);
1001                 tilemode[28] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1002                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1003                                 PIPE_CONFIG(ADDR_SURF_P2) |
1004                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1005                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1006                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1007                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1008                                 NUM_BANKS(ADDR_SURF_4_BANK);
1009                 tilemode[29] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1010                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1011                                 PIPE_CONFIG(ADDR_SURF_P2) |
1012                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1013                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1014                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1015                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1016                                 NUM_BANKS(ADDR_SURF_4_BANK);
1017                 tilemode[30] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1018                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1019                                 PIPE_CONFIG(ADDR_SURF_P2) |
1020                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1021                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1022                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1023                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1024                                 NUM_BANKS(ADDR_SURF_4_BANK);
1025                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1026                         WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1027         } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1028                 tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1029                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1030                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1031                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1032                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1033                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1034                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1035                                 NUM_BANKS(ADDR_SURF_16_BANK);
1036                 tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1037                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1039                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1040                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1041                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1042                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1043                                 NUM_BANKS(ADDR_SURF_16_BANK);
1044                 tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1045                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1047                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1048                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1049                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1050                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1051                                 NUM_BANKS(ADDR_SURF_16_BANK);
1052                 tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1053                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1055                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1056                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1057                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1058                                 NUM_BANKS(ADDR_SURF_4_BANK) |
1059                                 TILE_SPLIT(split_equal_to_row_size);
1060                 tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1061                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1062                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1063                 tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1064                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1065                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1066                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1067                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1068                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1069                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1070                                 NUM_BANKS(ADDR_SURF_2_BANK);
1071                 tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1072                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1073                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1074                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1075                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1076                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1077                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1078                                 NUM_BANKS(ADDR_SURF_2_BANK);
1079                 tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1080                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1081                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1082                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1083                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1084                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1085                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1086                                 NUM_BANKS(ADDR_SURF_2_BANK);
1087                 tilemode[8] =   ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1088                 tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1089                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1090                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1091                 tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1092                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1093                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1094                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1095                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1096                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1097                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1098                                 NUM_BANKS(ADDR_SURF_16_BANK);
1099                 tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1100                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1101                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1102                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1103                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1104                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1105                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1106                                 NUM_BANKS(ADDR_SURF_16_BANK);
1107                 tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1108                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1109                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1110                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1111                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1112                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1113                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1114                                 NUM_BANKS(ADDR_SURF_16_BANK);
1115                 tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1116                                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1117                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1118                 tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1119                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1120                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1121                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1122                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1123                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1124                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1125                                 NUM_BANKS(ADDR_SURF_16_BANK);
1126                 tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1127                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1128                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1129                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1130                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1131                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1132                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1133                                 NUM_BANKS(ADDR_SURF_16_BANK);
1134                 tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1135                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1136                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1137                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1138                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1139                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1140                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1141                                 NUM_BANKS(ADDR_SURF_16_BANK);
1142                 tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1143                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1144                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1145                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1146                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1147                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1148                                 NUM_BANKS(ADDR_SURF_16_BANK) |
1149                                 TILE_SPLIT(split_equal_to_row_size);
1150                 tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1151                                 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1152                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1153                 tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1154                                 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1155                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1156                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1159                                 NUM_BANKS(ADDR_SURF_16_BANK) |
1160                                 TILE_SPLIT(split_equal_to_row_size);
1161                 tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1162                                 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1163                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1164                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1167                                 NUM_BANKS(ADDR_SURF_16_BANK) |
1168                                 TILE_SPLIT(split_equal_to_row_size);
1169                 tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1170                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1171                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1172                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1173                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1174                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1175                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1176                                 NUM_BANKS(ADDR_SURF_4_BANK);
1177                 tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1178                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1179                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1180                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1181                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1182                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1183                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1184                                 NUM_BANKS(ADDR_SURF_4_BANK);
1185                 tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1186                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1187                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1188                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1189                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1191                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1192                                 NUM_BANKS(ADDR_SURF_2_BANK);
1193                 tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1194                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1196                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1197                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1199                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1200                                 NUM_BANKS(ADDR_SURF_2_BANK);
1201                 tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1202                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1204                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1205                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1208                                 NUM_BANKS(ADDR_SURF_2_BANK);
1209                 tilemode[26] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1210                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1211                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1212                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1213                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1214                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1215                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1216                                 NUM_BANKS(ADDR_SURF_2_BANK);
1217                 tilemode[27] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1218                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1219                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1220                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1221                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1222                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1223                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1224                                 NUM_BANKS(ADDR_SURF_2_BANK);
1225                 tilemode[28] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1226                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1228                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1229                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1231                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1232                                 NUM_BANKS(ADDR_SURF_2_BANK);
1233                 tilemode[29] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1234                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1236                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1237                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1240                                 NUM_BANKS(ADDR_SURF_2_BANK);
1241                 tilemode[30] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1242                                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243                                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1244                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1245                                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1246                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1247                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1248                                 NUM_BANKS(ADDR_SURF_2_BANK);
1249                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1250                         WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1251         } else {
1252                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1253         }
1254 }
1255
1256 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1257                                   u32 sh_num, u32 instance)
1258 {
1259         u32 data;
1260
1261         if (instance == 0xffffffff)
1262                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1263         else
1264                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1265
1266         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1267                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1268                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1269         else if (se_num == 0xffffffff)
1270                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1271                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1272         else if (sh_num == 0xffffffff)
1273                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1274                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1275         else
1276                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1277                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1278         WREG32(mmGRBM_GFX_INDEX, data);
1279 }
1280
1281 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1282 {
1283         u32 data, mask;
1284
1285         data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1286                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1287
1288         data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1289
1290         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1291                                          adev->gfx.config.max_sh_per_se);
1292
1293         return ~data & mask;
1294 }
1295
1296 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1297 {
1298         switch (adev->asic_type) {
1299         case CHIP_TAHITI:
1300         case CHIP_PITCAIRN:
1301                 *rconf |=
1302                            (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1303                            (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1304                            (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1305                            (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1306                            (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1307                            (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1308                            (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1309                 break;
1310         case CHIP_VERDE:
1311                 *rconf |=
1312                            (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1313                            (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1314                            (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1315                 break;
1316         case CHIP_OLAND:
1317                 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1318                 break;
1319         case CHIP_HAINAN:
1320                 *rconf |= 0x0;
1321                 break;
1322         default:
1323                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1324                 break;
1325         }
1326 }
1327
1328 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1329                                                     u32 raster_config, unsigned rb_mask,
1330                                                     unsigned num_rb)
1331 {
1332         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1333         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1334         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1335         unsigned rb_per_se = num_rb / num_se;
1336         unsigned se_mask[4];
1337         unsigned se;
1338
1339         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1340         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1341         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1342         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1343
1344         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1345         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1346         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1347
1348         for (se = 0; se < num_se; se++) {
1349                 unsigned raster_config_se = raster_config;
1350                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1351                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1352                 int idx = (se / 2) * 2;
1353
1354                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1355                         raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1356
1357                         if (!se_mask[idx])
1358                                 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1359                         else
1360                                 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1361                 }
1362
1363                 pkr0_mask &= rb_mask;
1364                 pkr1_mask &= rb_mask;
1365                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1366                         raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1367
1368                         if (!pkr0_mask)
1369                                 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1370                         else
1371                                 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1372                 }
1373
1374                 if (rb_per_se >= 2) {
1375                         unsigned rb0_mask = 1 << (se * rb_per_se);
1376                         unsigned rb1_mask = rb0_mask << 1;
1377
1378                         rb0_mask &= rb_mask;
1379                         rb1_mask &= rb_mask;
1380                         if (!rb0_mask || !rb1_mask) {
1381                                 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1382
1383                                 if (!rb0_mask)
1384                                         raster_config_se |=
1385                                                 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1386                                 else
1387                                         raster_config_se |=
1388                                                 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1389                         }
1390
1391                         if (rb_per_se > 2) {
1392                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1393                                 rb1_mask = rb0_mask << 1;
1394                                 rb0_mask &= rb_mask;
1395                                 rb1_mask &= rb_mask;
1396                                 if (!rb0_mask || !rb1_mask) {
1397                                         raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1398
1399                                         if (!rb0_mask)
1400                                                 raster_config_se |=
1401                                                         RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1402                                         else
1403                                                 raster_config_se |=
1404                                                         RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1405                                 }
1406                         }
1407                 }
1408
1409                 /* GRBM_GFX_INDEX has a different offset on SI */
1410                 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1411                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1412         }
1413
1414         /* GRBM_GFX_INDEX has a different offset on SI */
1415         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1416 }
1417
1418 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1419 {
1420         int i, j;
1421         u32 data;
1422         u32 raster_config = 0;
1423         u32 active_rbs = 0;
1424         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1425                                         adev->gfx.config.max_sh_per_se;
1426         unsigned num_rb_pipes;
1427
1428         mutex_lock(&adev->grbm_idx_mutex);
1429         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1430                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1431                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1432                         data = gfx_v6_0_get_rb_active_bitmap(adev);
1433                         active_rbs |= data <<
1434                                 ((i * adev->gfx.config.max_sh_per_se + j) *
1435                                  rb_bitmap_width_per_sh);
1436                 }
1437         }
1438         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1439
1440         adev->gfx.config.backend_enable_mask = active_rbs;
1441         adev->gfx.config.num_rbs = hweight32(active_rbs);
1442
1443         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1444                              adev->gfx.config.max_shader_engines, 16);
1445
1446         gfx_v6_0_raster_config(adev, &raster_config);
1447
1448         if (!adev->gfx.config.backend_enable_mask ||
1449              adev->gfx.config.num_rbs >= num_rb_pipes)
1450                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1451         else
1452                 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1453                                                         adev->gfx.config.backend_enable_mask,
1454                                                         num_rb_pipes);
1455
1456         /* cache the values for userspace */
1457         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1458                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1459                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1460                         adev->gfx.config.rb_config[i][j].rb_backend_disable =
1461                                 RREG32(mmCC_RB_BACKEND_DISABLE);
1462                         adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1463                                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1464                         adev->gfx.config.rb_config[i][j].raster_config =
1465                                 RREG32(mmPA_SC_RASTER_CONFIG);
1466                 }
1467         }
1468         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1469         mutex_unlock(&adev->grbm_idx_mutex);
1470 }
1471
1472 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1473                                                  u32 bitmap)
1474 {
1475         u32 data;
1476
1477         if (!bitmap)
1478                 return;
1479
1480         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1481         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1482
1483         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1484 }
1485
1486 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1487 {
1488         u32 data, mask;
1489
1490         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1491                 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1492
1493         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1494         return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1495 }
1496
1497
1498 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1499 {
1500         int i, j, k;
1501         u32 data, mask;
1502         u32 active_cu = 0;
1503
1504         mutex_lock(&adev->grbm_idx_mutex);
1505         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1506                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1507                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1508                         data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1509                         active_cu = gfx_v6_0_get_cu_enabled(adev);
1510
1511                         mask = 1;
1512                         for (k = 0; k < 16; k++) {
1513                                 mask <<= k;
1514                                 if (active_cu & mask) {
1515                                         data &= ~mask;
1516                                         WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1517                                         break;
1518                                 }
1519                         }
1520                 }
1521         }
1522         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1523         mutex_unlock(&adev->grbm_idx_mutex);
1524 }
1525
1526 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1527 {
1528         adev->gfx.config.double_offchip_lds_buf = 0;
1529 }
1530
1531 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1532 {
1533         u32 gb_addr_config = 0;
1534         u32 mc_shared_chmap, mc_arb_ramcfg;
1535         u32 sx_debug_1;
1536         u32 hdp_host_path_cntl;
1537         u32 tmp;
1538
1539         switch (adev->asic_type) {
1540         case CHIP_TAHITI:
1541                 adev->gfx.config.max_shader_engines = 2;
1542                 adev->gfx.config.max_tile_pipes = 12;
1543                 adev->gfx.config.max_cu_per_sh = 8;
1544                 adev->gfx.config.max_sh_per_se = 2;
1545                 adev->gfx.config.max_backends_per_se = 4;
1546                 adev->gfx.config.max_texture_channel_caches = 12;
1547                 adev->gfx.config.max_gprs = 256;
1548                 adev->gfx.config.max_gs_threads = 32;
1549                 adev->gfx.config.max_hw_contexts = 8;
1550
1551                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1552                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1553                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1554                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1555                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1556                 break;
1557         case CHIP_PITCAIRN:
1558                 adev->gfx.config.max_shader_engines = 2;
1559                 adev->gfx.config.max_tile_pipes = 8;
1560                 adev->gfx.config.max_cu_per_sh = 5;
1561                 adev->gfx.config.max_sh_per_se = 2;
1562                 adev->gfx.config.max_backends_per_se = 4;
1563                 adev->gfx.config.max_texture_channel_caches = 8;
1564                 adev->gfx.config.max_gprs = 256;
1565                 adev->gfx.config.max_gs_threads = 32;
1566                 adev->gfx.config.max_hw_contexts = 8;
1567
1568                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1569                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1570                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1571                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1572                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1573                 break;
1574         case CHIP_VERDE:
1575                 adev->gfx.config.max_shader_engines = 1;
1576                 adev->gfx.config.max_tile_pipes = 4;
1577                 adev->gfx.config.max_cu_per_sh = 5;
1578                 adev->gfx.config.max_sh_per_se = 2;
1579                 adev->gfx.config.max_backends_per_se = 4;
1580                 adev->gfx.config.max_texture_channel_caches = 4;
1581                 adev->gfx.config.max_gprs = 256;
1582                 adev->gfx.config.max_gs_threads = 32;
1583                 adev->gfx.config.max_hw_contexts = 8;
1584
1585                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1586                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1587                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1588                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1589                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1590                 break;
1591         case CHIP_OLAND:
1592                 adev->gfx.config.max_shader_engines = 1;
1593                 adev->gfx.config.max_tile_pipes = 4;
1594                 adev->gfx.config.max_cu_per_sh = 6;
1595                 adev->gfx.config.max_sh_per_se = 1;
1596                 adev->gfx.config.max_backends_per_se = 2;
1597                 adev->gfx.config.max_texture_channel_caches = 4;
1598                 adev->gfx.config.max_gprs = 256;
1599                 adev->gfx.config.max_gs_threads = 16;
1600                 adev->gfx.config.max_hw_contexts = 8;
1601
1602                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1603                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1604                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1605                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1606                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1607                 break;
1608         case CHIP_HAINAN:
1609                 adev->gfx.config.max_shader_engines = 1;
1610                 adev->gfx.config.max_tile_pipes = 4;
1611                 adev->gfx.config.max_cu_per_sh = 5;
1612                 adev->gfx.config.max_sh_per_se = 1;
1613                 adev->gfx.config.max_backends_per_se = 1;
1614                 adev->gfx.config.max_texture_channel_caches = 2;
1615                 adev->gfx.config.max_gprs = 256;
1616                 adev->gfx.config.max_gs_threads = 16;
1617                 adev->gfx.config.max_hw_contexts = 8;
1618
1619                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1620                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1621                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1622                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1623                 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1624                 break;
1625         default:
1626                 BUG();
1627                 break;
1628         }
1629
1630         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1631         WREG32(mmSRBM_INT_CNTL, 1);
1632         WREG32(mmSRBM_INT_ACK, 1);
1633
1634         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1635
1636         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1637         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1638         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1639
1640         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1641         adev->gfx.config.mem_max_burst_length_bytes = 256;
1642         tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1643         adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1644         if (adev->gfx.config.mem_row_size_in_kb > 4)
1645                 adev->gfx.config.mem_row_size_in_kb = 4;
1646         adev->gfx.config.shader_engine_tile_size = 32;
1647         adev->gfx.config.num_gpus = 1;
1648         adev->gfx.config.multi_gpu_tile_size = 64;
1649
1650         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1651         switch (adev->gfx.config.mem_row_size_in_kb) {
1652         case 1:
1653         default:
1654                 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1655                 break;
1656         case 2:
1657                 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1658                 break;
1659         case 4:
1660                 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1661                 break;
1662         }
1663         gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1664         if (adev->gfx.config.max_shader_engines == 2)
1665                 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1666         adev->gfx.config.gb_addr_config = gb_addr_config;
1667
1668         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1669         WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1670         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1671         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1672         WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1673         WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1674
1675 #if 0
1676         if (adev->has_uvd) {
1677                 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1678                 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1679                 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1680         }
1681 #endif
1682         gfx_v6_0_tiling_mode_table_init(adev);
1683
1684         gfx_v6_0_setup_rb(adev);
1685
1686         gfx_v6_0_setup_spi(adev);
1687
1688         gfx_v6_0_get_cu_info(adev);
1689         gfx_v6_0_config_init(adev);
1690
1691         WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1692                                        (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1693         WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1694                                     (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1695
1696         sx_debug_1 = RREG32(mmSX_DEBUG_1);
1697         WREG32(mmSX_DEBUG_1, sx_debug_1);
1698
1699         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1700
1701         WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1702                                    (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1703                                    (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1704                                    (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1705
1706         WREG32(mmVGT_NUM_INSTANCES, 1);
1707         WREG32(mmCP_PERFMON_CNTL, 0);
1708         WREG32(mmSQ_CONFIG, 0);
1709         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1710                                           (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1711
1712         WREG32(mmVGT_CACHE_INVALIDATION,
1713                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1714                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1715
1716         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1717         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1718
1719         WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1720         WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1721         WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1722         WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1723         WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1724         WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1725         WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1726         WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1727
1728         hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1729         WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1730
1731         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1732                                 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1733
1734         udelay(50);
1735 }
1736
1737
1738 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1739 {
1740         adev->gfx.scratch.num_reg = 8;
1741         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1742         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1743 }
1744
1745 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1746 {
1747         struct amdgpu_device *adev = ring->adev;
1748         uint32_t scratch;
1749         uint32_t tmp = 0;
1750         unsigned i;
1751         int r;
1752
1753         r = amdgpu_gfx_scratch_get(adev, &scratch);
1754         if (r) {
1755                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1756                 return r;
1757         }
1758         WREG32(scratch, 0xCAFEDEAD);
1759
1760         r = amdgpu_ring_alloc(ring, 3);
1761         if (r) {
1762                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1763                 amdgpu_gfx_scratch_free(adev, scratch);
1764                 return r;
1765         }
1766         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1767         amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1768         amdgpu_ring_write(ring, 0xDEADBEEF);
1769         amdgpu_ring_commit(ring);
1770
1771         for (i = 0; i < adev->usec_timeout; i++) {
1772                 tmp = RREG32(scratch);
1773                 if (tmp == 0xDEADBEEF)
1774                         break;
1775                 DRM_UDELAY(1);
1776         }
1777         if (i < adev->usec_timeout) {
1778                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1779         } else {
1780                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1781                           ring->idx, scratch, tmp);
1782                 r = -EINVAL;
1783         }
1784         amdgpu_gfx_scratch_free(adev, scratch);
1785         return r;
1786 }
1787
1788 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1789 {
1790         /* flush hdp cache */
1791         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1792         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1793                                  WRITE_DATA_DST_SEL(0)));
1794         amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1795         amdgpu_ring_write(ring, 0);
1796         amdgpu_ring_write(ring, 0x1);
1797 }
1798
1799 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1800 {
1801         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1802         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1803                 EVENT_INDEX(0));
1804 }
1805
1806 /**
1807  * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1808  *
1809  * @adev: amdgpu_device pointer
1810  * @ridx: amdgpu ring index
1811  *
1812  * Emits an hdp invalidate on the cp.
1813  */
1814 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1815 {
1816         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1817         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1818                                  WRITE_DATA_DST_SEL(0)));
1819         amdgpu_ring_write(ring, mmHDP_DEBUG0);
1820         amdgpu_ring_write(ring, 0);
1821         amdgpu_ring_write(ring, 0x1);
1822 }
1823
1824 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1825                                      u64 seq, unsigned flags)
1826 {
1827         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1828         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1829         /* flush read cache over gart */
1830         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1831         amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1832         amdgpu_ring_write(ring, 0);
1833         amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1834         amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1835                           PACKET3_TC_ACTION_ENA |
1836                           PACKET3_SH_KCACHE_ACTION_ENA |
1837                           PACKET3_SH_ICACHE_ACTION_ENA);
1838         amdgpu_ring_write(ring, 0xFFFFFFFF);
1839         amdgpu_ring_write(ring, 0);
1840         amdgpu_ring_write(ring, 10); /* poll interval */
1841         /* EVENT_WRITE_EOP - flush caches, send int */
1842         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1843         amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1844         amdgpu_ring_write(ring, addr & 0xfffffffc);
1845         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1846                                 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1847                                 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1848         amdgpu_ring_write(ring, lower_32_bits(seq));
1849         amdgpu_ring_write(ring, upper_32_bits(seq));
1850 }
1851
1852 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1853                                   struct amdgpu_ib *ib,
1854                                   unsigned vm_id, bool ctx_switch)
1855 {
1856         u32 header, control = 0;
1857
1858         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1859         if (ctx_switch) {
1860                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1861                 amdgpu_ring_write(ring, 0);
1862         }
1863
1864         if (ib->flags & AMDGPU_IB_FLAG_CE)
1865                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1866         else
1867                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1868
1869         control |= ib->length_dw | (vm_id << 24);
1870
1871         amdgpu_ring_write(ring, header);
1872         amdgpu_ring_write(ring,
1873 #ifdef __BIG_ENDIAN
1874                           (2 << 0) |
1875 #endif
1876                           (ib->gpu_addr & 0xFFFFFFFC));
1877         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1878         amdgpu_ring_write(ring, control);
1879 }
1880
1881 /**
1882  * gfx_v6_0_ring_test_ib - basic ring IB test
1883  *
1884  * @ring: amdgpu_ring structure holding ring information
1885  *
1886  * Allocate an IB and execute it on the gfx ring (SI).
1887  * Provides a basic gfx ring test to verify that IBs are working.
1888  * Returns 0 on success, error on failure.
1889  */
1890 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1891 {
1892         struct amdgpu_device *adev = ring->adev;
1893         struct amdgpu_ib ib;
1894         struct dma_fence *f = NULL;
1895         uint32_t scratch;
1896         uint32_t tmp = 0;
1897         long r;
1898
1899         r = amdgpu_gfx_scratch_get(adev, &scratch);
1900         if (r) {
1901                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1902                 return r;
1903         }
1904         WREG32(scratch, 0xCAFEDEAD);
1905         memset(&ib, 0, sizeof(ib));
1906         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1907         if (r) {
1908                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1909                 goto err1;
1910         }
1911         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1912         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1913         ib.ptr[2] = 0xDEADBEEF;
1914         ib.length_dw = 3;
1915
1916         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1917         if (r)
1918                 goto err2;
1919
1920         r = dma_fence_wait_timeout(f, false, timeout);
1921         if (r == 0) {
1922                 DRM_ERROR("amdgpu: IB test timed out\n");
1923                 r = -ETIMEDOUT;
1924                 goto err2;
1925         } else if (r < 0) {
1926                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1927                 goto err2;
1928         }
1929         tmp = RREG32(scratch);
1930         if (tmp == 0xDEADBEEF) {
1931                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1932                 r = 0;
1933         } else {
1934                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1935                           scratch, tmp);
1936                 r = -EINVAL;
1937         }
1938
1939 err2:
1940         amdgpu_ib_free(adev, &ib, NULL);
1941         dma_fence_put(f);
1942 err1:
1943         amdgpu_gfx_scratch_free(adev, scratch);
1944         return r;
1945 }
1946
1947 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1948 {
1949         int i;
1950         if (enable) {
1951                 WREG32(mmCP_ME_CNTL, 0);
1952         } else {
1953                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1954                                       CP_ME_CNTL__PFP_HALT_MASK |
1955                                       CP_ME_CNTL__CE_HALT_MASK));
1956                 WREG32(mmSCRATCH_UMSK, 0);
1957                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1958                         adev->gfx.gfx_ring[i].ready = false;
1959                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1960                         adev->gfx.compute_ring[i].ready = false;
1961         }
1962         udelay(50);
1963 }
1964
1965 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1966 {
1967         unsigned i;
1968         const struct gfx_firmware_header_v1_0 *pfp_hdr;
1969         const struct gfx_firmware_header_v1_0 *ce_hdr;
1970         const struct gfx_firmware_header_v1_0 *me_hdr;
1971         const __le32 *fw_data;
1972         u32 fw_size;
1973
1974         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1975                 return -EINVAL;
1976
1977         gfx_v6_0_cp_gfx_enable(adev, false);
1978         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1979         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1980         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1981
1982         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1983         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1984         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1985
1986         /* PFP */
1987         fw_data = (const __le32 *)
1988                 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1989         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1990         WREG32(mmCP_PFP_UCODE_ADDR, 0);
1991         for (i = 0; i < fw_size; i++)
1992                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1993         WREG32(mmCP_PFP_UCODE_ADDR, 0);
1994
1995         /* CE */
1996         fw_data = (const __le32 *)
1997                 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1998         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1999         WREG32(mmCP_CE_UCODE_ADDR, 0);
2000         for (i = 0; i < fw_size; i++)
2001                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2002         WREG32(mmCP_CE_UCODE_ADDR, 0);
2003
2004         /* ME */
2005         fw_data = (const __be32 *)
2006                 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2007         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2008         WREG32(mmCP_ME_RAM_WADDR, 0);
2009         for (i = 0; i < fw_size; i++)
2010                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2011         WREG32(mmCP_ME_RAM_WADDR, 0);
2012
2013         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2014         WREG32(mmCP_CE_UCODE_ADDR, 0);
2015         WREG32(mmCP_ME_RAM_WADDR, 0);
2016         WREG32(mmCP_ME_RAM_RADDR, 0);
2017         return 0;
2018 }
2019
2020 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2021 {
2022         const struct cs_section_def *sect = NULL;
2023         const struct cs_extent_def *ext = NULL;
2024         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2025         int r, i;
2026
2027         r = amdgpu_ring_alloc(ring, 7 + 4);
2028         if (r) {
2029                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2030                 return r;
2031         }
2032         amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2033         amdgpu_ring_write(ring, 0x1);
2034         amdgpu_ring_write(ring, 0x0);
2035         amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2036         amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2037         amdgpu_ring_write(ring, 0);
2038         amdgpu_ring_write(ring, 0);
2039
2040         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2041         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2042         amdgpu_ring_write(ring, 0xc000);
2043         amdgpu_ring_write(ring, 0xe000);
2044         amdgpu_ring_commit(ring);
2045
2046         gfx_v6_0_cp_gfx_enable(adev, true);
2047
2048         r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2049         if (r) {
2050                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2051                 return r;
2052         }
2053
2054         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2055         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2056
2057         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2058                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2059                         if (sect->id == SECT_CONTEXT) {
2060                                 amdgpu_ring_write(ring,
2061                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2062                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2063                                 for (i = 0; i < ext->reg_count; i++)
2064                                         amdgpu_ring_write(ring, ext->extent[i]);
2065                         }
2066                 }
2067         }
2068
2069         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2070         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2071
2072         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2073         amdgpu_ring_write(ring, 0);
2074
2075         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2076         amdgpu_ring_write(ring, 0x00000316);
2077         amdgpu_ring_write(ring, 0x0000000e);
2078         amdgpu_ring_write(ring, 0x00000010);
2079
2080         amdgpu_ring_commit(ring);
2081
2082         return 0;
2083 }
2084
2085 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2086 {
2087         struct amdgpu_ring *ring;
2088         u32 tmp;
2089         u32 rb_bufsz;
2090         int r;
2091         u64 rptr_addr;
2092
2093         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2094         WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2095
2096         /* Set the write pointer delay */
2097         WREG32(mmCP_RB_WPTR_DELAY, 0);
2098
2099         WREG32(mmCP_DEBUG, 0);
2100         WREG32(mmSCRATCH_ADDR, 0);
2101
2102         /* ring 0 - compute and gfx */
2103         /* Set ring buffer size */
2104         ring = &adev->gfx.gfx_ring[0];
2105         rb_bufsz = order_base_2(ring->ring_size / 8);
2106         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2107
2108 #ifdef __BIG_ENDIAN
2109         tmp |= BUF_SWAP_32BIT;
2110 #endif
2111         WREG32(mmCP_RB0_CNTL, tmp);
2112
2113         /* Initialize the ring buffer's read and write pointers */
2114         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2115         ring->wptr = 0;
2116         WREG32(mmCP_RB0_WPTR, ring->wptr);
2117
2118         /* set the wb address whether it's enabled or not */
2119         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2120         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2121         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2122
2123         WREG32(mmSCRATCH_UMSK, 0);
2124
2125         mdelay(1);
2126         WREG32(mmCP_RB0_CNTL, tmp);
2127
2128         WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2129
2130         /* start the rings */
2131         gfx_v6_0_cp_gfx_start(adev);
2132         ring->ready = true;
2133         r = amdgpu_ring_test_ring(ring);
2134         if (r) {
2135                 ring->ready = false;
2136                 return r;
2137         }
2138
2139         return 0;
2140 }
2141
2142 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2143 {
2144         return ring->adev->wb.wb[ring->rptr_offs];
2145 }
2146
2147 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2148 {
2149         struct amdgpu_device *adev = ring->adev;
2150
2151         if (ring == &adev->gfx.gfx_ring[0])
2152                 return RREG32(mmCP_RB0_WPTR);
2153         else if (ring == &adev->gfx.compute_ring[0])
2154                 return RREG32(mmCP_RB1_WPTR);
2155         else if (ring == &adev->gfx.compute_ring[1])
2156                 return RREG32(mmCP_RB2_WPTR);
2157         else
2158                 BUG();
2159 }
2160
2161 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2162 {
2163         struct amdgpu_device *adev = ring->adev;
2164
2165         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2166         (void)RREG32(mmCP_RB0_WPTR);
2167 }
2168
2169 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2170 {
2171         struct amdgpu_device *adev = ring->adev;
2172
2173         if (ring == &adev->gfx.compute_ring[0]) {
2174                 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2175                 (void)RREG32(mmCP_RB1_WPTR);
2176         } else if (ring == &adev->gfx.compute_ring[1]) {
2177                 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2178                 (void)RREG32(mmCP_RB2_WPTR);
2179         } else {
2180                 BUG();
2181         }
2182
2183 }
2184
2185 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2186 {
2187         struct amdgpu_ring *ring;
2188         u32 tmp;
2189         u32 rb_bufsz;
2190         int i, r;
2191         u64 rptr_addr;
2192
2193         /* ring1  - compute only */
2194         /* Set ring buffer size */
2195
2196         ring = &adev->gfx.compute_ring[0];
2197         rb_bufsz = order_base_2(ring->ring_size / 8);
2198         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2199 #ifdef __BIG_ENDIAN
2200         tmp |= BUF_SWAP_32BIT;
2201 #endif
2202         WREG32(mmCP_RB1_CNTL, tmp);
2203
2204         WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2205         ring->wptr = 0;
2206         WREG32(mmCP_RB1_WPTR, ring->wptr);
2207
2208         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2209         WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2210         WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2211
2212         mdelay(1);
2213         WREG32(mmCP_RB1_CNTL, tmp);
2214         WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2215
2216         ring = &adev->gfx.compute_ring[1];
2217         rb_bufsz = order_base_2(ring->ring_size / 8);
2218         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2219 #ifdef __BIG_ENDIAN
2220         tmp |= BUF_SWAP_32BIT;
2221 #endif
2222         WREG32(mmCP_RB2_CNTL, tmp);
2223
2224         WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2225         ring->wptr = 0;
2226         WREG32(mmCP_RB2_WPTR, ring->wptr);
2227         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2228         WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2229         WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2230
2231         mdelay(1);
2232         WREG32(mmCP_RB2_CNTL, tmp);
2233         WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2234
2235         adev->gfx.compute_ring[0].ready = false;
2236         adev->gfx.compute_ring[1].ready = false;
2237
2238         for (i = 0; i < 2; i++) {
2239                 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2240                 if (r)
2241                         return r;
2242                 adev->gfx.compute_ring[i].ready = true;
2243         }
2244
2245         return 0;
2246 }
2247
2248 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2249 {
2250         gfx_v6_0_cp_gfx_enable(adev, enable);
2251 }
2252
2253 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2254 {
2255         return gfx_v6_0_cp_gfx_load_microcode(adev);
2256 }
2257
2258 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2259                                                bool enable)
2260 {
2261         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2262         u32 mask;
2263         int i;
2264
2265         if (enable)
2266                 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2267                         CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2268         else
2269                 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2270                          CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2271         WREG32(mmCP_INT_CNTL_RING0, tmp);
2272
2273         if (!enable) {
2274                 /* read a gfx register */
2275                 tmp = RREG32(mmDB_DEPTH_INFO);
2276
2277                 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2278                 for (i = 0; i < adev->usec_timeout; i++) {
2279                         if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2280                                 break;
2281                         udelay(1);
2282                 }
2283         }
2284 }
2285
2286 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2287 {
2288         int r;
2289
2290         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2291
2292         r = gfx_v6_0_cp_load_microcode(adev);
2293         if (r)
2294                 return r;
2295
2296         r = gfx_v6_0_cp_gfx_resume(adev);
2297         if (r)
2298                 return r;
2299         r = gfx_v6_0_cp_compute_resume(adev);
2300         if (r)
2301                 return r;
2302
2303         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2304
2305         return 0;
2306 }
2307
2308 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2309 {
2310         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2311         uint32_t seq = ring->fence_drv.sync_seq;
2312         uint64_t addr = ring->fence_drv.gpu_addr;
2313
2314         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2315         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2316                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
2317                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2318         amdgpu_ring_write(ring, addr & 0xfffffffc);
2319         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2320         amdgpu_ring_write(ring, seq);
2321         amdgpu_ring_write(ring, 0xffffffff);
2322         amdgpu_ring_write(ring, 4); /* poll interval */
2323
2324         if (usepfp) {
2325                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2326                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2327                 amdgpu_ring_write(ring, 0);
2328                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2329                 amdgpu_ring_write(ring, 0);
2330         }
2331 }
2332
2333 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2334                                         unsigned vm_id, uint64_t pd_addr)
2335 {
2336         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2337
2338         /* write new base address */
2339         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2340         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2341                                  WRITE_DATA_DST_SEL(0)));
2342         if (vm_id < 8) {
2343                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
2344         } else {
2345                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
2346         }
2347         amdgpu_ring_write(ring, 0);
2348         amdgpu_ring_write(ring, pd_addr >> 12);
2349
2350         /* bits 0-15 are the VM contexts0-15 */
2351         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2352         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2353                                  WRITE_DATA_DST_SEL(0)));
2354         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2355         amdgpu_ring_write(ring, 0);
2356         amdgpu_ring_write(ring, 1 << vm_id);
2357
2358         /* wait for the invalidate to complete */
2359         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2360         amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |  /* always */
2361                                  WAIT_REG_MEM_ENGINE(0))); /* me */
2362         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2363         amdgpu_ring_write(ring, 0);
2364         amdgpu_ring_write(ring, 0); /* ref */
2365         amdgpu_ring_write(ring, 0); /* mask */
2366         amdgpu_ring_write(ring, 0x20); /* poll interval */
2367
2368         if (usepfp) {
2369                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2370                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2371                 amdgpu_ring_write(ring, 0x0);
2372
2373                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2374                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2375                 amdgpu_ring_write(ring, 0);
2376                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2377                 amdgpu_ring_write(ring, 0);
2378         }
2379 }
2380
2381
2382 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2383 {
2384         amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2385         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2386         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2387 }
2388
2389 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2390 {
2391         const u32 *src_ptr;
2392         volatile u32 *dst_ptr;
2393         u32 dws, i;
2394         u64 reg_list_mc_addr;
2395         const struct cs_section_def *cs_data;
2396         int r;
2397
2398         adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2399         adev->gfx.rlc.reg_list_size =
2400                         (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2401
2402         adev->gfx.rlc.cs_data = si_cs_data;
2403         src_ptr = adev->gfx.rlc.reg_list;
2404         dws = adev->gfx.rlc.reg_list_size;
2405         cs_data = adev->gfx.rlc.cs_data;
2406
2407         if (src_ptr) {
2408                 /* save restore block */
2409                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2410                                               AMDGPU_GEM_DOMAIN_VRAM,
2411                                               &adev->gfx.rlc.save_restore_obj,
2412                                               &adev->gfx.rlc.save_restore_gpu_addr,
2413                                               (void **)&adev->gfx.rlc.sr_ptr);
2414                 if (r) {
2415                         dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2416                                  r);
2417                         gfx_v6_0_rlc_fini(adev);
2418                         return r;
2419                 }
2420
2421                 /* write the sr buffer */
2422                 dst_ptr = adev->gfx.rlc.sr_ptr;
2423                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2424                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2425
2426                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2427                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2428         }
2429
2430         if (cs_data) {
2431                 /* clear state block */
2432                 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2433                 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2434
2435                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2436                                               AMDGPU_GEM_DOMAIN_VRAM,
2437                                               &adev->gfx.rlc.clear_state_obj,
2438                                               &adev->gfx.rlc.clear_state_gpu_addr,
2439                                               (void **)&adev->gfx.rlc.cs_ptr);
2440                 if (r) {
2441                         dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2442                         gfx_v6_0_rlc_fini(adev);
2443                         return r;
2444                 }
2445
2446                 /* set up the cs buffer */
2447                 dst_ptr = adev->gfx.rlc.cs_ptr;
2448                 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2449                 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2450                 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2451                 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2452                 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2453                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2454                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2455         }
2456
2457         return 0;
2458 }
2459
2460 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2461 {
2462         WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2463
2464         if (!enable) {
2465                 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2466                 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2467         }
2468 }
2469
2470 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2471 {
2472         int i;
2473
2474         for (i = 0; i < adev->usec_timeout; i++) {
2475                 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2476                         break;
2477                 udelay(1);
2478         }
2479
2480         for (i = 0; i < adev->usec_timeout; i++) {
2481                 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2482                         break;
2483                 udelay(1);
2484         }
2485 }
2486
2487 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2488 {
2489         u32 tmp;
2490
2491         tmp = RREG32(mmRLC_CNTL);
2492         if (tmp != rlc)
2493                 WREG32(mmRLC_CNTL, rlc);
2494 }
2495
2496 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2497 {
2498         u32 data, orig;
2499
2500         orig = data = RREG32(mmRLC_CNTL);
2501
2502         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2503                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2504                 WREG32(mmRLC_CNTL, data);
2505
2506                 gfx_v6_0_wait_for_rlc_serdes(adev);
2507         }
2508
2509         return orig;
2510 }
2511
2512 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2513 {
2514         WREG32(mmRLC_CNTL, 0);
2515
2516         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2517         gfx_v6_0_wait_for_rlc_serdes(adev);
2518 }
2519
2520 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2521 {
2522         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2523
2524         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2525
2526         udelay(50);
2527 }
2528
2529 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2530 {
2531         WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2532         udelay(50);
2533         WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2534         udelay(50);
2535 }
2536
2537 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2538 {
2539         u32 tmp;
2540
2541         /* Enable LBPW only for DDR3 */
2542         tmp = RREG32(mmMC_SEQ_MISC0);
2543         if ((tmp & 0xF0000000) == 0xB0000000)
2544                 return true;
2545         return false;
2546 }
2547
2548 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2549 {
2550 }
2551
2552 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2553 {
2554         u32 i;
2555         const struct rlc_firmware_header_v1_0 *hdr;
2556         const __le32 *fw_data;
2557         u32 fw_size;
2558
2559
2560         if (!adev->gfx.rlc_fw)
2561                 return -EINVAL;
2562
2563         gfx_v6_0_rlc_stop(adev);
2564         gfx_v6_0_rlc_reset(adev);
2565         gfx_v6_0_init_pg(adev);
2566         gfx_v6_0_init_cg(adev);
2567
2568         WREG32(mmRLC_RL_BASE, 0);
2569         WREG32(mmRLC_RL_SIZE, 0);
2570         WREG32(mmRLC_LB_CNTL, 0);
2571         WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2572         WREG32(mmRLC_LB_CNTR_INIT, 0);
2573         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2574
2575         WREG32(mmRLC_MC_CNTL, 0);
2576         WREG32(mmRLC_UCODE_CNTL, 0);
2577
2578         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2579         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2580         fw_data = (const __le32 *)
2581                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2582
2583         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2584
2585         for (i = 0; i < fw_size; i++) {
2586                 WREG32(mmRLC_UCODE_ADDR, i);
2587                 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2588         }
2589         WREG32(mmRLC_UCODE_ADDR, 0);
2590
2591         gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2592         gfx_v6_0_rlc_start(adev);
2593
2594         return 0;
2595 }
2596
2597 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2598 {
2599         u32 data, orig, tmp;
2600
2601         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2602
2603         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2604                 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2605
2606                 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2607
2608                 tmp = gfx_v6_0_halt_rlc(adev);
2609
2610                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2611                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2612                 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2613
2614                 gfx_v6_0_wait_for_rlc_serdes(adev);
2615                 gfx_v6_0_update_rlc(adev, tmp);
2616
2617                 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2618
2619                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2620         } else {
2621                 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2622
2623                 RREG32(mmCB_CGTT_SCLK_CTRL);
2624                 RREG32(mmCB_CGTT_SCLK_CTRL);
2625                 RREG32(mmCB_CGTT_SCLK_CTRL);
2626                 RREG32(mmCB_CGTT_SCLK_CTRL);
2627
2628                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2629         }
2630
2631         if (orig != data)
2632                 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2633
2634 }
2635
2636 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2637 {
2638
2639         u32 data, orig, tmp = 0;
2640
2641         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2642                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2643                 data = 0x96940200;
2644                 if (orig != data)
2645                         WREG32(mmCGTS_SM_CTRL_REG, data);
2646
2647                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2648                         orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2649                         data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2650                         if (orig != data)
2651                                 WREG32(mmCP_MEM_SLP_CNTL, data);
2652                 }
2653
2654                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2655                 data &= 0xffffffc0;
2656                 if (orig != data)
2657                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2658
2659                 tmp = gfx_v6_0_halt_rlc(adev);
2660
2661                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2662                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2663                 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2664
2665                 gfx_v6_0_update_rlc(adev, tmp);
2666         } else {
2667                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2668                 data |= 0x00000003;
2669                 if (orig != data)
2670                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2671
2672                 data = RREG32(mmCP_MEM_SLP_CNTL);
2673                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2674                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2675                         WREG32(mmCP_MEM_SLP_CNTL, data);
2676                 }
2677                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2678                 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2679                 if (orig != data)
2680                         WREG32(mmCGTS_SM_CTRL_REG, data);
2681
2682                 tmp = gfx_v6_0_halt_rlc(adev);
2683
2684                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2685                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2686                 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2687
2688                 gfx_v6_0_update_rlc(adev, tmp);
2689         }
2690 }
2691 /*
2692 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2693                                bool enable)
2694 {
2695         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2696         if (enable) {
2697                 gfx_v6_0_enable_mgcg(adev, true);
2698                 gfx_v6_0_enable_cgcg(adev, true);
2699         } else {
2700                 gfx_v6_0_enable_cgcg(adev, false);
2701                 gfx_v6_0_enable_mgcg(adev, false);
2702         }
2703         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2704 }
2705 */
2706
2707 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2708                                                 bool enable)
2709 {
2710 }
2711
2712 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2713                                                 bool enable)
2714 {
2715 }
2716
2717 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2718 {
2719         u32 data, orig;
2720
2721         orig = data = RREG32(mmRLC_PG_CNTL);
2722         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2723                 data &= ~0x8000;
2724         else
2725                 data |= 0x8000;
2726         if (orig != data)
2727                 WREG32(mmRLC_PG_CNTL, data);
2728 }
2729
2730 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2731 {
2732 }
2733 /*
2734 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2735 {
2736         const __le32 *fw_data;
2737         volatile u32 *dst_ptr;
2738         int me, i, max_me = 4;
2739         u32 bo_offset = 0;
2740         u32 table_offset, table_size;
2741
2742         if (adev->asic_type == CHIP_KAVERI)
2743                 max_me = 5;
2744
2745         if (adev->gfx.rlc.cp_table_ptr == NULL)
2746                 return;
2747
2748         dst_ptr = adev->gfx.rlc.cp_table_ptr;
2749         for (me = 0; me < max_me; me++) {
2750                 if (me == 0) {
2751                         const struct gfx_firmware_header_v1_0 *hdr =
2752                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2753                         fw_data = (const __le32 *)
2754                                 (adev->gfx.ce_fw->data +
2755                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2756                         table_offset = le32_to_cpu(hdr->jt_offset);
2757                         table_size = le32_to_cpu(hdr->jt_size);
2758                 } else if (me == 1) {
2759                         const struct gfx_firmware_header_v1_0 *hdr =
2760                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2761                         fw_data = (const __le32 *)
2762                                 (adev->gfx.pfp_fw->data +
2763                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2764                         table_offset = le32_to_cpu(hdr->jt_offset);
2765                         table_size = le32_to_cpu(hdr->jt_size);
2766                 } else if (me == 2) {
2767                         const struct gfx_firmware_header_v1_0 *hdr =
2768                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2769                         fw_data = (const __le32 *)
2770                                 (adev->gfx.me_fw->data +
2771                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2772                         table_offset = le32_to_cpu(hdr->jt_offset);
2773                         table_size = le32_to_cpu(hdr->jt_size);
2774                 } else if (me == 3) {
2775                         const struct gfx_firmware_header_v1_0 *hdr =
2776                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2777                         fw_data = (const __le32 *)
2778                                 (adev->gfx.mec_fw->data +
2779                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2780                         table_offset = le32_to_cpu(hdr->jt_offset);
2781                         table_size = le32_to_cpu(hdr->jt_size);
2782                 } else {
2783                         const struct gfx_firmware_header_v1_0 *hdr =
2784                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2785                         fw_data = (const __le32 *)
2786                                 (adev->gfx.mec2_fw->data +
2787                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2788                         table_offset = le32_to_cpu(hdr->jt_offset);
2789                         table_size = le32_to_cpu(hdr->jt_size);
2790                 }
2791
2792                 for (i = 0; i < table_size; i ++) {
2793                         dst_ptr[bo_offset + i] =
2794                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2795                 }
2796
2797                 bo_offset += table_size;
2798         }
2799 }
2800 */
2801 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2802                                      bool enable)
2803 {
2804         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2805                 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2806                 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2807                 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2808         } else {
2809                 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2810                 (void)RREG32(mmDB_RENDER_CONTROL);
2811         }
2812 }
2813
2814 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2815 {
2816         u32 tmp;
2817
2818         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2819
2820         tmp = RREG32(mmRLC_MAX_PG_CU);
2821         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2822         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2823         WREG32(mmRLC_MAX_PG_CU, tmp);
2824 }
2825
2826 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2827                                             bool enable)
2828 {
2829         u32 data, orig;
2830
2831         orig = data = RREG32(mmRLC_PG_CNTL);
2832         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2833                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2834         else
2835                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2836         if (orig != data)
2837                 WREG32(mmRLC_PG_CNTL, data);
2838 }
2839
2840 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2841                                              bool enable)
2842 {
2843         u32 data, orig;
2844
2845         orig = data = RREG32(mmRLC_PG_CNTL);
2846         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2847                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2848         else
2849                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2850         if (orig != data)
2851                 WREG32(mmRLC_PG_CNTL, data);
2852 }
2853
2854 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2855 {
2856         u32 tmp;
2857
2858         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2859         WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2860         WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2861
2862         tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2863         tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2864         tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2865         tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2866         WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2867 }
2868
2869 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2870 {
2871         gfx_v6_0_enable_gfx_cgpg(adev, enable);
2872         gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2873         gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2874 }
2875
2876 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2877 {
2878         u32 count = 0;
2879         const struct cs_section_def *sect = NULL;
2880         const struct cs_extent_def *ext = NULL;
2881
2882         if (adev->gfx.rlc.cs_data == NULL)
2883                 return 0;
2884
2885         /* begin clear state */
2886         count += 2;
2887         /* context control state */
2888         count += 3;
2889
2890         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2891                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2892                         if (sect->id == SECT_CONTEXT)
2893                                 count += 2 + ext->reg_count;
2894                         else
2895                                 return 0;
2896                 }
2897         }
2898         /* pa_sc_raster_config */
2899         count += 3;
2900         /* end clear state */
2901         count += 2;
2902         /* clear state */
2903         count += 2;
2904
2905         return count;
2906 }
2907
2908 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2909                                     volatile u32 *buffer)
2910 {
2911         u32 count = 0, i;
2912         const struct cs_section_def *sect = NULL;
2913         const struct cs_extent_def *ext = NULL;
2914
2915         if (adev->gfx.rlc.cs_data == NULL)
2916                 return;
2917         if (buffer == NULL)
2918                 return;
2919
2920         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2921         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2922         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2923         buffer[count++] = cpu_to_le32(0x80000000);
2924         buffer[count++] = cpu_to_le32(0x80000000);
2925
2926         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2927                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2928                         if (sect->id == SECT_CONTEXT) {
2929                                 buffer[count++] =
2930                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2931                                 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2932                                 for (i = 0; i < ext->reg_count; i++)
2933                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
2934                         } else {
2935                                 return;
2936                         }
2937                 }
2938         }
2939
2940         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2941         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2942
2943         switch (adev->asic_type) {
2944         case CHIP_TAHITI:
2945         case CHIP_PITCAIRN:
2946                 buffer[count++] = cpu_to_le32(0x2a00126a);
2947                 break;
2948         case CHIP_VERDE:
2949                 buffer[count++] = cpu_to_le32(0x0000124a);
2950                 break;
2951         case CHIP_OLAND:
2952                 buffer[count++] = cpu_to_le32(0x00000082);
2953                 break;
2954         case CHIP_HAINAN:
2955                 buffer[count++] = cpu_to_le32(0x00000000);
2956                 break;
2957         default:
2958                 buffer[count++] = cpu_to_le32(0x00000000);
2959                 break;
2960         }
2961
2962         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2963         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2964
2965         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2966         buffer[count++] = cpu_to_le32(0);
2967 }
2968
2969 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2970 {
2971         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2972                               AMD_PG_SUPPORT_GFX_SMG |
2973                               AMD_PG_SUPPORT_GFX_DMG |
2974                               AMD_PG_SUPPORT_CP |
2975                               AMD_PG_SUPPORT_GDS |
2976                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2977                 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2978                 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2979                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2980                         gfx_v6_0_init_gfx_cgpg(adev);
2981                         gfx_v6_0_enable_cp_pg(adev, true);
2982                         gfx_v6_0_enable_gds_pg(adev, true);
2983                 } else {
2984                         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2985                         WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2986
2987                 }
2988                 gfx_v6_0_init_ao_cu_mask(adev);
2989                 gfx_v6_0_update_gfx_pg(adev, true);
2990         } else {
2991
2992                 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2993                 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2994         }
2995 }
2996
2997 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2998 {
2999         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3000                               AMD_PG_SUPPORT_GFX_SMG |
3001                               AMD_PG_SUPPORT_GFX_DMG |
3002                               AMD_PG_SUPPORT_CP |
3003                               AMD_PG_SUPPORT_GDS |
3004                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3005                 gfx_v6_0_update_gfx_pg(adev, false);
3006                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3007                         gfx_v6_0_enable_cp_pg(adev, false);
3008                         gfx_v6_0_enable_gds_pg(adev, false);
3009                 }
3010         }
3011 }
3012
3013 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3014 {
3015         uint64_t clock;
3016
3017         mutex_lock(&adev->gfx.gpu_clock_mutex);
3018         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3019         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3020                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3021         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3022         return clock;
3023 }
3024
3025 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3026 {
3027         if (flags & AMDGPU_HAVE_CTX_SWITCH)
3028                 gfx_v6_0_ring_emit_vgt_flush(ring);
3029         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3030         amdgpu_ring_write(ring, 0x80000000);
3031         amdgpu_ring_write(ring, 0);
3032 }
3033
3034
3035 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3036 {
3037         WREG32(mmSQ_IND_INDEX,
3038                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3039                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3040                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3041                 (SQ_IND_INDEX__FORCE_READ_MASK));
3042         return RREG32(mmSQ_IND_DATA);
3043 }
3044
3045 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3046                            uint32_t wave, uint32_t thread,
3047                            uint32_t regno, uint32_t num, uint32_t *out)
3048 {
3049         WREG32(mmSQ_IND_INDEX,
3050                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3051                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3052                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3053                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3054                 (SQ_IND_INDEX__FORCE_READ_MASK) |
3055                 (SQ_IND_INDEX__AUTO_INCR_MASK));
3056         while (num--)
3057                 *(out++) = RREG32(mmSQ_IND_DATA);
3058 }
3059
3060 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3061 {
3062         /* type 0 wave data */
3063         dst[(*no_fields)++] = 0;
3064         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3065         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3066         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3067         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3068         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3069         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3070         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3071         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3072         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3073         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3074         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3075         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3076         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3077         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3078         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3079         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3080         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3081         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3082 }
3083
3084 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3085                                      uint32_t wave, uint32_t start,
3086                                      uint32_t size, uint32_t *dst)
3087 {
3088         wave_read_regs(
3089                 adev, simd, wave, 0,
3090                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3091 }
3092
3093 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3094         .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3095         .select_se_sh = &gfx_v6_0_select_se_sh,
3096         .read_wave_data = &gfx_v6_0_read_wave_data,
3097         .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3098 };
3099
3100 static int gfx_v6_0_early_init(void *handle)
3101 {
3102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3103
3104         adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3105         adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3106         adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3107         gfx_v6_0_set_ring_funcs(adev);
3108         gfx_v6_0_set_irq_funcs(adev);
3109
3110         return 0;
3111 }
3112
3113 static int gfx_v6_0_sw_init(void *handle)
3114 {
3115         struct amdgpu_ring *ring;
3116         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3117         int i, r;
3118
3119         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3120         if (r)
3121                 return r;
3122
3123         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3124         if (r)
3125                 return r;
3126
3127         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3128         if (r)
3129                 return r;
3130
3131         gfx_v6_0_scratch_init(adev);
3132
3133         r = gfx_v6_0_init_microcode(adev);
3134         if (r) {
3135                 DRM_ERROR("Failed to load gfx firmware!\n");
3136                 return r;
3137         }
3138
3139         r = gfx_v6_0_rlc_init(adev);
3140         if (r) {
3141                 DRM_ERROR("Failed to init rlc BOs!\n");
3142                 return r;
3143         }
3144
3145         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3146                 ring = &adev->gfx.gfx_ring[i];
3147                 ring->ring_obj = NULL;
3148                 sprintf(ring->name, "gfx");
3149                 r = amdgpu_ring_init(adev, ring, 1024,
3150                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3151                 if (r)
3152                         return r;
3153         }
3154
3155         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3156                 unsigned irq_type;
3157
3158                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3159                         DRM_ERROR("Too many (%d) compute rings!\n", i);
3160                         break;
3161                 }
3162                 ring = &adev->gfx.compute_ring[i];
3163                 ring->ring_obj = NULL;
3164                 ring->use_doorbell = false;
3165                 ring->doorbell_index = 0;
3166                 ring->me = 1;
3167                 ring->pipe = i;
3168                 ring->queue = i;
3169                 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3170                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3171                 r = amdgpu_ring_init(adev, ring, 1024,
3172                                      &adev->gfx.eop_irq, irq_type);
3173                 if (r)
3174                         return r;
3175         }
3176
3177         return r;
3178 }
3179
3180 static int gfx_v6_0_sw_fini(void *handle)
3181 {
3182         int i;
3183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3184
3185         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3186                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3187         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3188                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3189
3190         gfx_v6_0_rlc_fini(adev);
3191
3192         return 0;
3193 }
3194
3195 static int gfx_v6_0_hw_init(void *handle)
3196 {
3197         int r;
3198         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3199
3200         gfx_v6_0_gpu_init(adev);
3201
3202         r = gfx_v6_0_rlc_resume(adev);
3203         if (r)
3204                 return r;
3205
3206         r = gfx_v6_0_cp_resume(adev);
3207         if (r)
3208                 return r;
3209
3210         adev->gfx.ce_ram_size = 0x8000;
3211
3212         return r;
3213 }
3214
3215 static int gfx_v6_0_hw_fini(void *handle)
3216 {
3217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3218
3219         gfx_v6_0_cp_enable(adev, false);
3220         gfx_v6_0_rlc_stop(adev);
3221         gfx_v6_0_fini_pg(adev);
3222
3223         return 0;
3224 }
3225
3226 static int gfx_v6_0_suspend(void *handle)
3227 {
3228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3229
3230         return gfx_v6_0_hw_fini(adev);
3231 }
3232
3233 static int gfx_v6_0_resume(void *handle)
3234 {
3235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3236
3237         return gfx_v6_0_hw_init(adev);
3238 }
3239
3240 static bool gfx_v6_0_is_idle(void *handle)
3241 {
3242         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3243
3244         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3245                 return false;
3246         else
3247                 return true;
3248 }
3249
3250 static int gfx_v6_0_wait_for_idle(void *handle)
3251 {
3252         unsigned i;
3253         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3254
3255         for (i = 0; i < adev->usec_timeout; i++) {
3256                 if (gfx_v6_0_is_idle(handle))
3257                         return 0;
3258                 udelay(1);
3259         }
3260         return -ETIMEDOUT;
3261 }
3262
3263 static int gfx_v6_0_soft_reset(void *handle)
3264 {
3265         return 0;
3266 }
3267
3268 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3269                                                  enum amdgpu_interrupt_state state)
3270 {
3271         u32 cp_int_cntl;
3272
3273         switch (state) {
3274         case AMDGPU_IRQ_STATE_DISABLE:
3275                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3276                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3277                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3278                 break;
3279         case AMDGPU_IRQ_STATE_ENABLE:
3280                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3281                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3282                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3283                 break;
3284         default:
3285                 break;
3286         }
3287 }
3288
3289 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3290                                                      int ring,
3291                                                      enum amdgpu_interrupt_state state)
3292 {
3293         u32 cp_int_cntl;
3294         switch (state){
3295         case AMDGPU_IRQ_STATE_DISABLE:
3296                 if (ring == 0) {
3297                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3298                         cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3299                         WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3300                         break;
3301                 } else {
3302                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3303                         cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3304                         WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3305                         break;
3306
3307                 }
3308         case AMDGPU_IRQ_STATE_ENABLE:
3309                 if (ring == 0) {
3310                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3311                         cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3312                         WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3313                         break;
3314                 } else {
3315                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3316                         cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3317                         WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3318                         break;
3319
3320                 }
3321
3322         default:
3323                 BUG();
3324                 break;
3325
3326         }
3327 }
3328
3329 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3330                                              struct amdgpu_irq_src *src,
3331                                              unsigned type,
3332                                              enum amdgpu_interrupt_state state)
3333 {
3334         u32 cp_int_cntl;
3335
3336         switch (state) {
3337         case AMDGPU_IRQ_STATE_DISABLE:
3338                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3339                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3340                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3341                 break;
3342         case AMDGPU_IRQ_STATE_ENABLE:
3343                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3344                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3345                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3346                 break;
3347         default:
3348                 break;
3349         }
3350
3351         return 0;
3352 }
3353
3354 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3355                                               struct amdgpu_irq_src *src,
3356                                               unsigned type,
3357                                               enum amdgpu_interrupt_state state)
3358 {
3359         u32 cp_int_cntl;
3360
3361         switch (state) {
3362         case AMDGPU_IRQ_STATE_DISABLE:
3363                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3364                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3365                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3366                 break;
3367         case AMDGPU_IRQ_STATE_ENABLE:
3368                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3369                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3370                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3371                 break;
3372         default:
3373                 break;
3374         }
3375
3376         return 0;
3377 }
3378
3379 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3380                                             struct amdgpu_irq_src *src,
3381                                             unsigned type,
3382                                             enum amdgpu_interrupt_state state)
3383 {
3384         switch (type) {
3385         case AMDGPU_CP_IRQ_GFX_EOP:
3386                 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3387                 break;
3388         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3389                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3390                 break;
3391         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3392                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3393                 break;
3394         default:
3395                 break;
3396         }
3397         return 0;
3398 }
3399
3400 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3401                             struct amdgpu_irq_src *source,
3402                             struct amdgpu_iv_entry *entry)
3403 {
3404         switch (entry->ring_id) {
3405         case 0:
3406                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3407                 break;
3408         case 1:
3409         case 2:
3410                 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3411                 break;
3412         default:
3413                 break;
3414         }
3415         return 0;
3416 }
3417
3418 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3419                                  struct amdgpu_irq_src *source,
3420                                  struct amdgpu_iv_entry *entry)
3421 {
3422         DRM_ERROR("Illegal register access in command stream\n");
3423         schedule_work(&adev->reset_work);
3424         return 0;
3425 }
3426
3427 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3428                                   struct amdgpu_irq_src *source,
3429                                   struct amdgpu_iv_entry *entry)
3430 {
3431         DRM_ERROR("Illegal instruction in command stream\n");
3432         schedule_work(&adev->reset_work);
3433         return 0;
3434 }
3435
3436 static int gfx_v6_0_set_clockgating_state(void *handle,
3437                                           enum amd_clockgating_state state)
3438 {
3439         bool gate = false;
3440         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3441
3442         if (state == AMD_CG_STATE_GATE)
3443                 gate = true;
3444
3445         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3446         if (gate) {
3447                 gfx_v6_0_enable_mgcg(adev, true);
3448                 gfx_v6_0_enable_cgcg(adev, true);
3449         } else {
3450                 gfx_v6_0_enable_cgcg(adev, false);
3451                 gfx_v6_0_enable_mgcg(adev, false);
3452         }
3453         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3454
3455         return 0;
3456 }
3457
3458 static int gfx_v6_0_set_powergating_state(void *handle,
3459                                           enum amd_powergating_state state)
3460 {
3461         bool gate = false;
3462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3463
3464         if (state == AMD_PG_STATE_GATE)
3465                 gate = true;
3466
3467         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3468                               AMD_PG_SUPPORT_GFX_SMG |
3469                               AMD_PG_SUPPORT_GFX_DMG |
3470                               AMD_PG_SUPPORT_CP |
3471                               AMD_PG_SUPPORT_GDS |
3472                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3473                 gfx_v6_0_update_gfx_pg(adev, gate);
3474                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3475                         gfx_v6_0_enable_cp_pg(adev, gate);
3476                         gfx_v6_0_enable_gds_pg(adev, gate);
3477                 }
3478         }
3479
3480         return 0;
3481 }
3482
3483 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3484         .name = "gfx_v6_0",
3485         .early_init = gfx_v6_0_early_init,
3486         .late_init = NULL,
3487         .sw_init = gfx_v6_0_sw_init,
3488         .sw_fini = gfx_v6_0_sw_fini,
3489         .hw_init = gfx_v6_0_hw_init,
3490         .hw_fini = gfx_v6_0_hw_fini,
3491         .suspend = gfx_v6_0_suspend,
3492         .resume = gfx_v6_0_resume,
3493         .is_idle = gfx_v6_0_is_idle,
3494         .wait_for_idle = gfx_v6_0_wait_for_idle,
3495         .soft_reset = gfx_v6_0_soft_reset,
3496         .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3497         .set_powergating_state = gfx_v6_0_set_powergating_state,
3498 };
3499
3500 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3501         .type = AMDGPU_RING_TYPE_GFX,
3502         .align_mask = 0xff,
3503         .nop = 0x80000000,
3504         .support_64bit_ptrs = false,
3505         .get_rptr = gfx_v6_0_ring_get_rptr,
3506         .get_wptr = gfx_v6_0_ring_get_wptr,
3507         .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3508         .emit_frame_size =
3509                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3510                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3511                 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3512                 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3513                 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3514                 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3515         .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3516         .emit_ib = gfx_v6_0_ring_emit_ib,
3517         .emit_fence = gfx_v6_0_ring_emit_fence,
3518         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3519         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3520         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3521         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3522         .test_ring = gfx_v6_0_ring_test_ring,
3523         .test_ib = gfx_v6_0_ring_test_ib,
3524         .insert_nop = amdgpu_ring_insert_nop,
3525         .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3526 };
3527
3528 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3529         .type = AMDGPU_RING_TYPE_COMPUTE,
3530         .align_mask = 0xff,
3531         .nop = 0x80000000,
3532         .get_rptr = gfx_v6_0_ring_get_rptr,
3533         .get_wptr = gfx_v6_0_ring_get_wptr,
3534         .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3535         .emit_frame_size =
3536                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3537                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3538                 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3539                 17 + /* gfx_v6_0_ring_emit_vm_flush */
3540                 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3541         .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3542         .emit_ib = gfx_v6_0_ring_emit_ib,
3543         .emit_fence = gfx_v6_0_ring_emit_fence,
3544         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3545         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3546         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3547         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3548         .test_ring = gfx_v6_0_ring_test_ring,
3549         .test_ib = gfx_v6_0_ring_test_ib,
3550         .insert_nop = amdgpu_ring_insert_nop,
3551 };
3552
3553 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3554 {
3555         int i;
3556
3557         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3558                 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3559         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3560                 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3561 }
3562
3563 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3564         .set = gfx_v6_0_set_eop_interrupt_state,
3565         .process = gfx_v6_0_eop_irq,
3566 };
3567
3568 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3569         .set = gfx_v6_0_set_priv_reg_fault_state,
3570         .process = gfx_v6_0_priv_reg_irq,
3571 };
3572
3573 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3574         .set = gfx_v6_0_set_priv_inst_fault_state,
3575         .process = gfx_v6_0_priv_inst_irq,
3576 };
3577
3578 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3579 {
3580         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3581         adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3582
3583         adev->gfx.priv_reg_irq.num_types = 1;
3584         adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3585
3586         adev->gfx.priv_inst_irq.num_types = 1;
3587         adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3588 }
3589
3590 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3591 {
3592         int i, j, k, counter, active_cu_number = 0;
3593         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3594         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3595         unsigned disable_masks[4 * 2];
3596         u32 ao_cu_num;
3597
3598         if (adev->flags & AMD_IS_APU)
3599                 ao_cu_num = 2;
3600         else
3601                 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3602
3603         memset(cu_info, 0, sizeof(*cu_info));
3604
3605         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3606
3607         mutex_lock(&adev->grbm_idx_mutex);
3608         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3609                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3610                         mask = 1;
3611                         ao_bitmap = 0;
3612                         counter = 0;
3613                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3614                         if (i < 4 && j < 2)
3615                                 gfx_v6_0_set_user_cu_inactive_bitmap(
3616                                         adev, disable_masks[i * 2 + j]);
3617                         bitmap = gfx_v6_0_get_cu_enabled(adev);
3618                         cu_info->bitmap[i][j] = bitmap;
3619
3620                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3621                                 if (bitmap & mask) {
3622                                         if (counter < ao_cu_num)
3623                                                 ao_bitmap |= mask;
3624                                         counter ++;
3625                                 }
3626                                 mask <<= 1;
3627                         }
3628                         active_cu_number += counter;
3629                         if (i < 2 && j < 2)
3630                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3631                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3632                 }
3633         }
3634
3635         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3636         mutex_unlock(&adev->grbm_idx_mutex);
3637
3638         cu_info->number = active_cu_number;
3639         cu_info->ao_cu_mask = ao_cu_mask;
3640 }
3641
3642 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3643 {
3644         .type = AMD_IP_BLOCK_TYPE_GFX,
3645         .major = 6,
3646         .minor = 0,
3647         .rev = 0,
3648         .funcs = &gfx_v6_0_ip_funcs,
3649 };