2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
28 #include "amdgpu_pll.h"
29 #include "amdgpu_connectors.h"
30 #ifdef CONFIG_DRM_AMDGPU_SI
33 #ifdef CONFIG_DRM_AMDGPU_CIK
36 #include "dce_v10_0.h"
37 #include "dce_v11_0.h"
38 #include "dce_virtual.h"
40 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
43 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
45 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
49 * dce_virtual_vblank_wait - vblank wait asic callback.
51 * @adev: amdgpu_device pointer
52 * @crtc: crtc to wait for vblank on
54 * Wait for vblank on the requested crtc (evergreen+).
56 static void dce_virtual_vblank_wait(struct amdgpu_device *adev, int crtc)
61 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
66 static void dce_virtual_page_flip(struct amdgpu_device *adev,
67 int crtc_id, u64 crtc_base, bool async)
72 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
73 u32 *vbl, u32 *position)
81 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
82 enum amdgpu_hpd_id hpd)
87 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
88 enum amdgpu_hpd_id hpd)
93 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
99 * dce_virtual_bandwidth_update - program display watermarks
101 * @adev: amdgpu_device pointer
103 * Calculate and program the display watermarks and line
104 * buffer allocation (CIK).
106 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
111 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
112 u16 *green, u16 *blue, uint32_t size,
113 struct drm_modeset_acquire_ctx *ctx)
118 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
120 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
122 drm_crtc_cleanup(crtc);
126 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
129 .gamma_set = dce_virtual_crtc_gamma_set,
130 .set_config = amdgpu_crtc_set_config,
131 .destroy = dce_virtual_crtc_destroy,
132 .page_flip_target = amdgpu_crtc_page_flip_target,
135 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
137 struct drm_device *dev = crtc->dev;
138 struct amdgpu_device *adev = dev->dev_private;
139 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
142 if (amdgpu_sriov_vf(adev))
146 case DRM_MODE_DPMS_ON:
147 amdgpu_crtc->enabled = true;
148 /* Make sure VBLANK interrupts are still enabled */
149 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
150 amdgpu_irq_update(adev, &adev->crtc_irq, type);
151 drm_crtc_vblank_on(crtc);
153 case DRM_MODE_DPMS_STANDBY:
154 case DRM_MODE_DPMS_SUSPEND:
155 case DRM_MODE_DPMS_OFF:
156 drm_crtc_vblank_off(crtc);
157 amdgpu_crtc->enabled = false;
163 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
165 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
168 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
170 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
173 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
175 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
177 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
178 if (crtc->primary->fb) {
180 struct amdgpu_framebuffer *amdgpu_fb;
181 struct amdgpu_bo *abo;
183 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
184 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
185 r = amdgpu_bo_reserve(abo, true);
187 DRM_ERROR("failed to reserve abo before unpin\n");
189 amdgpu_bo_unpin(abo);
190 amdgpu_bo_unreserve(abo);
194 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
195 amdgpu_crtc->encoder = NULL;
196 amdgpu_crtc->connector = NULL;
199 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
200 struct drm_display_mode *mode,
201 struct drm_display_mode *adjusted_mode,
202 int x, int y, struct drm_framebuffer *old_fb)
204 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
206 /* update the hw version fpr dpm */
207 amdgpu_crtc->hw_mode = *adjusted_mode;
212 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
213 const struct drm_display_mode *mode,
214 struct drm_display_mode *adjusted_mode)
220 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
221 struct drm_framebuffer *old_fb)
226 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
227 struct drm_framebuffer *fb,
228 int x, int y, enum mode_set_atomic state)
233 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
234 .dpms = dce_virtual_crtc_dpms,
235 .mode_fixup = dce_virtual_crtc_mode_fixup,
236 .mode_set = dce_virtual_crtc_mode_set,
237 .mode_set_base = dce_virtual_crtc_set_base,
238 .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
239 .prepare = dce_virtual_crtc_prepare,
240 .commit = dce_virtual_crtc_commit,
241 .disable = dce_virtual_crtc_disable,
244 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
246 struct amdgpu_crtc *amdgpu_crtc;
248 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
249 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
250 if (amdgpu_crtc == NULL)
253 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
255 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
256 amdgpu_crtc->crtc_id = index;
257 adev->mode_info.crtcs[index] = amdgpu_crtc;
259 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
260 amdgpu_crtc->encoder = NULL;
261 amdgpu_crtc->connector = NULL;
262 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
263 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
268 static int dce_virtual_early_init(void *handle)
270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
272 dce_virtual_set_display_funcs(adev);
273 dce_virtual_set_irq_funcs(adev);
275 adev->mode_info.num_hpd = 1;
276 adev->mode_info.num_dig = 1;
280 static struct drm_encoder *
281 dce_virtual_encoder(struct drm_connector *connector)
283 int enc_id = connector->encoder_ids[0];
284 struct drm_encoder *encoder;
287 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
288 if (connector->encoder_ids[i] == 0)
291 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
295 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
299 /* pick the first one */
301 return drm_encoder_find(connector->dev, enc_id);
305 static int dce_virtual_get_modes(struct drm_connector *connector)
307 struct drm_device *dev = connector->dev;
308 struct drm_display_mode *mode = NULL;
310 static const struct mode_size {
313 } common_modes[17] = {
333 for (i = 0; i < 17; i++) {
334 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
335 drm_mode_probed_add(connector, mode);
341 static int dce_virtual_mode_valid(struct drm_connector *connector,
342 struct drm_display_mode *mode)
348 dce_virtual_dpms(struct drm_connector *connector, int mode)
354 dce_virtual_set_property(struct drm_connector *connector,
355 struct drm_property *property,
361 static void dce_virtual_destroy(struct drm_connector *connector)
363 drm_connector_unregister(connector);
364 drm_connector_cleanup(connector);
368 static void dce_virtual_force(struct drm_connector *connector)
373 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
374 .get_modes = dce_virtual_get_modes,
375 .mode_valid = dce_virtual_mode_valid,
376 .best_encoder = dce_virtual_encoder,
379 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
380 .dpms = dce_virtual_dpms,
381 .fill_modes = drm_helper_probe_single_connector_modes,
382 .set_property = dce_virtual_set_property,
383 .destroy = dce_virtual_destroy,
384 .force = dce_virtual_force,
387 static int dce_virtual_sw_init(void *handle)
390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
392 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
396 adev->ddev->max_vblank_count = 0;
398 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
400 adev->ddev->mode_config.max_width = 16384;
401 adev->ddev->mode_config.max_height = 16384;
403 adev->ddev->mode_config.preferred_depth = 24;
404 adev->ddev->mode_config.prefer_shadow = 1;
406 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
408 r = amdgpu_modeset_create_props(adev);
412 adev->ddev->mode_config.max_width = 16384;
413 adev->ddev->mode_config.max_height = 16384;
415 /* allocate crtcs, encoders, connectors */
416 for (i = 0; i < adev->mode_info.num_crtc; i++) {
417 r = dce_virtual_crtc_init(adev, i);
420 r = dce_virtual_connector_encoder_init(adev, i);
425 drm_kms_helper_poll_init(adev->ddev);
427 adev->mode_info.mode_config_initialized = true;
431 static int dce_virtual_sw_fini(void *handle)
433 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
435 kfree(adev->mode_info.bios_hardcoded_edid);
437 drm_kms_helper_poll_fini(adev->ddev);
439 drm_mode_config_cleanup(adev->ddev);
440 /* clear crtcs pointer to avoid dce irq finish routine access freed data */
441 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
442 adev->mode_info.mode_config_initialized = false;
446 static int dce_virtual_hw_init(void *handle)
448 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
450 switch (adev->asic_type) {
451 #ifdef CONFIG_DRM_AMDGPU_SI
456 dce_v6_0_disable_dce(adev);
459 #ifdef CONFIG_DRM_AMDGPU_CIK
465 dce_v8_0_disable_dce(adev);
470 dce_v10_0_disable_dce(adev);
476 dce_v11_0_disable_dce(adev);
479 #ifdef CONFIG_DRM_AMDGPU_SI
487 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
492 static int dce_virtual_hw_fini(void *handle)
497 static int dce_virtual_suspend(void *handle)
499 return dce_virtual_hw_fini(handle);
502 static int dce_virtual_resume(void *handle)
504 return dce_virtual_hw_init(handle);
507 static bool dce_virtual_is_idle(void *handle)
512 static int dce_virtual_wait_for_idle(void *handle)
517 static int dce_virtual_soft_reset(void *handle)
522 static int dce_virtual_set_clockgating_state(void *handle,
523 enum amd_clockgating_state state)
528 static int dce_virtual_set_powergating_state(void *handle,
529 enum amd_powergating_state state)
534 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
535 .name = "dce_virtual",
536 .early_init = dce_virtual_early_init,
538 .sw_init = dce_virtual_sw_init,
539 .sw_fini = dce_virtual_sw_fini,
540 .hw_init = dce_virtual_hw_init,
541 .hw_fini = dce_virtual_hw_fini,
542 .suspend = dce_virtual_suspend,
543 .resume = dce_virtual_resume,
544 .is_idle = dce_virtual_is_idle,
545 .wait_for_idle = dce_virtual_wait_for_idle,
546 .soft_reset = dce_virtual_soft_reset,
547 .set_clockgating_state = dce_virtual_set_clockgating_state,
548 .set_powergating_state = dce_virtual_set_powergating_state,
551 /* these are handled by the primary encoders */
552 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
557 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
563 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
564 struct drm_display_mode *mode,
565 struct drm_display_mode *adjusted_mode)
570 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
576 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
581 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
582 const struct drm_display_mode *mode,
583 struct drm_display_mode *adjusted_mode)
588 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
589 .dpms = dce_virtual_encoder_dpms,
590 .mode_fixup = dce_virtual_encoder_mode_fixup,
591 .prepare = dce_virtual_encoder_prepare,
592 .mode_set = dce_virtual_encoder_mode_set,
593 .commit = dce_virtual_encoder_commit,
594 .disable = dce_virtual_encoder_disable,
597 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
599 drm_encoder_cleanup(encoder);
603 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
604 .destroy = dce_virtual_encoder_destroy,
607 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
610 struct drm_encoder *encoder;
611 struct drm_connector *connector;
613 /* add a new encoder */
614 encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
617 encoder->possible_crtcs = 1 << index;
618 drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
619 DRM_MODE_ENCODER_VIRTUAL, NULL);
620 drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
622 connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
628 /* add a new connector */
629 drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
630 DRM_MODE_CONNECTOR_VIRTUAL);
631 drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
632 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
633 connector->interlace_allowed = false;
634 connector->doublescan_allowed = false;
635 drm_connector_register(connector);
638 drm_mode_connector_attach_encoder(connector, encoder);
643 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
644 .bandwidth_update = &dce_virtual_bandwidth_update,
645 .vblank_get_counter = &dce_virtual_vblank_get_counter,
646 .vblank_wait = &dce_virtual_vblank_wait,
647 .backlight_set_level = NULL,
648 .backlight_get_level = NULL,
649 .hpd_sense = &dce_virtual_hpd_sense,
650 .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
651 .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
652 .page_flip = &dce_virtual_page_flip,
653 .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
655 .add_connector = NULL,
658 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
660 if (adev->mode_info.funcs == NULL)
661 adev->mode_info.funcs = &dce_virtual_display_funcs;
664 static int dce_virtual_pageflip(struct amdgpu_device *adev,
668 struct amdgpu_crtc *amdgpu_crtc;
669 struct amdgpu_flip_work *works;
671 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
673 if (crtc_id >= adev->mode_info.num_crtc) {
674 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
678 /* IRQ could occur when in initial stage */
679 if (amdgpu_crtc == NULL)
682 spin_lock_irqsave(&adev->ddev->event_lock, flags);
683 works = amdgpu_crtc->pflip_works;
684 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
685 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
686 "AMDGPU_FLIP_SUBMITTED(%d)\n",
687 amdgpu_crtc->pflip_status,
688 AMDGPU_FLIP_SUBMITTED);
689 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
693 /* page flip completed. clean up */
694 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
695 amdgpu_crtc->pflip_works = NULL;
697 /* wakeup usersapce */
699 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
701 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
703 drm_crtc_vblank_put(&amdgpu_crtc->base);
704 schedule_work(&works->unpin_work);
709 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
711 struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
712 struct amdgpu_crtc, vblank_timer);
713 struct drm_device *ddev = amdgpu_crtc->base.dev;
714 struct amdgpu_device *adev = ddev->dev_private;
716 drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
717 dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
718 hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
721 return HRTIMER_NORESTART;
724 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
726 enum amdgpu_interrupt_state state)
728 if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
729 DRM_DEBUG("invalid crtc %d\n", crtc);
733 if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
734 DRM_DEBUG("Enable software vsync timer\n");
735 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
736 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
737 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
738 DCE_VIRTUAL_VBLANK_PERIOD);
739 adev->mode_info.crtcs[crtc]->vblank_timer.function =
740 dce_virtual_vblank_timer_handle;
741 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
742 DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
743 } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
744 DRM_DEBUG("Disable software vsync timer\n");
745 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
748 adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
749 DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
753 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
754 struct amdgpu_irq_src *source,
756 enum amdgpu_interrupt_state state)
758 if (type > AMDGPU_CRTC_IRQ_VBLANK6)
761 dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
766 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
767 .set = dce_virtual_set_crtc_irq_state,
771 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
773 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
774 adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
777 const struct amdgpu_ip_block_version dce_virtual_ip_block =
779 .type = AMD_IP_BLOCK_TYPE_DCE,
783 .funcs = &dce_virtual_ip_funcs,