2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
28 #include "amdgpu_atombios.h"
29 #include "atombios_crtc.h"
30 #include "atombios_encoders.h"
31 #include "amdgpu_pll.h"
32 #include "amdgpu_connectors.h"
33 #include "si/si_reg.h"
36 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
37 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
39 static const u32 crtc_offsets[6] =
41 SI_CRTC0_REGISTER_OFFSET,
42 SI_CRTC1_REGISTER_OFFSET,
43 SI_CRTC2_REGISTER_OFFSET,
44 SI_CRTC3_REGISTER_OFFSET,
45 SI_CRTC4_REGISTER_OFFSET,
46 SI_CRTC5_REGISTER_OFFSET
49 static const uint32_t dig_offsets[] = {
50 SI_CRTC0_REGISTER_OFFSET,
51 SI_CRTC1_REGISTER_OFFSET,
52 SI_CRTC2_REGISTER_OFFSET,
53 SI_CRTC3_REGISTER_OFFSET,
54 SI_CRTC4_REGISTER_OFFSET,
55 SI_CRTC5_REGISTER_OFFSET,
56 (0x13830 - 0x7030) >> 2,
65 } interrupt_status_offsets[6] = { {
66 .reg = DISP_INTERRUPT_STATUS,
67 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
68 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
69 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
71 .reg = DISP_INTERRUPT_STATUS_CONTINUE,
72 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
73 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
74 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
76 .reg = DISP_INTERRUPT_STATUS_CONTINUE2,
77 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
81 .reg = DISP_INTERRUPT_STATUS_CONTINUE3,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
86 .reg = DISP_INTERRUPT_STATUS_CONTINUE4,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
91 .reg = DISP_INTERRUPT_STATUS_CONTINUE5,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
97 static const uint32_t hpd_int_control_offsets[6] = {
106 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
107 u32 block_offset, u32 reg)
109 DRM_INFO("xxxx: dce_v6_0_audio_endpt_rreg ----no impl!!!!\n");
113 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
114 u32 block_offset, u32 reg, u32 v)
116 DRM_INFO("xxxx: dce_v6_0_audio_endpt_wreg ----no impl!!!!\n");
119 static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
121 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
127 static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
131 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
132 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
141 * dce_v6_0_wait_for_vblank - vblank wait asic callback.
143 * @crtc: crtc to wait for vblank on
145 * Wait for vblank on the requested crtc (evergreen+).
147 static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
151 if (crtc >= adev->mode_info.num_crtc)
154 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
157 /* depending on when we hit vblank, we may be close to active; if so,
158 * wait for another frame.
160 while (dce_v6_0_is_in_vblank(adev, crtc)) {
163 if (!dce_v6_0_is_counter_moving(adev, crtc))
168 while (!dce_v6_0_is_in_vblank(adev, crtc)) {
171 if (!dce_v6_0_is_counter_moving(adev, crtc))
177 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
179 if (crtc >= adev->mode_info.num_crtc)
182 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
185 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
189 /* Enable pflip interrupts */
190 for (i = 0; i < adev->mode_info.num_crtc; i++)
191 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
194 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
198 /* Disable pflip interrupts */
199 for (i = 0; i < adev->mode_info.num_crtc; i++)
200 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
204 * dce_v6_0_page_flip - pageflip callback.
206 * @adev: amdgpu_device pointer
207 * @crtc_id: crtc to cleanup pageflip on
208 * @crtc_base: new address of the crtc (GPU MC address)
210 * Does the actual pageflip (evergreen+).
211 * During vblank we take the crtc lock and wait for the update_pending
212 * bit to go high, when it does, we release the lock, and allow the
213 * double buffered update to take place.
214 * Returns the current update pending status.
216 static void dce_v6_0_page_flip(struct amdgpu_device *adev,
217 int crtc_id, u64 crtc_base, bool async)
219 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
221 /* flip at hsync for async, default is vsync */
222 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
223 EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
224 /* update the scanout addresses */
225 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
226 upper_32_bits(crtc_base));
227 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
231 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
234 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
235 u32 *vbl, u32 *position)
237 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
239 *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]);
240 *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
247 * dce_v6_0_hpd_sense - hpd sense callback.
249 * @adev: amdgpu_device pointer
250 * @hpd: hpd (hotplug detect) pin
252 * Checks if a digital monitor is connected (evergreen+).
253 * Returns true if connected, false if not connected.
255 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
256 enum amdgpu_hpd_id hpd)
258 bool connected = false;
262 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
266 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
270 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
274 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
278 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
282 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
293 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
295 * @adev: amdgpu_device pointer
296 * @hpd: hpd (hotplug detect) pin
298 * Set the polarity of the hpd pin (evergreen+).
300 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
301 enum amdgpu_hpd_id hpd)
304 bool connected = dce_v6_0_hpd_sense(adev, hpd);
308 tmp = RREG32(DC_HPD1_INT_CONTROL);
310 tmp &= ~DC_HPDx_INT_POLARITY;
312 tmp |= DC_HPDx_INT_POLARITY;
313 WREG32(DC_HPD1_INT_CONTROL, tmp);
316 tmp = RREG32(DC_HPD2_INT_CONTROL);
318 tmp &= ~DC_HPDx_INT_POLARITY;
320 tmp |= DC_HPDx_INT_POLARITY;
321 WREG32(DC_HPD2_INT_CONTROL, tmp);
324 tmp = RREG32(DC_HPD3_INT_CONTROL);
326 tmp &= ~DC_HPDx_INT_POLARITY;
328 tmp |= DC_HPDx_INT_POLARITY;
329 WREG32(DC_HPD3_INT_CONTROL, tmp);
332 tmp = RREG32(DC_HPD4_INT_CONTROL);
334 tmp &= ~DC_HPDx_INT_POLARITY;
336 tmp |= DC_HPDx_INT_POLARITY;
337 WREG32(DC_HPD4_INT_CONTROL, tmp);
340 tmp = RREG32(DC_HPD5_INT_CONTROL);
342 tmp &= ~DC_HPDx_INT_POLARITY;
344 tmp |= DC_HPDx_INT_POLARITY;
345 WREG32(DC_HPD5_INT_CONTROL, tmp);
348 tmp = RREG32(DC_HPD6_INT_CONTROL);
350 tmp &= ~DC_HPDx_INT_POLARITY;
352 tmp |= DC_HPDx_INT_POLARITY;
353 WREG32(DC_HPD6_INT_CONTROL, tmp);
361 * dce_v6_0_hpd_init - hpd setup callback.
363 * @adev: amdgpu_device pointer
365 * Setup the hpd pins used by the card (evergreen+).
366 * Enable the pin, set the polarity, and enable the hpd interrupts.
368 static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
370 struct drm_device *dev = adev->ddev;
371 struct drm_connector *connector;
372 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
373 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
376 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
378 switch (amdgpu_connector->hpd.hpd) {
380 WREG32(DC_HPD1_CONTROL, tmp);
383 WREG32(DC_HPD2_CONTROL, tmp);
386 WREG32(DC_HPD3_CONTROL, tmp);
389 WREG32(DC_HPD4_CONTROL, tmp);
392 WREG32(DC_HPD5_CONTROL, tmp);
395 WREG32(DC_HPD6_CONTROL, tmp);
401 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
402 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
403 /* don't try to enable hpd on eDP or LVDS avoid breaking the
404 * aux dp channel on imac and help (but not completely fix)
405 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
406 * also avoid interrupt storms during dpms.
408 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
410 switch (amdgpu_connector->hpd.hpd) {
412 dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL;
415 dc_hpd_int_cntl_reg = DC_HPD2_INT_CONTROL;
418 dc_hpd_int_cntl_reg = DC_HPD3_INT_CONTROL;
421 dc_hpd_int_cntl_reg = DC_HPD4_INT_CONTROL;
424 dc_hpd_int_cntl_reg = DC_HPD5_INT_CONTROL;
427 dc_hpd_int_cntl_reg = DC_HPD6_INT_CONTROL;
433 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
434 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
435 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
439 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
440 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
446 * dce_v6_0_hpd_fini - hpd tear down callback.
448 * @adev: amdgpu_device pointer
450 * Tear down the hpd pins used by the card (evergreen+).
451 * Disable the hpd interrupts.
453 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
455 struct drm_device *dev = adev->ddev;
456 struct drm_connector *connector;
458 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
459 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
461 switch (amdgpu_connector->hpd.hpd) {
463 WREG32(DC_HPD1_CONTROL, 0);
466 WREG32(DC_HPD2_CONTROL, 0);
469 WREG32(DC_HPD3_CONTROL, 0);
472 WREG32(DC_HPD4_CONTROL, 0);
475 WREG32(DC_HPD5_CONTROL, 0);
478 WREG32(DC_HPD6_CONTROL, 0);
483 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
487 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
489 return SI_DC_GPIO_HPD_A;
492 static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
494 DRM_INFO("xxxx: dce_v6_0_is_display_hung ----no imp!!!!!\n");
499 static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
501 if (crtc >= adev->mode_info.num_crtc)
504 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
507 static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
508 struct amdgpu_mode_mc_save *save)
510 u32 crtc_enabled, tmp, frame_count;
513 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
514 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
516 /* disable VGA render */
517 WREG32(VGA_RENDER_CONTROL, 0);
519 /* blank the display controllers */
520 for (i = 0; i < adev->mode_info.num_crtc; i++) {
521 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
523 save->crtc_enabled[i] = true;
524 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
526 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
527 dce_v6_0_vblank_wait(adev, i);
528 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
529 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
530 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
531 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
533 /* wait for the next frame */
534 frame_count = evergreen_get_vblank_counter(adev, i);
535 for (j = 0; j < adev->usec_timeout; j++) {
536 if (evergreen_get_vblank_counter(adev, i) != frame_count)
541 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
542 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
543 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
544 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
545 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
546 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
547 save->crtc_enabled[i] = false;
550 save->crtc_enabled[i] = false;
555 static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
556 struct amdgpu_mode_mc_save *save)
561 /* update crtc base addresses */
562 for (i = 0; i < adev->mode_info.num_crtc; i++) {
563 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
564 upper_32_bits(adev->mc.vram_start));
565 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
566 upper_32_bits(adev->mc.vram_start));
567 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
568 (u32)adev->mc.vram_start);
569 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
570 (u32)adev->mc.vram_start);
573 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
574 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
576 /* unlock regs and wait for update */
577 for (i = 0; i < adev->mode_info.num_crtc; i++) {
578 if (save->crtc_enabled[i]) {
579 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
580 if ((tmp & 0x7) != 3) {
583 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
585 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
586 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
587 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
588 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
590 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
593 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
595 for (j = 0; j < adev->usec_timeout; j++) {
596 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
597 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
604 /* Unlock vga access */
605 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
607 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
611 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
615 WREG32(R_000300_VGA_RENDER_CONTROL,
616 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
620 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
623 struct drm_device *dev = encoder->dev;
624 struct amdgpu_device *adev = dev->dev_private;
625 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
626 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
627 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
630 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
633 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
634 bpc = amdgpu_connector_get_monitor_bpc(connector);
635 dither = amdgpu_connector->dither;
638 /* LVDS FMT is set up by atom */
639 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
648 if (dither == AMDGPU_FMT_DITHER_ENABLE)
649 /* XXX sort out optimal dither settings */
650 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
651 FMT_SPATIAL_DITHER_EN);
653 tmp |= FMT_TRUNCATE_EN;
656 if (dither == AMDGPU_FMT_DITHER_ENABLE)
657 /* XXX sort out optimal dither settings */
658 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
659 FMT_RGB_RANDOM_ENABLE |
660 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
662 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
670 WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
674 * cik_get_number_of_dram_channels - get the number of dram channels
676 * @adev: amdgpu_device pointer
678 * Look up the number of video ram channels (CIK).
679 * Used for display watermark bandwidth calculations
680 * Returns the number of dram channels
682 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
684 u32 tmp = RREG32(MC_SHARED_CHMAP);
686 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
709 struct dce6_wm_params {
710 u32 dram_channels; /* number of dram channels */
711 u32 yclk; /* bandwidth per dram data pin in kHz */
712 u32 sclk; /* engine clock in kHz */
713 u32 disp_clk; /* display clock in kHz */
714 u32 src_width; /* viewport width */
715 u32 active_time; /* active display time in ns */
716 u32 blank_time; /* blank time in ns */
717 bool interlaced; /* mode is interlaced */
718 fixed20_12 vsc; /* vertical scale ratio */
719 u32 num_heads; /* number of active crtcs */
720 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
721 u32 lb_size; /* line buffer allocated to pipe */
722 u32 vtaps; /* vertical scaler taps */
726 * dce_v6_0_dram_bandwidth - get the dram bandwidth
728 * @wm: watermark calculation data
730 * Calculate the raw dram bandwidth (CIK).
731 * Used for display watermark bandwidth calculations
732 * Returns the dram bandwidth in MBytes/s
734 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
736 /* Calculate raw DRAM Bandwidth */
737 fixed20_12 dram_efficiency; /* 0.7 */
738 fixed20_12 yclk, dram_channels, bandwidth;
741 a.full = dfixed_const(1000);
742 yclk.full = dfixed_const(wm->yclk);
743 yclk.full = dfixed_div(yclk, a);
744 dram_channels.full = dfixed_const(wm->dram_channels * 4);
745 a.full = dfixed_const(10);
746 dram_efficiency.full = dfixed_const(7);
747 dram_efficiency.full = dfixed_div(dram_efficiency, a);
748 bandwidth.full = dfixed_mul(dram_channels, yclk);
749 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
751 return dfixed_trunc(bandwidth);
755 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
757 * @wm: watermark calculation data
759 * Calculate the dram bandwidth used for display (CIK).
760 * Used for display watermark bandwidth calculations
761 * Returns the dram bandwidth for display in MBytes/s
763 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
765 /* Calculate DRAM Bandwidth and the part allocated to display. */
766 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
767 fixed20_12 yclk, dram_channels, bandwidth;
770 a.full = dfixed_const(1000);
771 yclk.full = dfixed_const(wm->yclk);
772 yclk.full = dfixed_div(yclk, a);
773 dram_channels.full = dfixed_const(wm->dram_channels * 4);
774 a.full = dfixed_const(10);
775 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
776 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
777 bandwidth.full = dfixed_mul(dram_channels, yclk);
778 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
780 return dfixed_trunc(bandwidth);
784 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
786 * @wm: watermark calculation data
788 * Calculate the data return bandwidth used for display (CIK).
789 * Used for display watermark bandwidth calculations
790 * Returns the data return bandwidth in MBytes/s
792 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
794 /* Calculate the display Data return Bandwidth */
795 fixed20_12 return_efficiency; /* 0.8 */
796 fixed20_12 sclk, bandwidth;
799 a.full = dfixed_const(1000);
800 sclk.full = dfixed_const(wm->sclk);
801 sclk.full = dfixed_div(sclk, a);
802 a.full = dfixed_const(10);
803 return_efficiency.full = dfixed_const(8);
804 return_efficiency.full = dfixed_div(return_efficiency, a);
805 a.full = dfixed_const(32);
806 bandwidth.full = dfixed_mul(a, sclk);
807 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
809 return dfixed_trunc(bandwidth);
813 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
815 * @wm: watermark calculation data
817 * Calculate the dmif bandwidth used for display (CIK).
818 * Used for display watermark bandwidth calculations
819 * Returns the dmif bandwidth in MBytes/s
821 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
823 /* Calculate the DMIF Request Bandwidth */
824 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
825 fixed20_12 disp_clk, bandwidth;
828 a.full = dfixed_const(1000);
829 disp_clk.full = dfixed_const(wm->disp_clk);
830 disp_clk.full = dfixed_div(disp_clk, a);
831 a.full = dfixed_const(32);
832 b.full = dfixed_mul(a, disp_clk);
834 a.full = dfixed_const(10);
835 disp_clk_request_efficiency.full = dfixed_const(8);
836 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
838 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
840 return dfixed_trunc(bandwidth);
844 * dce_v6_0_available_bandwidth - get the min available bandwidth
846 * @wm: watermark calculation data
848 * Calculate the min available bandwidth used for display (CIK).
849 * Used for display watermark bandwidth calculations
850 * Returns the min available bandwidth in MBytes/s
852 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
854 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
855 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
856 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
857 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
859 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
863 * dce_v6_0_average_bandwidth - get the average available bandwidth
865 * @wm: watermark calculation data
867 * Calculate the average available bandwidth used for display (CIK).
868 * Used for display watermark bandwidth calculations
869 * Returns the average available bandwidth in MBytes/s
871 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
873 /* Calculate the display mode Average Bandwidth
874 * DisplayMode should contain the source and destination dimensions,
878 fixed20_12 line_time;
879 fixed20_12 src_width;
880 fixed20_12 bandwidth;
883 a.full = dfixed_const(1000);
884 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
885 line_time.full = dfixed_div(line_time, a);
886 bpp.full = dfixed_const(wm->bytes_per_pixel);
887 src_width.full = dfixed_const(wm->src_width);
888 bandwidth.full = dfixed_mul(src_width, bpp);
889 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
890 bandwidth.full = dfixed_div(bandwidth, line_time);
892 return dfixed_trunc(bandwidth);
896 * dce_v6_0_latency_watermark - get the latency watermark
898 * @wm: watermark calculation data
900 * Calculate the latency watermark (CIK).
901 * Used for display watermark bandwidth calculations
902 * Returns the latency watermark in ns
904 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
906 /* First calculate the latency in ns */
907 u32 mc_latency = 2000; /* 2000 ns. */
908 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
909 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
910 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
911 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
912 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
913 (wm->num_heads * cursor_line_pair_return_time);
914 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
915 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
916 u32 tmp, dmif_size = 12288;
919 if (wm->num_heads == 0)
922 a.full = dfixed_const(2);
923 b.full = dfixed_const(1);
924 if ((wm->vsc.full > a.full) ||
925 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
927 ((wm->vsc.full >= a.full) && wm->interlaced))
928 max_src_lines_per_dst_line = 4;
930 max_src_lines_per_dst_line = 2;
932 a.full = dfixed_const(available_bandwidth);
933 b.full = dfixed_const(wm->num_heads);
934 a.full = dfixed_div(a, b);
935 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
936 tmp = min(dfixed_trunc(a), tmp);
938 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
940 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
941 b.full = dfixed_const(1000);
942 c.full = dfixed_const(lb_fill_bw);
943 b.full = dfixed_div(c, b);
944 a.full = dfixed_div(a, b);
945 line_fill_time = dfixed_trunc(a);
947 if (line_fill_time < wm->active_time)
950 return latency + (line_fill_time - wm->active_time);
955 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
956 * average and available dram bandwidth
958 * @wm: watermark calculation data
960 * Check if the display average bandwidth fits in the display
961 * dram bandwidth (CIK).
962 * Used for display watermark bandwidth calculations
963 * Returns true if the display fits, false if not.
965 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
967 if (dce_v6_0_average_bandwidth(wm) <=
968 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
975 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
976 * average and available bandwidth
978 * @wm: watermark calculation data
980 * Check if the display average bandwidth fits in the display
981 * available bandwidth (CIK).
982 * Used for display watermark bandwidth calculations
983 * Returns true if the display fits, false if not.
985 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
987 if (dce_v6_0_average_bandwidth(wm) <=
988 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
995 * dce_v6_0_check_latency_hiding - check latency hiding
997 * @wm: watermark calculation data
999 * Check latency hiding (CIK).
1000 * Used for display watermark bandwidth calculations
1001 * Returns true if the display fits, false if not.
1003 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
1005 u32 lb_partitions = wm->lb_size / wm->src_width;
1006 u32 line_time = wm->active_time + wm->blank_time;
1007 u32 latency_tolerant_lines;
1011 a.full = dfixed_const(1);
1012 if (wm->vsc.full > a.full)
1013 latency_tolerant_lines = 1;
1015 if (lb_partitions <= (wm->vtaps + 1))
1016 latency_tolerant_lines = 1;
1018 latency_tolerant_lines = 2;
1021 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1023 if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
1030 * dce_v6_0_program_watermarks - program display watermarks
1032 * @adev: amdgpu_device pointer
1033 * @amdgpu_crtc: the selected display controller
1034 * @lb_size: line buffer size
1035 * @num_heads: number of display controllers in use
1037 * Calculate and program the display watermarks for the
1038 * selected display controller (CIK).
1040 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
1041 struct amdgpu_crtc *amdgpu_crtc,
1042 u32 lb_size, u32 num_heads)
1044 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1045 struct dce6_wm_params wm_low, wm_high;
1049 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1050 u32 priority_a_mark = 0, priority_b_mark = 0;
1051 u32 priority_a_cnt = PRIORITY_OFF;
1052 u32 priority_b_cnt = PRIORITY_OFF;
1053 u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
1056 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1057 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1059 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1061 line_time = min(line_time, (u32)65535);
1065 dram_channels = si_get_number_of_dram_channels(adev);
1067 /* watermark for high clocks */
1068 if (adev->pm.dpm_enabled) {
1070 amdgpu_dpm_get_mclk(adev, false) * 10;
1072 amdgpu_dpm_get_sclk(adev, false) * 10;
1074 wm_high.yclk = adev->pm.current_mclk * 10;
1075 wm_high.sclk = adev->pm.current_sclk * 10;
1078 wm_high.disp_clk = mode->clock;
1079 wm_high.src_width = mode->crtc_hdisplay;
1080 wm_high.active_time = active_time;
1081 wm_high.blank_time = line_time - wm_high.active_time;
1082 wm_high.interlaced = false;
1083 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1084 wm_high.interlaced = true;
1085 wm_high.vsc = amdgpu_crtc->vsc;
1087 if (amdgpu_crtc->rmx_type != RMX_OFF)
1089 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1090 wm_high.lb_size = lb_size;
1091 wm_high.dram_channels = dram_channels;
1092 wm_high.num_heads = num_heads;
1094 if (adev->pm.dpm_enabled) {
1095 /* watermark for low clocks */
1097 amdgpu_dpm_get_mclk(adev, true) * 10;
1099 amdgpu_dpm_get_sclk(adev, true) * 10;
1101 wm_low.yclk = adev->pm.current_mclk * 10;
1102 wm_low.sclk = adev->pm.current_sclk * 10;
1105 wm_low.disp_clk = mode->clock;
1106 wm_low.src_width = mode->crtc_hdisplay;
1107 wm_low.active_time = active_time;
1108 wm_low.blank_time = line_time - wm_low.active_time;
1109 wm_low.interlaced = false;
1110 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1111 wm_low.interlaced = true;
1112 wm_low.vsc = amdgpu_crtc->vsc;
1114 if (amdgpu_crtc->rmx_type != RMX_OFF)
1116 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1117 wm_low.lb_size = lb_size;
1118 wm_low.dram_channels = dram_channels;
1119 wm_low.num_heads = num_heads;
1121 /* set for high clocks */
1122 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
1123 /* set for low clocks */
1124 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
1126 /* possibly force display priority to high */
1127 /* should really do this at mode validation time... */
1128 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1129 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1130 !dce_v6_0_check_latency_hiding(&wm_high) ||
1131 (adev->mode_info.disp_priority == 2)) {
1132 DRM_DEBUG_KMS("force priority to high\n");
1133 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1134 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1136 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1137 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1138 !dce_v6_0_check_latency_hiding(&wm_low) ||
1139 (adev->mode_info.disp_priority == 2)) {
1140 DRM_DEBUG_KMS("force priority to high\n");
1141 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1142 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1145 a.full = dfixed_const(1000);
1146 b.full = dfixed_const(mode->clock);
1147 b.full = dfixed_div(b, a);
1148 c.full = dfixed_const(latency_watermark_a);
1149 c.full = dfixed_mul(c, b);
1150 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1151 c.full = dfixed_div(c, a);
1152 a.full = dfixed_const(16);
1153 c.full = dfixed_div(c, a);
1154 priority_a_mark = dfixed_trunc(c);
1155 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1157 a.full = dfixed_const(1000);
1158 b.full = dfixed_const(mode->clock);
1159 b.full = dfixed_div(b, a);
1160 c.full = dfixed_const(latency_watermark_b);
1161 c.full = dfixed_mul(c, b);
1162 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1163 c.full = dfixed_div(c, a);
1164 a.full = dfixed_const(16);
1165 c.full = dfixed_div(c, a);
1166 priority_b_mark = dfixed_trunc(c);
1167 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1169 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1173 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1175 tmp &= ~LATENCY_WATERMARK_MASK(3);
1176 tmp |= LATENCY_WATERMARK_MASK(1);
1177 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1178 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
1179 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1180 LATENCY_HIGH_WATERMARK(line_time)));
1182 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1183 tmp &= ~LATENCY_WATERMARK_MASK(3);
1184 tmp |= LATENCY_WATERMARK_MASK(2);
1185 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1186 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
1187 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1188 LATENCY_HIGH_WATERMARK(line_time)));
1189 /* restore original selection */
1190 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
1192 /* write the priority marks */
1193 WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
1194 WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
1196 /* save values for DPM */
1197 amdgpu_crtc->line_time = line_time;
1198 amdgpu_crtc->wm_high = latency_watermark_a;
1200 /* Save number of lines the linebuffer leads before the scanout */
1201 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1204 /* watermark setup */
1205 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1206 struct amdgpu_crtc *amdgpu_crtc,
1207 struct drm_display_mode *mode,
1208 struct drm_display_mode *other_mode)
1210 u32 tmp, buffer_alloc, i;
1211 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
1214 * There are 3 line buffers, each one shared by 2 display controllers.
1215 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1216 * the display controllers. The paritioning is done via one of four
1217 * preset allocations specified in bits 21:20:
1219 * 2 - whole lb, other crtc must be disabled
1221 /* this can get tricky if we have two large displays on a paired group
1222 * of crtcs. Ideally for multiple large displays we'd assign them to
1223 * non-linked crtcs for maximum line buffer allocation.
1225 if (amdgpu_crtc->base.enabled && mode) {
1230 tmp = 2; /* whole */
1238 WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1239 DC_LB_MEMORY_CONFIG(tmp));
1241 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1242 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
1243 for (i = 0; i < adev->usec_timeout; i++) {
1244 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1245 DMIF_BUFFERS_ALLOCATED_COMPLETED)
1250 if (amdgpu_crtc->base.enabled && mode) {
1260 /* controller not enabled, so no lb used */
1267 * dce_v6_0_bandwidth_update - program display watermarks
1269 * @adev: amdgpu_device pointer
1271 * Calculate and program the display watermarks and line
1272 * buffer allocation (CIK).
1274 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1276 struct drm_display_mode *mode0 = NULL;
1277 struct drm_display_mode *mode1 = NULL;
1278 u32 num_heads = 0, lb_size;
1281 if (!adev->mode_info.mode_config_initialized)
1284 amdgpu_update_display_priority(adev);
1286 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1287 if (adev->mode_info.crtcs[i]->base.enabled)
1290 for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1291 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1292 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1293 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1294 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1295 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1296 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1300 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1305 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1306 offset = adev->mode_info.audio.pin[i].offset;
1307 tmp = RREG32_AUDIO_ENDPT(offset,
1308 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1309 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
1310 adev->mode_info.audio.pin[i].connected = false;
1312 adev->mode_info.audio.pin[i].connected = true;
1317 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1321 dce_v6_0_audio_get_connected_pins(adev);
1323 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1324 if (adev->mode_info.audio.pin[i].connected)
1325 return &adev->mode_info.audio.pin[i];
1327 DRM_ERROR("No connected audio pins found!\n");
1331 static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1333 struct amdgpu_device *adev = encoder->dev->dev_private;
1334 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1335 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1338 if (!dig || !dig->afmt || !dig->afmt->pin)
1341 offset = dig->afmt->offset;
1343 WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
1344 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
1348 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1349 struct drm_display_mode *mode)
1351 DRM_INFO("xxxx: dce_v6_0_audio_write_latency_fields---no imp!!!!!\n");
1354 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1356 DRM_INFO("xxxx: dce_v6_0_audio_write_speaker_allocation---no imp!!!!!\n");
1359 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1361 DRM_INFO("xxxx: dce_v6_0_audio_write_sad_regs---no imp!!!!!\n");
1365 static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1366 struct amdgpu_audio_pin *pin,
1369 DRM_INFO("xxxx: dce_v6_0_audio_enable---no imp!!!!!\n");
1372 static const u32 pin_offsets[7] =
1383 static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1388 static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1394 static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1396 DRM_INFO("xxxx: dce_v6_0_afmt_update_ACR---no imp!!!!!\n");
1400 * build a HDMI Video Info Frame
1403 static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1404 void *buffer, size_t size)
1406 DRM_INFO("xxxx: dce_v6_0_afmt_update_avi_infoframe---no imp!!!!!\n");
1409 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1411 DRM_INFO("xxxx: dce_v6_0_audio_set_dto---no imp!!!!!\n");
1415 * update the info frames with the data from the current display mode
1417 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1418 struct drm_display_mode *mode)
1420 DRM_INFO("xxxx: dce_v6_0_afmt_setmode ----no impl !!!!!!!!\n");
1423 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1425 struct drm_device *dev = encoder->dev;
1426 struct amdgpu_device *adev = dev->dev_private;
1427 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1428 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1430 if (!dig || !dig->afmt)
1433 /* Silent, r600_hdmi_enable will raise WARN for us */
1434 if (enable && dig->afmt->enabled)
1436 if (!enable && !dig->afmt->enabled)
1439 if (!enable && dig->afmt->pin) {
1440 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1441 dig->afmt->pin = NULL;
1444 dig->afmt->enabled = enable;
1446 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1447 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1450 static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1454 for (i = 0; i < adev->mode_info.num_dig; i++)
1455 adev->mode_info.afmt[i] = NULL;
1457 /* DCE6 has audio blocks tied to DIG encoders */
1458 for (i = 0; i < adev->mode_info.num_dig; i++) {
1459 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1460 if (adev->mode_info.afmt[i]) {
1461 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1462 adev->mode_info.afmt[i]->id = i;
1464 for (j = 0; j < i; j++) {
1465 kfree(adev->mode_info.afmt[j]);
1466 adev->mode_info.afmt[j] = NULL;
1468 DRM_ERROR("Out of memory allocating afmt table\n");
1475 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1479 for (i = 0; i < adev->mode_info.num_dig; i++) {
1480 kfree(adev->mode_info.afmt[i]);
1481 adev->mode_info.afmt[i] = NULL;
1485 static const u32 vga_control_regs[6] =
1487 AVIVO_D1VGA_CONTROL,
1488 AVIVO_D2VGA_CONTROL,
1489 EVERGREEN_D3VGA_CONTROL,
1490 EVERGREEN_D4VGA_CONTROL,
1491 EVERGREEN_D5VGA_CONTROL,
1492 EVERGREEN_D6VGA_CONTROL,
1495 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1497 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1498 struct drm_device *dev = crtc->dev;
1499 struct amdgpu_device *adev = dev->dev_private;
1502 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1503 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1506 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1508 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1509 struct drm_device *dev = crtc->dev;
1510 struct amdgpu_device *adev = dev->dev_private;
1512 WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1515 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1516 struct drm_framebuffer *fb,
1517 int x, int y, int atomic)
1519 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1520 struct drm_device *dev = crtc->dev;
1521 struct amdgpu_device *adev = dev->dev_private;
1522 struct amdgpu_framebuffer *amdgpu_fb;
1523 struct drm_framebuffer *target_fb;
1524 struct drm_gem_object *obj;
1525 struct amdgpu_bo *abo;
1526 uint64_t fb_location, tiling_flags;
1527 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1528 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1529 u32 viewport_w, viewport_h;
1531 bool bypass_lut = false;
1534 if (!atomic && !crtc->primary->fb) {
1535 DRM_DEBUG_KMS("No FB bound\n");
1540 amdgpu_fb = to_amdgpu_framebuffer(fb);
1543 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1544 target_fb = crtc->primary->fb;
1547 /* If atomic, assume fb object is pinned & idle & fenced and
1548 * just update base pointers
1550 obj = amdgpu_fb->obj;
1551 abo = gem_to_amdgpu_bo(obj);
1552 r = amdgpu_bo_reserve(abo, false);
1553 if (unlikely(r != 0))
1557 fb_location = amdgpu_bo_gpu_offset(abo);
1559 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1560 if (unlikely(r != 0)) {
1561 amdgpu_bo_unreserve(abo);
1566 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1567 amdgpu_bo_unreserve(abo);
1569 switch (target_fb->pixel_format) {
1571 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1572 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1574 case DRM_FORMAT_XRGB4444:
1575 case DRM_FORMAT_ARGB4444:
1576 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1577 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1579 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1582 case DRM_FORMAT_XRGB1555:
1583 case DRM_FORMAT_ARGB1555:
1584 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1585 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1587 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1590 case DRM_FORMAT_BGRX5551:
1591 case DRM_FORMAT_BGRA5551:
1592 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1593 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1595 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1598 case DRM_FORMAT_RGB565:
1599 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1600 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1602 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1605 case DRM_FORMAT_XRGB8888:
1606 case DRM_FORMAT_ARGB8888:
1607 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1608 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1610 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1613 case DRM_FORMAT_XRGB2101010:
1614 case DRM_FORMAT_ARGB2101010:
1615 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1616 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1618 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1620 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1623 case DRM_FORMAT_BGRX1010102:
1624 case DRM_FORMAT_BGRA1010102:
1625 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1626 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1628 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1630 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1634 DRM_ERROR("Unsupported screen format %s\n",
1635 drm_get_format_name(target_fb->pixel_format));
1639 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1640 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1642 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1643 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1644 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1645 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1646 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1648 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1649 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1650 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1651 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1652 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1653 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1654 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1655 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1658 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1659 fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
1661 dce_v6_0_vga_enable(crtc, false);
1663 /* Make sure surface address is updated at vertical blank rather than
1666 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1668 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1669 upper_32_bits(fb_location));
1670 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1671 upper_32_bits(fb_location));
1672 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1673 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1674 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1675 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1676 WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1677 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap);
1680 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1681 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1682 * retain the full precision throughout the pipeline.
1684 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1685 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1686 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1689 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1691 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1692 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1693 WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1694 WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1695 WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1696 WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1698 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1699 WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1701 dce_v6_0_grph_enable(crtc, true);
1703 WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1707 WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset,
1709 viewport_w = crtc->mode.hdisplay;
1710 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1712 WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1713 (viewport_w << 16) | viewport_h);
1715 /* set pageflip to happen anywhere in vblank interval */
1716 WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1718 if (!atomic && fb && fb != crtc->primary->fb) {
1719 amdgpu_fb = to_amdgpu_framebuffer(fb);
1720 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1721 r = amdgpu_bo_reserve(abo, false);
1722 if (unlikely(r != 0))
1724 amdgpu_bo_unpin(abo);
1725 amdgpu_bo_unreserve(abo);
1728 /* Bytes per pixel may have changed */
1729 dce_v6_0_bandwidth_update(adev);
1735 static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1736 struct drm_display_mode *mode)
1738 struct drm_device *dev = crtc->dev;
1739 struct amdgpu_device *adev = dev->dev_private;
1740 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1742 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1743 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset,
1744 EVERGREEN_INTERLEAVE_EN);
1746 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1749 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
1752 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1753 struct drm_device *dev = crtc->dev;
1754 struct amdgpu_device *adev = dev->dev_private;
1757 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
1759 WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1760 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
1761 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
1762 WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
1763 NI_GRPH_PRESCALE_BYPASS);
1764 WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
1765 NI_OVL_PRESCALE_BYPASS);
1766 WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1767 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
1768 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
1772 WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
1774 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
1775 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
1776 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
1778 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
1779 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
1780 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
1782 WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
1783 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
1785 WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
1786 for (i = 0; i < 256; i++) {
1787 WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
1788 (amdgpu_crtc->lut_r[i] << 20) |
1789 (amdgpu_crtc->lut_g[i] << 10) |
1790 (amdgpu_crtc->lut_b[i] << 0));
1793 WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1794 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
1795 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
1796 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
1797 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
1798 WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
1799 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
1800 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
1801 WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1802 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
1803 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
1804 WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1805 (NI_OUTPUT_CSC_GRPH_MODE(0) |
1806 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
1807 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
1808 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
1813 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
1815 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1816 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1818 switch (amdgpu_encoder->encoder_id) {
1819 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1820 return dig->linkb ? 1 : 0;
1821 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1822 return dig->linkb ? 3 : 2;
1823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1824 return dig->linkb ? 5 : 4;
1825 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1828 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
1834 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
1838 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1839 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1840 * monitors a dedicated PPLL must be used. If a particular board has
1841 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1842 * as there is no need to program the PLL itself. If we are not able to
1843 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1844 * avoid messing up an existing monitor.
1848 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
1850 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1851 struct drm_device *dev = crtc->dev;
1852 struct amdgpu_device *adev = dev->dev_private;
1856 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
1857 if (adev->clock.dp_extclk)
1858 /* skip PPLL programming if using ext clock */
1859 return ATOM_PPLL_INVALID;
1863 /* use the same PPLL for all monitors with the same clock */
1864 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
1865 if (pll != ATOM_PPLL_INVALID)
1869 /* PPLL1, and PPLL2 */
1870 pll_in_use = amdgpu_pll_get_use_mask(crtc);
1871 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1873 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1875 DRM_ERROR("unable to allocate a PPLL\n");
1876 return ATOM_PPLL_INVALID;
1879 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
1881 struct amdgpu_device *adev = crtc->dev->dev_private;
1882 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1885 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset);
1887 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
1889 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
1890 WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
1893 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
1895 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1896 struct amdgpu_device *adev = crtc->dev->dev_private;
1898 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
1899 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
1900 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
1905 static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
1907 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1908 struct amdgpu_device *adev = crtc->dev->dev_private;
1910 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1911 upper_32_bits(amdgpu_crtc->cursor_addr));
1912 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1913 lower_32_bits(amdgpu_crtc->cursor_addr));
1915 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
1916 EVERGREEN_CURSOR_EN |
1917 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
1918 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
1922 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1925 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1926 struct amdgpu_device *adev = crtc->dev->dev_private;
1927 int xorigin = 0, yorigin = 0;
1929 int w = amdgpu_crtc->cursor_width;
1931 amdgpu_crtc->cursor_x = x;
1932 amdgpu_crtc->cursor_y = y;
1934 /* avivo cursor are offset into the total surface */
1937 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
1940 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1944 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1948 WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
1949 WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
1950 WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset,
1951 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
1956 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
1961 dce_v6_0_lock_cursor(crtc, true);
1962 ret = dce_v6_0_cursor_move_locked(crtc, x, y);
1963 dce_v6_0_lock_cursor(crtc, false);
1968 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1969 struct drm_file *file_priv,
1976 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1977 struct drm_gem_object *obj;
1978 struct amdgpu_bo *aobj;
1982 /* turn off cursor */
1983 dce_v6_0_hide_cursor(crtc);
1988 if ((width > amdgpu_crtc->max_cursor_width) ||
1989 (height > amdgpu_crtc->max_cursor_height)) {
1990 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
1994 obj = drm_gem_object_lookup(file_priv, handle);
1996 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2000 aobj = gem_to_amdgpu_bo(obj);
2001 ret = amdgpu_bo_reserve(aobj, false);
2003 drm_gem_object_unreference_unlocked(obj);
2007 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2008 amdgpu_bo_unreserve(aobj);
2010 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2011 drm_gem_object_unreference_unlocked(obj);
2015 dce_v6_0_lock_cursor(crtc, true);
2017 if (width != amdgpu_crtc->cursor_width ||
2018 height != amdgpu_crtc->cursor_height ||
2019 hot_x != amdgpu_crtc->cursor_hot_x ||
2020 hot_y != amdgpu_crtc->cursor_hot_y) {
2023 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2024 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2026 dce_v6_0_cursor_move_locked(crtc, x, y);
2028 amdgpu_crtc->cursor_width = width;
2029 amdgpu_crtc->cursor_height = height;
2030 amdgpu_crtc->cursor_hot_x = hot_x;
2031 amdgpu_crtc->cursor_hot_y = hot_y;
2034 dce_v6_0_show_cursor(crtc);
2035 dce_v6_0_lock_cursor(crtc, false);
2038 if (amdgpu_crtc->cursor_bo) {
2039 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2040 ret = amdgpu_bo_reserve(aobj, false);
2041 if (likely(ret == 0)) {
2042 amdgpu_bo_unpin(aobj);
2043 amdgpu_bo_unreserve(aobj);
2045 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2048 amdgpu_crtc->cursor_bo = obj;
2052 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
2054 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2056 if (amdgpu_crtc->cursor_bo) {
2057 dce_v6_0_lock_cursor(crtc, true);
2059 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2060 amdgpu_crtc->cursor_y);
2062 dce_v6_0_show_cursor(crtc);
2063 dce_v6_0_lock_cursor(crtc, false);
2067 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2068 u16 *blue, uint32_t size)
2070 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2073 /* userspace palettes are always correct as is */
2074 for (i = 0; i < size; i++) {
2075 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2076 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2077 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2079 dce_v6_0_crtc_load_lut(crtc);
2084 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2086 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2088 drm_crtc_cleanup(crtc);
2092 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2093 .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2094 .cursor_move = dce_v6_0_crtc_cursor_move,
2095 .gamma_set = dce_v6_0_crtc_gamma_set,
2096 .set_config = amdgpu_crtc_set_config,
2097 .destroy = dce_v6_0_crtc_destroy,
2098 .page_flip_target = amdgpu_crtc_page_flip_target,
2101 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2103 struct drm_device *dev = crtc->dev;
2104 struct amdgpu_device *adev = dev->dev_private;
2105 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2109 case DRM_MODE_DPMS_ON:
2110 amdgpu_crtc->enabled = true;
2111 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2112 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2113 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2114 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2115 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2116 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2117 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2118 dce_v6_0_crtc_load_lut(crtc);
2120 case DRM_MODE_DPMS_STANDBY:
2121 case DRM_MODE_DPMS_SUSPEND:
2122 case DRM_MODE_DPMS_OFF:
2123 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2124 if (amdgpu_crtc->enabled)
2125 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2126 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2127 amdgpu_crtc->enabled = false;
2130 /* adjust pm to dpms */
2131 amdgpu_pm_compute_clocks(adev);
2134 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2136 /* disable crtc pair power gating before programming */
2137 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2138 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2139 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2142 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2144 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2145 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2148 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2151 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2152 struct drm_device *dev = crtc->dev;
2153 struct amdgpu_device *adev = dev->dev_private;
2154 struct amdgpu_atom_ss ss;
2157 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2158 if (crtc->primary->fb) {
2160 struct amdgpu_framebuffer *amdgpu_fb;
2161 struct amdgpu_bo *abo;
2163 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2164 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2165 r = amdgpu_bo_reserve(abo, false);
2167 DRM_ERROR("failed to reserve abo before unpin\n");
2169 amdgpu_bo_unpin(abo);
2170 amdgpu_bo_unreserve(abo);
2173 /* disable the GRPH */
2174 dce_v6_0_grph_enable(crtc, false);
2176 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2178 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2179 if (adev->mode_info.crtcs[i] &&
2180 adev->mode_info.crtcs[i]->enabled &&
2181 i != amdgpu_crtc->crtc_id &&
2182 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2183 /* one other crtc is using this pll don't turn
2190 switch (amdgpu_crtc->pll_id) {
2193 /* disable the ppll */
2194 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2195 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2201 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2202 amdgpu_crtc->adjusted_clock = 0;
2203 amdgpu_crtc->encoder = NULL;
2204 amdgpu_crtc->connector = NULL;
2207 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2208 struct drm_display_mode *mode,
2209 struct drm_display_mode *adjusted_mode,
2210 int x, int y, struct drm_framebuffer *old_fb)
2212 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2214 if (!amdgpu_crtc->adjusted_clock)
2217 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2218 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2219 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2220 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2221 amdgpu_atombios_crtc_scaler_setup(crtc);
2222 dce_v6_0_cursor_reset(crtc);
2223 /* update the hw version fpr dpm */
2224 amdgpu_crtc->hw_mode = *adjusted_mode;
2229 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2230 const struct drm_display_mode *mode,
2231 struct drm_display_mode *adjusted_mode)
2234 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2235 struct drm_device *dev = crtc->dev;
2236 struct drm_encoder *encoder;
2238 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2239 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2240 if (encoder->crtc == crtc) {
2241 amdgpu_crtc->encoder = encoder;
2242 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2246 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2247 amdgpu_crtc->encoder = NULL;
2248 amdgpu_crtc->connector = NULL;
2251 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2253 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2256 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2257 /* if we can't get a PPLL for a non-DP encoder, fail */
2258 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2259 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2265 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2266 struct drm_framebuffer *old_fb)
2268 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2271 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2272 struct drm_framebuffer *fb,
2273 int x, int y, enum mode_set_atomic state)
2275 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2278 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2279 .dpms = dce_v6_0_crtc_dpms,
2280 .mode_fixup = dce_v6_0_crtc_mode_fixup,
2281 .mode_set = dce_v6_0_crtc_mode_set,
2282 .mode_set_base = dce_v6_0_crtc_set_base,
2283 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2284 .prepare = dce_v6_0_crtc_prepare,
2285 .commit = dce_v6_0_crtc_commit,
2286 .load_lut = dce_v6_0_crtc_load_lut,
2287 .disable = dce_v6_0_crtc_disable,
2290 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2292 struct amdgpu_crtc *amdgpu_crtc;
2295 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2296 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2297 if (amdgpu_crtc == NULL)
2300 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2302 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2303 amdgpu_crtc->crtc_id = index;
2304 adev->mode_info.crtcs[index] = amdgpu_crtc;
2306 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2307 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2308 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2309 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2311 for (i = 0; i < 256; i++) {
2312 amdgpu_crtc->lut_r[i] = i << 2;
2313 amdgpu_crtc->lut_g[i] = i << 2;
2314 amdgpu_crtc->lut_b[i] = i << 2;
2317 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2319 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2320 amdgpu_crtc->adjusted_clock = 0;
2321 amdgpu_crtc->encoder = NULL;
2322 amdgpu_crtc->connector = NULL;
2323 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2328 static int dce_v6_0_early_init(void *handle)
2330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2332 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2333 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2335 dce_v6_0_set_display_funcs(adev);
2336 dce_v6_0_set_irq_funcs(adev);
2338 switch (adev->asic_type) {
2342 adev->mode_info.num_crtc = 6;
2343 adev->mode_info.num_hpd = 6;
2344 adev->mode_info.num_dig = 6;
2347 adev->mode_info.num_crtc = 2;
2348 adev->mode_info.num_hpd = 2;
2349 adev->mode_info.num_dig = 2;
2352 /* FIXME: not supported yet */
2359 static int dce_v6_0_sw_init(void *handle)
2363 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2365 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2366 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2371 for (i = 8; i < 20; i += 2) {
2372 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2378 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2382 adev->mode_info.mode_config_initialized = true;
2384 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2385 adev->ddev->mode_config.async_page_flip = true;
2386 adev->ddev->mode_config.max_width = 16384;
2387 adev->ddev->mode_config.max_height = 16384;
2388 adev->ddev->mode_config.preferred_depth = 24;
2389 adev->ddev->mode_config.prefer_shadow = 1;
2390 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2392 r = amdgpu_modeset_create_props(adev);
2396 adev->ddev->mode_config.max_width = 16384;
2397 adev->ddev->mode_config.max_height = 16384;
2399 /* allocate crtcs */
2400 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2401 r = dce_v6_0_crtc_init(adev, i);
2406 ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2408 amdgpu_print_display_setup(adev->ddev);
2413 r = dce_v6_0_afmt_init(adev);
2417 r = dce_v6_0_audio_init(adev);
2421 drm_kms_helper_poll_init(adev->ddev);
2426 static int dce_v6_0_sw_fini(void *handle)
2428 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2430 kfree(adev->mode_info.bios_hardcoded_edid);
2432 drm_kms_helper_poll_fini(adev->ddev);
2434 dce_v6_0_audio_fini(adev);
2435 dce_v6_0_afmt_fini(adev);
2437 drm_mode_config_cleanup(adev->ddev);
2438 adev->mode_info.mode_config_initialized = false;
2443 static int dce_v6_0_hw_init(void *handle)
2446 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2448 /* init dig PHYs, disp eng pll */
2449 amdgpu_atombios_encoder_init_dig(adev);
2450 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2452 /* initialize hpd */
2453 dce_v6_0_hpd_init(adev);
2455 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2456 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2459 dce_v6_0_pageflip_interrupt_init(adev);
2464 static int dce_v6_0_hw_fini(void *handle)
2467 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2469 dce_v6_0_hpd_fini(adev);
2471 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2472 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2475 dce_v6_0_pageflip_interrupt_fini(adev);
2480 static int dce_v6_0_suspend(void *handle)
2482 return dce_v6_0_hw_fini(handle);
2485 static int dce_v6_0_resume(void *handle)
2487 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2490 ret = dce_v6_0_hw_init(handle);
2492 /* turn on the BL */
2493 if (adev->mode_info.bl_encoder) {
2494 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2495 adev->mode_info.bl_encoder);
2496 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2503 static bool dce_v6_0_is_idle(void *handle)
2508 static int dce_v6_0_wait_for_idle(void *handle)
2513 static int dce_v6_0_soft_reset(void *handle)
2515 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2519 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2521 enum amdgpu_interrupt_state state)
2523 u32 reg_block, interrupt_mask;
2525 if (crtc >= adev->mode_info.num_crtc) {
2526 DRM_DEBUG("invalid crtc %d\n", crtc);
2532 reg_block = SI_CRTC0_REGISTER_OFFSET;
2535 reg_block = SI_CRTC1_REGISTER_OFFSET;
2538 reg_block = SI_CRTC2_REGISTER_OFFSET;
2541 reg_block = SI_CRTC3_REGISTER_OFFSET;
2544 reg_block = SI_CRTC4_REGISTER_OFFSET;
2547 reg_block = SI_CRTC5_REGISTER_OFFSET;
2550 DRM_DEBUG("invalid crtc %d\n", crtc);
2555 case AMDGPU_IRQ_STATE_DISABLE:
2556 interrupt_mask = RREG32(INT_MASK + reg_block);
2557 interrupt_mask &= ~VBLANK_INT_MASK;
2558 WREG32(INT_MASK + reg_block, interrupt_mask);
2560 case AMDGPU_IRQ_STATE_ENABLE:
2561 interrupt_mask = RREG32(INT_MASK + reg_block);
2562 interrupt_mask |= VBLANK_INT_MASK;
2563 WREG32(INT_MASK + reg_block, interrupt_mask);
2570 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2572 enum amdgpu_interrupt_state state)
2577 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2578 struct amdgpu_irq_src *src,
2580 enum amdgpu_interrupt_state state)
2582 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
2586 dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL;
2589 dc_hpd_int_cntl_reg = DC_HPD2_INT_CONTROL;
2592 dc_hpd_int_cntl_reg = DC_HPD3_INT_CONTROL;
2595 dc_hpd_int_cntl_reg = DC_HPD4_INT_CONTROL;
2598 dc_hpd_int_cntl_reg = DC_HPD5_INT_CONTROL;
2601 dc_hpd_int_cntl_reg = DC_HPD6_INT_CONTROL;
2604 DRM_DEBUG("invalid hdp %d\n", type);
2609 case AMDGPU_IRQ_STATE_DISABLE:
2610 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
2611 dc_hpd_int_cntl &= ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
2612 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
2614 case AMDGPU_IRQ_STATE_ENABLE:
2615 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
2616 dc_hpd_int_cntl |= (DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
2617 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
2626 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2627 struct amdgpu_irq_src *src,
2629 enum amdgpu_interrupt_state state)
2632 case AMDGPU_CRTC_IRQ_VBLANK1:
2633 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2635 case AMDGPU_CRTC_IRQ_VBLANK2:
2636 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2638 case AMDGPU_CRTC_IRQ_VBLANK3:
2639 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2641 case AMDGPU_CRTC_IRQ_VBLANK4:
2642 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2644 case AMDGPU_CRTC_IRQ_VBLANK5:
2645 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2647 case AMDGPU_CRTC_IRQ_VBLANK6:
2648 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2650 case AMDGPU_CRTC_IRQ_VLINE1:
2651 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2653 case AMDGPU_CRTC_IRQ_VLINE2:
2654 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2656 case AMDGPU_CRTC_IRQ_VLINE3:
2657 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2659 case AMDGPU_CRTC_IRQ_VLINE4:
2660 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2662 case AMDGPU_CRTC_IRQ_VLINE5:
2663 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2665 case AMDGPU_CRTC_IRQ_VLINE6:
2666 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2674 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2675 struct amdgpu_irq_src *source,
2676 struct amdgpu_iv_entry *entry)
2678 unsigned crtc = entry->src_id - 1;
2679 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2680 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
2682 switch (entry->src_data) {
2683 case 0: /* vblank */
2684 if (disp_int & interrupt_status_offsets[crtc].vblank)
2685 WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2687 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2689 if (amdgpu_irq_enabled(adev, source, irq_type)) {
2690 drm_handle_vblank(adev->ddev, crtc);
2692 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
2695 if (disp_int & interrupt_status_offsets[crtc].vline)
2696 WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2698 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2700 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
2703 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
2710 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2711 struct amdgpu_irq_src *src,
2713 enum amdgpu_interrupt_state state)
2717 if (type >= adev->mode_info.num_crtc) {
2718 DRM_ERROR("invalid pageflip crtc %d\n", type);
2722 reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]);
2723 if (state == AMDGPU_IRQ_STATE_DISABLE)
2724 WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
2725 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2727 WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
2728 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2733 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2734 struct amdgpu_irq_src *source,
2735 struct amdgpu_iv_entry *entry)
2737 unsigned long flags;
2739 struct amdgpu_crtc *amdgpu_crtc;
2740 struct amdgpu_flip_work *works;
2742 crtc_id = (entry->src_id - 8) >> 1;
2743 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
2745 if (crtc_id >= adev->mode_info.num_crtc) {
2746 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
2750 if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) &
2751 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2752 WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id],
2753 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2755 /* IRQ could occur when in initial stage */
2756 if (amdgpu_crtc == NULL)
2759 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2760 works = amdgpu_crtc->pflip_works;
2761 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
2762 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
2763 "AMDGPU_FLIP_SUBMITTED(%d)\n",
2764 amdgpu_crtc->pflip_status,
2765 AMDGPU_FLIP_SUBMITTED);
2766 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2770 /* page flip completed. clean up */
2771 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
2772 amdgpu_crtc->pflip_works = NULL;
2774 /* wakeup usersapce */
2776 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
2778 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2780 drm_crtc_vblank_put(&amdgpu_crtc->base);
2781 schedule_work(&works->unpin_work);
2786 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
2787 struct amdgpu_irq_src *source,
2788 struct amdgpu_iv_entry *entry)
2790 uint32_t disp_int, mask, int_control, tmp;
2793 if (entry->src_data >= adev->mode_info.num_hpd) {
2794 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
2798 hpd = entry->src_data;
2799 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
2800 mask = interrupt_status_offsets[hpd].hpd;
2801 int_control = hpd_int_control_offsets[hpd];
2803 if (disp_int & mask) {
2804 tmp = RREG32(int_control);
2805 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
2806 WREG32(int_control, tmp);
2807 schedule_work(&adev->hotplug_work);
2808 DRM_INFO("IH: HPD%d\n", hpd + 1);
2815 static int dce_v6_0_set_clockgating_state(void *handle,
2816 enum amd_clockgating_state state)
2821 static int dce_v6_0_set_powergating_state(void *handle,
2822 enum amd_powergating_state state)
2827 const struct amd_ip_funcs dce_v6_0_ip_funcs = {
2829 .early_init = dce_v6_0_early_init,
2831 .sw_init = dce_v6_0_sw_init,
2832 .sw_fini = dce_v6_0_sw_fini,
2833 .hw_init = dce_v6_0_hw_init,
2834 .hw_fini = dce_v6_0_hw_fini,
2835 .suspend = dce_v6_0_suspend,
2836 .resume = dce_v6_0_resume,
2837 .is_idle = dce_v6_0_is_idle,
2838 .wait_for_idle = dce_v6_0_wait_for_idle,
2839 .soft_reset = dce_v6_0_soft_reset,
2840 .set_clockgating_state = dce_v6_0_set_clockgating_state,
2841 .set_powergating_state = dce_v6_0_set_powergating_state,
2845 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
2846 struct drm_display_mode *mode,
2847 struct drm_display_mode *adjusted_mode)
2850 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2852 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
2854 /* need to call this here rather than in prepare() since we need some crtc info */
2855 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2857 /* set scaler clears this on some chips */
2858 dce_v6_0_set_interleave(encoder->crtc, mode);
2860 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2861 dce_v6_0_afmt_enable(encoder, true);
2862 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
2866 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
2869 struct amdgpu_device *adev = encoder->dev->dev_private;
2870 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2871 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
2873 if ((amdgpu_encoder->active_device &
2874 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2875 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
2876 ENCODER_OBJECT_ID_NONE)) {
2877 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2879 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
2880 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
2881 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
2885 amdgpu_atombios_scratch_regs_lock(adev, true);
2888 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
2890 /* select the clock/data port if it uses a router */
2891 if (amdgpu_connector->router.cd_valid)
2892 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
2894 /* turn eDP panel on for mode set */
2895 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2896 amdgpu_atombios_encoder_set_edp_panel_power(connector,
2897 ATOM_TRANSMITTER_ACTION_POWER_ON);
2900 /* this is needed for the pll/ss setup to work correctly in some cases */
2901 amdgpu_atombios_encoder_set_crtc_source(encoder);
2902 /* set up the FMT blocks */
2903 dce_v6_0_program_fmt(encoder);
2906 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
2909 struct drm_device *dev = encoder->dev;
2910 struct amdgpu_device *adev = dev->dev_private;
2912 /* need to call this here as we need the crtc set up */
2913 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2914 amdgpu_atombios_scratch_regs_lock(adev, false);
2917 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
2920 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2921 struct amdgpu_encoder_atom_dig *dig;
2923 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2925 if (amdgpu_atombios_encoder_is_digital(encoder)) {
2926 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2927 dce_v6_0_afmt_enable(encoder, false);
2928 dig = amdgpu_encoder->enc_priv;
2929 dig->dig_encoder = -1;
2931 amdgpu_encoder->active_device = 0;
2934 /* these are handled by the primary encoders */
2935 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
2940 static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
2946 dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
2947 struct drm_display_mode *mode,
2948 struct drm_display_mode *adjusted_mode)
2953 static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
2959 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
2964 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
2965 const struct drm_display_mode *mode,
2966 struct drm_display_mode *adjusted_mode)
2971 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
2972 .dpms = dce_v6_0_ext_dpms,
2973 .mode_fixup = dce_v6_0_ext_mode_fixup,
2974 .prepare = dce_v6_0_ext_prepare,
2975 .mode_set = dce_v6_0_ext_mode_set,
2976 .commit = dce_v6_0_ext_commit,
2977 .disable = dce_v6_0_ext_disable,
2978 /* no detect for TMDS/LVDS yet */
2981 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
2982 .dpms = amdgpu_atombios_encoder_dpms,
2983 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2984 .prepare = dce_v6_0_encoder_prepare,
2985 .mode_set = dce_v6_0_encoder_mode_set,
2986 .commit = dce_v6_0_encoder_commit,
2987 .disable = dce_v6_0_encoder_disable,
2988 .detect = amdgpu_atombios_encoder_dig_detect,
2991 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
2992 .dpms = amdgpu_atombios_encoder_dpms,
2993 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2994 .prepare = dce_v6_0_encoder_prepare,
2995 .mode_set = dce_v6_0_encoder_mode_set,
2996 .commit = dce_v6_0_encoder_commit,
2997 .detect = amdgpu_atombios_encoder_dac_detect,
3000 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
3002 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3003 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3004 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3005 kfree(amdgpu_encoder->enc_priv);
3006 drm_encoder_cleanup(encoder);
3007 kfree(amdgpu_encoder);
3010 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
3011 .destroy = dce_v6_0_encoder_destroy,
3014 static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
3015 uint32_t encoder_enum,
3016 uint32_t supported_device,
3019 struct drm_device *dev = adev->ddev;
3020 struct drm_encoder *encoder;
3021 struct amdgpu_encoder *amdgpu_encoder;
3023 /* see if we already added it */
3024 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3025 amdgpu_encoder = to_amdgpu_encoder(encoder);
3026 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3027 amdgpu_encoder->devices |= supported_device;
3034 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3035 if (!amdgpu_encoder)
3038 encoder = &amdgpu_encoder->base;
3039 switch (adev->mode_info.num_crtc) {
3041 encoder->possible_crtcs = 0x1;
3045 encoder->possible_crtcs = 0x3;
3048 encoder->possible_crtcs = 0xf;
3051 encoder->possible_crtcs = 0x3f;
3055 amdgpu_encoder->enc_priv = NULL;
3056 amdgpu_encoder->encoder_enum = encoder_enum;
3057 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3058 amdgpu_encoder->devices = supported_device;
3059 amdgpu_encoder->rmx_type = RMX_OFF;
3060 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3061 amdgpu_encoder->is_ext_encoder = false;
3062 amdgpu_encoder->caps = caps;
3064 switch (amdgpu_encoder->encoder_id) {
3065 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3066 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3067 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3068 DRM_MODE_ENCODER_DAC, NULL);
3069 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
3071 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3072 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3073 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3074 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3075 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3076 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3077 amdgpu_encoder->rmx_type = RMX_FULL;
3078 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3079 DRM_MODE_ENCODER_LVDS, NULL);
3080 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3081 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3082 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3083 DRM_MODE_ENCODER_DAC, NULL);
3084 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3086 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3087 DRM_MODE_ENCODER_TMDS, NULL);
3088 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3090 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
3092 case ENCODER_OBJECT_ID_SI170B:
3093 case ENCODER_OBJECT_ID_CH7303:
3094 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3095 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3096 case ENCODER_OBJECT_ID_TITFP513:
3097 case ENCODER_OBJECT_ID_VT1623:
3098 case ENCODER_OBJECT_ID_HDMI_SI1930:
3099 case ENCODER_OBJECT_ID_TRAVIS:
3100 case ENCODER_OBJECT_ID_NUTMEG:
3101 /* these are handled by the primary encoders */
3102 amdgpu_encoder->is_ext_encoder = true;
3103 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3104 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3105 DRM_MODE_ENCODER_LVDS, NULL);
3106 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3107 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3108 DRM_MODE_ENCODER_DAC, NULL);
3110 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3111 DRM_MODE_ENCODER_TMDS, NULL);
3112 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3117 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3118 .set_vga_render_state = &dce_v6_0_set_vga_render_state,
3119 .bandwidth_update = &dce_v6_0_bandwidth_update,
3120 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3121 .vblank_wait = &dce_v6_0_vblank_wait,
3122 .is_display_hung = &dce_v6_0_is_display_hung,
3123 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3124 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3125 .hpd_sense = &dce_v6_0_hpd_sense,
3126 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3127 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3128 .page_flip = &dce_v6_0_page_flip,
3129 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3130 .add_encoder = &dce_v6_0_encoder_add,
3131 .add_connector = &amdgpu_connector_add,
3132 .stop_mc_access = &dce_v6_0_stop_mc_access,
3133 .resume_mc_access = &dce_v6_0_resume_mc_access,
3136 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3138 if (adev->mode_info.funcs == NULL)
3139 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3142 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3143 .set = dce_v6_0_set_crtc_interrupt_state,
3144 .process = dce_v6_0_crtc_irq,
3147 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3148 .set = dce_v6_0_set_pageflip_interrupt_state,
3149 .process = dce_v6_0_pageflip_irq,
3152 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3153 .set = dce_v6_0_set_hpd_interrupt_state,
3154 .process = dce_v6_0_hpd_irq,
3157 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3159 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3160 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3162 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3163 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3165 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3166 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;