drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_11_0_d.h"
  36 #include "dce/dce_11_0_sh_mask.h"
  37 #include "dce/dce_11_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET,
  75         DIG7_REGISTER_OFFSET,
  76         DIG8_REGISTER_OFFSET
  77 };
  78
  79 static const struct {
  80         uint32_t        reg;
  81         uint32_t        vblank;
  82         uint32_t        vline;
  83         uint32_t        hpd;
  84
  85 } interrupt_status_offsets[] = { {
  86         .reg = mmDISP_INTERRUPT_STATUS,
  87         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 115 } };
 116
 117 static const u32 cz_golden_settings_a11[] =
 118 {
 119         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 120         mmFBC_MISC, 0x1f311fff, 0x14300000,
 121 };
 122
 123 static const u32 cz_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 stoney_golden_settings_a11[] =
 130 {
 131         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 132         mmFBC_MISC, 0x1f311fff, 0x14302000,
 133 };
 134
 135
 136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 137 {
 138         switch (adev->asic_type) {
 139         case CHIP_CARRIZO:
 140                 amdgpu_program_register_sequence(adev,
 141                                                  cz_mgcg_cgcg_init,
 142                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 143                 amdgpu_program_register_sequence(adev,
 144                                                  cz_golden_settings_a11,
 145                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 146                 break;
 147         case CHIP_STONEY:
 148                 amdgpu_program_register_sequence(adev,
 149                                                  stoney_golden_settings_a11,
 150                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 151                 break;
 152         default:
 153                 break;
 154         }
 155 }
 156
 157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 158                                      u32 block_offset, u32 reg)
 159 {
 160         unsigned long flags;
 161         u32 r;
 162
 163         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 164         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 165         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 166         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 167
 168         return r;
 169 }
 170
 171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 172                                       u32 block_offset, u32 reg, u32 v)
 173 {
 174         unsigned long flags;
 175
 176         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 177         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 178         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 179         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 180 }
 181
 182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 183 {
 184         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 185                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 186                 return true;
 187         else
 188                 return false;
 189 }
 190
 191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 192 {
 193         u32 pos1, pos2;
 194
 195         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 196         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 197
 198         if (pos1 != pos2)
 199                 return true;
 200         else
 201                 return false;
 202 }
 203
 204 /**
 205  * dce_v11_0_vblank_wait - vblank wait asic callback.
 206  *
 207  * @adev: amdgpu_device pointer
 208  * @crtc: crtc to wait for vblank on
 209  *
 210  * Wait for vblank on the requested crtc (evergreen+).
 211  */
 212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 213 {
 214         unsigned i = 0;
 215
 216         if (crtc >= adev->mode_info.num_crtc)
 217                 return;
 218
 219         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 220                 return;
 221
 222         /* depending on when we hit vblank, we may be close to active; if so,
 223          * wait for another frame.
 224          */
 225         while (dce_v11_0_is_in_vblank(adev, crtc)) {
 226                 if (i++ % 100 == 0) {
 227                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 228                                 break;
 229                 }
 230         }
 231
 232         while (!dce_v11_0_is_in_vblank(adev, crtc)) {
 233                 if (i++ % 100 == 0) {
 234                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 235                                 break;
 236                 }
 237         }
 238 }
 239
 240 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 241 {
 242         if (crtc >= adev->mode_info.num_crtc)
 243                 return 0;
 244         else
 245                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 246 }
 247
 248 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 249 {
 250         unsigned i;
 251
 252         /* Enable pflip interrupts */
 253         for (i = 0; i < adev->mode_info.num_crtc; i++)
 254                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 255 }
 256
 257 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 258 {
 259         unsigned i;
 260
 261         /* Disable pflip interrupts */
 262         for (i = 0; i < adev->mode_info.num_crtc; i++)
 263                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 264 }
 265
 266 /**
 267  * dce_v11_0_page_flip - pageflip callback.
 268  *
 269  * @adev: amdgpu_device pointer
 270  * @crtc_id: crtc to cleanup pageflip on
 271  * @crtc_base: new address of the crtc (GPU MC address)
 272  *
 273  * Triggers the actual pageflip by updating the primary
 274  * surface base address.
 275  */
 276 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 277                               int crtc_id, u64 crtc_base)
 278 {
 279         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 280
 281         /* update the scanout addresses */
 282         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 283                upper_32_bits(crtc_base));
 284         /* writing to the low address triggers the update */
 285         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 286                lower_32_bits(crtc_base));
 287         /* post the write */
 288         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 289 }
 290
 291 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 292                                         u32 *vbl, u32 *position)
 293 {
 294         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 295                 return -EINVAL;
 296
 297         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 298         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 299
 300         return 0;
 301 }
 302
 303 /**
 304  * dce_v11_0_hpd_sense - hpd sense callback.
 305  *
 306  * @adev: amdgpu_device pointer
 307  * @hpd: hpd (hotplug detect) pin
 308  *
 309  * Checks if a digital monitor is connected (evergreen+).
 310  * Returns true if connected, false if not connected.
 311  */
 312 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 313                                enum amdgpu_hpd_id hpd)
 314 {
 315         int idx;
 316         bool connected = false;
 317
 318         switch (hpd) {
 319         case AMDGPU_HPD_1:
 320                 idx = 0;
 321                 break;
 322         case AMDGPU_HPD_2:
 323                 idx = 1;
 324                 break;
 325         case AMDGPU_HPD_3:
 326                 idx = 2;
 327                 break;
 328         case AMDGPU_HPD_4:
 329                 idx = 3;
 330                 break;
 331         case AMDGPU_HPD_5:
 332                 idx = 4;
 333                 break;
 334         case AMDGPU_HPD_6:
 335                 idx = 5;
 336                 break;
 337         default:
 338                 return connected;
 339         }
 340
 341         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 342             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 343                 connected = true;
 344
 345         return connected;
 346 }
 347
 348 /**
 349  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 350  *
 351  * @adev: amdgpu_device pointer
 352  * @hpd: hpd (hotplug detect) pin
 353  *
 354  * Set the polarity of the hpd pin (evergreen+).
 355  */
 356 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 357                                       enum amdgpu_hpd_id hpd)
 358 {
 359         u32 tmp;
 360         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 361         int idx;
 362
 363         switch (hpd) {
 364         case AMDGPU_HPD_1:
 365                 idx = 0;
 366                 break;
 367         case AMDGPU_HPD_2:
 368                 idx = 1;
 369                 break;
 370         case AMDGPU_HPD_3:
 371                 idx = 2;
 372                 break;
 373         case AMDGPU_HPD_4:
 374                 idx = 3;
 375                 break;
 376         case AMDGPU_HPD_5:
 377                 idx = 4;
 378                 break;
 379         case AMDGPU_HPD_6:
 380                 idx = 5;
 381                 break;
 382         default:
 383                 return;
 384         }
 385
 386         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 387         if (connected)
 388                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 389         else
 390                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 391         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 392 }
 393
 394 /**
 395  * dce_v11_0_hpd_init - hpd setup callback.
 396  *
 397  * @adev: amdgpu_device pointer
 398  *
 399  * Setup the hpd pins used by the card (evergreen+).
 400  * Enable the pin, set the polarity, and enable the hpd interrupts.
 401  */
 402 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 403 {
 404         struct drm_device *dev = adev->ddev;
 405         struct drm_connector *connector;
 406         u32 tmp;
 407         int idx;
 408
 409         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 410                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 411
 412                 switch (amdgpu_connector->hpd.hpd) {
 413                 case AMDGPU_HPD_1:
 414                         idx = 0;
 415                         break;
 416                 case AMDGPU_HPD_2:
 417                         idx = 1;
 418                         break;
 419                 case AMDGPU_HPD_3:
 420                         idx = 2;
 421                         break;
 422                 case AMDGPU_HPD_4:
 423                         idx = 3;
 424                         break;
 425                 case AMDGPU_HPD_5:
 426                         idx = 4;
 427                         break;
 428                 case AMDGPU_HPD_6:
 429                         idx = 5;
 430                         break;
 431                 default:
 432                         continue;
 433                 }
 434
 435                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 436                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 437                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 438                          * aux dp channel on imac and help (but not completely fix)
 439                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 440                          * also avoid interrupt storms during dpms.
 441                          */
 442                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 443                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 444                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 445                         continue;
 446                 }
 447
 448                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 449                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 450                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 451
 452                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 453                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 454                                     DC_HPD_CONNECT_INT_DELAY,
 455                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 456                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 457                                     DC_HPD_DISCONNECT_INT_DELAY,
 458                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 459                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 460
 461                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 462                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 463         }
 464 }
 465
 466 /**
 467  * dce_v11_0_hpd_fini - hpd tear down callback.
 468  *
 469  * @adev: amdgpu_device pointer
 470  *
 471  * Tear down the hpd pins used by the card (evergreen+).
 472  * Disable the hpd interrupts.
 473  */
 474 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 475 {
 476         struct drm_device *dev = adev->ddev;
 477         struct drm_connector *connector;
 478         u32 tmp;
 479         int idx;
 480
 481         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 482                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 483
 484                 switch (amdgpu_connector->hpd.hpd) {
 485                 case AMDGPU_HPD_1:
 486                         idx = 0;
 487                         break;
 488                 case AMDGPU_HPD_2:
 489                         idx = 1;
 490                         break;
 491                 case AMDGPU_HPD_3:
 492                         idx = 2;
 493                         break;
 494                 case AMDGPU_HPD_4:
 495                         idx = 3;
 496                         break;
 497                 case AMDGPU_HPD_5:
 498                         idx = 4;
 499                         break;
 500                 case AMDGPU_HPD_6:
 501                         idx = 5;
 502                         break;
 503                 default:
 504                         continue;
 505                 }
 506
 507                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 508                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 509                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 510
 511                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 512         }
 513 }
 514
 515 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 516 {
 517         return mmDC_GPIO_HPD_A;
 518 }
 519
 520 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 521 {
 522         u32 crtc_hung = 0;
 523         u32 crtc_status[6];
 524         u32 i, j, tmp;
 525
 526         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 527                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 528                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 529                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 530                         crtc_hung |= (1 << i);
 531                 }
 532         }
 533
 534         for (j = 0; j < 10; j++) {
 535                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 536                         if (crtc_hung & (1 << i)) {
 537                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 538                                 if (tmp != crtc_status[i])
 539                                         crtc_hung &= ~(1 << i);
 540                         }
 541                 }
 542                 if (crtc_hung == 0)
 543                         return false;
 544                 udelay(100);
 545         }
 546
 547         return true;
 548 }
 549
 550 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
 551                                      struct amdgpu_mode_mc_save *save)
 552 {
 553         u32 crtc_enabled, tmp;
 554         int i;
 555
 556         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 557         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 558
 559         /* disable VGA render */
 560         tmp = RREG32(mmVGA_RENDER_CONTROL);
 561         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 562         WREG32(mmVGA_RENDER_CONTROL, tmp);
 563
 564         /* blank the display controllers */
 565         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 566                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 567                                              CRTC_CONTROL, CRTC_MASTER_EN);
 568                 if (crtc_enabled) {
 569 #if 0
 570                         u32 frame_count;
 571                         int j;
 572
 573                         save->crtc_enabled[i] = true;
 574                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 575                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 576                                 amdgpu_display_vblank_wait(adev, i);
 577                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 578                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 579                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 580                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 581                         }
 582                         /* wait for the next frame */
 583                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 584                         for (j = 0; j < adev->usec_timeout; j++) {
 585                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 586                                         break;
 587                                 udelay(1);
 588                         }
 589                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 590                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 591                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 592                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 593                         }
 594                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 595                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 596                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 597                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 598                         }
 599 #else
 600                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 601                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 602                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 603                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 604                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 605                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 606                         save->crtc_enabled[i] = false;
 607                         /* ***** */
 608 #endif
 609                 } else {
 610                         save->crtc_enabled[i] = false;
 611                 }
 612         }
 613 }
 614
 615 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
 616                                        struct amdgpu_mode_mc_save *save)
 617 {
 618         u32 tmp, frame_count;
 619         int i, j;
 620
 621         /* update crtc base addresses */
 622         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 623                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 624                        upper_32_bits(adev->mc.vram_start));
 625                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 626                        upper_32_bits(adev->mc.vram_start));
 627                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 628                        (u32)adev->mc.vram_start);
 629                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 630                        (u32)adev->mc.vram_start);
 631
 632                 if (save->crtc_enabled[i]) {
 633                         tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
 634                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 635                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 636                                 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 637                         }
 638                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 639                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 640                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 641                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 642                         }
 643                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 644                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 645                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 646                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 647                         }
 648                         for (j = 0; j < adev->usec_timeout; j++) {
 649                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 650                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 651                                         break;
 652                                 udelay(1);
 653                         }
 654                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 655                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 656                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 657                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 658                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 659                         /* wait for the next frame */
 660                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 661                         for (j = 0; j < adev->usec_timeout; j++) {
 662                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 663                                         break;
 664                                 udelay(1);
 665                         }
 666                 }
 667         }
 668
 669         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 670         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 671
 672         /* Unlock vga access */
 673         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 674         mdelay(1);
 675         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 676 }
 677
 678 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 679                                            bool render)
 680 {
 681         u32 tmp;
 682
 683         /* Lockout access through VGA aperture*/
 684         tmp = RREG32(mmVGA_HDP_CONTROL);
 685         if (render)
 686                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 687         else
 688                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 689         WREG32(mmVGA_HDP_CONTROL, tmp);
 690
 691         /* disable VGA render */
 692         tmp = RREG32(mmVGA_RENDER_CONTROL);
 693         if (render)
 694                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 695         else
 696                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 697         WREG32(mmVGA_RENDER_CONTROL, tmp);
 698 }
 699
 700 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 701 {
 702         struct drm_device *dev = encoder->dev;
 703         struct amdgpu_device *adev = dev->dev_private;
 704         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 705         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 706         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 707         int bpc = 0;
 708         u32 tmp = 0;
 709         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 710
 711         if (connector) {
 712                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 713                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 714                 dither = amdgpu_connector->dither;
 715         }
 716
 717         /* LVDS/eDP FMT is set up by atom */
 718         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 719                 return;
 720
 721         /* not needed for analog */
 722         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 723             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 724                 return;
 725
 726         if (bpc == 0)
 727                 return;
 728
 729         switch (bpc) {
 730         case 6:
 731                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 732                         /* XXX sort out optimal dither settings */
 733                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 734                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 735                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 737                 } else {
 738                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 739                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 740                 }
 741                 break;
 742         case 8:
 743                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 744                         /* XXX sort out optimal dither settings */
 745                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 746                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 747                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 748                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 749                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 750                 } else {
 751                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 752                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 753                 }
 754                 break;
 755         case 10:
 756                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 757                         /* XXX sort out optimal dither settings */
 758                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 759                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 760                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 761                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 762                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 763                 } else {
 764                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 765                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 766                 }
 767                 break;
 768         default:
 769                 /* not needed */
 770                 break;
 771         }
 772
 773         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 774 }
 775
 776
 777 /* display watermark setup */
 778 /**
 779  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 780  *
 781  * @adev: amdgpu_device pointer
 782  * @amdgpu_crtc: the selected display controller
 783  * @mode: the current display mode on the selected display
 784  * controller
 785  *
 786  * Setup up the line buffer allocation for
 787  * the selected display controller (CIK).
 788  * Returns the line buffer size in pixels.
 789  */
 790 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 791                                        struct amdgpu_crtc *amdgpu_crtc,
 792                                        struct drm_display_mode *mode)
 793 {
 794         u32 tmp, buffer_alloc, i, mem_cfg;
 795         u32 pipe_offset = amdgpu_crtc->crtc_id;
 796         /*
 797          * Line Buffer Setup
 798          * There are 6 line buffers, one for each display controllers.
 799          * There are 3 partitions per LB. Select the number of partitions
 800          * to enable based on the display width.  For display widths larger
 801          * than 4096, you need use to use 2 display controllers and combine
 802          * them using the stereo blender.
 803          */
 804         if (amdgpu_crtc->base.enabled && mode) {
 805                 if (mode->crtc_hdisplay < 1920) {
 806                         mem_cfg = 1;
 807                         buffer_alloc = 2;
 808                 } else if (mode->crtc_hdisplay < 2560) {
 809                         mem_cfg = 2;
 810                         buffer_alloc = 2;
 811                 } else if (mode->crtc_hdisplay < 4096) {
 812                         mem_cfg = 0;
 813                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 814                 } else {
 815                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 816                         mem_cfg = 0;
 817                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 818                 }
 819         } else {
 820                 mem_cfg = 1;
 821                 buffer_alloc = 0;
 822         }
 823
 824         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 825         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 826         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 827
 828         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 829         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 830         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 831
 832         for (i = 0; i < adev->usec_timeout; i++) {
 833                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 834                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 835                         break;
 836                 udelay(1);
 837         }
 838
 839         if (amdgpu_crtc->base.enabled && mode) {
 840                 switch (mem_cfg) {
 841                 case 0:
 842                 default:
 843                         return 4096 * 2;
 844                 case 1:
 845                         return 1920 * 2;
 846                 case 2:
 847                         return 2560 * 2;
 848                 }
 849         }
 850
 851         /* controller not enabled, so no lb used */
 852         return 0;
 853 }
 854
 855 /**
 856  * cik_get_number_of_dram_channels - get the number of dram channels
 857  *
 858  * @adev: amdgpu_device pointer
 859  *
 860  * Look up the number of video ram channels (CIK).
 861  * Used for display watermark bandwidth calculations
 862  * Returns the number of dram channels
 863  */
 864 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 865 {
 866         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 867
 868         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 869         case 0:
 870         default:
 871                 return 1;
 872         case 1:
 873                 return 2;
 874         case 2:
 875                 return 4;
 876         case 3:
 877                 return 8;
 878         case 4:
 879                 return 3;
 880         case 5:
 881                 return 6;
 882         case 6:
 883                 return 10;
 884         case 7:
 885                 return 12;
 886         case 8:
 887                 return 16;
 888         }
 889 }
 890
 891 struct dce10_wm_params {
 892         u32 dram_channels; /* number of dram channels */
 893         u32 yclk;          /* bandwidth per dram data pin in kHz */
 894         u32 sclk;          /* engine clock in kHz */
 895         u32 disp_clk;      /* display clock in kHz */
 896         u32 src_width;     /* viewport width */
 897         u32 active_time;   /* active display time in ns */
 898         u32 blank_time;    /* blank time in ns */
 899         bool interlaced;    /* mode is interlaced */
 900         fixed20_12 vsc;    /* vertical scale ratio */
 901         u32 num_heads;     /* number of active crtcs */
 902         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 903         u32 lb_size;       /* line buffer allocated to pipe */
 904         u32 vtaps;         /* vertical scaler taps */
 905 };
 906
 907 /**
 908  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 909  *
 910  * @wm: watermark calculation data
 911  *
 912  * Calculate the raw dram bandwidth (CIK).
 913  * Used for display watermark bandwidth calculations
 914  * Returns the dram bandwidth in MBytes/s
 915  */
 916 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 917 {
 918         /* Calculate raw DRAM Bandwidth */
 919         fixed20_12 dram_efficiency; /* 0.7 */
 920         fixed20_12 yclk, dram_channels, bandwidth;
 921         fixed20_12 a;
 922
 923         a.full = dfixed_const(1000);
 924         yclk.full = dfixed_const(wm->yclk);
 925         yclk.full = dfixed_div(yclk, a);
 926         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 927         a.full = dfixed_const(10);
 928         dram_efficiency.full = dfixed_const(7);
 929         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 930         bandwidth.full = dfixed_mul(dram_channels, yclk);
 931         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 932
 933         return dfixed_trunc(bandwidth);
 934 }
 935
 936 /**
 937  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 938  *
 939  * @wm: watermark calculation data
 940  *
 941  * Calculate the dram bandwidth used for display (CIK).
 942  * Used for display watermark bandwidth calculations
 943  * Returns the dram bandwidth for display in MBytes/s
 944  */
 945 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 946 {
 947         /* Calculate DRAM Bandwidth and the part allocated to display. */
 948         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 949         fixed20_12 yclk, dram_channels, bandwidth;
 950         fixed20_12 a;
 951
 952         a.full = dfixed_const(1000);
 953         yclk.full = dfixed_const(wm->yclk);
 954         yclk.full = dfixed_div(yclk, a);
 955         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 956         a.full = dfixed_const(10);
 957         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 958         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 959         bandwidth.full = dfixed_mul(dram_channels, yclk);
 960         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 961
 962         return dfixed_trunc(bandwidth);
 963 }
 964
 965 /**
 966  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 967  *
 968  * @wm: watermark calculation data
 969  *
 970  * Calculate the data return bandwidth used for display (CIK).
 971  * Used for display watermark bandwidth calculations
 972  * Returns the data return bandwidth in MBytes/s
 973  */
 974 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 975 {
 976         /* Calculate the display Data return Bandwidth */
 977         fixed20_12 return_efficiency; /* 0.8 */
 978         fixed20_12 sclk, bandwidth;
 979         fixed20_12 a;
 980
 981         a.full = dfixed_const(1000);
 982         sclk.full = dfixed_const(wm->sclk);
 983         sclk.full = dfixed_div(sclk, a);
 984         a.full = dfixed_const(10);
 985         return_efficiency.full = dfixed_const(8);
 986         return_efficiency.full = dfixed_div(return_efficiency, a);
 987         a.full = dfixed_const(32);
 988         bandwidth.full = dfixed_mul(a, sclk);
 989         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 990
 991         return dfixed_trunc(bandwidth);
 992 }
 993
 994 /**
 995  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 996  *
 997  * @wm: watermark calculation data
 998  *
 999  * Calculate the dmif bandwidth used for display (CIK).
1000  * Used for display watermark bandwidth calculations
1001  * Returns the dmif bandwidth in MBytes/s
1002  */
1003 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1004 {
1005         /* Calculate the DMIF Request Bandwidth */
1006         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1007         fixed20_12 disp_clk, bandwidth;
1008         fixed20_12 a, b;
1009
1010         a.full = dfixed_const(1000);
1011         disp_clk.full = dfixed_const(wm->disp_clk);
1012         disp_clk.full = dfixed_div(disp_clk, a);
1013         a.full = dfixed_const(32);
1014         b.full = dfixed_mul(a, disp_clk);
1015
1016         a.full = dfixed_const(10);
1017         disp_clk_request_efficiency.full = dfixed_const(8);
1018         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1019
1020         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1021
1022         return dfixed_trunc(bandwidth);
1023 }
1024
1025 /**
1026  * dce_v11_0_available_bandwidth - get the min available bandwidth
1027  *
1028  * @wm: watermark calculation data
1029  *
1030  * Calculate the min available bandwidth used for display (CIK).
1031  * Used for display watermark bandwidth calculations
1032  * Returns the min available bandwidth in MBytes/s
1033  */
1034 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1035 {
1036         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1037         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1038         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1039         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1040
1041         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1042 }
1043
1044 /**
1045  * dce_v11_0_average_bandwidth - get the average available bandwidth
1046  *
1047  * @wm: watermark calculation data
1048  *
1049  * Calculate the average available bandwidth used for display (CIK).
1050  * Used for display watermark bandwidth calculations
1051  * Returns the average available bandwidth in MBytes/s
1052  */
1053 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1054 {
1055         /* Calculate the display mode Average Bandwidth
1056          * DisplayMode should contain the source and destination dimensions,
1057          * timing, etc.
1058          */
1059         fixed20_12 bpp;
1060         fixed20_12 line_time;
1061         fixed20_12 src_width;
1062         fixed20_12 bandwidth;
1063         fixed20_12 a;
1064
1065         a.full = dfixed_const(1000);
1066         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1067         line_time.full = dfixed_div(line_time, a);
1068         bpp.full = dfixed_const(wm->bytes_per_pixel);
1069         src_width.full = dfixed_const(wm->src_width);
1070         bandwidth.full = dfixed_mul(src_width, bpp);
1071         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1072         bandwidth.full = dfixed_div(bandwidth, line_time);
1073
1074         return dfixed_trunc(bandwidth);
1075 }
1076
1077 /**
1078  * dce_v11_0_latency_watermark - get the latency watermark
1079  *
1080  * @wm: watermark calculation data
1081  *
1082  * Calculate the latency watermark (CIK).
1083  * Used for display watermark bandwidth calculations
1084  * Returns the latency watermark in ns
1085  */
1086 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1087 {
1088         /* First calculate the latency in ns */
1089         u32 mc_latency = 2000; /* 2000 ns. */
1090         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1091         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1092         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1093         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1094         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1095                 (wm->num_heads * cursor_line_pair_return_time);
1096         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1097         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1098         u32 tmp, dmif_size = 12288;
1099         fixed20_12 a, b, c;
1100
1101         if (wm->num_heads == 0)
1102                 return 0;
1103
1104         a.full = dfixed_const(2);
1105         b.full = dfixed_const(1);
1106         if ((wm->vsc.full > a.full) ||
1107             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1108             (wm->vtaps >= 5) ||
1109             ((wm->vsc.full >= a.full) && wm->interlaced))
1110                 max_src_lines_per_dst_line = 4;
1111         else
1112                 max_src_lines_per_dst_line = 2;
1113
1114         a.full = dfixed_const(available_bandwidth);
1115         b.full = dfixed_const(wm->num_heads);
1116         a.full = dfixed_div(a, b);
1117         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1118         tmp = min(dfixed_trunc(a), tmp);
1119
1120         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1121
1122         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1123         b.full = dfixed_const(1000);
1124         c.full = dfixed_const(lb_fill_bw);
1125         b.full = dfixed_div(c, b);
1126         a.full = dfixed_div(a, b);
1127         line_fill_time = dfixed_trunc(a);
1128
1129         if (line_fill_time < wm->active_time)
1130                 return latency;
1131         else
1132                 return latency + (line_fill_time - wm->active_time);
1133
1134 }
1135
1136 /**
1137  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1138  * average and available dram bandwidth
1139  *
1140  * @wm: watermark calculation data
1141  *
1142  * Check if the display average bandwidth fits in the display
1143  * dram bandwidth (CIK).
1144  * Used for display watermark bandwidth calculations
1145  * Returns true if the display fits, false if not.
1146  */
1147 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1148 {
1149         if (dce_v11_0_average_bandwidth(wm) <=
1150             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1151                 return true;
1152         else
1153                 return false;
1154 }
1155
1156 /**
1157  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1158  * average and available bandwidth
1159  *
1160  * @wm: watermark calculation data
1161  *
1162  * Check if the display average bandwidth fits in the display
1163  * available bandwidth (CIK).
1164  * Used for display watermark bandwidth calculations
1165  * Returns true if the display fits, false if not.
1166  */
1167 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1168 {
1169         if (dce_v11_0_average_bandwidth(wm) <=
1170             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1171                 return true;
1172         else
1173                 return false;
1174 }
1175
1176 /**
1177  * dce_v11_0_check_latency_hiding - check latency hiding
1178  *
1179  * @wm: watermark calculation data
1180  *
1181  * Check latency hiding (CIK).
1182  * Used for display watermark bandwidth calculations
1183  * Returns true if the display fits, false if not.
1184  */
1185 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1186 {
1187         u32 lb_partitions = wm->lb_size / wm->src_width;
1188         u32 line_time = wm->active_time + wm->blank_time;
1189         u32 latency_tolerant_lines;
1190         u32 latency_hiding;
1191         fixed20_12 a;
1192
1193         a.full = dfixed_const(1);
1194         if (wm->vsc.full > a.full)
1195                 latency_tolerant_lines = 1;
1196         else {
1197                 if (lb_partitions <= (wm->vtaps + 1))
1198                         latency_tolerant_lines = 1;
1199                 else
1200                         latency_tolerant_lines = 2;
1201         }
1202
1203         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1204
1205         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1206                 return true;
1207         else
1208                 return false;
1209 }
1210
1211 /**
1212  * dce_v11_0_program_watermarks - program display watermarks
1213  *
1214  * @adev: amdgpu_device pointer
1215  * @amdgpu_crtc: the selected display controller
1216  * @lb_size: line buffer size
1217  * @num_heads: number of display controllers in use
1218  *
1219  * Calculate and program the display watermarks for the
1220  * selected display controller (CIK).
1221  */
1222 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1223                                         struct amdgpu_crtc *amdgpu_crtc,
1224                                         u32 lb_size, u32 num_heads)
1225 {
1226         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1227         struct dce10_wm_params wm_low, wm_high;
1228         u32 active_time;
1229         u32 line_time = 0;
1230         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1231         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1232
1233         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1234                 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1235                 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1236
1237                 /* watermark for high clocks */
1238                 if (adev->pm.dpm_enabled) {
1239                         wm_high.yclk =
1240                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1241                         wm_high.sclk =
1242                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1243                 } else {
1244                         wm_high.yclk = adev->pm.current_mclk * 10;
1245                         wm_high.sclk = adev->pm.current_sclk * 10;
1246                 }
1247
1248                 wm_high.disp_clk = mode->clock;
1249                 wm_high.src_width = mode->crtc_hdisplay;
1250                 wm_high.active_time = active_time;
1251                 wm_high.blank_time = line_time - wm_high.active_time;
1252                 wm_high.interlaced = false;
1253                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1254                         wm_high.interlaced = true;
1255                 wm_high.vsc = amdgpu_crtc->vsc;
1256                 wm_high.vtaps = 1;
1257                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1258                         wm_high.vtaps = 2;
1259                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1260                 wm_high.lb_size = lb_size;
1261                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1262                 wm_high.num_heads = num_heads;
1263
1264                 /* set for high clocks */
1265                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1266
1267                 /* possibly force display priority to high */
1268                 /* should really do this at mode validation time... */
1269                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1270                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1271                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1272                     (adev->mode_info.disp_priority == 2)) {
1273                         DRM_DEBUG_KMS("force priority to high\n");
1274                 }
1275
1276                 /* watermark for low clocks */
1277                 if (adev->pm.dpm_enabled) {
1278                         wm_low.yclk =
1279                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1280                         wm_low.sclk =
1281                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1282                 } else {
1283                         wm_low.yclk = adev->pm.current_mclk * 10;
1284                         wm_low.sclk = adev->pm.current_sclk * 10;
1285                 }
1286
1287                 wm_low.disp_clk = mode->clock;
1288                 wm_low.src_width = mode->crtc_hdisplay;
1289                 wm_low.active_time = active_time;
1290                 wm_low.blank_time = line_time - wm_low.active_time;
1291                 wm_low.interlaced = false;
1292                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1293                         wm_low.interlaced = true;
1294                 wm_low.vsc = amdgpu_crtc->vsc;
1295                 wm_low.vtaps = 1;
1296                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1297                         wm_low.vtaps = 2;
1298                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1299                 wm_low.lb_size = lb_size;
1300                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1301                 wm_low.num_heads = num_heads;
1302
1303                 /* set for low clocks */
1304                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1305
1306                 /* possibly force display priority to high */
1307                 /* should really do this at mode validation time... */
1308                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1309                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1310                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1311                     (adev->mode_info.disp_priority == 2)) {
1312                         DRM_DEBUG_KMS("force priority to high\n");
1313                 }
1314                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1315         }
1316
1317         /* select wm A */
1318         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1319         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1320         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1321         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1322         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1323         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1324         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1325         /* select wm B */
1326         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1327         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1328         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1329         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1330         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1331         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1332         /* restore original selection */
1333         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1334
1335         /* save values for DPM */
1336         amdgpu_crtc->line_time = line_time;
1337         amdgpu_crtc->wm_high = latency_watermark_a;
1338         amdgpu_crtc->wm_low = latency_watermark_b;
1339         /* Save number of lines the linebuffer leads before the scanout */
1340         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1341 }
1342
1343 /**
1344  * dce_v11_0_bandwidth_update - program display watermarks
1345  *
1346  * @adev: amdgpu_device pointer
1347  *
1348  * Calculate and program the display watermarks and line
1349  * buffer allocation (CIK).
1350  */
1351 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1352 {
1353         struct drm_display_mode *mode = NULL;
1354         u32 num_heads = 0, lb_size;
1355         int i;
1356
1357         amdgpu_update_display_priority(adev);
1358
1359         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1360                 if (adev->mode_info.crtcs[i]->base.enabled)
1361                         num_heads++;
1362         }
1363         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1364                 mode = &adev->mode_info.crtcs[i]->base.mode;
1365                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1366                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1367                                             lb_size, num_heads);
1368         }
1369 }
1370
1371 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1372 {
1373         int i;
1374         u32 offset, tmp;
1375
1376         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1377                 offset = adev->mode_info.audio.pin[i].offset;
1378                 tmp = RREG32_AUDIO_ENDPT(offset,
1379                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1380                 if (((tmp &
1381                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1382                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1383                         adev->mode_info.audio.pin[i].connected = false;
1384                 else
1385                         adev->mode_info.audio.pin[i].connected = true;
1386         }
1387 }
1388
1389 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1390 {
1391         int i;
1392
1393         dce_v11_0_audio_get_connected_pins(adev);
1394
1395         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1396                 if (adev->mode_info.audio.pin[i].connected)
1397                         return &adev->mode_info.audio.pin[i];
1398         }
1399         DRM_ERROR("No connected audio pins found!\n");
1400         return NULL;
1401 }
1402
1403 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1404 {
1405         struct amdgpu_device *adev = encoder->dev->dev_private;
1406         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1407         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1408         u32 tmp;
1409
1410         if (!dig || !dig->afmt || !dig->afmt->pin)
1411                 return;
1412
1413         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1414         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1415         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1416 }
1417
1418 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1419                                                 struct drm_display_mode *mode)
1420 {
1421         struct amdgpu_device *adev = encoder->dev->dev_private;
1422         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1423         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1424         struct drm_connector *connector;
1425         struct amdgpu_connector *amdgpu_connector = NULL;
1426         u32 tmp;
1427         int interlace = 0;
1428
1429         if (!dig || !dig->afmt || !dig->afmt->pin)
1430                 return;
1431
1432         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1433                 if (connector->encoder == encoder) {
1434                         amdgpu_connector = to_amdgpu_connector(connector);
1435                         break;
1436                 }
1437         }
1438
1439         if (!amdgpu_connector) {
1440                 DRM_ERROR("Couldn't find encoder's connector\n");
1441                 return;
1442         }
1443
1444         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1445                 interlace = 1;
1446         if (connector->latency_present[interlace]) {
1447                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1448                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1449                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1450                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1451         } else {
1452                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1453                                     VIDEO_LIPSYNC, 0);
1454                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1455                                     AUDIO_LIPSYNC, 0);
1456         }
1457         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1458                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1459 }
1460
1461 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1462 {
1463         struct amdgpu_device *adev = encoder->dev->dev_private;
1464         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1465         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1466         struct drm_connector *connector;
1467         struct amdgpu_connector *amdgpu_connector = NULL;
1468         u32 tmp;
1469         u8 *sadb = NULL;
1470         int sad_count;
1471
1472         if (!dig || !dig->afmt || !dig->afmt->pin)
1473                 return;
1474
1475         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1476                 if (connector->encoder == encoder) {
1477                         amdgpu_connector = to_amdgpu_connector(connector);
1478                         break;
1479                 }
1480         }
1481
1482         if (!amdgpu_connector) {
1483                 DRM_ERROR("Couldn't find encoder's connector\n");
1484                 return;
1485         }
1486
1487         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1488         if (sad_count < 0) {
1489                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1490                 sad_count = 0;
1491         }
1492
1493         /* program the speaker allocation */
1494         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1495                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1496         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1497                             DP_CONNECTION, 0);
1498         /* set HDMI mode */
1499         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1500                             HDMI_CONNECTION, 1);
1501         if (sad_count)
1502                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1503                                     SPEAKER_ALLOCATION, sadb[0]);
1504         else
1505                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1506                                     SPEAKER_ALLOCATION, 5); /* stereo */
1507         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1508                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1509
1510         kfree(sadb);
1511 }
1512
1513 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1514 {
1515         struct amdgpu_device *adev = encoder->dev->dev_private;
1516         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1517         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1518         struct drm_connector *connector;
1519         struct amdgpu_connector *amdgpu_connector = NULL;
1520         struct cea_sad *sads;
1521         int i, sad_count;
1522
1523         static const u16 eld_reg_to_type[][2] = {
1524                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1525                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1526                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1527                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1528                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1529                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1530                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1531                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1532                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1533                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1534                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1535                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1536         };
1537
1538         if (!dig || !dig->afmt || !dig->afmt->pin)
1539                 return;
1540
1541         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1542                 if (connector->encoder == encoder) {
1543                         amdgpu_connector = to_amdgpu_connector(connector);
1544                         break;
1545                 }
1546         }
1547
1548         if (!amdgpu_connector) {
1549                 DRM_ERROR("Couldn't find encoder's connector\n");
1550                 return;
1551         }
1552
1553         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1554         if (sad_count <= 0) {
1555                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1556                 return;
1557         }
1558         BUG_ON(!sads);
1559
1560         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1561                 u32 tmp = 0;
1562                 u8 stereo_freqs = 0;
1563                 int max_channels = -1;
1564                 int j;
1565
1566                 for (j = 0; j < sad_count; j++) {
1567                         struct cea_sad *sad = &sads[j];
1568
1569                         if (sad->format == eld_reg_to_type[i][1]) {
1570                                 if (sad->channels > max_channels) {
1571                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1572                                                             MAX_CHANNELS, sad->channels);
1573                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1574                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1575                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1576                                                             SUPPORTED_FREQUENCIES, sad->freq);
1577                                         max_channels = sad->channels;
1578                                 }
1579
1580                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1581                                         stereo_freqs |= sad->freq;
1582                                 else
1583                                         break;
1584                         }
1585                 }
1586
1587                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1588                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1589                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1590         }
1591
1592         kfree(sads);
1593 }
1594
1595 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1596                                   struct amdgpu_audio_pin *pin,
1597                                   bool enable)
1598 {
1599         if (!pin)
1600                 return;
1601
1602         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1603                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1604 }
1605
1606 static const u32 pin_offsets[] =
1607 {
1608         AUD0_REGISTER_OFFSET,
1609         AUD1_REGISTER_OFFSET,
1610         AUD2_REGISTER_OFFSET,
1611         AUD3_REGISTER_OFFSET,
1612         AUD4_REGISTER_OFFSET,
1613         AUD5_REGISTER_OFFSET,
1614         AUD6_REGISTER_OFFSET,
1615 };
1616
1617 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1618 {
1619         int i;
1620
1621         if (!amdgpu_audio)
1622                 return 0;
1623
1624         adev->mode_info.audio.enabled = true;
1625
1626         adev->mode_info.audio.num_pins = 7;
1627
1628         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1629                 adev->mode_info.audio.pin[i].channels = -1;
1630                 adev->mode_info.audio.pin[i].rate = -1;
1631                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1632                 adev->mode_info.audio.pin[i].status_bits = 0;
1633                 adev->mode_info.audio.pin[i].category_code = 0;
1634                 adev->mode_info.audio.pin[i].connected = false;
1635                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1636                 adev->mode_info.audio.pin[i].id = i;
1637                 /* disable audio.  it will be set up later */
1638                 /* XXX remove once we switch to ip funcs */
1639                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1640         }
1641
1642         return 0;
1643 }
1644
1645 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1646 {
1647         int i;
1648
1649         if (!adev->mode_info.audio.enabled)
1650                 return;
1651
1652         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1653                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1654
1655         adev->mode_info.audio.enabled = false;
1656 }
1657
1658 /*
1659  * update the N and CTS parameters for a given pixel clock rate
1660  */
1661 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1662 {
1663         struct drm_device *dev = encoder->dev;
1664         struct amdgpu_device *adev = dev->dev_private;
1665         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1666         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1667         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1668         u32 tmp;
1669
1670         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1671         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1672         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1673         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1674         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1675         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1676
1677         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1678         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1679         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1680         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1681         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1682         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1683
1684         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1685         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1686         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1687         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1688         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1689         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1690
1691 }
1692
1693 /*
1694  * build a HDMI Video Info Frame
1695  */
1696 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1697                                                void *buffer, size_t size)
1698 {
1699         struct drm_device *dev = encoder->dev;
1700         struct amdgpu_device *adev = dev->dev_private;
1701         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1702         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1703         uint8_t *frame = buffer + 3;
1704         uint8_t *header = buffer;
1705
1706         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1707                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1708         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1709                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1710         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1711                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1712         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1713                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1714 }
1715
1716 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1717 {
1718         struct drm_device *dev = encoder->dev;
1719         struct amdgpu_device *adev = dev->dev_private;
1720         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1721         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1722         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1723         u32 dto_phase = 24 * 1000;
1724         u32 dto_modulo = clock;
1725         u32 tmp;
1726
1727         if (!dig || !dig->afmt)
1728                 return;
1729
1730         /* XXX two dtos; generally use dto0 for hdmi */
1731         /* Express [24MHz / target pixel clock] as an exact rational
1732          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1733          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1734          */
1735         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1736         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1737                             amdgpu_crtc->crtc_id);
1738         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1739         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1740         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1741 }
1742
1743 /*
1744  * update the info frames with the data from the current display mode
1745  */
1746 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1747                                   struct drm_display_mode *mode)
1748 {
1749         struct drm_device *dev = encoder->dev;
1750         struct amdgpu_device *adev = dev->dev_private;
1751         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1752         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1753         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1754         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1755         struct hdmi_avi_infoframe frame;
1756         ssize_t err;
1757         u32 tmp;
1758         int bpc = 8;
1759
1760         if (!dig || !dig->afmt)
1761                 return;
1762
1763         /* Silent, r600_hdmi_enable will raise WARN for us */
1764         if (!dig->afmt->enabled)
1765                 return;
1766
1767         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1768         if (encoder->crtc) {
1769                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1770                 bpc = amdgpu_crtc->bpc;
1771         }
1772
1773         /* disable audio prior to setting up hw */
1774         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1775         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1776
1777         dce_v11_0_audio_set_dto(encoder, mode->clock);
1778
1779         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1780         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1781         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1782
1783         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1784
1785         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1786         switch (bpc) {
1787         case 0:
1788         case 6:
1789         case 8:
1790         case 16:
1791         default:
1792                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1793                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1794                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1795                           connector->name, bpc);
1796                 break;
1797         case 10:
1798                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1799                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1800                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1801                           connector->name);
1802                 break;
1803         case 12:
1804                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1805                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1806                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1807                           connector->name);
1808                 break;
1809         }
1810         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1811
1812         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1813         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1814         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1815         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1816         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1817
1818         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1819         /* enable audio info frames (frames won't be set until audio is enabled) */
1820         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1821         /* required for audio info values to be updated */
1822         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1823         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1824
1825         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1826         /* required for audio info values to be updated */
1827         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1828         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1829
1830         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1831         /* anything other than 0 */
1832         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1833         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1834
1835         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1836
1837         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1838         /* set the default audio delay */
1839         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1840         /* should be suffient for all audio modes and small enough for all hblanks */
1841         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1842         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1843
1844         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1845         /* allow 60958 channel status fields to be updated */
1846         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1847         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1848
1849         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1850         if (bpc > 8)
1851                 /* clear SW CTS value */
1852                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1853         else
1854                 /* select SW CTS value */
1855                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1856         /* allow hw to sent ACR packets when required */
1857         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1858         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1859
1860         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1861
1862         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1863         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1864         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1865
1866         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1867         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1868         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1869
1870         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1871         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1872         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1873         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1874         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1875         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1876         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1877         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1878
1879         dce_v11_0_audio_write_speaker_allocation(encoder);
1880
1881         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1882                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1883
1884         dce_v11_0_afmt_audio_select_pin(encoder);
1885         dce_v11_0_audio_write_sad_regs(encoder);
1886         dce_v11_0_audio_write_latency_fields(encoder, mode);
1887
1888         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1889         if (err < 0) {
1890                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1891                 return;
1892         }
1893
1894         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1895         if (err < 0) {
1896                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1897                 return;
1898         }
1899
1900         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1901
1902         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1903         /* enable AVI info frames */
1904         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1905         /* required for audio info values to be updated */
1906         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1907         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1908
1909         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1910         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1911         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1912
1913         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1914         /* send audio packets */
1915         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1916         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1917
1918         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1919         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1920         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1921         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1922
1923         /* enable audio after to setting up hw */
1924         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1925 }
1926
1927 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1928 {
1929         struct drm_device *dev = encoder->dev;
1930         struct amdgpu_device *adev = dev->dev_private;
1931         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1932         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1933
1934         if (!dig || !dig->afmt)
1935                 return;
1936
1937         /* Silent, r600_hdmi_enable will raise WARN for us */
1938         if (enable && dig->afmt->enabled)
1939                 return;
1940         if (!enable && !dig->afmt->enabled)
1941                 return;
1942
1943         if (!enable && dig->afmt->pin) {
1944                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1945                 dig->afmt->pin = NULL;
1946         }
1947
1948         dig->afmt->enabled = enable;
1949
1950         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1951                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1952 }
1953
1954 static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
1955 {
1956         int i;
1957
1958         for (i = 0; i < adev->mode_info.num_dig; i++)
1959                 adev->mode_info.afmt[i] = NULL;
1960
1961         /* DCE11 has audio blocks tied to DIG encoders */
1962         for (i = 0; i < adev->mode_info.num_dig; i++) {
1963                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1964                 if (adev->mode_info.afmt[i]) {
1965                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1966                         adev->mode_info.afmt[i]->id = i;
1967                 }
1968         }
1969 }
1970
1971 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1972 {
1973         int i;
1974
1975         for (i = 0; i < adev->mode_info.num_dig; i++) {
1976                 kfree(adev->mode_info.afmt[i]);
1977                 adev->mode_info.afmt[i] = NULL;
1978         }
1979 }
1980
1981 static const u32 vga_control_regs[6] =
1982 {
1983         mmD1VGA_CONTROL,
1984         mmD2VGA_CONTROL,
1985         mmD3VGA_CONTROL,
1986         mmD4VGA_CONTROL,
1987         mmD5VGA_CONTROL,
1988         mmD6VGA_CONTROL,
1989 };
1990
1991 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1992 {
1993         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1994         struct drm_device *dev = crtc->dev;
1995         struct amdgpu_device *adev = dev->dev_private;
1996         u32 vga_control;
1997
1998         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1999         if (enable)
2000                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2001         else
2002                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2003 }
2004
2005 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2006 {
2007         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2008         struct drm_device *dev = crtc->dev;
2009         struct amdgpu_device *adev = dev->dev_private;
2010
2011         if (enable)
2012                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2013         else
2014                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2015 }
2016
2017 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2018                                      struct drm_framebuffer *fb,
2019                                      int x, int y, int atomic)
2020 {
2021         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2022         struct drm_device *dev = crtc->dev;
2023         struct amdgpu_device *adev = dev->dev_private;
2024         struct amdgpu_framebuffer *amdgpu_fb;
2025         struct drm_framebuffer *target_fb;
2026         struct drm_gem_object *obj;
2027         struct amdgpu_bo *rbo;
2028         uint64_t fb_location, tiling_flags;
2029         uint32_t fb_format, fb_pitch_pixels;
2030         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2031         u32 pipe_config;
2032         u32 tmp, viewport_w, viewport_h;
2033         int r;
2034         bool bypass_lut = false;
2035
2036         /* no fb bound */
2037         if (!atomic && !crtc->primary->fb) {
2038                 DRM_DEBUG_KMS("No FB bound\n");
2039                 return 0;
2040         }
2041
2042         if (atomic) {
2043                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2044                 target_fb = fb;
2045         }
2046         else {
2047                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2048                 target_fb = crtc->primary->fb;
2049         }
2050
2051         /* If atomic, assume fb object is pinned & idle & fenced and
2052          * just update base pointers
2053          */
2054         obj = amdgpu_fb->obj;
2055         rbo = gem_to_amdgpu_bo(obj);
2056         r = amdgpu_bo_reserve(rbo, false);
2057         if (unlikely(r != 0))
2058                 return r;
2059
2060         if (atomic)
2061                 fb_location = amdgpu_bo_gpu_offset(rbo);
2062         else {
2063                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2064                 if (unlikely(r != 0)) {
2065                         amdgpu_bo_unreserve(rbo);
2066                         return -EINVAL;
2067                 }
2068         }
2069
2070         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2071         amdgpu_bo_unreserve(rbo);
2072
2073         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2074
2075         switch (target_fb->pixel_format) {
2076         case DRM_FORMAT_C8:
2077                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2078                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2079                 break;
2080         case DRM_FORMAT_XRGB4444:
2081         case DRM_FORMAT_ARGB4444:
2082                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2083                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2084 #ifdef __BIG_ENDIAN
2085                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2086                                         ENDIAN_8IN16);
2087 #endif
2088                 break;
2089         case DRM_FORMAT_XRGB1555:
2090         case DRM_FORMAT_ARGB1555:
2091                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2092                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2093 #ifdef __BIG_ENDIAN
2094                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2095                                         ENDIAN_8IN16);
2096 #endif
2097                 break;
2098         case DRM_FORMAT_BGRX5551:
2099         case DRM_FORMAT_BGRA5551:
2100                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2101                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2102 #ifdef __BIG_ENDIAN
2103                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2104                                         ENDIAN_8IN16);
2105 #endif
2106                 break;
2107         case DRM_FORMAT_RGB565:
2108                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2109                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2110 #ifdef __BIG_ENDIAN
2111                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2112                                         ENDIAN_8IN16);
2113 #endif
2114                 break;
2115         case DRM_FORMAT_XRGB8888:
2116         case DRM_FORMAT_ARGB8888:
2117                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2118                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2119 #ifdef __BIG_ENDIAN
2120                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2121                                         ENDIAN_8IN32);
2122 #endif
2123                 break;
2124         case DRM_FORMAT_XRGB2101010:
2125         case DRM_FORMAT_ARGB2101010:
2126                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2127                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2128 #ifdef __BIG_ENDIAN
2129                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2130                                         ENDIAN_8IN32);
2131 #endif
2132                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2133                 bypass_lut = true;
2134                 break;
2135         case DRM_FORMAT_BGRX1010102:
2136         case DRM_FORMAT_BGRA1010102:
2137                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2138                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2139 #ifdef __BIG_ENDIAN
2140                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2141                                         ENDIAN_8IN32);
2142 #endif
2143                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2144                 bypass_lut = true;
2145                 break;
2146         default:
2147                 DRM_ERROR("Unsupported screen format %s\n",
2148                         drm_get_format_name(target_fb->pixel_format));
2149                 return -EINVAL;
2150         }
2151
2152         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2153                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2154
2155                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2156                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2157                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2158                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2159                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2160
2161                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2162                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2163                                           ARRAY_2D_TILED_THIN1);
2164                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2165                                           tile_split);
2166                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2167                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2168                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2169                                           mtaspect);
2170                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2171                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2172         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2173                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2174                                           ARRAY_1D_TILED_THIN1);
2175         }
2176
2177         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2178                                   pipe_config);
2179
2180         dce_v11_0_vga_enable(crtc, false);
2181
2182         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2183                upper_32_bits(fb_location));
2184         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2185                upper_32_bits(fb_location));
2186         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2187                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2188         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2189                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2190         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2191         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2192
2193         /*
2194          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2195          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2196          * retain the full precision throughout the pipeline.
2197          */
2198         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2199         if (bypass_lut)
2200                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2201         else
2202                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2203         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2204
2205         if (bypass_lut)
2206                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2207
2208         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2209         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2210         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2211         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2212         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2213         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2214
2215         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2216         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2217
2218         dce_v11_0_grph_enable(crtc, true);
2219
2220         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2221                target_fb->height);
2222
2223         x &= ~3;
2224         y &= ~1;
2225         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2226                (x << 16) | y);
2227         viewport_w = crtc->mode.hdisplay;
2228         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2229         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2230                (viewport_w << 16) | viewport_h);
2231
2232         /* pageflip setup */
2233         /* make sure flip is at vb rather than hb */
2234         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2235         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2236                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2237         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2238
2239         /* set pageflip to happen only at start of vblank interval (front porch) */
2240         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2241
2242         if (!atomic && fb && fb != crtc->primary->fb) {
2243                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2244                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2245                 r = amdgpu_bo_reserve(rbo, false);
2246                 if (unlikely(r != 0))
2247                         return r;
2248                 amdgpu_bo_unpin(rbo);
2249                 amdgpu_bo_unreserve(rbo);
2250         }
2251
2252         /* Bytes per pixel may have changed */
2253         dce_v11_0_bandwidth_update(adev);
2254
2255         return 0;
2256 }
2257
2258 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2259                                      struct drm_display_mode *mode)
2260 {
2261         struct drm_device *dev = crtc->dev;
2262         struct amdgpu_device *adev = dev->dev_private;
2263         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2264         u32 tmp;
2265
2266         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2267         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2268                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2269         else
2270                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2271         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2272 }
2273
2274 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2275 {
2276         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2277         struct drm_device *dev = crtc->dev;
2278         struct amdgpu_device *adev = dev->dev_private;
2279         int i;
2280         u32 tmp;
2281
2282         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2283
2284         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2285         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2286         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2287
2288         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2289         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2290         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2291
2292         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2293         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2294         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2295
2296         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2297
2298         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2299         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2300         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2301
2302         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2303         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2304         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2305
2306         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2307         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2308
2309         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2310         for (i = 0; i < 256; i++) {
2311                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2312                        (amdgpu_crtc->lut_r[i] << 20) |
2313                        (amdgpu_crtc->lut_g[i] << 10) |
2314                        (amdgpu_crtc->lut_b[i] << 0));
2315         }
2316
2317         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2318         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2319         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2320         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2321         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2322
2323         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2324         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2325         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2326
2327         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2328         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2329         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2330
2331         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2332         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2333         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2334
2335         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2336         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2337         /* XXX this only needs to be programmed once per crtc at startup,
2338          * not sure where the best place for it is
2339          */
2340         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2341         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2342         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2343 }
2344
2345 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2346 {
2347         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2348         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2349
2350         switch (amdgpu_encoder->encoder_id) {
2351         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2352                 if (dig->linkb)
2353                         return 1;
2354                 else
2355                         return 0;
2356                 break;
2357         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2358                 if (dig->linkb)
2359                         return 3;
2360                 else
2361                         return 2;
2362                 break;
2363         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2364                 if (dig->linkb)
2365                         return 5;
2366                 else
2367                         return 4;
2368                 break;
2369         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2370                 return 6;
2371                 break;
2372         default:
2373                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2374                 return 0;
2375         }
2376 }
2377
2378 /**
2379  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2380  *
2381  * @crtc: drm crtc
2382  *
2383  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2384  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2385  * monitors a dedicated PPLL must be used.  If a particular board has
2386  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2387  * as there is no need to program the PLL itself.  If we are not able to
2388  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2389  * avoid messing up an existing monitor.
2390  *
2391  * Asic specific PLL information
2392  *
2393  * DCE 10.x
2394  * Tonga
2395  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2396  * CI
2397  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2398  *
2399  */
2400 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2401 {
2402         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2403         struct drm_device *dev = crtc->dev;
2404         struct amdgpu_device *adev = dev->dev_private;
2405         u32 pll_in_use;
2406         int pll;
2407
2408         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2409                 if (adev->clock.dp_extclk)
2410                         /* skip PPLL programming if using ext clock */
2411                         return ATOM_PPLL_INVALID;
2412                 else {
2413                         /* use the same PPLL for all DP monitors */
2414                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2415                         if (pll != ATOM_PPLL_INVALID)
2416                                 return pll;
2417                 }
2418         } else {
2419                 /* use the same PPLL for all monitors with the same clock */
2420                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2421                 if (pll != ATOM_PPLL_INVALID)
2422                         return pll;
2423         }
2424
2425         /* XXX need to determine what plls are available on each DCE11 part */
2426         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2427         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2428                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2429                         return ATOM_PPLL1;
2430                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2431                         return ATOM_PPLL0;
2432                 DRM_ERROR("unable to allocate a PPLL\n");
2433                 return ATOM_PPLL_INVALID;
2434         } else {
2435                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2436                         return ATOM_PPLL2;
2437                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2438                         return ATOM_PPLL1;
2439                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2440                         return ATOM_PPLL0;
2441                 DRM_ERROR("unable to allocate a PPLL\n");
2442                 return ATOM_PPLL_INVALID;
2443         }
2444         return ATOM_PPLL_INVALID;
2445 }
2446
2447 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2448 {
2449         struct amdgpu_device *adev = crtc->dev->dev_private;
2450         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2451         uint32_t cur_lock;
2452
2453         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2454         if (lock)
2455                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2456         else
2457                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2458         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2459 }
2460
2461 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2462 {
2463         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2464         struct amdgpu_device *adev = crtc->dev->dev_private;
2465         u32 tmp;
2466
2467         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2468         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2469         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2470 }
2471
2472 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2473 {
2474         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2475         struct amdgpu_device *adev = crtc->dev->dev_private;
2476         u32 tmp;
2477
2478         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2479                upper_32_bits(amdgpu_crtc->cursor_addr));
2480         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2481                lower_32_bits(amdgpu_crtc->cursor_addr));
2482
2483         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2484         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2485         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2486         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2487 }
2488
2489 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2490                                         int x, int y)
2491 {
2492         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2493         struct amdgpu_device *adev = crtc->dev->dev_private;
2494         int xorigin = 0, yorigin = 0;
2495
2496         /* avivo cursor are offset into the total surface */
2497         x += crtc->x;
2498         y += crtc->y;
2499         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2500
2501         if (x < 0) {
2502                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2503                 x = 0;
2504         }
2505         if (y < 0) {
2506                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2507                 y = 0;
2508         }
2509
2510         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2511         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2512         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2513                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2514
2515         amdgpu_crtc->cursor_x = x;
2516         amdgpu_crtc->cursor_y = y;
2517
2518         return 0;
2519 }
2520
2521 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2522                                       int x, int y)
2523 {
2524         int ret;
2525
2526         dce_v11_0_lock_cursor(crtc, true);
2527         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2528         dce_v11_0_lock_cursor(crtc, false);
2529
2530         return ret;
2531 }
2532
2533 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2534                                       struct drm_file *file_priv,
2535                                       uint32_t handle,
2536                                       uint32_t width,
2537                                       uint32_t height,
2538                                       int32_t hot_x,
2539                                       int32_t hot_y)
2540 {
2541         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2542         struct drm_gem_object *obj;
2543         struct amdgpu_bo *aobj;
2544         int ret;
2545
2546         if (!handle) {
2547                 /* turn off cursor */
2548                 dce_v11_0_hide_cursor(crtc);
2549                 obj = NULL;
2550                 goto unpin;
2551         }
2552
2553         if ((width > amdgpu_crtc->max_cursor_width) ||
2554             (height > amdgpu_crtc->max_cursor_height)) {
2555                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2556                 return -EINVAL;
2557         }
2558
2559         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2560         if (!obj) {
2561                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2562                 return -ENOENT;
2563         }
2564
2565         aobj = gem_to_amdgpu_bo(obj);
2566         ret = amdgpu_bo_reserve(aobj, false);
2567         if (ret != 0) {
2568                 drm_gem_object_unreference_unlocked(obj);
2569                 return ret;
2570         }
2571
2572         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2573         amdgpu_bo_unreserve(aobj);
2574         if (ret) {
2575                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2576                 drm_gem_object_unreference_unlocked(obj);
2577                 return ret;
2578         }
2579
2580         amdgpu_crtc->cursor_width = width;
2581         amdgpu_crtc->cursor_height = height;
2582
2583         dce_v11_0_lock_cursor(crtc, true);
2584
2585         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2586             hot_y != amdgpu_crtc->cursor_hot_y) {
2587                 int x, y;
2588
2589                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2590                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2591
2592                 dce_v11_0_cursor_move_locked(crtc, x, y);
2593
2594                 amdgpu_crtc->cursor_hot_x = hot_x;
2595                 amdgpu_crtc->cursor_hot_y = hot_y;
2596         }
2597
2598         dce_v11_0_show_cursor(crtc);
2599         dce_v11_0_lock_cursor(crtc, false);
2600
2601 unpin:
2602         if (amdgpu_crtc->cursor_bo) {
2603                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2604                 ret = amdgpu_bo_reserve(aobj, false);
2605                 if (likely(ret == 0)) {
2606                         amdgpu_bo_unpin(aobj);
2607                         amdgpu_bo_unreserve(aobj);
2608                 }
2609                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2610         }
2611
2612         amdgpu_crtc->cursor_bo = obj;
2613         return 0;
2614 }
2615
2616 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2617 {
2618         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2619
2620         if (amdgpu_crtc->cursor_bo) {
2621                 dce_v11_0_lock_cursor(crtc, true);
2622
2623                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2624                                              amdgpu_crtc->cursor_y);
2625
2626                 dce_v11_0_show_cursor(crtc);
2627
2628                 dce_v11_0_lock_cursor(crtc, false);
2629         }
2630 }
2631
2632 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2633                                     u16 *blue, uint32_t start, uint32_t size)
2634 {
2635         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2636         int end = (start + size > 256) ? 256 : start + size, i;
2637
2638         /* userspace palettes are always correct as is */
2639         for (i = start; i < end; i++) {
2640                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2641                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2642                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2643         }
2644         dce_v11_0_crtc_load_lut(crtc);
2645 }
2646
2647 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2648 {
2649         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2650
2651         drm_crtc_cleanup(crtc);
2652         destroy_workqueue(amdgpu_crtc->pflip_queue);
2653         kfree(amdgpu_crtc);
2654 }
2655
2656 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2657         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2658         .cursor_move = dce_v11_0_crtc_cursor_move,
2659         .gamma_set = dce_v11_0_crtc_gamma_set,
2660         .set_config = amdgpu_crtc_set_config,
2661         .destroy = dce_v11_0_crtc_destroy,
2662         .page_flip = amdgpu_crtc_page_flip,
2663 };
2664
2665 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2666 {
2667         struct drm_device *dev = crtc->dev;
2668         struct amdgpu_device *adev = dev->dev_private;
2669         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2670         unsigned type;
2671
2672         switch (mode) {
2673         case DRM_MODE_DPMS_ON:
2674                 amdgpu_crtc->enabled = true;
2675                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2676                 dce_v11_0_vga_enable(crtc, true);
2677                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2678                 dce_v11_0_vga_enable(crtc, false);
2679                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2680                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2681                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2682                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2683                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2684                 dce_v11_0_crtc_load_lut(crtc);
2685                 break;
2686         case DRM_MODE_DPMS_STANDBY:
2687         case DRM_MODE_DPMS_SUSPEND:
2688         case DRM_MODE_DPMS_OFF:
2689                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2690                 if (amdgpu_crtc->enabled) {
2691                         dce_v11_0_vga_enable(crtc, true);
2692                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2693                         dce_v11_0_vga_enable(crtc, false);
2694                 }
2695                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2696                 amdgpu_crtc->enabled = false;
2697                 break;
2698         }
2699         /* adjust pm to dpms */
2700         amdgpu_pm_compute_clocks(adev);
2701 }
2702
2703 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2704 {
2705         /* disable crtc pair power gating before programming */
2706         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2707         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2708         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2709 }
2710
2711 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2712 {
2713         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2714         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2715 }
2716
2717 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2718 {
2719         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2720         struct drm_device *dev = crtc->dev;
2721         struct amdgpu_device *adev = dev->dev_private;
2722         struct amdgpu_atom_ss ss;
2723         int i;
2724
2725         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2726         if (crtc->primary->fb) {
2727                 int r;
2728                 struct amdgpu_framebuffer *amdgpu_fb;
2729                 struct amdgpu_bo *rbo;
2730
2731                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2732                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2733                 r = amdgpu_bo_reserve(rbo, false);
2734                 if (unlikely(r))
2735                         DRM_ERROR("failed to reserve rbo before unpin\n");
2736                 else {
2737                         amdgpu_bo_unpin(rbo);
2738                         amdgpu_bo_unreserve(rbo);
2739                 }
2740         }
2741         /* disable the GRPH */
2742         dce_v11_0_grph_enable(crtc, false);
2743
2744         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2745
2746         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2747                 if (adev->mode_info.crtcs[i] &&
2748                     adev->mode_info.crtcs[i]->enabled &&
2749                     i != amdgpu_crtc->crtc_id &&
2750                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2751                         /* one other crtc is using this pll don't turn
2752                          * off the pll
2753                          */
2754                         goto done;
2755                 }
2756         }
2757
2758         switch (amdgpu_crtc->pll_id) {
2759         case ATOM_PPLL0:
2760         case ATOM_PPLL1:
2761         case ATOM_PPLL2:
2762                 /* disable the ppll */
2763                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2764                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2765                 break;
2766         default:
2767                 break;
2768         }
2769 done:
2770         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2771         amdgpu_crtc->adjusted_clock = 0;
2772         amdgpu_crtc->encoder = NULL;
2773         amdgpu_crtc->connector = NULL;
2774 }
2775
2776 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2777                                   struct drm_display_mode *mode,
2778                                   struct drm_display_mode *adjusted_mode,
2779                                   int x, int y, struct drm_framebuffer *old_fb)
2780 {
2781         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2782
2783         if (!amdgpu_crtc->adjusted_clock)
2784                 return -EINVAL;
2785
2786         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2787         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2788         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2789         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2790         amdgpu_atombios_crtc_scaler_setup(crtc);
2791         dce_v11_0_cursor_reset(crtc);
2792         /* update the hw version fpr dpm */
2793         amdgpu_crtc->hw_mode = *adjusted_mode;
2794
2795         return 0;
2796 }
2797
2798 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2799                                      const struct drm_display_mode *mode,
2800                                      struct drm_display_mode *adjusted_mode)
2801 {
2802         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2803         struct drm_device *dev = crtc->dev;
2804         struct drm_encoder *encoder;
2805
2806         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2807         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2808                 if (encoder->crtc == crtc) {
2809                         amdgpu_crtc->encoder = encoder;
2810                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2811                         break;
2812                 }
2813         }
2814         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2815                 amdgpu_crtc->encoder = NULL;
2816                 amdgpu_crtc->connector = NULL;
2817                 return false;
2818         }
2819         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2820                 return false;
2821         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2822                 return false;
2823         /* pick pll */
2824         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2825         /* if we can't get a PPLL for a non-DP encoder, fail */
2826         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2827             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2828                 return false;
2829
2830         return true;
2831 }
2832
2833 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2834                                   struct drm_framebuffer *old_fb)
2835 {
2836         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2837 }
2838
2839 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2840                                          struct drm_framebuffer *fb,
2841                                          int x, int y, enum mode_set_atomic state)
2842 {
2843        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2844 }
2845
2846 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2847         .dpms = dce_v11_0_crtc_dpms,
2848         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2849         .mode_set = dce_v11_0_crtc_mode_set,
2850         .mode_set_base = dce_v11_0_crtc_set_base,
2851         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2852         .prepare = dce_v11_0_crtc_prepare,
2853         .commit = dce_v11_0_crtc_commit,
2854         .load_lut = dce_v11_0_crtc_load_lut,
2855         .disable = dce_v11_0_crtc_disable,
2856 };
2857
2858 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2859 {
2860         struct amdgpu_crtc *amdgpu_crtc;
2861         int i;
2862
2863         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2864                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2865         if (amdgpu_crtc == NULL)
2866                 return -ENOMEM;
2867
2868         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2869
2870         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2871         amdgpu_crtc->crtc_id = index;
2872         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2873         adev->mode_info.crtcs[index] = amdgpu_crtc;
2874
2875         amdgpu_crtc->max_cursor_width = 128;
2876         amdgpu_crtc->max_cursor_height = 128;
2877         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2878         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2879
2880         for (i = 0; i < 256; i++) {
2881                 amdgpu_crtc->lut_r[i] = i << 2;
2882                 amdgpu_crtc->lut_g[i] = i << 2;
2883                 amdgpu_crtc->lut_b[i] = i << 2;
2884         }
2885
2886         switch (amdgpu_crtc->crtc_id) {
2887         case 0:
2888         default:
2889                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2890                 break;
2891         case 1:
2892                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2893                 break;
2894         case 2:
2895                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2896                 break;
2897         case 3:
2898                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2899                 break;
2900         case 4:
2901                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2902                 break;
2903         case 5:
2904                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2905                 break;
2906         }
2907
2908         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2909         amdgpu_crtc->adjusted_clock = 0;
2910         amdgpu_crtc->encoder = NULL;
2911         amdgpu_crtc->connector = NULL;
2912         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2913
2914         return 0;
2915 }
2916
2917 static int dce_v11_0_early_init(void *handle)
2918 {
2919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2920
2921         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2922         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2923
2924         dce_v11_0_set_display_funcs(adev);
2925         dce_v11_0_set_irq_funcs(adev);
2926
2927         switch (adev->asic_type) {
2928         case CHIP_CARRIZO:
2929                 adev->mode_info.num_crtc = 3;
2930                 adev->mode_info.num_hpd = 6;
2931                 adev->mode_info.num_dig = 9;
2932                 break;
2933         case CHIP_STONEY:
2934                 adev->mode_info.num_crtc = 2;
2935                 adev->mode_info.num_hpd = 6;
2936                 adev->mode_info.num_dig = 9;
2937                 break;
2938         default:
2939                 /* FIXME: not supported yet */
2940                 return -EINVAL;
2941         }
2942
2943         return 0;
2944 }
2945
2946 static int dce_v11_0_sw_init(void *handle)
2947 {
2948         int r, i;
2949         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2950
2951         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2952                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2953                 if (r)
2954                 return r;
2955         }
2956
2957         for (i = 8; i < 20; i += 2) {
2958                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2959                 if (r)
2960                         return r;
2961         }
2962
2963         /* HPD hotplug */
2964         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2965         if (r)
2966         return r;
2967
2968         adev->mode_info.mode_config_initialized = true;
2969
2970         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2971
2972         adev->ddev->mode_config.max_width = 16384;
2973         adev->ddev->mode_config.max_height = 16384;
2974
2975         adev->ddev->mode_config.preferred_depth = 24;
2976         adev->ddev->mode_config.prefer_shadow = 1;
2977
2978         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2979
2980         r = amdgpu_modeset_create_props(adev);
2981         if (r)
2982                 return r;
2983
2984         adev->ddev->mode_config.max_width = 16384;
2985         adev->ddev->mode_config.max_height = 16384;
2986
2987         /* allocate crtcs */
2988         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2989                 r = dce_v11_0_crtc_init(adev, i);
2990                 if (r)
2991                         return r;
2992         }
2993
2994         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2995                 amdgpu_print_display_setup(adev->ddev);
2996         else
2997                 return -EINVAL;
2998
2999         /* setup afmt */
3000         dce_v11_0_afmt_init(adev);
3001
3002         r = dce_v11_0_audio_init(adev);
3003         if (r)
3004                 return r;
3005
3006         drm_kms_helper_poll_init(adev->ddev);
3007
3008         return r;
3009 }
3010
3011 static int dce_v11_0_sw_fini(void *handle)
3012 {
3013         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3014
3015         kfree(adev->mode_info.bios_hardcoded_edid);
3016
3017         drm_kms_helper_poll_fini(adev->ddev);
3018
3019         dce_v11_0_audio_fini(adev);
3020
3021         dce_v11_0_afmt_fini(adev);
3022
3023         drm_mode_config_cleanup(adev->ddev);
3024         adev->mode_info.mode_config_initialized = false;
3025
3026         return 0;
3027 }
3028
3029 static int dce_v11_0_hw_init(void *handle)
3030 {
3031         int i;
3032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3033
3034         dce_v11_0_init_golden_registers(adev);
3035
3036         /* init dig PHYs, disp eng pll */
3037         amdgpu_atombios_crtc_powergate_init(adev);
3038         amdgpu_atombios_encoder_init_dig(adev);
3039         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3040
3041         /* initialize hpd */
3042         dce_v11_0_hpd_init(adev);
3043
3044         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3045                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3046         }
3047
3048         dce_v11_0_pageflip_interrupt_init(adev);
3049
3050         return 0;
3051 }
3052
3053 static int dce_v11_0_hw_fini(void *handle)
3054 {
3055         int i;
3056         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3057
3058         dce_v11_0_hpd_fini(adev);
3059
3060         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3061                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3062         }
3063
3064         dce_v11_0_pageflip_interrupt_fini(adev);
3065
3066         return 0;
3067 }
3068
3069 static int dce_v11_0_suspend(void *handle)
3070 {
3071         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3072
3073         amdgpu_atombios_scratch_regs_save(adev);
3074
3075         return dce_v11_0_hw_fini(handle);
3076 }
3077
3078 static int dce_v11_0_resume(void *handle)
3079 {
3080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3081         int ret;
3082
3083         ret = dce_v11_0_hw_init(handle);
3084
3085         amdgpu_atombios_scratch_regs_restore(adev);
3086
3087         /* turn on the BL */
3088         if (adev->mode_info.bl_encoder) {
3089                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3090                                                                   adev->mode_info.bl_encoder);
3091                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3092                                                     bl_level);
3093         }
3094
3095         return ret;
3096 }
3097
3098 static bool dce_v11_0_is_idle(void *handle)
3099 {
3100         return true;
3101 }
3102
3103 static int dce_v11_0_wait_for_idle(void *handle)
3104 {
3105         return 0;
3106 }
3107
3108 static void dce_v11_0_print_status(void *handle)
3109 {
3110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3111
3112         dev_info(adev->dev, "DCE 10.x registers\n");
3113         /* XXX todo */
3114 }
3115
3116 static int dce_v11_0_soft_reset(void *handle)
3117 {
3118         u32 srbm_soft_reset = 0, tmp;
3119         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3120
3121         if (dce_v11_0_is_display_hung(adev))
3122                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3123
3124         if (srbm_soft_reset) {
3125                 dce_v11_0_print_status((void *)adev);
3126
3127                 tmp = RREG32(mmSRBM_SOFT_RESET);
3128                 tmp |= srbm_soft_reset;
3129                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3130                 WREG32(mmSRBM_SOFT_RESET, tmp);
3131                 tmp = RREG32(mmSRBM_SOFT_RESET);
3132
3133                 udelay(50);
3134
3135                 tmp &= ~srbm_soft_reset;
3136                 WREG32(mmSRBM_SOFT_RESET, tmp);
3137                 tmp = RREG32(mmSRBM_SOFT_RESET);
3138
3139                 /* Wait a little for things to settle down */
3140                 udelay(50);
3141                 dce_v11_0_print_status((void *)adev);
3142         }
3143         return 0;
3144 }
3145
3146 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3147                                                      int crtc,
3148                                                      enum amdgpu_interrupt_state state)
3149 {
3150         u32 lb_interrupt_mask;
3151
3152         if (crtc >= adev->mode_info.num_crtc) {
3153                 DRM_DEBUG("invalid crtc %d\n", crtc);
3154                 return;
3155         }
3156
3157         switch (state) {
3158         case AMDGPU_IRQ_STATE_DISABLE:
3159                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3160                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3161                                                   VBLANK_INTERRUPT_MASK, 0);
3162                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3163                 break;
3164         case AMDGPU_IRQ_STATE_ENABLE:
3165                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3166                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3167                                                   VBLANK_INTERRUPT_MASK, 1);
3168                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3169                 break;
3170         default:
3171                 break;
3172         }
3173 }
3174
3175 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3176                                                     int crtc,
3177                                                     enum amdgpu_interrupt_state state)
3178 {
3179         u32 lb_interrupt_mask;
3180
3181         if (crtc >= adev->mode_info.num_crtc) {
3182                 DRM_DEBUG("invalid crtc %d\n", crtc);
3183                 return;
3184         }
3185
3186         switch (state) {
3187         case AMDGPU_IRQ_STATE_DISABLE:
3188                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3189                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3190                                                   VLINE_INTERRUPT_MASK, 0);
3191                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3192                 break;
3193         case AMDGPU_IRQ_STATE_ENABLE:
3194                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3195                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3196                                                   VLINE_INTERRUPT_MASK, 1);
3197                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3198                 break;
3199         default:
3200                 break;
3201         }
3202 }
3203
3204 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3205                                         struct amdgpu_irq_src *source,
3206                                         unsigned hpd,
3207                                         enum amdgpu_interrupt_state state)
3208 {
3209         u32 tmp;
3210
3211         if (hpd >= adev->mode_info.num_hpd) {
3212                 DRM_DEBUG("invalid hdp %d\n", hpd);
3213                 return 0;
3214         }
3215
3216         switch (state) {
3217         case AMDGPU_IRQ_STATE_DISABLE:
3218                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3219                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3220                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3221                 break;
3222         case AMDGPU_IRQ_STATE_ENABLE:
3223                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3224                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3225                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3226                 break;
3227         default:
3228                 break;
3229         }
3230
3231         return 0;
3232 }
3233
3234 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3235                                         struct amdgpu_irq_src *source,
3236                                         unsigned type,
3237                                         enum amdgpu_interrupt_state state)
3238 {
3239         switch (type) {
3240         case AMDGPU_CRTC_IRQ_VBLANK1:
3241                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3242                 break;
3243         case AMDGPU_CRTC_IRQ_VBLANK2:
3244                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3245                 break;
3246         case AMDGPU_CRTC_IRQ_VBLANK3:
3247                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3248                 break;
3249         case AMDGPU_CRTC_IRQ_VBLANK4:
3250                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3251                 break;
3252         case AMDGPU_CRTC_IRQ_VBLANK5:
3253                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3254                 break;
3255         case AMDGPU_CRTC_IRQ_VBLANK6:
3256                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3257                 break;
3258         case AMDGPU_CRTC_IRQ_VLINE1:
3259                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3260                 break;
3261         case AMDGPU_CRTC_IRQ_VLINE2:
3262                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3263                 break;
3264         case AMDGPU_CRTC_IRQ_VLINE3:
3265                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3266                 break;
3267         case AMDGPU_CRTC_IRQ_VLINE4:
3268                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3269                 break;
3270         case AMDGPU_CRTC_IRQ_VLINE5:
3271                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3272                 break;
3273          case AMDGPU_CRTC_IRQ_VLINE6:
3274                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3275                 break;
3276         default:
3277                 break;
3278         }
3279         return 0;
3280 }
3281
3282 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3283                                             struct amdgpu_irq_src *src,
3284                                             unsigned type,
3285                                             enum amdgpu_interrupt_state state)
3286 {
3287         u32 reg;
3288
3289         if (type >= adev->mode_info.num_crtc) {
3290                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3291                 return -EINVAL;
3292         }
3293
3294         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3295         if (state == AMDGPU_IRQ_STATE_DISABLE)
3296                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3297                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3298         else
3299                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3300                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3301
3302         return 0;
3303 }
3304
3305 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3306                                   struct amdgpu_irq_src *source,
3307                                   struct amdgpu_iv_entry *entry)
3308 {
3309         unsigned long flags;
3310         unsigned crtc_id;
3311         struct amdgpu_crtc *amdgpu_crtc;
3312         struct amdgpu_flip_work *works;
3313
3314         crtc_id = (entry->src_id - 8) >> 1;
3315         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3316
3317         if (crtc_id >= adev->mode_info.num_crtc) {
3318                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3319                 return -EINVAL;
3320         }
3321
3322         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3323             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3324                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3325                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3326
3327         /* IRQ could occur when in initial stage */
3328         if(amdgpu_crtc == NULL)
3329                 return 0;
3330
3331         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3332         works = amdgpu_crtc->pflip_works;
3333         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3334                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3335                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3336                                                  amdgpu_crtc->pflip_status,
3337                                                  AMDGPU_FLIP_SUBMITTED);
3338                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3339                 return 0;
3340         }
3341
3342         /* page flip completed. clean up */
3343         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3344         amdgpu_crtc->pflip_works = NULL;
3345
3346         /* wakeup usersapce */
3347         if(works->event)
3348                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3349
3350         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3351
3352         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3353         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3354
3355         return 0;
3356 }
3357
3358 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3359                                   int hpd)
3360 {
3361         u32 tmp;
3362
3363         if (hpd >= adev->mode_info.num_hpd) {
3364                 DRM_DEBUG("invalid hdp %d\n", hpd);
3365                 return;
3366         }
3367
3368         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3369         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3370         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3371 }
3372
3373 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3374                                           int crtc)
3375 {
3376         u32 tmp;
3377
3378         if (crtc >= adev->mode_info.num_crtc) {
3379                 DRM_DEBUG("invalid crtc %d\n", crtc);
3380                 return;
3381         }
3382
3383         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3384         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3385         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3386 }
3387
3388 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3389                                          int crtc)
3390 {
3391         u32 tmp;
3392
3393         if (crtc >= adev->mode_info.num_crtc) {
3394                 DRM_DEBUG("invalid crtc %d\n", crtc);
3395                 return;
3396         }
3397
3398         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3399         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3400         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3401 }
3402
3403 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3404                                 struct amdgpu_irq_src *source,
3405                                 struct amdgpu_iv_entry *entry)
3406 {
3407         unsigned crtc = entry->src_id - 1;
3408         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3409         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3410
3411         switch (entry->src_data) {
3412         case 0: /* vblank */
3413                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3414                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3415                 else
3416                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3417
3418                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3419                         drm_handle_vblank(adev->ddev, crtc);
3420                 }
3421                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3422
3423                 break;
3424         case 1: /* vline */
3425                 if (disp_int & interrupt_status_offsets[crtc].vline)
3426                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3427                 else
3428                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3429
3430                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3431
3432                 break;
3433         default:
3434                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3435                 break;
3436         }
3437
3438         return 0;
3439 }
3440
3441 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3442                              struct amdgpu_irq_src *source,
3443                              struct amdgpu_iv_entry *entry)
3444 {
3445         uint32_t disp_int, mask;
3446         unsigned hpd;
3447
3448         if (entry->src_data >= adev->mode_info.num_hpd) {
3449                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3450                 return 0;
3451         }
3452
3453         hpd = entry->src_data;
3454         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3455         mask = interrupt_status_offsets[hpd].hpd;
3456
3457         if (disp_int & mask) {
3458                 dce_v11_0_hpd_int_ack(adev, hpd);
3459                 schedule_work(&adev->hotplug_work);
3460                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3461         }
3462
3463         return 0;
3464 }
3465
3466 static int dce_v11_0_set_clockgating_state(void *handle,
3467                                           enum amd_clockgating_state state)
3468 {
3469         return 0;
3470 }
3471
3472 static int dce_v11_0_set_powergating_state(void *handle,
3473                                           enum amd_powergating_state state)
3474 {
3475         return 0;
3476 }
3477
3478 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3479         .early_init = dce_v11_0_early_init,
3480         .late_init = NULL,
3481         .sw_init = dce_v11_0_sw_init,
3482         .sw_fini = dce_v11_0_sw_fini,
3483         .hw_init = dce_v11_0_hw_init,
3484         .hw_fini = dce_v11_0_hw_fini,
3485         .suspend = dce_v11_0_suspend,
3486         .resume = dce_v11_0_resume,
3487         .is_idle = dce_v11_0_is_idle,
3488         .wait_for_idle = dce_v11_0_wait_for_idle,
3489         .soft_reset = dce_v11_0_soft_reset,
3490         .print_status = dce_v11_0_print_status,
3491         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3492         .set_powergating_state = dce_v11_0_set_powergating_state,
3493 };
3494
3495 static void
3496 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3497                           struct drm_display_mode *mode,
3498                           struct drm_display_mode *adjusted_mode)
3499 {
3500         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3501
3502         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3503
3504         /* need to call this here rather than in prepare() since we need some crtc info */
3505         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3506
3507         /* set scaler clears this on some chips */
3508         dce_v11_0_set_interleave(encoder->crtc, mode);
3509
3510         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3511                 dce_v11_0_afmt_enable(encoder, true);
3512                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3513         }
3514 }
3515
3516 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3517 {
3518         struct amdgpu_device *adev = encoder->dev->dev_private;
3519         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3520         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3521
3522         if ((amdgpu_encoder->active_device &
3523              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3524             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3525              ENCODER_OBJECT_ID_NONE)) {
3526                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3527                 if (dig) {
3528                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3529                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3530                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3531                 }
3532         }
3533
3534         amdgpu_atombios_scratch_regs_lock(adev, true);
3535
3536         if (connector) {
3537                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3538
3539                 /* select the clock/data port if it uses a router */
3540                 if (amdgpu_connector->router.cd_valid)
3541                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3542
3543                 /* turn eDP panel on for mode set */
3544                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3545                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3546                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3547         }
3548
3549         /* this is needed for the pll/ss setup to work correctly in some cases */
3550         amdgpu_atombios_encoder_set_crtc_source(encoder);
3551         /* set up the FMT blocks */
3552         dce_v11_0_program_fmt(encoder);
3553 }
3554
3555 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3556 {
3557         struct drm_device *dev = encoder->dev;
3558         struct amdgpu_device *adev = dev->dev_private;
3559
3560         /* need to call this here as we need the crtc set up */
3561         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3562         amdgpu_atombios_scratch_regs_lock(adev, false);
3563 }
3564
3565 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3566 {
3567         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3568         struct amdgpu_encoder_atom_dig *dig;
3569
3570         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3571
3572         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3573                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3574                         dce_v11_0_afmt_enable(encoder, false);
3575                 dig = amdgpu_encoder->enc_priv;
3576                 dig->dig_encoder = -1;
3577         }
3578         amdgpu_encoder->active_device = 0;
3579 }
3580
3581 /* these are handled by the primary encoders */
3582 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3583 {
3584
3585 }
3586
3587 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3588 {
3589
3590 }
3591
3592 static void
3593 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3594                       struct drm_display_mode *mode,
3595                       struct drm_display_mode *adjusted_mode)
3596 {
3597
3598 }
3599
3600 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3601 {
3602
3603 }
3604
3605 static void
3606 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3607 {
3608
3609 }
3610
3611 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder,
3612                                     const struct drm_display_mode *mode,
3613                                     struct drm_display_mode *adjusted_mode)
3614 {
3615         return true;
3616 }
3617
3618 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3619         .dpms = dce_v11_0_ext_dpms,
3620         .mode_fixup = dce_v11_0_ext_mode_fixup,
3621         .prepare = dce_v11_0_ext_prepare,
3622         .mode_set = dce_v11_0_ext_mode_set,
3623         .commit = dce_v11_0_ext_commit,
3624         .disable = dce_v11_0_ext_disable,
3625         /* no detect for TMDS/LVDS yet */
3626 };
3627
3628 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3629         .dpms = amdgpu_atombios_encoder_dpms,
3630         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3631         .prepare = dce_v11_0_encoder_prepare,
3632         .mode_set = dce_v11_0_encoder_mode_set,
3633         .commit = dce_v11_0_encoder_commit,
3634         .disable = dce_v11_0_encoder_disable,
3635         .detect = amdgpu_atombios_encoder_dig_detect,
3636 };
3637
3638 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3639         .dpms = amdgpu_atombios_encoder_dpms,
3640         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3641         .prepare = dce_v11_0_encoder_prepare,
3642         .mode_set = dce_v11_0_encoder_mode_set,
3643         .commit = dce_v11_0_encoder_commit,
3644         .detect = amdgpu_atombios_encoder_dac_detect,
3645 };
3646
3647 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3648 {
3649         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3650         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3651                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3652         kfree(amdgpu_encoder->enc_priv);
3653         drm_encoder_cleanup(encoder);
3654         kfree(amdgpu_encoder);
3655 }
3656
3657 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3658         .destroy = dce_v11_0_encoder_destroy,
3659 };
3660
3661 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3662                                  uint32_t encoder_enum,
3663                                  uint32_t supported_device,
3664                                  u16 caps)
3665 {
3666         struct drm_device *dev = adev->ddev;
3667         struct drm_encoder *encoder;
3668         struct amdgpu_encoder *amdgpu_encoder;
3669
3670         /* see if we already added it */
3671         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3672                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3673                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3674                         amdgpu_encoder->devices |= supported_device;
3675                         return;
3676                 }
3677
3678         }
3679
3680         /* add a new one */
3681         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3682         if (!amdgpu_encoder)
3683                 return;
3684
3685         encoder = &amdgpu_encoder->base;
3686         switch (adev->mode_info.num_crtc) {
3687         case 1:
3688                 encoder->possible_crtcs = 0x1;
3689                 break;
3690         case 2:
3691         default:
3692                 encoder->possible_crtcs = 0x3;
3693                 break;
3694         case 3:
3695                 encoder->possible_crtcs = 0x7;
3696                 break;
3697         case 4:
3698                 encoder->possible_crtcs = 0xf;
3699                 break;
3700         case 5:
3701                 encoder->possible_crtcs = 0x1f;
3702                 break;
3703         case 6:
3704                 encoder->possible_crtcs = 0x3f;
3705                 break;
3706         }
3707
3708         amdgpu_encoder->enc_priv = NULL;
3709
3710         amdgpu_encoder->encoder_enum = encoder_enum;
3711         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3712         amdgpu_encoder->devices = supported_device;
3713         amdgpu_encoder->rmx_type = RMX_OFF;
3714         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3715         amdgpu_encoder->is_ext_encoder = false;
3716         amdgpu_encoder->caps = caps;
3717
3718         switch (amdgpu_encoder->encoder_id) {
3719         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3720         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3721                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3722                                  DRM_MODE_ENCODER_DAC);
3723                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3724                 break;
3725         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3726         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3727         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3728         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3729         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3730                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3731                         amdgpu_encoder->rmx_type = RMX_FULL;
3732                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3733                                          DRM_MODE_ENCODER_LVDS);
3734                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3735                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3736                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3737                                          DRM_MODE_ENCODER_DAC);
3738                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3739                 } else {
3740                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3741                                          DRM_MODE_ENCODER_TMDS);
3742                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3743                 }
3744                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3745                 break;
3746         case ENCODER_OBJECT_ID_SI170B:
3747         case ENCODER_OBJECT_ID_CH7303:
3748         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3749         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3750         case ENCODER_OBJECT_ID_TITFP513:
3751         case ENCODER_OBJECT_ID_VT1623:
3752         case ENCODER_OBJECT_ID_HDMI_SI1930:
3753         case ENCODER_OBJECT_ID_TRAVIS:
3754         case ENCODER_OBJECT_ID_NUTMEG:
3755                 /* these are handled by the primary encoders */
3756                 amdgpu_encoder->is_ext_encoder = true;
3757                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3758                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3759                                          DRM_MODE_ENCODER_LVDS);
3760                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3761                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3762                                          DRM_MODE_ENCODER_DAC);
3763                 else
3764                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3765                                          DRM_MODE_ENCODER_TMDS);
3766                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3767                 break;
3768         }
3769 }
3770
3771 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3772         .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3773         .bandwidth_update = &dce_v11_0_bandwidth_update,
3774         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3775         .vblank_wait = &dce_v11_0_vblank_wait,
3776         .is_display_hung = &dce_v11_0_is_display_hung,
3777         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3778         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3779         .hpd_sense = &dce_v11_0_hpd_sense,
3780         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3781         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3782         .page_flip = &dce_v11_0_page_flip,
3783         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3784         .add_encoder = &dce_v11_0_encoder_add,
3785         .add_connector = &amdgpu_connector_add,
3786         .stop_mc_access = &dce_v11_0_stop_mc_access,
3787         .resume_mc_access = &dce_v11_0_resume_mc_access,
3788 };
3789
3790 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3791 {
3792         if (adev->mode_info.funcs == NULL)
3793                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3794 }
3795
3796 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3797         .set = dce_v11_0_set_crtc_irq_state,
3798         .process = dce_v11_0_crtc_irq,
3799 };
3800
3801 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3802         .set = dce_v11_0_set_pageflip_irq_state,
3803         .process = dce_v11_0_pageflip_irq,
3804 };
3805
3806 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3807         .set = dce_v11_0_set_hpd_irq_state,
3808         .process = dce_v11_0_hpd_irq,
3809 };
3810
3811 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3812 {
3813         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3814         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3815
3816         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3817         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3818
3819         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3820         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3821 }