2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_11_0_d.h"
36 #include "dce/dce_11_0_sh_mask.h"
37 #include "dce/dce_11_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46 static const u32 crtc_offsets[] =
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
57 static const u32 hpd_offsets[] =
67 static const uint32_t dig_offsets[] = {
85 } interrupt_status_offsets[] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
117 static const u32 cz_golden_settings_a11[] =
119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120 mmFBC_MISC, 0x1f311fff, 0x14300000,
123 static const u32 cz_mgcg_cgcg_init[] =
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
129 static const u32 stoney_golden_settings_a11[] =
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14302000,
135 static const u32 polaris11_golden_settings_a11[] =
137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
140 mmFBC_MISC, 0x9f313fff, 0x14302008,
141 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
144 static const u32 polaris10_golden_settings_a11[] =
146 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
147 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
148 mmFBC_MISC, 0x9f313fff, 0x14302008,
149 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154 switch (adev->asic_type) {
156 amdgpu_program_register_sequence(adev,
158 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
159 amdgpu_program_register_sequence(adev,
160 cz_golden_settings_a11,
161 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
164 amdgpu_program_register_sequence(adev,
165 stoney_golden_settings_a11,
166 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
169 amdgpu_program_register_sequence(adev,
170 polaris11_golden_settings_a11,
171 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
174 amdgpu_program_register_sequence(adev,
175 polaris10_golden_settings_a11,
176 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
184 u32 block_offset, u32 reg)
189 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
190 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
191 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
192 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
198 u32 block_offset, u32 reg, u32 v)
202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
210 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
211 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
221 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
222 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
231 * dce_v11_0_vblank_wait - vblank wait asic callback.
233 * @adev: amdgpu_device pointer
234 * @crtc: crtc to wait for vblank on
236 * Wait for vblank on the requested crtc (evergreen+).
238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
242 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
245 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
248 /* depending on when we hit vblank, we may be close to active; if so,
249 * wait for another frame.
251 while (dce_v11_0_is_in_vblank(adev, crtc)) {
254 if (!dce_v11_0_is_counter_moving(adev, crtc))
259 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
262 if (!dce_v11_0_is_counter_moving(adev, crtc))
268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
270 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
273 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
280 /* Enable pflip interrupts */
281 for (i = 0; i < adev->mode_info.num_crtc; i++)
282 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
289 /* Disable pflip interrupts */
290 for (i = 0; i < adev->mode_info.num_crtc; i++)
291 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
295 * dce_v11_0_page_flip - pageflip callback.
297 * @adev: amdgpu_device pointer
298 * @crtc_id: crtc to cleanup pageflip on
299 * @crtc_base: new address of the crtc (GPU MC address)
301 * Triggers the actual pageflip by updating the primary
302 * surface base address.
304 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
305 int crtc_id, u64 crtc_base, bool async)
307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
310 /* flip immediate for async, default is vsync */
311 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
312 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
313 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
314 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
315 /* update the scanout addresses */
316 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
317 upper_32_bits(crtc_base));
318 /* writing to the low address triggers the update */
319 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
320 lower_32_bits(crtc_base));
322 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
325 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
326 u32 *vbl, u32 *position)
328 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
331 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
332 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
338 * dce_v11_0_hpd_sense - hpd sense callback.
340 * @adev: amdgpu_device pointer
341 * @hpd: hpd (hotplug detect) pin
343 * Checks if a digital monitor is connected (evergreen+).
344 * Returns true if connected, false if not connected.
346 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
347 enum amdgpu_hpd_id hpd)
350 bool connected = false;
375 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
376 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
383 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
385 * @adev: amdgpu_device pointer
386 * @hpd: hpd (hotplug detect) pin
388 * Set the polarity of the hpd pin (evergreen+).
390 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
391 enum amdgpu_hpd_id hpd)
394 bool connected = dce_v11_0_hpd_sense(adev, hpd);
420 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
422 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
424 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
425 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
429 * dce_v11_0_hpd_init - hpd setup callback.
431 * @adev: amdgpu_device pointer
433 * Setup the hpd pins used by the card (evergreen+).
434 * Enable the pin, set the polarity, and enable the hpd interrupts.
436 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
438 struct drm_device *dev = adev->ddev;
439 struct drm_connector *connector;
443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
444 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
446 switch (amdgpu_connector->hpd.hpd) {
469 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
470 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
471 /* don't try to enable hpd on eDP or LVDS avoid breaking the
472 * aux dp channel on imac and help (but not completely fix)
473 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
474 * also avoid interrupt storms during dpms.
476 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
477 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
478 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
482 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
483 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
484 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
486 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
487 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
488 DC_HPD_CONNECT_INT_DELAY,
489 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
490 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
491 DC_HPD_DISCONNECT_INT_DELAY,
492 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
493 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
495 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
496 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
501 * dce_v11_0_hpd_fini - hpd tear down callback.
503 * @adev: amdgpu_device pointer
505 * Tear down the hpd pins used by the card (evergreen+).
506 * Disable the hpd interrupts.
508 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
510 struct drm_device *dev = adev->ddev;
511 struct drm_connector *connector;
515 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
518 switch (amdgpu_connector->hpd.hpd) {
541 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
542 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
543 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
545 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
549 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
551 return mmDC_GPIO_HPD_A;
554 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
560 for (i = 0; i < adev->mode_info.num_crtc; i++) {
561 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
562 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
563 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
564 crtc_hung |= (1 << i);
568 for (j = 0; j < 10; j++) {
569 for (i = 0; i < adev->mode_info.num_crtc; i++) {
570 if (crtc_hung & (1 << i)) {
571 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
572 if (tmp != crtc_status[i])
573 crtc_hung &= ~(1 << i);
584 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
585 struct amdgpu_mode_mc_save *save)
587 u32 crtc_enabled, tmp;
590 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
591 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
593 /* disable VGA render */
594 tmp = RREG32(mmVGA_RENDER_CONTROL);
595 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
596 WREG32(mmVGA_RENDER_CONTROL, tmp);
598 /* blank the display controllers */
599 for (i = 0; i < adev->mode_info.num_crtc; i++) {
600 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
601 CRTC_CONTROL, CRTC_MASTER_EN);
604 save->crtc_enabled[i] = true;
605 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
606 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
607 /*it is correct only for RGB ; black is 0*/
608 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
609 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
610 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
613 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
614 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
615 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
616 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
617 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
618 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
619 save->crtc_enabled[i] = false;
623 save->crtc_enabled[i] = false;
628 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
629 struct amdgpu_mode_mc_save *save)
634 /* update crtc base addresses */
635 for (i = 0; i < adev->mode_info.num_crtc; i++) {
636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
637 upper_32_bits(adev->mc.vram_start));
638 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
639 (u32)adev->mc.vram_start);
641 if (save->crtc_enabled[i]) {
642 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
643 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
644 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
648 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
649 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
651 /* Unlock vga access */
652 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
654 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
657 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
662 /* Lockout access through VGA aperture*/
663 tmp = RREG32(mmVGA_HDP_CONTROL);
665 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
667 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
668 WREG32(mmVGA_HDP_CONTROL, tmp);
670 /* disable VGA render */
671 tmp = RREG32(mmVGA_RENDER_CONTROL);
673 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
675 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
676 WREG32(mmVGA_RENDER_CONTROL, tmp);
679 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
683 switch (adev->asic_type) {
702 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
704 /*Disable VGA render and enabled crtc, if has DCE engine*/
705 if (amdgpu_atombios_has_dce_engine_info(adev)) {
709 dce_v11_0_set_vga_render_state(adev, false);
712 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
713 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
714 CRTC_CONTROL, CRTC_MASTER_EN);
716 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
717 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
718 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
719 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
720 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
726 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
728 struct drm_device *dev = encoder->dev;
729 struct amdgpu_device *adev = dev->dev_private;
730 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
731 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
732 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
735 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
738 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
739 bpc = amdgpu_connector_get_monitor_bpc(connector);
740 dither = amdgpu_connector->dither;
743 /* LVDS/eDP FMT is set up by atom */
744 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
747 /* not needed for analog */
748 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
749 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
757 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
758 /* XXX sort out optimal dither settings */
759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
762 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
764 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
765 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
769 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
770 /* XXX sort out optimal dither settings */
771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
772 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
773 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
775 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
777 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
778 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
782 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
783 /* XXX sort out optimal dither settings */
784 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
785 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
786 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
787 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
788 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
790 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
791 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
799 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
803 /* display watermark setup */
805 * dce_v11_0_line_buffer_adjust - Set up the line buffer
807 * @adev: amdgpu_device pointer
808 * @amdgpu_crtc: the selected display controller
809 * @mode: the current display mode on the selected display
812 * Setup up the line buffer allocation for
813 * the selected display controller (CIK).
814 * Returns the line buffer size in pixels.
816 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
817 struct amdgpu_crtc *amdgpu_crtc,
818 struct drm_display_mode *mode)
820 u32 tmp, buffer_alloc, i, mem_cfg;
821 u32 pipe_offset = amdgpu_crtc->crtc_id;
824 * There are 6 line buffers, one for each display controllers.
825 * There are 3 partitions per LB. Select the number of partitions
826 * to enable based on the display width. For display widths larger
827 * than 4096, you need use to use 2 display controllers and combine
828 * them using the stereo blender.
830 if (amdgpu_crtc->base.enabled && mode) {
831 if (mode->crtc_hdisplay < 1920) {
834 } else if (mode->crtc_hdisplay < 2560) {
837 } else if (mode->crtc_hdisplay < 4096) {
839 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
841 DRM_DEBUG_KMS("Mode too big for LB!\n");
843 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
850 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
851 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
852 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
854 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
855 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
856 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
858 for (i = 0; i < adev->usec_timeout; i++) {
859 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
860 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
865 if (amdgpu_crtc->base.enabled && mode) {
877 /* controller not enabled, so no lb used */
882 * cik_get_number_of_dram_channels - get the number of dram channels
884 * @adev: amdgpu_device pointer
886 * Look up the number of video ram channels (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the number of dram channels
890 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
892 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
894 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
917 struct dce10_wm_params {
918 u32 dram_channels; /* number of dram channels */
919 u32 yclk; /* bandwidth per dram data pin in kHz */
920 u32 sclk; /* engine clock in kHz */
921 u32 disp_clk; /* display clock in kHz */
922 u32 src_width; /* viewport width */
923 u32 active_time; /* active display time in ns */
924 u32 blank_time; /* blank time in ns */
925 bool interlaced; /* mode is interlaced */
926 fixed20_12 vsc; /* vertical scale ratio */
927 u32 num_heads; /* number of active crtcs */
928 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
929 u32 lb_size; /* line buffer allocated to pipe */
930 u32 vtaps; /* vertical scaler taps */
934 * dce_v11_0_dram_bandwidth - get the dram bandwidth
936 * @wm: watermark calculation data
938 * Calculate the raw dram bandwidth (CIK).
939 * Used for display watermark bandwidth calculations
940 * Returns the dram bandwidth in MBytes/s
942 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
944 /* Calculate raw DRAM Bandwidth */
945 fixed20_12 dram_efficiency; /* 0.7 */
946 fixed20_12 yclk, dram_channels, bandwidth;
949 a.full = dfixed_const(1000);
950 yclk.full = dfixed_const(wm->yclk);
951 yclk.full = dfixed_div(yclk, a);
952 dram_channels.full = dfixed_const(wm->dram_channels * 4);
953 a.full = dfixed_const(10);
954 dram_efficiency.full = dfixed_const(7);
955 dram_efficiency.full = dfixed_div(dram_efficiency, a);
956 bandwidth.full = dfixed_mul(dram_channels, yclk);
957 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
959 return dfixed_trunc(bandwidth);
963 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
965 * @wm: watermark calculation data
967 * Calculate the dram bandwidth used for display (CIK).
968 * Used for display watermark bandwidth calculations
969 * Returns the dram bandwidth for display in MBytes/s
971 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
973 /* Calculate DRAM Bandwidth and the part allocated to display. */
974 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
975 fixed20_12 yclk, dram_channels, bandwidth;
978 a.full = dfixed_const(1000);
979 yclk.full = dfixed_const(wm->yclk);
980 yclk.full = dfixed_div(yclk, a);
981 dram_channels.full = dfixed_const(wm->dram_channels * 4);
982 a.full = dfixed_const(10);
983 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
984 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
985 bandwidth.full = dfixed_mul(dram_channels, yclk);
986 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
988 return dfixed_trunc(bandwidth);
992 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
994 * @wm: watermark calculation data
996 * Calculate the data return bandwidth used for display (CIK).
997 * Used for display watermark bandwidth calculations
998 * Returns the data return bandwidth in MBytes/s
1000 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
1002 /* Calculate the display Data return Bandwidth */
1003 fixed20_12 return_efficiency; /* 0.8 */
1004 fixed20_12 sclk, bandwidth;
1007 a.full = dfixed_const(1000);
1008 sclk.full = dfixed_const(wm->sclk);
1009 sclk.full = dfixed_div(sclk, a);
1010 a.full = dfixed_const(10);
1011 return_efficiency.full = dfixed_const(8);
1012 return_efficiency.full = dfixed_div(return_efficiency, a);
1013 a.full = dfixed_const(32);
1014 bandwidth.full = dfixed_mul(a, sclk);
1015 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1017 return dfixed_trunc(bandwidth);
1021 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
1023 * @wm: watermark calculation data
1025 * Calculate the dmif bandwidth used for display (CIK).
1026 * Used for display watermark bandwidth calculations
1027 * Returns the dmif bandwidth in MBytes/s
1029 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1031 /* Calculate the DMIF Request Bandwidth */
1032 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1033 fixed20_12 disp_clk, bandwidth;
1036 a.full = dfixed_const(1000);
1037 disp_clk.full = dfixed_const(wm->disp_clk);
1038 disp_clk.full = dfixed_div(disp_clk, a);
1039 a.full = dfixed_const(32);
1040 b.full = dfixed_mul(a, disp_clk);
1042 a.full = dfixed_const(10);
1043 disp_clk_request_efficiency.full = dfixed_const(8);
1044 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1046 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1048 return dfixed_trunc(bandwidth);
1052 * dce_v11_0_available_bandwidth - get the min available bandwidth
1054 * @wm: watermark calculation data
1056 * Calculate the min available bandwidth used for display (CIK).
1057 * Used for display watermark bandwidth calculations
1058 * Returns the min available bandwidth in MBytes/s
1060 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1062 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1063 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1064 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1065 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1067 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1071 * dce_v11_0_average_bandwidth - get the average available bandwidth
1073 * @wm: watermark calculation data
1075 * Calculate the average available bandwidth used for display (CIK).
1076 * Used for display watermark bandwidth calculations
1077 * Returns the average available bandwidth in MBytes/s
1079 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1081 /* Calculate the display mode Average Bandwidth
1082 * DisplayMode should contain the source and destination dimensions,
1086 fixed20_12 line_time;
1087 fixed20_12 src_width;
1088 fixed20_12 bandwidth;
1091 a.full = dfixed_const(1000);
1092 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1093 line_time.full = dfixed_div(line_time, a);
1094 bpp.full = dfixed_const(wm->bytes_per_pixel);
1095 src_width.full = dfixed_const(wm->src_width);
1096 bandwidth.full = dfixed_mul(src_width, bpp);
1097 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1098 bandwidth.full = dfixed_div(bandwidth, line_time);
1100 return dfixed_trunc(bandwidth);
1104 * dce_v11_0_latency_watermark - get the latency watermark
1106 * @wm: watermark calculation data
1108 * Calculate the latency watermark (CIK).
1109 * Used for display watermark bandwidth calculations
1110 * Returns the latency watermark in ns
1112 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1114 /* First calculate the latency in ns */
1115 u32 mc_latency = 2000; /* 2000 ns. */
1116 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1117 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1118 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1119 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1120 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1121 (wm->num_heads * cursor_line_pair_return_time);
1122 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1123 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1124 u32 tmp, dmif_size = 12288;
1127 if (wm->num_heads == 0)
1130 a.full = dfixed_const(2);
1131 b.full = dfixed_const(1);
1132 if ((wm->vsc.full > a.full) ||
1133 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1135 ((wm->vsc.full >= a.full) && wm->interlaced))
1136 max_src_lines_per_dst_line = 4;
1138 max_src_lines_per_dst_line = 2;
1140 a.full = dfixed_const(available_bandwidth);
1141 b.full = dfixed_const(wm->num_heads);
1142 a.full = dfixed_div(a, b);
1143 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1144 tmp = min(dfixed_trunc(a), tmp);
1146 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1148 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1149 b.full = dfixed_const(1000);
1150 c.full = dfixed_const(lb_fill_bw);
1151 b.full = dfixed_div(c, b);
1152 a.full = dfixed_div(a, b);
1153 line_fill_time = dfixed_trunc(a);
1155 if (line_fill_time < wm->active_time)
1158 return latency + (line_fill_time - wm->active_time);
1163 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1164 * average and available dram bandwidth
1166 * @wm: watermark calculation data
1168 * Check if the display average bandwidth fits in the display
1169 * dram bandwidth (CIK).
1170 * Used for display watermark bandwidth calculations
1171 * Returns true if the display fits, false if not.
1173 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1175 if (dce_v11_0_average_bandwidth(wm) <=
1176 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1183 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1184 * average and available bandwidth
1186 * @wm: watermark calculation data
1188 * Check if the display average bandwidth fits in the display
1189 * available bandwidth (CIK).
1190 * Used for display watermark bandwidth calculations
1191 * Returns true if the display fits, false if not.
1193 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1195 if (dce_v11_0_average_bandwidth(wm) <=
1196 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1203 * dce_v11_0_check_latency_hiding - check latency hiding
1205 * @wm: watermark calculation data
1207 * Check latency hiding (CIK).
1208 * Used for display watermark bandwidth calculations
1209 * Returns true if the display fits, false if not.
1211 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1213 u32 lb_partitions = wm->lb_size / wm->src_width;
1214 u32 line_time = wm->active_time + wm->blank_time;
1215 u32 latency_tolerant_lines;
1219 a.full = dfixed_const(1);
1220 if (wm->vsc.full > a.full)
1221 latency_tolerant_lines = 1;
1223 if (lb_partitions <= (wm->vtaps + 1))
1224 latency_tolerant_lines = 1;
1226 latency_tolerant_lines = 2;
1229 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1231 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1238 * dce_v11_0_program_watermarks - program display watermarks
1240 * @adev: amdgpu_device pointer
1241 * @amdgpu_crtc: the selected display controller
1242 * @lb_size: line buffer size
1243 * @num_heads: number of display controllers in use
1245 * Calculate and program the display watermarks for the
1246 * selected display controller (CIK).
1248 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1249 struct amdgpu_crtc *amdgpu_crtc,
1250 u32 lb_size, u32 num_heads)
1252 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1253 struct dce10_wm_params wm_low, wm_high;
1256 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1257 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1259 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1260 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1262 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1264 line_time = min(line_time, (u32)65535);
1266 /* watermark for high clocks */
1267 if (adev->pm.dpm_enabled) {
1269 amdgpu_dpm_get_mclk(adev, false) * 10;
1271 amdgpu_dpm_get_sclk(adev, false) * 10;
1273 wm_high.yclk = adev->pm.current_mclk * 10;
1274 wm_high.sclk = adev->pm.current_sclk * 10;
1277 wm_high.disp_clk = mode->clock;
1278 wm_high.src_width = mode->crtc_hdisplay;
1279 wm_high.active_time = active_time;
1280 wm_high.blank_time = line_time - wm_high.active_time;
1281 wm_high.interlaced = false;
1282 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1283 wm_high.interlaced = true;
1284 wm_high.vsc = amdgpu_crtc->vsc;
1286 if (amdgpu_crtc->rmx_type != RMX_OFF)
1288 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1289 wm_high.lb_size = lb_size;
1290 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1291 wm_high.num_heads = num_heads;
1293 /* set for high clocks */
1294 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1296 /* possibly force display priority to high */
1297 /* should really do this at mode validation time... */
1298 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1299 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1300 !dce_v11_0_check_latency_hiding(&wm_high) ||
1301 (adev->mode_info.disp_priority == 2)) {
1302 DRM_DEBUG_KMS("force priority to high\n");
1305 /* watermark for low clocks */
1306 if (adev->pm.dpm_enabled) {
1308 amdgpu_dpm_get_mclk(adev, true) * 10;
1310 amdgpu_dpm_get_sclk(adev, true) * 10;
1312 wm_low.yclk = adev->pm.current_mclk * 10;
1313 wm_low.sclk = adev->pm.current_sclk * 10;
1316 wm_low.disp_clk = mode->clock;
1317 wm_low.src_width = mode->crtc_hdisplay;
1318 wm_low.active_time = active_time;
1319 wm_low.blank_time = line_time - wm_low.active_time;
1320 wm_low.interlaced = false;
1321 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1322 wm_low.interlaced = true;
1323 wm_low.vsc = amdgpu_crtc->vsc;
1325 if (amdgpu_crtc->rmx_type != RMX_OFF)
1327 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1328 wm_low.lb_size = lb_size;
1329 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1330 wm_low.num_heads = num_heads;
1332 /* set for low clocks */
1333 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1335 /* possibly force display priority to high */
1336 /* should really do this at mode validation time... */
1337 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1338 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1339 !dce_v11_0_check_latency_hiding(&wm_low) ||
1340 (adev->mode_info.disp_priority == 2)) {
1341 DRM_DEBUG_KMS("force priority to high\n");
1343 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1347 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1348 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1349 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1350 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1351 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1352 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1353 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1355 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1356 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1357 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1358 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1359 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1360 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1361 /* restore original selection */
1362 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1364 /* save values for DPM */
1365 amdgpu_crtc->line_time = line_time;
1366 amdgpu_crtc->wm_high = latency_watermark_a;
1367 amdgpu_crtc->wm_low = latency_watermark_b;
1368 /* Save number of lines the linebuffer leads before the scanout */
1369 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1373 * dce_v11_0_bandwidth_update - program display watermarks
1375 * @adev: amdgpu_device pointer
1377 * Calculate and program the display watermarks and line
1378 * buffer allocation (CIK).
1380 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1382 struct drm_display_mode *mode = NULL;
1383 u32 num_heads = 0, lb_size;
1386 amdgpu_update_display_priority(adev);
1388 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1389 if (adev->mode_info.crtcs[i]->base.enabled)
1392 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1393 mode = &adev->mode_info.crtcs[i]->base.mode;
1394 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1395 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1396 lb_size, num_heads);
1400 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1405 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1406 offset = adev->mode_info.audio.pin[i].offset;
1407 tmp = RREG32_AUDIO_ENDPT(offset,
1408 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1410 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1411 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1412 adev->mode_info.audio.pin[i].connected = false;
1414 adev->mode_info.audio.pin[i].connected = true;
1418 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1422 dce_v11_0_audio_get_connected_pins(adev);
1424 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1425 if (adev->mode_info.audio.pin[i].connected)
1426 return &adev->mode_info.audio.pin[i];
1428 DRM_ERROR("No connected audio pins found!\n");
1432 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1434 struct amdgpu_device *adev = encoder->dev->dev_private;
1435 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1436 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1439 if (!dig || !dig->afmt || !dig->afmt->pin)
1442 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1443 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1444 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1447 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1448 struct drm_display_mode *mode)
1450 struct amdgpu_device *adev = encoder->dev->dev_private;
1451 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1452 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1453 struct drm_connector *connector;
1454 struct amdgpu_connector *amdgpu_connector = NULL;
1458 if (!dig || !dig->afmt || !dig->afmt->pin)
1461 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1462 if (connector->encoder == encoder) {
1463 amdgpu_connector = to_amdgpu_connector(connector);
1468 if (!amdgpu_connector) {
1469 DRM_ERROR("Couldn't find encoder's connector\n");
1473 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1475 if (connector->latency_present[interlace]) {
1476 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1477 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1478 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1479 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1481 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1483 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1486 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1487 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1490 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1492 struct amdgpu_device *adev = encoder->dev->dev_private;
1493 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1494 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1495 struct drm_connector *connector;
1496 struct amdgpu_connector *amdgpu_connector = NULL;
1501 if (!dig || !dig->afmt || !dig->afmt->pin)
1504 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1505 if (connector->encoder == encoder) {
1506 amdgpu_connector = to_amdgpu_connector(connector);
1511 if (!amdgpu_connector) {
1512 DRM_ERROR("Couldn't find encoder's connector\n");
1516 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1517 if (sad_count < 0) {
1518 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1522 /* program the speaker allocation */
1523 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1524 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1525 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1528 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1529 HDMI_CONNECTION, 1);
1531 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1532 SPEAKER_ALLOCATION, sadb[0]);
1534 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1535 SPEAKER_ALLOCATION, 5); /* stereo */
1536 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1537 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1542 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1544 struct amdgpu_device *adev = encoder->dev->dev_private;
1545 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1546 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1547 struct drm_connector *connector;
1548 struct amdgpu_connector *amdgpu_connector = NULL;
1549 struct cea_sad *sads;
1552 static const u16 eld_reg_to_type[][2] = {
1553 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1554 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1555 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1556 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1557 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1558 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1559 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1560 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1561 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1562 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1563 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1564 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1567 if (!dig || !dig->afmt || !dig->afmt->pin)
1570 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1571 if (connector->encoder == encoder) {
1572 amdgpu_connector = to_amdgpu_connector(connector);
1577 if (!amdgpu_connector) {
1578 DRM_ERROR("Couldn't find encoder's connector\n");
1582 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1583 if (sad_count <= 0) {
1584 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1589 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1591 u8 stereo_freqs = 0;
1592 int max_channels = -1;
1595 for (j = 0; j < sad_count; j++) {
1596 struct cea_sad *sad = &sads[j];
1598 if (sad->format == eld_reg_to_type[i][1]) {
1599 if (sad->channels > max_channels) {
1600 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1601 MAX_CHANNELS, sad->channels);
1602 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1603 DESCRIPTOR_BYTE_2, sad->byte2);
1604 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1605 SUPPORTED_FREQUENCIES, sad->freq);
1606 max_channels = sad->channels;
1609 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1610 stereo_freqs |= sad->freq;
1616 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1617 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1618 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1624 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1625 struct amdgpu_audio_pin *pin,
1631 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1632 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1635 static const u32 pin_offsets[] =
1637 AUD0_REGISTER_OFFSET,
1638 AUD1_REGISTER_OFFSET,
1639 AUD2_REGISTER_OFFSET,
1640 AUD3_REGISTER_OFFSET,
1641 AUD4_REGISTER_OFFSET,
1642 AUD5_REGISTER_OFFSET,
1643 AUD6_REGISTER_OFFSET,
1644 AUD7_REGISTER_OFFSET,
1647 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1654 adev->mode_info.audio.enabled = true;
1656 switch (adev->asic_type) {
1659 adev->mode_info.audio.num_pins = 7;
1661 case CHIP_POLARIS10:
1662 adev->mode_info.audio.num_pins = 8;
1664 case CHIP_POLARIS11:
1665 adev->mode_info.audio.num_pins = 6;
1671 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1672 adev->mode_info.audio.pin[i].channels = -1;
1673 adev->mode_info.audio.pin[i].rate = -1;
1674 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1675 adev->mode_info.audio.pin[i].status_bits = 0;
1676 adev->mode_info.audio.pin[i].category_code = 0;
1677 adev->mode_info.audio.pin[i].connected = false;
1678 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1679 adev->mode_info.audio.pin[i].id = i;
1680 /* disable audio. it will be set up later */
1681 /* XXX remove once we switch to ip funcs */
1682 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1688 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1695 if (!adev->mode_info.audio.enabled)
1698 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1699 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1701 adev->mode_info.audio.enabled = false;
1705 * update the N and CTS parameters for a given pixel clock rate
1707 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1709 struct drm_device *dev = encoder->dev;
1710 struct amdgpu_device *adev = dev->dev_private;
1711 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1713 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1716 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1717 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1718 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1719 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1720 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1721 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1723 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1724 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1725 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1726 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1727 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1728 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1730 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1731 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1732 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1733 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1734 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1735 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1740 * build a HDMI Video Info Frame
1742 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1743 void *buffer, size_t size)
1745 struct drm_device *dev = encoder->dev;
1746 struct amdgpu_device *adev = dev->dev_private;
1747 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1748 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1749 uint8_t *frame = buffer + 3;
1750 uint8_t *header = buffer;
1752 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1753 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1754 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1755 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1756 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1757 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1758 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1759 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1762 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1764 struct drm_device *dev = encoder->dev;
1765 struct amdgpu_device *adev = dev->dev_private;
1766 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1767 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1768 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1769 u32 dto_phase = 24 * 1000;
1770 u32 dto_modulo = clock;
1773 if (!dig || !dig->afmt)
1776 /* XXX two dtos; generally use dto0 for hdmi */
1777 /* Express [24MHz / target pixel clock] as an exact rational
1778 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1779 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1781 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1782 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1783 amdgpu_crtc->crtc_id);
1784 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1785 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1786 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1790 * update the info frames with the data from the current display mode
1792 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1793 struct drm_display_mode *mode)
1795 struct drm_device *dev = encoder->dev;
1796 struct amdgpu_device *adev = dev->dev_private;
1797 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1798 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1799 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1800 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1801 struct hdmi_avi_infoframe frame;
1806 if (!dig || !dig->afmt)
1809 /* Silent, r600_hdmi_enable will raise WARN for us */
1810 if (!dig->afmt->enabled)
1813 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1814 if (encoder->crtc) {
1815 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1816 bpc = amdgpu_crtc->bpc;
1819 /* disable audio prior to setting up hw */
1820 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1821 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1823 dce_v11_0_audio_set_dto(encoder, mode->clock);
1825 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1826 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1827 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1829 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1831 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1838 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1839 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1840 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1841 connector->name, bpc);
1844 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1845 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1846 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1850 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1851 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1852 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1856 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1858 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1859 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1860 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1861 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1862 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1864 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1865 /* enable audio info frames (frames won't be set until audio is enabled) */
1866 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1867 /* required for audio info values to be updated */
1868 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1869 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1871 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1872 /* required for audio info values to be updated */
1873 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1874 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1876 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1877 /* anything other than 0 */
1878 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1879 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1881 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1883 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1884 /* set the default audio delay */
1885 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1886 /* should be suffient for all audio modes and small enough for all hblanks */
1887 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1888 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1890 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1891 /* allow 60958 channel status fields to be updated */
1892 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1893 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1895 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1897 /* clear SW CTS value */
1898 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1900 /* select SW CTS value */
1901 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1902 /* allow hw to sent ACR packets when required */
1903 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1904 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1906 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1908 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1909 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1910 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1912 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1913 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1914 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1916 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1917 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1918 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1919 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1920 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1921 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1922 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1923 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1925 dce_v11_0_audio_write_speaker_allocation(encoder);
1927 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1928 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1930 dce_v11_0_afmt_audio_select_pin(encoder);
1931 dce_v11_0_audio_write_sad_regs(encoder);
1932 dce_v11_0_audio_write_latency_fields(encoder, mode);
1934 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1936 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1940 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1942 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1946 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1948 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1949 /* enable AVI info frames */
1950 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1951 /* required for audio info values to be updated */
1952 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1953 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1955 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1956 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1957 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1959 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1960 /* send audio packets */
1961 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1962 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1964 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1965 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1966 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1967 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1969 /* enable audio after to setting up hw */
1970 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1973 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1975 struct drm_device *dev = encoder->dev;
1976 struct amdgpu_device *adev = dev->dev_private;
1977 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1978 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1980 if (!dig || !dig->afmt)
1983 /* Silent, r600_hdmi_enable will raise WARN for us */
1984 if (enable && dig->afmt->enabled)
1986 if (!enable && !dig->afmt->enabled)
1989 if (!enable && dig->afmt->pin) {
1990 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1991 dig->afmt->pin = NULL;
1994 dig->afmt->enabled = enable;
1996 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1997 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
2000 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
2004 for (i = 0; i < adev->mode_info.num_dig; i++)
2005 adev->mode_info.afmt[i] = NULL;
2007 /* DCE11 has audio blocks tied to DIG encoders */
2008 for (i = 0; i < adev->mode_info.num_dig; i++) {
2009 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
2010 if (adev->mode_info.afmt[i]) {
2011 adev->mode_info.afmt[i]->offset = dig_offsets[i];
2012 adev->mode_info.afmt[i]->id = i;
2015 for (j = 0; j < i; j++) {
2016 kfree(adev->mode_info.afmt[j]);
2017 adev->mode_info.afmt[j] = NULL;
2025 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
2029 for (i = 0; i < adev->mode_info.num_dig; i++) {
2030 kfree(adev->mode_info.afmt[i]);
2031 adev->mode_info.afmt[i] = NULL;
2035 static const u32 vga_control_regs[6] =
2045 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2047 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2048 struct drm_device *dev = crtc->dev;
2049 struct amdgpu_device *adev = dev->dev_private;
2052 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2054 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2056 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2059 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2061 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2062 struct drm_device *dev = crtc->dev;
2063 struct amdgpu_device *adev = dev->dev_private;
2066 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2068 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2071 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2072 struct drm_framebuffer *fb,
2073 int x, int y, int atomic)
2075 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2076 struct drm_device *dev = crtc->dev;
2077 struct amdgpu_device *adev = dev->dev_private;
2078 struct amdgpu_framebuffer *amdgpu_fb;
2079 struct drm_framebuffer *target_fb;
2080 struct drm_gem_object *obj;
2081 struct amdgpu_bo *abo;
2082 uint64_t fb_location, tiling_flags;
2083 uint32_t fb_format, fb_pitch_pixels;
2084 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2086 u32 tmp, viewport_w, viewport_h;
2088 bool bypass_lut = false;
2092 if (!atomic && !crtc->primary->fb) {
2093 DRM_DEBUG_KMS("No FB bound\n");
2098 amdgpu_fb = to_amdgpu_framebuffer(fb);
2101 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2102 target_fb = crtc->primary->fb;
2105 /* If atomic, assume fb object is pinned & idle & fenced and
2106 * just update base pointers
2108 obj = amdgpu_fb->obj;
2109 abo = gem_to_amdgpu_bo(obj);
2110 r = amdgpu_bo_reserve(abo, false);
2111 if (unlikely(r != 0))
2115 fb_location = amdgpu_bo_gpu_offset(abo);
2117 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2118 if (unlikely(r != 0)) {
2119 amdgpu_bo_unreserve(abo);
2124 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2125 amdgpu_bo_unreserve(abo);
2127 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2129 switch (target_fb->pixel_format) {
2131 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2132 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2134 case DRM_FORMAT_XRGB4444:
2135 case DRM_FORMAT_ARGB4444:
2136 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2137 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2139 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2143 case DRM_FORMAT_XRGB1555:
2144 case DRM_FORMAT_ARGB1555:
2145 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2146 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2148 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2152 case DRM_FORMAT_BGRX5551:
2153 case DRM_FORMAT_BGRA5551:
2154 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2155 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2157 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2161 case DRM_FORMAT_RGB565:
2162 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2163 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2165 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2169 case DRM_FORMAT_XRGB8888:
2170 case DRM_FORMAT_ARGB8888:
2171 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2172 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2174 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2178 case DRM_FORMAT_XRGB2101010:
2179 case DRM_FORMAT_ARGB2101010:
2180 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2181 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2183 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2186 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2189 case DRM_FORMAT_BGRX1010102:
2190 case DRM_FORMAT_BGRA1010102:
2191 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2192 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2194 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2197 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2201 format_name = drm_get_format_name(target_fb->pixel_format);
2202 DRM_ERROR("Unsupported screen format %s\n", format_name);
2207 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2208 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2210 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2211 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2212 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2213 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2214 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2216 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2217 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2218 ARRAY_2D_TILED_THIN1);
2219 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2221 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2222 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2223 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2225 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2226 ADDR_SURF_MICRO_TILING_DISPLAY);
2227 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2228 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2229 ARRAY_1D_TILED_THIN1);
2232 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2235 dce_v11_0_vga_enable(crtc, false);
2237 /* Make sure surface address is updated at vertical blank rather than
2240 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2241 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2242 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2243 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2245 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2246 upper_32_bits(fb_location));
2247 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2248 upper_32_bits(fb_location));
2249 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2250 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2251 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2252 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2253 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2254 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2257 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2258 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2259 * retain the full precision throughout the pipeline.
2261 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2263 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2265 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2266 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2269 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2271 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2272 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2273 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2274 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2275 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2276 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2278 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2279 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2281 dce_v11_0_grph_enable(crtc, true);
2283 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2288 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2290 viewport_w = crtc->mode.hdisplay;
2291 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2292 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2293 (viewport_w << 16) | viewport_h);
2295 /* set pageflip to happen anywhere in vblank interval */
2296 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2298 if (!atomic && fb && fb != crtc->primary->fb) {
2299 amdgpu_fb = to_amdgpu_framebuffer(fb);
2300 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2301 r = amdgpu_bo_reserve(abo, false);
2302 if (unlikely(r != 0))
2304 amdgpu_bo_unpin(abo);
2305 amdgpu_bo_unreserve(abo);
2308 /* Bytes per pixel may have changed */
2309 dce_v11_0_bandwidth_update(adev);
2314 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2315 struct drm_display_mode *mode)
2317 struct drm_device *dev = crtc->dev;
2318 struct amdgpu_device *adev = dev->dev_private;
2319 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2322 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2323 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2324 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2326 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2327 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2330 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2332 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2333 struct drm_device *dev = crtc->dev;
2334 struct amdgpu_device *adev = dev->dev_private;
2338 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2340 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2341 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2342 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2344 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2345 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2346 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2348 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2349 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2350 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2352 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2354 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2355 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2356 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2358 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2359 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2360 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2362 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2363 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2365 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2366 for (i = 0; i < 256; i++) {
2367 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2368 (amdgpu_crtc->lut_r[i] << 20) |
2369 (amdgpu_crtc->lut_g[i] << 10) |
2370 (amdgpu_crtc->lut_b[i] << 0));
2373 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2374 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2375 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2376 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2377 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2379 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2380 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2381 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2383 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2384 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2385 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2387 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2388 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2389 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2391 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2392 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2393 /* XXX this only needs to be programmed once per crtc at startup,
2394 * not sure where the best place for it is
2396 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2397 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2398 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2401 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2403 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2404 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2406 switch (amdgpu_encoder->encoder_id) {
2407 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2413 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2419 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2425 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2429 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2435 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2439 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2440 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2441 * monitors a dedicated PPLL must be used. If a particular board has
2442 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2443 * as there is no need to program the PLL itself. If we are not able to
2444 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2445 * avoid messing up an existing monitor.
2447 * Asic specific PLL information
2451 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2453 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2456 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2458 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2459 struct drm_device *dev = crtc->dev;
2460 struct amdgpu_device *adev = dev->dev_private;
2464 if ((adev->asic_type == CHIP_POLARIS10) ||
2465 (adev->asic_type == CHIP_POLARIS11)) {
2466 struct amdgpu_encoder *amdgpu_encoder =
2467 to_amdgpu_encoder(amdgpu_crtc->encoder);
2468 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2470 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2473 switch (amdgpu_encoder->encoder_id) {
2474 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2476 return ATOM_COMBOPHY_PLL1;
2478 return ATOM_COMBOPHY_PLL0;
2480 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2482 return ATOM_COMBOPHY_PLL3;
2484 return ATOM_COMBOPHY_PLL2;
2486 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2488 return ATOM_COMBOPHY_PLL5;
2490 return ATOM_COMBOPHY_PLL4;
2493 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2494 return ATOM_PPLL_INVALID;
2498 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2499 if (adev->clock.dp_extclk)
2500 /* skip PPLL programming if using ext clock */
2501 return ATOM_PPLL_INVALID;
2503 /* use the same PPLL for all DP monitors */
2504 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2505 if (pll != ATOM_PPLL_INVALID)
2509 /* use the same PPLL for all monitors with the same clock */
2510 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2511 if (pll != ATOM_PPLL_INVALID)
2515 /* XXX need to determine what plls are available on each DCE11 part */
2516 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2517 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2518 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2520 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2522 DRM_ERROR("unable to allocate a PPLL\n");
2523 return ATOM_PPLL_INVALID;
2525 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2527 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2529 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2531 DRM_ERROR("unable to allocate a PPLL\n");
2532 return ATOM_PPLL_INVALID;
2534 return ATOM_PPLL_INVALID;
2537 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2539 struct amdgpu_device *adev = crtc->dev->dev_private;
2540 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2543 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2545 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2547 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2548 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2551 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2553 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2554 struct amdgpu_device *adev = crtc->dev->dev_private;
2557 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2558 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2559 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2562 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2564 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2565 struct amdgpu_device *adev = crtc->dev->dev_private;
2568 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2569 upper_32_bits(amdgpu_crtc->cursor_addr));
2570 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2571 lower_32_bits(amdgpu_crtc->cursor_addr));
2573 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2574 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2575 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2576 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2579 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2582 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2583 struct amdgpu_device *adev = crtc->dev->dev_private;
2584 int xorigin = 0, yorigin = 0;
2586 amdgpu_crtc->cursor_x = x;
2587 amdgpu_crtc->cursor_y = y;
2589 /* avivo cursor are offset into the total surface */
2592 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2595 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2599 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2603 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2604 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2605 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2606 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2611 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2616 dce_v11_0_lock_cursor(crtc, true);
2617 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2618 dce_v11_0_lock_cursor(crtc, false);
2623 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2624 struct drm_file *file_priv,
2631 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2632 struct drm_gem_object *obj;
2633 struct amdgpu_bo *aobj;
2637 /* turn off cursor */
2638 dce_v11_0_hide_cursor(crtc);
2643 if ((width > amdgpu_crtc->max_cursor_width) ||
2644 (height > amdgpu_crtc->max_cursor_height)) {
2645 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2649 obj = drm_gem_object_lookup(file_priv, handle);
2651 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2655 aobj = gem_to_amdgpu_bo(obj);
2656 ret = amdgpu_bo_reserve(aobj, false);
2658 drm_gem_object_unreference_unlocked(obj);
2662 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2663 amdgpu_bo_unreserve(aobj);
2665 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2666 drm_gem_object_unreference_unlocked(obj);
2670 dce_v11_0_lock_cursor(crtc, true);
2672 if (width != amdgpu_crtc->cursor_width ||
2673 height != amdgpu_crtc->cursor_height ||
2674 hot_x != amdgpu_crtc->cursor_hot_x ||
2675 hot_y != amdgpu_crtc->cursor_hot_y) {
2678 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2679 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2681 dce_v11_0_cursor_move_locked(crtc, x, y);
2683 amdgpu_crtc->cursor_width = width;
2684 amdgpu_crtc->cursor_height = height;
2685 amdgpu_crtc->cursor_hot_x = hot_x;
2686 amdgpu_crtc->cursor_hot_y = hot_y;
2689 dce_v11_0_show_cursor(crtc);
2690 dce_v11_0_lock_cursor(crtc, false);
2693 if (amdgpu_crtc->cursor_bo) {
2694 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2695 ret = amdgpu_bo_reserve(aobj, false);
2696 if (likely(ret == 0)) {
2697 amdgpu_bo_unpin(aobj);
2698 amdgpu_bo_unreserve(aobj);
2700 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2703 amdgpu_crtc->cursor_bo = obj;
2707 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2709 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2711 if (amdgpu_crtc->cursor_bo) {
2712 dce_v11_0_lock_cursor(crtc, true);
2714 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2715 amdgpu_crtc->cursor_y);
2717 dce_v11_0_show_cursor(crtc);
2719 dce_v11_0_lock_cursor(crtc, false);
2723 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2724 u16 *blue, uint32_t size)
2726 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2729 /* userspace palettes are always correct as is */
2730 for (i = 0; i < size; i++) {
2731 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2732 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2733 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2735 dce_v11_0_crtc_load_lut(crtc);
2740 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2742 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2744 drm_crtc_cleanup(crtc);
2748 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2749 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2750 .cursor_move = dce_v11_0_crtc_cursor_move,
2751 .gamma_set = dce_v11_0_crtc_gamma_set,
2752 .set_config = amdgpu_crtc_set_config,
2753 .destroy = dce_v11_0_crtc_destroy,
2754 .page_flip_target = amdgpu_crtc_page_flip_target,
2757 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2759 struct drm_device *dev = crtc->dev;
2760 struct amdgpu_device *adev = dev->dev_private;
2761 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2765 case DRM_MODE_DPMS_ON:
2766 amdgpu_crtc->enabled = true;
2767 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2768 dce_v11_0_vga_enable(crtc, true);
2769 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2770 dce_v11_0_vga_enable(crtc, false);
2771 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2772 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2773 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2774 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2775 drm_crtc_vblank_on(crtc);
2776 dce_v11_0_crtc_load_lut(crtc);
2778 case DRM_MODE_DPMS_STANDBY:
2779 case DRM_MODE_DPMS_SUSPEND:
2780 case DRM_MODE_DPMS_OFF:
2781 drm_crtc_vblank_off(crtc);
2782 if (amdgpu_crtc->enabled) {
2783 dce_v11_0_vga_enable(crtc, true);
2784 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2785 dce_v11_0_vga_enable(crtc, false);
2787 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2788 amdgpu_crtc->enabled = false;
2791 /* adjust pm to dpms */
2792 amdgpu_pm_compute_clocks(adev);
2795 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2797 /* disable crtc pair power gating before programming */
2798 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2799 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2800 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2803 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2805 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2806 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2809 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2811 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2812 struct drm_device *dev = crtc->dev;
2813 struct amdgpu_device *adev = dev->dev_private;
2814 struct amdgpu_atom_ss ss;
2817 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2818 if (crtc->primary->fb) {
2820 struct amdgpu_framebuffer *amdgpu_fb;
2821 struct amdgpu_bo *abo;
2823 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2824 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2825 r = amdgpu_bo_reserve(abo, false);
2827 DRM_ERROR("failed to reserve abo before unpin\n");
2829 amdgpu_bo_unpin(abo);
2830 amdgpu_bo_unreserve(abo);
2833 /* disable the GRPH */
2834 dce_v11_0_grph_enable(crtc, false);
2836 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2838 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2839 if (adev->mode_info.crtcs[i] &&
2840 adev->mode_info.crtcs[i]->enabled &&
2841 i != amdgpu_crtc->crtc_id &&
2842 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2843 /* one other crtc is using this pll don't turn
2850 switch (amdgpu_crtc->pll_id) {
2854 /* disable the ppll */
2855 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2856 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2858 case ATOM_COMBOPHY_PLL0:
2859 case ATOM_COMBOPHY_PLL1:
2860 case ATOM_COMBOPHY_PLL2:
2861 case ATOM_COMBOPHY_PLL3:
2862 case ATOM_COMBOPHY_PLL4:
2863 case ATOM_COMBOPHY_PLL5:
2864 /* disable the ppll */
2865 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2866 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2872 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2873 amdgpu_crtc->adjusted_clock = 0;
2874 amdgpu_crtc->encoder = NULL;
2875 amdgpu_crtc->connector = NULL;
2878 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2879 struct drm_display_mode *mode,
2880 struct drm_display_mode *adjusted_mode,
2881 int x, int y, struct drm_framebuffer *old_fb)
2883 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2884 struct drm_device *dev = crtc->dev;
2885 struct amdgpu_device *adev = dev->dev_private;
2887 if (!amdgpu_crtc->adjusted_clock)
2890 if ((adev->asic_type == CHIP_POLARIS10) ||
2891 (adev->asic_type == CHIP_POLARIS11)) {
2892 struct amdgpu_encoder *amdgpu_encoder =
2893 to_amdgpu_encoder(amdgpu_crtc->encoder);
2895 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2897 /* SetPixelClock calculates the plls and ss values now */
2898 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2899 amdgpu_crtc->pll_id,
2900 encoder_mode, amdgpu_encoder->encoder_id,
2901 adjusted_mode->clock, 0, 0, 0, 0,
2902 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2904 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2906 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2907 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2908 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2909 amdgpu_atombios_crtc_scaler_setup(crtc);
2910 dce_v11_0_cursor_reset(crtc);
2911 /* update the hw version fpr dpm */
2912 amdgpu_crtc->hw_mode = *adjusted_mode;
2917 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2918 const struct drm_display_mode *mode,
2919 struct drm_display_mode *adjusted_mode)
2921 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2922 struct drm_device *dev = crtc->dev;
2923 struct drm_encoder *encoder;
2925 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2926 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2927 if (encoder->crtc == crtc) {
2928 amdgpu_crtc->encoder = encoder;
2929 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2933 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2934 amdgpu_crtc->encoder = NULL;
2935 amdgpu_crtc->connector = NULL;
2938 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2940 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2943 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2944 /* if we can't get a PPLL for a non-DP encoder, fail */
2945 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2946 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2952 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2953 struct drm_framebuffer *old_fb)
2955 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2958 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2959 struct drm_framebuffer *fb,
2960 int x, int y, enum mode_set_atomic state)
2962 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2965 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2966 .dpms = dce_v11_0_crtc_dpms,
2967 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2968 .mode_set = dce_v11_0_crtc_mode_set,
2969 .mode_set_base = dce_v11_0_crtc_set_base,
2970 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2971 .prepare = dce_v11_0_crtc_prepare,
2972 .commit = dce_v11_0_crtc_commit,
2973 .load_lut = dce_v11_0_crtc_load_lut,
2974 .disable = dce_v11_0_crtc_disable,
2977 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2979 struct amdgpu_crtc *amdgpu_crtc;
2982 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2983 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2984 if (amdgpu_crtc == NULL)
2987 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2989 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2990 amdgpu_crtc->crtc_id = index;
2991 adev->mode_info.crtcs[index] = amdgpu_crtc;
2993 amdgpu_crtc->max_cursor_width = 128;
2994 amdgpu_crtc->max_cursor_height = 128;
2995 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2996 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2998 for (i = 0; i < 256; i++) {
2999 amdgpu_crtc->lut_r[i] = i << 2;
3000 amdgpu_crtc->lut_g[i] = i << 2;
3001 amdgpu_crtc->lut_b[i] = i << 2;
3004 switch (amdgpu_crtc->crtc_id) {
3007 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
3010 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
3013 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
3016 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
3019 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
3022 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
3026 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
3027 amdgpu_crtc->adjusted_clock = 0;
3028 amdgpu_crtc->encoder = NULL;
3029 amdgpu_crtc->connector = NULL;
3030 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
3035 static int dce_v11_0_early_init(void *handle)
3037 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3039 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
3040 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
3042 dce_v11_0_set_display_funcs(adev);
3043 dce_v11_0_set_irq_funcs(adev);
3045 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
3047 switch (adev->asic_type) {
3049 adev->mode_info.num_hpd = 6;
3050 adev->mode_info.num_dig = 9;
3053 adev->mode_info.num_hpd = 6;
3054 adev->mode_info.num_dig = 9;
3056 case CHIP_POLARIS10:
3057 adev->mode_info.num_hpd = 6;
3058 adev->mode_info.num_dig = 6;
3060 case CHIP_POLARIS11:
3061 adev->mode_info.num_hpd = 5;
3062 adev->mode_info.num_dig = 5;
3065 /* FIXME: not supported yet */
3072 static int dce_v11_0_sw_init(void *handle)
3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3077 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3078 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3083 for (i = 8; i < 20; i += 2) {
3084 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3090 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3094 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3096 adev->ddev->mode_config.async_page_flip = true;
3098 adev->ddev->mode_config.max_width = 16384;
3099 adev->ddev->mode_config.max_height = 16384;
3101 adev->ddev->mode_config.preferred_depth = 24;
3102 adev->ddev->mode_config.prefer_shadow = 1;
3104 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3106 r = amdgpu_modeset_create_props(adev);
3110 adev->ddev->mode_config.max_width = 16384;
3111 adev->ddev->mode_config.max_height = 16384;
3114 /* allocate crtcs */
3115 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3116 r = dce_v11_0_crtc_init(adev, i);
3121 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3122 amdgpu_print_display_setup(adev->ddev);
3127 r = dce_v11_0_afmt_init(adev);
3131 r = dce_v11_0_audio_init(adev);
3135 drm_kms_helper_poll_init(adev->ddev);
3137 adev->mode_info.mode_config_initialized = true;
3141 static int dce_v11_0_sw_fini(void *handle)
3143 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3145 kfree(adev->mode_info.bios_hardcoded_edid);
3147 drm_kms_helper_poll_fini(adev->ddev);
3149 dce_v11_0_audio_fini(adev);
3151 dce_v11_0_afmt_fini(adev);
3153 drm_mode_config_cleanup(adev->ddev);
3154 adev->mode_info.mode_config_initialized = false;
3159 static int dce_v11_0_hw_init(void *handle)
3162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3164 dce_v11_0_init_golden_registers(adev);
3166 /* init dig PHYs, disp eng pll */
3167 amdgpu_atombios_crtc_powergate_init(adev);
3168 amdgpu_atombios_encoder_init_dig(adev);
3169 if ((adev->asic_type == CHIP_POLARIS10) ||
3170 (adev->asic_type == CHIP_POLARIS11)) {
3171 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3172 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3173 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3174 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3176 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3179 /* initialize hpd */
3180 dce_v11_0_hpd_init(adev);
3182 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3183 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3186 dce_v11_0_pageflip_interrupt_init(adev);
3191 static int dce_v11_0_hw_fini(void *handle)
3194 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3196 dce_v11_0_hpd_fini(adev);
3198 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3199 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3202 dce_v11_0_pageflip_interrupt_fini(adev);
3207 static int dce_v11_0_suspend(void *handle)
3209 return dce_v11_0_hw_fini(handle);
3212 static int dce_v11_0_resume(void *handle)
3214 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3217 ret = dce_v11_0_hw_init(handle);
3219 /* turn on the BL */
3220 if (adev->mode_info.bl_encoder) {
3221 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3222 adev->mode_info.bl_encoder);
3223 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3230 static bool dce_v11_0_is_idle(void *handle)
3235 static int dce_v11_0_wait_for_idle(void *handle)
3240 static int dce_v11_0_soft_reset(void *handle)
3242 u32 srbm_soft_reset = 0, tmp;
3243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3245 if (dce_v11_0_is_display_hung(adev))
3246 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3248 if (srbm_soft_reset) {
3249 tmp = RREG32(mmSRBM_SOFT_RESET);
3250 tmp |= srbm_soft_reset;
3251 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3252 WREG32(mmSRBM_SOFT_RESET, tmp);
3253 tmp = RREG32(mmSRBM_SOFT_RESET);
3257 tmp &= ~srbm_soft_reset;
3258 WREG32(mmSRBM_SOFT_RESET, tmp);
3259 tmp = RREG32(mmSRBM_SOFT_RESET);
3261 /* Wait a little for things to settle down */
3267 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3269 enum amdgpu_interrupt_state state)
3271 u32 lb_interrupt_mask;
3273 if (crtc >= adev->mode_info.num_crtc) {
3274 DRM_DEBUG("invalid crtc %d\n", crtc);
3279 case AMDGPU_IRQ_STATE_DISABLE:
3280 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3281 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3282 VBLANK_INTERRUPT_MASK, 0);
3283 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3285 case AMDGPU_IRQ_STATE_ENABLE:
3286 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3287 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3288 VBLANK_INTERRUPT_MASK, 1);
3289 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3296 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3298 enum amdgpu_interrupt_state state)
3300 u32 lb_interrupt_mask;
3302 if (crtc >= adev->mode_info.num_crtc) {
3303 DRM_DEBUG("invalid crtc %d\n", crtc);
3308 case AMDGPU_IRQ_STATE_DISABLE:
3309 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3310 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3311 VLINE_INTERRUPT_MASK, 0);
3312 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3314 case AMDGPU_IRQ_STATE_ENABLE:
3315 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3316 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3317 VLINE_INTERRUPT_MASK, 1);
3318 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3325 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3326 struct amdgpu_irq_src *source,
3328 enum amdgpu_interrupt_state state)
3332 if (hpd >= adev->mode_info.num_hpd) {
3333 DRM_DEBUG("invalid hdp %d\n", hpd);
3338 case AMDGPU_IRQ_STATE_DISABLE:
3339 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3340 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3343 case AMDGPU_IRQ_STATE_ENABLE:
3344 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3345 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3346 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3355 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3356 struct amdgpu_irq_src *source,
3358 enum amdgpu_interrupt_state state)
3361 case AMDGPU_CRTC_IRQ_VBLANK1:
3362 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3364 case AMDGPU_CRTC_IRQ_VBLANK2:
3365 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3367 case AMDGPU_CRTC_IRQ_VBLANK3:
3368 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3370 case AMDGPU_CRTC_IRQ_VBLANK4:
3371 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3373 case AMDGPU_CRTC_IRQ_VBLANK5:
3374 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3376 case AMDGPU_CRTC_IRQ_VBLANK6:
3377 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3379 case AMDGPU_CRTC_IRQ_VLINE1:
3380 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3382 case AMDGPU_CRTC_IRQ_VLINE2:
3383 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3385 case AMDGPU_CRTC_IRQ_VLINE3:
3386 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3388 case AMDGPU_CRTC_IRQ_VLINE4:
3389 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3391 case AMDGPU_CRTC_IRQ_VLINE5:
3392 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3394 case AMDGPU_CRTC_IRQ_VLINE6:
3395 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3403 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3404 struct amdgpu_irq_src *src,
3406 enum amdgpu_interrupt_state state)
3410 if (type >= adev->mode_info.num_crtc) {
3411 DRM_ERROR("invalid pageflip crtc %d\n", type);
3415 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3416 if (state == AMDGPU_IRQ_STATE_DISABLE)
3417 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3418 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3420 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3421 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3426 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3427 struct amdgpu_irq_src *source,
3428 struct amdgpu_iv_entry *entry)
3430 unsigned long flags;
3432 struct amdgpu_crtc *amdgpu_crtc;
3433 struct amdgpu_flip_work *works;
3435 crtc_id = (entry->src_id - 8) >> 1;
3436 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3438 if (crtc_id >= adev->mode_info.num_crtc) {
3439 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3443 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3444 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3445 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3446 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3448 /* IRQ could occur when in initial stage */
3449 if(amdgpu_crtc == NULL)
3452 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3453 works = amdgpu_crtc->pflip_works;
3454 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3455 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3456 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3457 amdgpu_crtc->pflip_status,
3458 AMDGPU_FLIP_SUBMITTED);
3459 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3463 /* page flip completed. clean up */
3464 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3465 amdgpu_crtc->pflip_works = NULL;
3467 /* wakeup usersapce */
3469 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3471 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3473 drm_crtc_vblank_put(&amdgpu_crtc->base);
3474 schedule_work(&works->unpin_work);
3479 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3484 if (hpd >= adev->mode_info.num_hpd) {
3485 DRM_DEBUG("invalid hdp %d\n", hpd);
3489 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3490 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3491 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3494 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3499 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3500 DRM_DEBUG("invalid crtc %d\n", crtc);
3504 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3505 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3506 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3509 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3514 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3515 DRM_DEBUG("invalid crtc %d\n", crtc);
3519 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3520 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3521 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3524 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3525 struct amdgpu_irq_src *source,
3526 struct amdgpu_iv_entry *entry)
3528 unsigned crtc = entry->src_id - 1;
3529 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3530 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3532 switch (entry->src_data) {
3533 case 0: /* vblank */
3534 if (disp_int & interrupt_status_offsets[crtc].vblank)
3535 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3537 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3539 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3540 drm_handle_vblank(adev->ddev, crtc);
3542 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3546 if (disp_int & interrupt_status_offsets[crtc].vline)
3547 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3549 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3551 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3555 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3562 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3563 struct amdgpu_irq_src *source,
3564 struct amdgpu_iv_entry *entry)
3566 uint32_t disp_int, mask;
3569 if (entry->src_data >= adev->mode_info.num_hpd) {
3570 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3574 hpd = entry->src_data;
3575 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3576 mask = interrupt_status_offsets[hpd].hpd;
3578 if (disp_int & mask) {
3579 dce_v11_0_hpd_int_ack(adev, hpd);
3580 schedule_work(&adev->hotplug_work);
3581 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3587 static int dce_v11_0_set_clockgating_state(void *handle,
3588 enum amd_clockgating_state state)
3593 static int dce_v11_0_set_powergating_state(void *handle,
3594 enum amd_powergating_state state)
3599 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3600 .name = "dce_v11_0",
3601 .early_init = dce_v11_0_early_init,
3603 .sw_init = dce_v11_0_sw_init,
3604 .sw_fini = dce_v11_0_sw_fini,
3605 .hw_init = dce_v11_0_hw_init,
3606 .hw_fini = dce_v11_0_hw_fini,
3607 .suspend = dce_v11_0_suspend,
3608 .resume = dce_v11_0_resume,
3609 .is_idle = dce_v11_0_is_idle,
3610 .wait_for_idle = dce_v11_0_wait_for_idle,
3611 .soft_reset = dce_v11_0_soft_reset,
3612 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3613 .set_powergating_state = dce_v11_0_set_powergating_state,
3617 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3618 struct drm_display_mode *mode,
3619 struct drm_display_mode *adjusted_mode)
3621 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3623 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3625 /* need to call this here rather than in prepare() since we need some crtc info */
3626 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3628 /* set scaler clears this on some chips */
3629 dce_v11_0_set_interleave(encoder->crtc, mode);
3631 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3632 dce_v11_0_afmt_enable(encoder, true);
3633 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3637 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3639 struct amdgpu_device *adev = encoder->dev->dev_private;
3640 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3641 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3643 if ((amdgpu_encoder->active_device &
3644 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3645 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3646 ENCODER_OBJECT_ID_NONE)) {
3647 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3649 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3650 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3651 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3655 amdgpu_atombios_scratch_regs_lock(adev, true);
3658 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3660 /* select the clock/data port if it uses a router */
3661 if (amdgpu_connector->router.cd_valid)
3662 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3664 /* turn eDP panel on for mode set */
3665 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3666 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3667 ATOM_TRANSMITTER_ACTION_POWER_ON);
3670 /* this is needed for the pll/ss setup to work correctly in some cases */
3671 amdgpu_atombios_encoder_set_crtc_source(encoder);
3672 /* set up the FMT blocks */
3673 dce_v11_0_program_fmt(encoder);
3676 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3678 struct drm_device *dev = encoder->dev;
3679 struct amdgpu_device *adev = dev->dev_private;
3681 /* need to call this here as we need the crtc set up */
3682 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3683 amdgpu_atombios_scratch_regs_lock(adev, false);
3686 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3688 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3689 struct amdgpu_encoder_atom_dig *dig;
3691 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3693 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3694 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3695 dce_v11_0_afmt_enable(encoder, false);
3696 dig = amdgpu_encoder->enc_priv;
3697 dig->dig_encoder = -1;
3699 amdgpu_encoder->active_device = 0;
3702 /* these are handled by the primary encoders */
3703 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3708 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3714 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3715 struct drm_display_mode *mode,
3716 struct drm_display_mode *adjusted_mode)
3721 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3727 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3732 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3733 .dpms = dce_v11_0_ext_dpms,
3734 .prepare = dce_v11_0_ext_prepare,
3735 .mode_set = dce_v11_0_ext_mode_set,
3736 .commit = dce_v11_0_ext_commit,
3737 .disable = dce_v11_0_ext_disable,
3738 /* no detect for TMDS/LVDS yet */
3741 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3742 .dpms = amdgpu_atombios_encoder_dpms,
3743 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3744 .prepare = dce_v11_0_encoder_prepare,
3745 .mode_set = dce_v11_0_encoder_mode_set,
3746 .commit = dce_v11_0_encoder_commit,
3747 .disable = dce_v11_0_encoder_disable,
3748 .detect = amdgpu_atombios_encoder_dig_detect,
3751 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3752 .dpms = amdgpu_atombios_encoder_dpms,
3753 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3754 .prepare = dce_v11_0_encoder_prepare,
3755 .mode_set = dce_v11_0_encoder_mode_set,
3756 .commit = dce_v11_0_encoder_commit,
3757 .detect = amdgpu_atombios_encoder_dac_detect,
3760 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3762 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3763 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3764 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3765 kfree(amdgpu_encoder->enc_priv);
3766 drm_encoder_cleanup(encoder);
3767 kfree(amdgpu_encoder);
3770 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3771 .destroy = dce_v11_0_encoder_destroy,
3774 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3775 uint32_t encoder_enum,
3776 uint32_t supported_device,
3779 struct drm_device *dev = adev->ddev;
3780 struct drm_encoder *encoder;
3781 struct amdgpu_encoder *amdgpu_encoder;
3783 /* see if we already added it */
3784 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3785 amdgpu_encoder = to_amdgpu_encoder(encoder);
3786 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3787 amdgpu_encoder->devices |= supported_device;
3794 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3795 if (!amdgpu_encoder)
3798 encoder = &amdgpu_encoder->base;
3799 switch (adev->mode_info.num_crtc) {
3801 encoder->possible_crtcs = 0x1;
3805 encoder->possible_crtcs = 0x3;
3808 encoder->possible_crtcs = 0x7;
3811 encoder->possible_crtcs = 0xf;
3814 encoder->possible_crtcs = 0x1f;
3817 encoder->possible_crtcs = 0x3f;
3821 amdgpu_encoder->enc_priv = NULL;
3823 amdgpu_encoder->encoder_enum = encoder_enum;
3824 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3825 amdgpu_encoder->devices = supported_device;
3826 amdgpu_encoder->rmx_type = RMX_OFF;
3827 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3828 amdgpu_encoder->is_ext_encoder = false;
3829 amdgpu_encoder->caps = caps;
3831 switch (amdgpu_encoder->encoder_id) {
3832 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3833 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3834 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3835 DRM_MODE_ENCODER_DAC, NULL);
3836 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3838 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3839 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3840 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3841 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3842 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3843 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3844 amdgpu_encoder->rmx_type = RMX_FULL;
3845 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3846 DRM_MODE_ENCODER_LVDS, NULL);
3847 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3848 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3849 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3850 DRM_MODE_ENCODER_DAC, NULL);
3851 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3853 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3854 DRM_MODE_ENCODER_TMDS, NULL);
3855 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3857 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3859 case ENCODER_OBJECT_ID_SI170B:
3860 case ENCODER_OBJECT_ID_CH7303:
3861 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3862 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3863 case ENCODER_OBJECT_ID_TITFP513:
3864 case ENCODER_OBJECT_ID_VT1623:
3865 case ENCODER_OBJECT_ID_HDMI_SI1930:
3866 case ENCODER_OBJECT_ID_TRAVIS:
3867 case ENCODER_OBJECT_ID_NUTMEG:
3868 /* these are handled by the primary encoders */
3869 amdgpu_encoder->is_ext_encoder = true;
3870 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3871 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3872 DRM_MODE_ENCODER_LVDS, NULL);
3873 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3874 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3875 DRM_MODE_ENCODER_DAC, NULL);
3877 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3878 DRM_MODE_ENCODER_TMDS, NULL);
3879 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3884 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3885 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3886 .bandwidth_update = &dce_v11_0_bandwidth_update,
3887 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3888 .vblank_wait = &dce_v11_0_vblank_wait,
3889 .is_display_hung = &dce_v11_0_is_display_hung,
3890 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3891 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3892 .hpd_sense = &dce_v11_0_hpd_sense,
3893 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3894 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3895 .page_flip = &dce_v11_0_page_flip,
3896 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3897 .add_encoder = &dce_v11_0_encoder_add,
3898 .add_connector = &amdgpu_connector_add,
3899 .stop_mc_access = &dce_v11_0_stop_mc_access,
3900 .resume_mc_access = &dce_v11_0_resume_mc_access,
3903 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3905 if (adev->mode_info.funcs == NULL)
3906 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3909 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3910 .set = dce_v11_0_set_crtc_irq_state,
3911 .process = dce_v11_0_crtc_irq,
3914 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3915 .set = dce_v11_0_set_pageflip_irq_state,
3916 .process = dce_v11_0_pageflip_irq,
3919 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3920 .set = dce_v11_0_set_hpd_irq_state,
3921 .process = dce_v11_0_hpd_irq,
3924 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3926 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3927 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3929 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3930 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3932 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3933 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;