drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_10_0_d.h"
  36 #include "dce/dce_10_0_sh_mask.h"
  37 #include "dce/dce_10_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET
  75 };
  76
  77 static const struct {
  78         uint32_t        reg;
  79         uint32_t        vblank;
  80         uint32_t        vline;
  81         uint32_t        hpd;
  82
  83 } interrupt_status_offsets[] = { {
  84         .reg = mmDISP_INTERRUPT_STATUS,
  85         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  86         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  87         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  88 }, {
  89         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  90         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  91         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  92         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  93 }, {
  94         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  95         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 113 } };
 114
 115 static const u32 golden_settings_tonga_a11[] =
 116 {
 117         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 118         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 119         mmFBC_MISC, 0x1f311fff, 0x12300000,
 120         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 121 };
 122
 123 static const u32 tonga_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 golden_settings_fiji_a10[] =
 130 {
 131         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 132         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 133         mmFBC_MISC, 0x1f311fff, 0x12300000,
 134         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 135 };
 136
 137 static const u32 fiji_mgcg_cgcg_init[] =
 138 {
 139         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 140         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 141 };
 142
 143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 144 {
 145         switch (adev->asic_type) {
 146         case CHIP_FIJI:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  fiji_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 150                 amdgpu_program_register_sequence(adev,
 151                                                  golden_settings_fiji_a10,
 152                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 153                 break;
 154         case CHIP_TONGA:
 155                 amdgpu_program_register_sequence(adev,
 156                                                  tonga_mgcg_cgcg_init,
 157                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 158                 amdgpu_program_register_sequence(adev,
 159                                                  golden_settings_tonga_a11,
 160                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 168                                      u32 block_offset, u32 reg)
 169 {
 170         unsigned long flags;
 171         u32 r;
 172
 173         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 174         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 175         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 176         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 177
 178         return r;
 179 }
 180
 181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 182                                       u32 block_offset, u32 reg, u32 v)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 187         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 188         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 189         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 190 }
 191
 192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 193 {
 194         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 195                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 196                 return true;
 197         else
 198                 return false;
 199 }
 200
 201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 202 {
 203         u32 pos1, pos2;
 204
 205         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 206         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 207
 208         if (pos1 != pos2)
 209                 return true;
 210         else
 211                 return false;
 212 }
 213
 214 /**
 215  * dce_v10_0_vblank_wait - vblank wait asic callback.
 216  *
 217  * @adev: amdgpu_device pointer
 218  * @crtc: crtc to wait for vblank on
 219  *
 220  * Wait for vblank on the requested crtc (evergreen+).
 221  */
 222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 223 {
 224         unsigned i = 100;
 225
 226         if (crtc >= adev->mode_info.num_crtc)
 227                 return;
 228
 229         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 230                 return;
 231
 232         /* depending on when we hit vblank, we may be close to active; if so,
 233          * wait for another frame.
 234          */
 235         while (dce_v10_0_is_in_vblank(adev, crtc)) {
 236                 if (i++ == 100) {
 237                         i = 0;
 238                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 239                                 break;
 240                 }
 241         }
 242
 243         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
 244                 if (i++ == 100) {
 245                         i = 0;
 246                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 247                                 break;
 248                 }
 249         }
 250 }
 251
 252 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 253 {
 254         if (crtc >= adev->mode_info.num_crtc)
 255                 return 0;
 256         else
 257                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 258 }
 259
 260 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 261 {
 262         unsigned i;
 263
 264         /* Enable pflip interrupts */
 265         for (i = 0; i < adev->mode_info.num_crtc; i++)
 266                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 267 }
 268
 269 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 270 {
 271         unsigned i;
 272
 273         /* Disable pflip interrupts */
 274         for (i = 0; i < adev->mode_info.num_crtc; i++)
 275                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 276 }
 277
 278 /**
 279  * dce_v10_0_page_flip - pageflip callback.
 280  *
 281  * @adev: amdgpu_device pointer
 282  * @crtc_id: crtc to cleanup pageflip on
 283  * @crtc_base: new address of the crtc (GPU MC address)
 284  *
 285  * Triggers the actual pageflip by updating the primary
 286  * surface base address.
 287  */
 288 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 289                                 int crtc_id, u64 crtc_base, bool async)
 290 {
 291         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 292         u32 tmp;
 293
 294         /* flip at hsync for async, default is vsync */
 295         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 296         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 297                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
 298         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 299         /* update the primary scanout address */
 300         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 301                upper_32_bits(crtc_base));
 302         /* writing to the low address triggers the update */
 303         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 304                lower_32_bits(crtc_base));
 305         /* post the write */
 306         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 307 }
 308
 309 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 310                                         u32 *vbl, u32 *position)
 311 {
 312         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 313                 return -EINVAL;
 314
 315         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 316         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 317
 318         return 0;
 319 }
 320
 321 /**
 322  * dce_v10_0_hpd_sense - hpd sense callback.
 323  *
 324  * @adev: amdgpu_device pointer
 325  * @hpd: hpd (hotplug detect) pin
 326  *
 327  * Checks if a digital monitor is connected (evergreen+).
 328  * Returns true if connected, false if not connected.
 329  */
 330 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 331                                enum amdgpu_hpd_id hpd)
 332 {
 333         int idx;
 334         bool connected = false;
 335
 336         switch (hpd) {
 337         case AMDGPU_HPD_1:
 338                 idx = 0;
 339                 break;
 340         case AMDGPU_HPD_2:
 341                 idx = 1;
 342                 break;
 343         case AMDGPU_HPD_3:
 344                 idx = 2;
 345                 break;
 346         case AMDGPU_HPD_4:
 347                 idx = 3;
 348                 break;
 349         case AMDGPU_HPD_5:
 350                 idx = 4;
 351                 break;
 352         case AMDGPU_HPD_6:
 353                 idx = 5;
 354                 break;
 355         default:
 356                 return connected;
 357         }
 358
 359         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 360             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 361                 connected = true;
 362
 363         return connected;
 364 }
 365
 366 /**
 367  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 368  *
 369  * @adev: amdgpu_device pointer
 370  * @hpd: hpd (hotplug detect) pin
 371  *
 372  * Set the polarity of the hpd pin (evergreen+).
 373  */
 374 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 375                                       enum amdgpu_hpd_id hpd)
 376 {
 377         u32 tmp;
 378         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 379         int idx;
 380
 381         switch (hpd) {
 382         case AMDGPU_HPD_1:
 383                 idx = 0;
 384                 break;
 385         case AMDGPU_HPD_2:
 386                 idx = 1;
 387                 break;
 388         case AMDGPU_HPD_3:
 389                 idx = 2;
 390                 break;
 391         case AMDGPU_HPD_4:
 392                 idx = 3;
 393                 break;
 394         case AMDGPU_HPD_5:
 395                 idx = 4;
 396                 break;
 397         case AMDGPU_HPD_6:
 398                 idx = 5;
 399                 break;
 400         default:
 401                 return;
 402         }
 403
 404         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 405         if (connected)
 406                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 407         else
 408                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 409         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 410 }
 411
 412 /**
 413  * dce_v10_0_hpd_init - hpd setup callback.
 414  *
 415  * @adev: amdgpu_device pointer
 416  *
 417  * Setup the hpd pins used by the card (evergreen+).
 418  * Enable the pin, set the polarity, and enable the hpd interrupts.
 419  */
 420 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 421 {
 422         struct drm_device *dev = adev->ddev;
 423         struct drm_connector *connector;
 424         u32 tmp;
 425         int idx;
 426
 427         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 428                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 429
 430                 switch (amdgpu_connector->hpd.hpd) {
 431                 case AMDGPU_HPD_1:
 432                         idx = 0;
 433                         break;
 434                 case AMDGPU_HPD_2:
 435                         idx = 1;
 436                         break;
 437                 case AMDGPU_HPD_3:
 438                         idx = 2;
 439                         break;
 440                 case AMDGPU_HPD_4:
 441                         idx = 3;
 442                         break;
 443                 case AMDGPU_HPD_5:
 444                         idx = 4;
 445                         break;
 446                 case AMDGPU_HPD_6:
 447                         idx = 5;
 448                         break;
 449                 default:
 450                         continue;
 451                 }
 452
 453                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 454                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 455                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 456                          * aux dp channel on imac and help (but not completely fix)
 457                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 458                          * also avoid interrupt storms during dpms.
 459                          */
 460                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 461                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 462                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 463                         continue;
 464                 }
 465
 466                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 467                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 468                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 469
 470                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 471                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 472                                     DC_HPD_CONNECT_INT_DELAY,
 473                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 474                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 475                                     DC_HPD_DISCONNECT_INT_DELAY,
 476                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 477                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 478
 479                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 480                 amdgpu_irq_get(adev, &adev->hpd_irq,
 481                                amdgpu_connector->hpd.hpd);
 482         }
 483 }
 484
 485 /**
 486  * dce_v10_0_hpd_fini - hpd tear down callback.
 487  *
 488  * @adev: amdgpu_device pointer
 489  *
 490  * Tear down the hpd pins used by the card (evergreen+).
 491  * Disable the hpd interrupts.
 492  */
 493 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 494 {
 495         struct drm_device *dev = adev->ddev;
 496         struct drm_connector *connector;
 497         u32 tmp;
 498         int idx;
 499
 500         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 501                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 502
 503                 switch (amdgpu_connector->hpd.hpd) {
 504                 case AMDGPU_HPD_1:
 505                         idx = 0;
 506                         break;
 507                 case AMDGPU_HPD_2:
 508                         idx = 1;
 509                         break;
 510                 case AMDGPU_HPD_3:
 511                         idx = 2;
 512                         break;
 513                 case AMDGPU_HPD_4:
 514                         idx = 3;
 515                         break;
 516                 case AMDGPU_HPD_5:
 517                         idx = 4;
 518                         break;
 519                 case AMDGPU_HPD_6:
 520                         idx = 5;
 521                         break;
 522                 default:
 523                         continue;
 524                 }
 525
 526                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 527                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 528                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 529
 530                 amdgpu_irq_put(adev, &adev->hpd_irq,
 531                                amdgpu_connector->hpd.hpd);
 532         }
 533 }
 534
 535 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 536 {
 537         return mmDC_GPIO_HPD_A;
 538 }
 539
 540 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 541 {
 542         u32 crtc_hung = 0;
 543         u32 crtc_status[6];
 544         u32 i, j, tmp;
 545
 546         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 547                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 548                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 549                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 550                         crtc_hung |= (1 << i);
 551                 }
 552         }
 553
 554         for (j = 0; j < 10; j++) {
 555                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 556                         if (crtc_hung & (1 << i)) {
 557                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 558                                 if (tmp != crtc_status[i])
 559                                         crtc_hung &= ~(1 << i);
 560                         }
 561                 }
 562                 if (crtc_hung == 0)
 563                         return false;
 564                 udelay(100);
 565         }
 566
 567         return true;
 568 }
 569
 570 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
 571                                      struct amdgpu_mode_mc_save *save)
 572 {
 573         u32 crtc_enabled, tmp;
 574         int i;
 575
 576         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 577         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 578
 579         /* disable VGA render */
 580         tmp = RREG32(mmVGA_RENDER_CONTROL);
 581         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 582         WREG32(mmVGA_RENDER_CONTROL, tmp);
 583
 584         /* blank the display controllers */
 585         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 586                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 587                                              CRTC_CONTROL, CRTC_MASTER_EN);
 588                 if (crtc_enabled) {
 589 #if 0
 590                         u32 frame_count;
 591                         int j;
 592
 593                         save->crtc_enabled[i] = true;
 594                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 595                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 596                                 amdgpu_display_vblank_wait(adev, i);
 597                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 598                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 599                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 600                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 601                         }
 602                         /* wait for the next frame */
 603                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 604                         for (j = 0; j < adev->usec_timeout; j++) {
 605                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 606                                         break;
 607                                 udelay(1);
 608                         }
 609                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 610                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 611                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 612                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 613                         }
 614                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 615                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 616                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 617                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 618                         }
 619 #else
 620                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 621                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 622                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 623                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 624                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 625                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 626                         save->crtc_enabled[i] = false;
 627                         /* ***** */
 628 #endif
 629                 } else {
 630                         save->crtc_enabled[i] = false;
 631                 }
 632         }
 633 }
 634
 635 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
 636                                        struct amdgpu_mode_mc_save *save)
 637 {
 638         u32 tmp, frame_count;
 639         int i, j;
 640
 641         /* update crtc base addresses */
 642         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 643                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 644                        upper_32_bits(adev->mc.vram_start));
 645                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 646                        upper_32_bits(adev->mc.vram_start));
 647                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 648                        (u32)adev->mc.vram_start);
 649                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 650                        (u32)adev->mc.vram_start);
 651
 652                 if (save->crtc_enabled[i]) {
 653                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 654                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
 655                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
 656                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 657                         }
 658                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 659                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 660                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 661                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 662                         }
 663                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 664                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 665                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 666                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 667                         }
 668                         for (j = 0; j < adev->usec_timeout; j++) {
 669                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 670                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 671                                         break;
 672                                 udelay(1);
 673                         }
 674                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 675                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 676                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 677                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 678                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 679                         /* wait for the next frame */
 680                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 681                         for (j = 0; j < adev->usec_timeout; j++) {
 682                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 683                                         break;
 684                                 udelay(1);
 685                         }
 686                 }
 687         }
 688
 689         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 690         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 691
 692         /* Unlock vga access */
 693         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 694         mdelay(1);
 695         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 696 }
 697
 698 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 699                                            bool render)
 700 {
 701         u32 tmp;
 702
 703         /* Lockout access through VGA aperture*/
 704         tmp = RREG32(mmVGA_HDP_CONTROL);
 705         if (render)
 706                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 707         else
 708                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 709         WREG32(mmVGA_HDP_CONTROL, tmp);
 710
 711         /* disable VGA render */
 712         tmp = RREG32(mmVGA_RENDER_CONTROL);
 713         if (render)
 714                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 715         else
 716                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 717         WREG32(mmVGA_RENDER_CONTROL, tmp);
 718 }
 719
 720 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
 721 {
 722         int num_crtc = 0;
 723
 724         switch (adev->asic_type) {
 725         case CHIP_FIJI:
 726         case CHIP_TONGA:
 727                 num_crtc = 6;
 728                 break;
 729         default:
 730                 num_crtc = 0;
 731         }
 732         return num_crtc;
 733 }
 734
 735 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
 736 {
 737         /*Disable VGA render and enabled crtc, if has DCE engine*/
 738         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 739                 u32 tmp;
 740                 int crtc_enabled, i;
 741
 742                 dce_v10_0_set_vga_render_state(adev, false);
 743
 744                 /*Disable crtc*/
 745                 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
 746                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 747                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 748                         if (crtc_enabled) {
 749                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 750                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 751                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 752                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 753                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 754                         }
 755                 }
 756         }
 757 }
 758
 759 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 760 {
 761         struct drm_device *dev = encoder->dev;
 762         struct amdgpu_device *adev = dev->dev_private;
 763         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 764         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 765         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 766         int bpc = 0;
 767         u32 tmp = 0;
 768         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 769
 770         if (connector) {
 771                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 772                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 773                 dither = amdgpu_connector->dither;
 774         }
 775
 776         /* LVDS/eDP FMT is set up by atom */
 777         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 778                 return;
 779
 780         /* not needed for analog */
 781         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 782             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 783                 return;
 784
 785         if (bpc == 0)
 786                 return;
 787
 788         switch (bpc) {
 789         case 6:
 790                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 791                         /* XXX sort out optimal dither settings */
 792                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 793                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 794                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 795                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 796                 } else {
 797                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 798                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 799                 }
 800                 break;
 801         case 8:
 802                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 803                         /* XXX sort out optimal dither settings */
 804                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 805                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 806                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 807                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 808                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 809                 } else {
 810                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 811                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 812                 }
 813                 break;
 814         case 10:
 815                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 816                         /* XXX sort out optimal dither settings */
 817                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 818                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 819                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 820                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 821                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 822                 } else {
 823                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 824                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 825                 }
 826                 break;
 827         default:
 828                 /* not needed */
 829                 break;
 830         }
 831
 832         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 833 }
 834
 835
 836 /* display watermark setup */
 837 /**
 838  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 839  *
 840  * @adev: amdgpu_device pointer
 841  * @amdgpu_crtc: the selected display controller
 842  * @mode: the current display mode on the selected display
 843  * controller
 844  *
 845  * Setup up the line buffer allocation for
 846  * the selected display controller (CIK).
 847  * Returns the line buffer size in pixels.
 848  */
 849 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 850                                        struct amdgpu_crtc *amdgpu_crtc,
 851                                        struct drm_display_mode *mode)
 852 {
 853         u32 tmp, buffer_alloc, i, mem_cfg;
 854         u32 pipe_offset = amdgpu_crtc->crtc_id;
 855         /*
 856          * Line Buffer Setup
 857          * There are 6 line buffers, one for each display controllers.
 858          * There are 3 partitions per LB. Select the number of partitions
 859          * to enable based on the display width.  For display widths larger
 860          * than 4096, you need use to use 2 display controllers and combine
 861          * them using the stereo blender.
 862          */
 863         if (amdgpu_crtc->base.enabled && mode) {
 864                 if (mode->crtc_hdisplay < 1920) {
 865                         mem_cfg = 1;
 866                         buffer_alloc = 2;
 867                 } else if (mode->crtc_hdisplay < 2560) {
 868                         mem_cfg = 2;
 869                         buffer_alloc = 2;
 870                 } else if (mode->crtc_hdisplay < 4096) {
 871                         mem_cfg = 0;
 872                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 873                 } else {
 874                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 875                         mem_cfg = 0;
 876                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 877                 }
 878         } else {
 879                 mem_cfg = 1;
 880                 buffer_alloc = 0;
 881         }
 882
 883         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 884         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 885         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 886
 887         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 888         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 889         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 890
 891         for (i = 0; i < adev->usec_timeout; i++) {
 892                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 893                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 894                         break;
 895                 udelay(1);
 896         }
 897
 898         if (amdgpu_crtc->base.enabled && mode) {
 899                 switch (mem_cfg) {
 900                 case 0:
 901                 default:
 902                         return 4096 * 2;
 903                 case 1:
 904                         return 1920 * 2;
 905                 case 2:
 906                         return 2560 * 2;
 907                 }
 908         }
 909
 910         /* controller not enabled, so no lb used */
 911         return 0;
 912 }
 913
 914 /**
 915  * cik_get_number_of_dram_channels - get the number of dram channels
 916  *
 917  * @adev: amdgpu_device pointer
 918  *
 919  * Look up the number of video ram channels (CIK).
 920  * Used for display watermark bandwidth calculations
 921  * Returns the number of dram channels
 922  */
 923 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 924 {
 925         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 926
 927         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 928         case 0:
 929         default:
 930                 return 1;
 931         case 1:
 932                 return 2;
 933         case 2:
 934                 return 4;
 935         case 3:
 936                 return 8;
 937         case 4:
 938                 return 3;
 939         case 5:
 940                 return 6;
 941         case 6:
 942                 return 10;
 943         case 7:
 944                 return 12;
 945         case 8:
 946                 return 16;
 947         }
 948 }
 949
 950 struct dce10_wm_params {
 951         u32 dram_channels; /* number of dram channels */
 952         u32 yclk;          /* bandwidth per dram data pin in kHz */
 953         u32 sclk;          /* engine clock in kHz */
 954         u32 disp_clk;      /* display clock in kHz */
 955         u32 src_width;     /* viewport width */
 956         u32 active_time;   /* active display time in ns */
 957         u32 blank_time;    /* blank time in ns */
 958         bool interlaced;    /* mode is interlaced */
 959         fixed20_12 vsc;    /* vertical scale ratio */
 960         u32 num_heads;     /* number of active crtcs */
 961         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 962         u32 lb_size;       /* line buffer allocated to pipe */
 963         u32 vtaps;         /* vertical scaler taps */
 964 };
 965
 966 /**
 967  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 968  *
 969  * @wm: watermark calculation data
 970  *
 971  * Calculate the raw dram bandwidth (CIK).
 972  * Used for display watermark bandwidth calculations
 973  * Returns the dram bandwidth in MBytes/s
 974  */
 975 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 976 {
 977         /* Calculate raw DRAM Bandwidth */
 978         fixed20_12 dram_efficiency; /* 0.7 */
 979         fixed20_12 yclk, dram_channels, bandwidth;
 980         fixed20_12 a;
 981
 982         a.full = dfixed_const(1000);
 983         yclk.full = dfixed_const(wm->yclk);
 984         yclk.full = dfixed_div(yclk, a);
 985         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 986         a.full = dfixed_const(10);
 987         dram_efficiency.full = dfixed_const(7);
 988         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 989         bandwidth.full = dfixed_mul(dram_channels, yclk);
 990         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 991
 992         return dfixed_trunc(bandwidth);
 993 }
 994
 995 /**
 996  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 997  *
 998  * @wm: watermark calculation data
 999  *
1000  * Calculate the dram bandwidth used for display (CIK).
1001  * Used for display watermark bandwidth calculations
1002  * Returns the dram bandwidth for display in MBytes/s
1003  */
1004 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1005 {
1006         /* Calculate DRAM Bandwidth and the part allocated to display. */
1007         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1008         fixed20_12 yclk, dram_channels, bandwidth;
1009         fixed20_12 a;
1010
1011         a.full = dfixed_const(1000);
1012         yclk.full = dfixed_const(wm->yclk);
1013         yclk.full = dfixed_div(yclk, a);
1014         dram_channels.full = dfixed_const(wm->dram_channels * 4);
1015         a.full = dfixed_const(10);
1016         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1017         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1018         bandwidth.full = dfixed_mul(dram_channels, yclk);
1019         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1020
1021         return dfixed_trunc(bandwidth);
1022 }
1023
1024 /**
1025  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
1026  *
1027  * @wm: watermark calculation data
1028  *
1029  * Calculate the data return bandwidth used for display (CIK).
1030  * Used for display watermark bandwidth calculations
1031  * Returns the data return bandwidth in MBytes/s
1032  */
1033 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
1034 {
1035         /* Calculate the display Data return Bandwidth */
1036         fixed20_12 return_efficiency; /* 0.8 */
1037         fixed20_12 sclk, bandwidth;
1038         fixed20_12 a;
1039
1040         a.full = dfixed_const(1000);
1041         sclk.full = dfixed_const(wm->sclk);
1042         sclk.full = dfixed_div(sclk, a);
1043         a.full = dfixed_const(10);
1044         return_efficiency.full = dfixed_const(8);
1045         return_efficiency.full = dfixed_div(return_efficiency, a);
1046         a.full = dfixed_const(32);
1047         bandwidth.full = dfixed_mul(a, sclk);
1048         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1049
1050         return dfixed_trunc(bandwidth);
1051 }
1052
1053 /**
1054  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1055  *
1056  * @wm: watermark calculation data
1057  *
1058  * Calculate the dmif bandwidth used for display (CIK).
1059  * Used for display watermark bandwidth calculations
1060  * Returns the dmif bandwidth in MBytes/s
1061  */
1062 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1063 {
1064         /* Calculate the DMIF Request Bandwidth */
1065         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1066         fixed20_12 disp_clk, bandwidth;
1067         fixed20_12 a, b;
1068
1069         a.full = dfixed_const(1000);
1070         disp_clk.full = dfixed_const(wm->disp_clk);
1071         disp_clk.full = dfixed_div(disp_clk, a);
1072         a.full = dfixed_const(32);
1073         b.full = dfixed_mul(a, disp_clk);
1074
1075         a.full = dfixed_const(10);
1076         disp_clk_request_efficiency.full = dfixed_const(8);
1077         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1078
1079         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1080
1081         return dfixed_trunc(bandwidth);
1082 }
1083
1084 /**
1085  * dce_v10_0_available_bandwidth - get the min available bandwidth
1086  *
1087  * @wm: watermark calculation data
1088  *
1089  * Calculate the min available bandwidth used for display (CIK).
1090  * Used for display watermark bandwidth calculations
1091  * Returns the min available bandwidth in MBytes/s
1092  */
1093 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1094 {
1095         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1096         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1097         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1098         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1099
1100         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1101 }
1102
1103 /**
1104  * dce_v10_0_average_bandwidth - get the average available bandwidth
1105  *
1106  * @wm: watermark calculation data
1107  *
1108  * Calculate the average available bandwidth used for display (CIK).
1109  * Used for display watermark bandwidth calculations
1110  * Returns the average available bandwidth in MBytes/s
1111  */
1112 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1113 {
1114         /* Calculate the display mode Average Bandwidth
1115          * DisplayMode should contain the source and destination dimensions,
1116          * timing, etc.
1117          */
1118         fixed20_12 bpp;
1119         fixed20_12 line_time;
1120         fixed20_12 src_width;
1121         fixed20_12 bandwidth;
1122         fixed20_12 a;
1123
1124         a.full = dfixed_const(1000);
1125         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1126         line_time.full = dfixed_div(line_time, a);
1127         bpp.full = dfixed_const(wm->bytes_per_pixel);
1128         src_width.full = dfixed_const(wm->src_width);
1129         bandwidth.full = dfixed_mul(src_width, bpp);
1130         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1131         bandwidth.full = dfixed_div(bandwidth, line_time);
1132
1133         return dfixed_trunc(bandwidth);
1134 }
1135
1136 /**
1137  * dce_v10_0_latency_watermark - get the latency watermark
1138  *
1139  * @wm: watermark calculation data
1140  *
1141  * Calculate the latency watermark (CIK).
1142  * Used for display watermark bandwidth calculations
1143  * Returns the latency watermark in ns
1144  */
1145 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1146 {
1147         /* First calculate the latency in ns */
1148         u32 mc_latency = 2000; /* 2000 ns. */
1149         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1150         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1151         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1152         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1153         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1154                 (wm->num_heads * cursor_line_pair_return_time);
1155         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1156         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1157         u32 tmp, dmif_size = 12288;
1158         fixed20_12 a, b, c;
1159
1160         if (wm->num_heads == 0)
1161                 return 0;
1162
1163         a.full = dfixed_const(2);
1164         b.full = dfixed_const(1);
1165         if ((wm->vsc.full > a.full) ||
1166             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1167             (wm->vtaps >= 5) ||
1168             ((wm->vsc.full >= a.full) && wm->interlaced))
1169                 max_src_lines_per_dst_line = 4;
1170         else
1171                 max_src_lines_per_dst_line = 2;
1172
1173         a.full = dfixed_const(available_bandwidth);
1174         b.full = dfixed_const(wm->num_heads);
1175         a.full = dfixed_div(a, b);
1176         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1177         tmp = min(dfixed_trunc(a), tmp);
1178
1179         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1180
1181         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1182         b.full = dfixed_const(1000);
1183         c.full = dfixed_const(lb_fill_bw);
1184         b.full = dfixed_div(c, b);
1185         a.full = dfixed_div(a, b);
1186         line_fill_time = dfixed_trunc(a);
1187
1188         if (line_fill_time < wm->active_time)
1189                 return latency;
1190         else
1191                 return latency + (line_fill_time - wm->active_time);
1192
1193 }
1194
1195 /**
1196  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1197  * average and available dram bandwidth
1198  *
1199  * @wm: watermark calculation data
1200  *
1201  * Check if the display average bandwidth fits in the display
1202  * dram bandwidth (CIK).
1203  * Used for display watermark bandwidth calculations
1204  * Returns true if the display fits, false if not.
1205  */
1206 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1207 {
1208         if (dce_v10_0_average_bandwidth(wm) <=
1209             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1210                 return true;
1211         else
1212                 return false;
1213 }
1214
1215 /**
1216  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1217  * average and available bandwidth
1218  *
1219  * @wm: watermark calculation data
1220  *
1221  * Check if the display average bandwidth fits in the display
1222  * available bandwidth (CIK).
1223  * Used for display watermark bandwidth calculations
1224  * Returns true if the display fits, false if not.
1225  */
1226 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1227 {
1228         if (dce_v10_0_average_bandwidth(wm) <=
1229             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1230                 return true;
1231         else
1232                 return false;
1233 }
1234
1235 /**
1236  * dce_v10_0_check_latency_hiding - check latency hiding
1237  *
1238  * @wm: watermark calculation data
1239  *
1240  * Check latency hiding (CIK).
1241  * Used for display watermark bandwidth calculations
1242  * Returns true if the display fits, false if not.
1243  */
1244 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1245 {
1246         u32 lb_partitions = wm->lb_size / wm->src_width;
1247         u32 line_time = wm->active_time + wm->blank_time;
1248         u32 latency_tolerant_lines;
1249         u32 latency_hiding;
1250         fixed20_12 a;
1251
1252         a.full = dfixed_const(1);
1253         if (wm->vsc.full > a.full)
1254                 latency_tolerant_lines = 1;
1255         else {
1256                 if (lb_partitions <= (wm->vtaps + 1))
1257                         latency_tolerant_lines = 1;
1258                 else
1259                         latency_tolerant_lines = 2;
1260         }
1261
1262         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1263
1264         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1265                 return true;
1266         else
1267                 return false;
1268 }
1269
1270 /**
1271  * dce_v10_0_program_watermarks - program display watermarks
1272  *
1273  * @adev: amdgpu_device pointer
1274  * @amdgpu_crtc: the selected display controller
1275  * @lb_size: line buffer size
1276  * @num_heads: number of display controllers in use
1277  *
1278  * Calculate and program the display watermarks for the
1279  * selected display controller (CIK).
1280  */
1281 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1282                                         struct amdgpu_crtc *amdgpu_crtc,
1283                                         u32 lb_size, u32 num_heads)
1284 {
1285         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1286         struct dce10_wm_params wm_low, wm_high;
1287         u32 active_time;
1288         u32 line_time = 0;
1289         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1290         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1291
1292         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1293                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1294                                             (u32)mode->clock);
1295                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1296                                           (u32)mode->clock);
1297                 line_time = min(line_time, (u32)65535);
1298
1299                 /* watermark for high clocks */
1300                 if (adev->pm.dpm_enabled) {
1301                         wm_high.yclk =
1302                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1303                         wm_high.sclk =
1304                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1305                 } else {
1306                         wm_high.yclk = adev->pm.current_mclk * 10;
1307                         wm_high.sclk = adev->pm.current_sclk * 10;
1308                 }
1309
1310                 wm_high.disp_clk = mode->clock;
1311                 wm_high.src_width = mode->crtc_hdisplay;
1312                 wm_high.active_time = active_time;
1313                 wm_high.blank_time = line_time - wm_high.active_time;
1314                 wm_high.interlaced = false;
1315                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1316                         wm_high.interlaced = true;
1317                 wm_high.vsc = amdgpu_crtc->vsc;
1318                 wm_high.vtaps = 1;
1319                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1320                         wm_high.vtaps = 2;
1321                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1322                 wm_high.lb_size = lb_size;
1323                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1324                 wm_high.num_heads = num_heads;
1325
1326                 /* set for high clocks */
1327                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1328
1329                 /* possibly force display priority to high */
1330                 /* should really do this at mode validation time... */
1331                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1332                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1333                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1334                     (adev->mode_info.disp_priority == 2)) {
1335                         DRM_DEBUG_KMS("force priority to high\n");
1336                 }
1337
1338                 /* watermark for low clocks */
1339                 if (adev->pm.dpm_enabled) {
1340                         wm_low.yclk =
1341                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1342                         wm_low.sclk =
1343                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1344                 } else {
1345                         wm_low.yclk = adev->pm.current_mclk * 10;
1346                         wm_low.sclk = adev->pm.current_sclk * 10;
1347                 }
1348
1349                 wm_low.disp_clk = mode->clock;
1350                 wm_low.src_width = mode->crtc_hdisplay;
1351                 wm_low.active_time = active_time;
1352                 wm_low.blank_time = line_time - wm_low.active_time;
1353                 wm_low.interlaced = false;
1354                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1355                         wm_low.interlaced = true;
1356                 wm_low.vsc = amdgpu_crtc->vsc;
1357                 wm_low.vtaps = 1;
1358                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1359                         wm_low.vtaps = 2;
1360                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1361                 wm_low.lb_size = lb_size;
1362                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1363                 wm_low.num_heads = num_heads;
1364
1365                 /* set for low clocks */
1366                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1367
1368                 /* possibly force display priority to high */
1369                 /* should really do this at mode validation time... */
1370                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1371                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1372                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1373                     (adev->mode_info.disp_priority == 2)) {
1374                         DRM_DEBUG_KMS("force priority to high\n");
1375                 }
1376                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1377         }
1378
1379         /* select wm A */
1380         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1381         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1382         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1383         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1384         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1385         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1386         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1387         /* select wm B */
1388         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1389         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1390         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1391         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1392         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1393         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1394         /* restore original selection */
1395         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1396
1397         /* save values for DPM */
1398         amdgpu_crtc->line_time = line_time;
1399         amdgpu_crtc->wm_high = latency_watermark_a;
1400         amdgpu_crtc->wm_low = latency_watermark_b;
1401         /* Save number of lines the linebuffer leads before the scanout */
1402         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1403 }
1404
1405 /**
1406  * dce_v10_0_bandwidth_update - program display watermarks
1407  *
1408  * @adev: amdgpu_device pointer
1409  *
1410  * Calculate and program the display watermarks and line
1411  * buffer allocation (CIK).
1412  */
1413 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1414 {
1415         struct drm_display_mode *mode = NULL;
1416         u32 num_heads = 0, lb_size;
1417         int i;
1418
1419         amdgpu_update_display_priority(adev);
1420
1421         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1422                 if (adev->mode_info.crtcs[i]->base.enabled)
1423                         num_heads++;
1424         }
1425         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1426                 mode = &adev->mode_info.crtcs[i]->base.mode;
1427                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1428                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1429                                             lb_size, num_heads);
1430         }
1431 }
1432
1433 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1434 {
1435         int i;
1436         u32 offset, tmp;
1437
1438         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1439                 offset = adev->mode_info.audio.pin[i].offset;
1440                 tmp = RREG32_AUDIO_ENDPT(offset,
1441                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1442                 if (((tmp &
1443                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1444                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1445                         adev->mode_info.audio.pin[i].connected = false;
1446                 else
1447                         adev->mode_info.audio.pin[i].connected = true;
1448         }
1449 }
1450
1451 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1452 {
1453         int i;
1454
1455         dce_v10_0_audio_get_connected_pins(adev);
1456
1457         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1458                 if (adev->mode_info.audio.pin[i].connected)
1459                         return &adev->mode_info.audio.pin[i];
1460         }
1461         DRM_ERROR("No connected audio pins found!\n");
1462         return NULL;
1463 }
1464
1465 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1466 {
1467         struct amdgpu_device *adev = encoder->dev->dev_private;
1468         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1469         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1470         u32 tmp;
1471
1472         if (!dig || !dig->afmt || !dig->afmt->pin)
1473                 return;
1474
1475         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1476         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1477         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1478 }
1479
1480 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1481                                                 struct drm_display_mode *mode)
1482 {
1483         struct amdgpu_device *adev = encoder->dev->dev_private;
1484         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1485         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1486         struct drm_connector *connector;
1487         struct amdgpu_connector *amdgpu_connector = NULL;
1488         u32 tmp;
1489         int interlace = 0;
1490
1491         if (!dig || !dig->afmt || !dig->afmt->pin)
1492                 return;
1493
1494         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1495                 if (connector->encoder == encoder) {
1496                         amdgpu_connector = to_amdgpu_connector(connector);
1497                         break;
1498                 }
1499         }
1500
1501         if (!amdgpu_connector) {
1502                 DRM_ERROR("Couldn't find encoder's connector\n");
1503                 return;
1504         }
1505
1506         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1507                 interlace = 1;
1508         if (connector->latency_present[interlace]) {
1509                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1510                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1511                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1512                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1513         } else {
1514                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1515                                     VIDEO_LIPSYNC, 0);
1516                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1517                                     AUDIO_LIPSYNC, 0);
1518         }
1519         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1520                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1521 }
1522
1523 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1524 {
1525         struct amdgpu_device *adev = encoder->dev->dev_private;
1526         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1527         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1528         struct drm_connector *connector;
1529         struct amdgpu_connector *amdgpu_connector = NULL;
1530         u32 tmp;
1531         u8 *sadb = NULL;
1532         int sad_count;
1533
1534         if (!dig || !dig->afmt || !dig->afmt->pin)
1535                 return;
1536
1537         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1538                 if (connector->encoder == encoder) {
1539                         amdgpu_connector = to_amdgpu_connector(connector);
1540                         break;
1541                 }
1542         }
1543
1544         if (!amdgpu_connector) {
1545                 DRM_ERROR("Couldn't find encoder's connector\n");
1546                 return;
1547         }
1548
1549         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1550         if (sad_count < 0) {
1551                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1552                 sad_count = 0;
1553         }
1554
1555         /* program the speaker allocation */
1556         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1557                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1558         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1559                             DP_CONNECTION, 0);
1560         /* set HDMI mode */
1561         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1562                             HDMI_CONNECTION, 1);
1563         if (sad_count)
1564                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1565                                     SPEAKER_ALLOCATION, sadb[0]);
1566         else
1567                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1568                                     SPEAKER_ALLOCATION, 5); /* stereo */
1569         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1570                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1571
1572         kfree(sadb);
1573 }
1574
1575 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1576 {
1577         struct amdgpu_device *adev = encoder->dev->dev_private;
1578         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1579         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1580         struct drm_connector *connector;
1581         struct amdgpu_connector *amdgpu_connector = NULL;
1582         struct cea_sad *sads;
1583         int i, sad_count;
1584
1585         static const u16 eld_reg_to_type[][2] = {
1586                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1587                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1588                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1589                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1590                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1591                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1592                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1593                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1594                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1595                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1596                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1597                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1598         };
1599
1600         if (!dig || !dig->afmt || !dig->afmt->pin)
1601                 return;
1602
1603         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1604                 if (connector->encoder == encoder) {
1605                         amdgpu_connector = to_amdgpu_connector(connector);
1606                         break;
1607                 }
1608         }
1609
1610         if (!amdgpu_connector) {
1611                 DRM_ERROR("Couldn't find encoder's connector\n");
1612                 return;
1613         }
1614
1615         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1616         if (sad_count <= 0) {
1617                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1618                 return;
1619         }
1620         BUG_ON(!sads);
1621
1622         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1623                 u32 tmp = 0;
1624                 u8 stereo_freqs = 0;
1625                 int max_channels = -1;
1626                 int j;
1627
1628                 for (j = 0; j < sad_count; j++) {
1629                         struct cea_sad *sad = &sads[j];
1630
1631                         if (sad->format == eld_reg_to_type[i][1]) {
1632                                 if (sad->channels > max_channels) {
1633                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1634                                                             MAX_CHANNELS, sad->channels);
1635                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1636                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1637                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1638                                                             SUPPORTED_FREQUENCIES, sad->freq);
1639                                         max_channels = sad->channels;
1640                                 }
1641
1642                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1643                                         stereo_freqs |= sad->freq;
1644                                 else
1645                                         break;
1646                         }
1647                 }
1648
1649                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1650                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1651                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1652         }
1653
1654         kfree(sads);
1655 }
1656
1657 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1658                                   struct amdgpu_audio_pin *pin,
1659                                   bool enable)
1660 {
1661         if (!pin)
1662                 return;
1663
1664         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1665                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1666 }
1667
1668 static const u32 pin_offsets[] =
1669 {
1670         AUD0_REGISTER_OFFSET,
1671         AUD1_REGISTER_OFFSET,
1672         AUD2_REGISTER_OFFSET,
1673         AUD3_REGISTER_OFFSET,
1674         AUD4_REGISTER_OFFSET,
1675         AUD5_REGISTER_OFFSET,
1676         AUD6_REGISTER_OFFSET,
1677 };
1678
1679 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1680 {
1681         int i;
1682
1683         if (!amdgpu_audio)
1684                 return 0;
1685
1686         adev->mode_info.audio.enabled = true;
1687
1688         adev->mode_info.audio.num_pins = 7;
1689
1690         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1691                 adev->mode_info.audio.pin[i].channels = -1;
1692                 adev->mode_info.audio.pin[i].rate = -1;
1693                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1694                 adev->mode_info.audio.pin[i].status_bits = 0;
1695                 adev->mode_info.audio.pin[i].category_code = 0;
1696                 adev->mode_info.audio.pin[i].connected = false;
1697                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1698                 adev->mode_info.audio.pin[i].id = i;
1699                 /* disable audio.  it will be set up later */
1700                 /* XXX remove once we switch to ip funcs */
1701                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1702         }
1703
1704         return 0;
1705 }
1706
1707 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1708 {
1709         int i;
1710
1711         if (!amdgpu_audio)
1712                 return;
1713
1714         if (!adev->mode_info.audio.enabled)
1715                 return;
1716
1717         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1718                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1719
1720         adev->mode_info.audio.enabled = false;
1721 }
1722
1723 /*
1724  * update the N and CTS parameters for a given pixel clock rate
1725  */
1726 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1727 {
1728         struct drm_device *dev = encoder->dev;
1729         struct amdgpu_device *adev = dev->dev_private;
1730         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1731         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1732         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1733         u32 tmp;
1734
1735         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1736         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1737         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1738         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1739         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1740         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1741
1742         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1743         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1744         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1745         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1746         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1747         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1748
1749         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1750         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1751         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1752         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1753         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1754         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1755
1756 }
1757
1758 /*
1759  * build a HDMI Video Info Frame
1760  */
1761 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1762                                                void *buffer, size_t size)
1763 {
1764         struct drm_device *dev = encoder->dev;
1765         struct amdgpu_device *adev = dev->dev_private;
1766         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1767         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1768         uint8_t *frame = buffer + 3;
1769         uint8_t *header = buffer;
1770
1771         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1772                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1773         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1774                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1775         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1776                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1777         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1778                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1779 }
1780
1781 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1782 {
1783         struct drm_device *dev = encoder->dev;
1784         struct amdgpu_device *adev = dev->dev_private;
1785         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1786         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1787         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1788         u32 dto_phase = 24 * 1000;
1789         u32 dto_modulo = clock;
1790         u32 tmp;
1791
1792         if (!dig || !dig->afmt)
1793                 return;
1794
1795         /* XXX two dtos; generally use dto0 for hdmi */
1796         /* Express [24MHz / target pixel clock] as an exact rational
1797          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1798          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1799          */
1800         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1801         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1802                             amdgpu_crtc->crtc_id);
1803         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1804         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1805         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1806 }
1807
1808 /*
1809  * update the info frames with the data from the current display mode
1810  */
1811 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1812                                   struct drm_display_mode *mode)
1813 {
1814         struct drm_device *dev = encoder->dev;
1815         struct amdgpu_device *adev = dev->dev_private;
1816         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1817         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1818         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1819         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1820         struct hdmi_avi_infoframe frame;
1821         ssize_t err;
1822         u32 tmp;
1823         int bpc = 8;
1824
1825         if (!dig || !dig->afmt)
1826                 return;
1827
1828         /* Silent, r600_hdmi_enable will raise WARN for us */
1829         if (!dig->afmt->enabled)
1830                 return;
1831
1832         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1833         if (encoder->crtc) {
1834                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1835                 bpc = amdgpu_crtc->bpc;
1836         }
1837
1838         /* disable audio prior to setting up hw */
1839         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1840         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1841
1842         dce_v10_0_audio_set_dto(encoder, mode->clock);
1843
1844         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1845         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1846         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1847
1848         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1849
1850         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1851         switch (bpc) {
1852         case 0:
1853         case 6:
1854         case 8:
1855         case 16:
1856         default:
1857                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1858                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1859                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1860                           connector->name, bpc);
1861                 break;
1862         case 10:
1863                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1864                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1865                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1866                           connector->name);
1867                 break;
1868         case 12:
1869                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1870                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1871                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1872                           connector->name);
1873                 break;
1874         }
1875         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1876
1877         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1878         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1879         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1880         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1881         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1882
1883         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1884         /* enable audio info frames (frames won't be set until audio is enabled) */
1885         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1886         /* required for audio info values to be updated */
1887         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1888         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1889
1890         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1891         /* required for audio info values to be updated */
1892         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1893         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1894
1895         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1896         /* anything other than 0 */
1897         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1898         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1899
1900         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1901
1902         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1903         /* set the default audio delay */
1904         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1905         /* should be suffient for all audio modes and small enough for all hblanks */
1906         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1907         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1908
1909         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1910         /* allow 60958 channel status fields to be updated */
1911         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1912         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1913
1914         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1915         if (bpc > 8)
1916                 /* clear SW CTS value */
1917                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1918         else
1919                 /* select SW CTS value */
1920                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1921         /* allow hw to sent ACR packets when required */
1922         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1923         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1924
1925         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1926
1927         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1928         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1929         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1930
1931         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1932         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1933         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1934
1935         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1936         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1937         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1938         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1939         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1940         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1941         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1942         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1943
1944         dce_v10_0_audio_write_speaker_allocation(encoder);
1945
1946         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1947                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1948
1949         dce_v10_0_afmt_audio_select_pin(encoder);
1950         dce_v10_0_audio_write_sad_regs(encoder);
1951         dce_v10_0_audio_write_latency_fields(encoder, mode);
1952
1953         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1954         if (err < 0) {
1955                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1956                 return;
1957         }
1958
1959         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1960         if (err < 0) {
1961                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1962                 return;
1963         }
1964
1965         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1966
1967         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1968         /* enable AVI info frames */
1969         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1970         /* required for audio info values to be updated */
1971         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1972         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1973
1974         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1975         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1976         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1977
1978         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1979         /* send audio packets */
1980         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1981         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1982
1983         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1984         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1985         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1986         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1987
1988         /* enable audio after to setting up hw */
1989         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1990 }
1991
1992 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1993 {
1994         struct drm_device *dev = encoder->dev;
1995         struct amdgpu_device *adev = dev->dev_private;
1996         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1997         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1998
1999         if (!dig || !dig->afmt)
2000                 return;
2001
2002         /* Silent, r600_hdmi_enable will raise WARN for us */
2003         if (enable && dig->afmt->enabled)
2004                 return;
2005         if (!enable && !dig->afmt->enabled)
2006                 return;
2007
2008         if (!enable && dig->afmt->pin) {
2009                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
2010                 dig->afmt->pin = NULL;
2011         }
2012
2013         dig->afmt->enabled = enable;
2014
2015         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
2016                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
2017 }
2018
2019 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
2020 {
2021         int i;
2022
2023         for (i = 0; i < adev->mode_info.num_dig; i++)
2024                 adev->mode_info.afmt[i] = NULL;
2025
2026         /* DCE10 has audio blocks tied to DIG encoders */
2027         for (i = 0; i < adev->mode_info.num_dig; i++) {
2028                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
2029                 if (adev->mode_info.afmt[i]) {
2030                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
2031                         adev->mode_info.afmt[i]->id = i;
2032                 } else {
2033                         int j;
2034                         for (j = 0; j < i; j++) {
2035                                 kfree(adev->mode_info.afmt[j]);
2036                                 adev->mode_info.afmt[j] = NULL;
2037                         }
2038                         return -ENOMEM;
2039                 }
2040         }
2041         return 0;
2042 }
2043
2044 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
2045 {
2046         int i;
2047
2048         for (i = 0; i < adev->mode_info.num_dig; i++) {
2049                 kfree(adev->mode_info.afmt[i]);
2050                 adev->mode_info.afmt[i] = NULL;
2051         }
2052 }
2053
2054 static const u32 vga_control_regs[6] =
2055 {
2056         mmD1VGA_CONTROL,
2057         mmD2VGA_CONTROL,
2058         mmD3VGA_CONTROL,
2059         mmD4VGA_CONTROL,
2060         mmD5VGA_CONTROL,
2061         mmD6VGA_CONTROL,
2062 };
2063
2064 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2065 {
2066         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2067         struct drm_device *dev = crtc->dev;
2068         struct amdgpu_device *adev = dev->dev_private;
2069         u32 vga_control;
2070
2071         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2072         if (enable)
2073                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2074         else
2075                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2076 }
2077
2078 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2079 {
2080         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2081         struct drm_device *dev = crtc->dev;
2082         struct amdgpu_device *adev = dev->dev_private;
2083
2084         if (enable)
2085                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2086         else
2087                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2088 }
2089
2090 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2091                                      struct drm_framebuffer *fb,
2092                                      int x, int y, int atomic)
2093 {
2094         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2095         struct drm_device *dev = crtc->dev;
2096         struct amdgpu_device *adev = dev->dev_private;
2097         struct amdgpu_framebuffer *amdgpu_fb;
2098         struct drm_framebuffer *target_fb;
2099         struct drm_gem_object *obj;
2100         struct amdgpu_bo *abo;
2101         uint64_t fb_location, tiling_flags;
2102         uint32_t fb_format, fb_pitch_pixels;
2103         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2104         u32 pipe_config;
2105         u32 tmp, viewport_w, viewport_h;
2106         int r;
2107         bool bypass_lut = false;
2108         char *format_name;
2109
2110         /* no fb bound */
2111         if (!atomic && !crtc->primary->fb) {
2112                 DRM_DEBUG_KMS("No FB bound\n");
2113                 return 0;
2114         }
2115
2116         if (atomic) {
2117                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2118                 target_fb = fb;
2119         } else {
2120                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2121                 target_fb = crtc->primary->fb;
2122         }
2123
2124         /* If atomic, assume fb object is pinned & idle & fenced and
2125          * just update base pointers
2126          */
2127         obj = amdgpu_fb->obj;
2128         abo = gem_to_amdgpu_bo(obj);
2129         r = amdgpu_bo_reserve(abo, false);
2130         if (unlikely(r != 0))
2131                 return r;
2132
2133         if (atomic) {
2134                 fb_location = amdgpu_bo_gpu_offset(abo);
2135         } else {
2136                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2137                 if (unlikely(r != 0)) {
2138                         amdgpu_bo_unreserve(abo);
2139                         return -EINVAL;
2140                 }
2141         }
2142
2143         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2144         amdgpu_bo_unreserve(abo);
2145
2146         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2147
2148         switch (target_fb->pixel_format) {
2149         case DRM_FORMAT_C8:
2150                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2151                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2152                 break;
2153         case DRM_FORMAT_XRGB4444:
2154         case DRM_FORMAT_ARGB4444:
2155                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2156                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2157 #ifdef __BIG_ENDIAN
2158                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2159                                         ENDIAN_8IN16);
2160 #endif
2161                 break;
2162         case DRM_FORMAT_XRGB1555:
2163         case DRM_FORMAT_ARGB1555:
2164                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2165                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2166 #ifdef __BIG_ENDIAN
2167                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2168                                         ENDIAN_8IN16);
2169 #endif
2170                 break;
2171         case DRM_FORMAT_BGRX5551:
2172         case DRM_FORMAT_BGRA5551:
2173                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2174                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2175 #ifdef __BIG_ENDIAN
2176                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2177                                         ENDIAN_8IN16);
2178 #endif
2179                 break;
2180         case DRM_FORMAT_RGB565:
2181                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2182                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2183 #ifdef __BIG_ENDIAN
2184                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2185                                         ENDIAN_8IN16);
2186 #endif
2187                 break;
2188         case DRM_FORMAT_XRGB8888:
2189         case DRM_FORMAT_ARGB8888:
2190                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2191                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2192 #ifdef __BIG_ENDIAN
2193                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2194                                         ENDIAN_8IN32);
2195 #endif
2196                 break;
2197         case DRM_FORMAT_XRGB2101010:
2198         case DRM_FORMAT_ARGB2101010:
2199                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2200                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2201 #ifdef __BIG_ENDIAN
2202                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2203                                         ENDIAN_8IN32);
2204 #endif
2205                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2206                 bypass_lut = true;
2207                 break;
2208         case DRM_FORMAT_BGRX1010102:
2209         case DRM_FORMAT_BGRA1010102:
2210                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2211                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2212 #ifdef __BIG_ENDIAN
2213                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2214                                         ENDIAN_8IN32);
2215 #endif
2216                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2217                 bypass_lut = true;
2218                 break;
2219         default:
2220                 format_name = drm_get_format_name(target_fb->pixel_format);
2221                 DRM_ERROR("Unsupported screen format %s\n", format_name);
2222                 kfree(format_name);
2223                 return -EINVAL;
2224         }
2225
2226         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2227                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2228
2229                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2230                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2231                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2232                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2233                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2234
2235                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2236                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2237                                           ARRAY_2D_TILED_THIN1);
2238                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2239                                           tile_split);
2240                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2241                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2242                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2243                                           mtaspect);
2244                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2245                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2246         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2247                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2248                                           ARRAY_1D_TILED_THIN1);
2249         }
2250
2251         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2252                                   pipe_config);
2253
2254         dce_v10_0_vga_enable(crtc, false);
2255
2256         /* Make sure surface address is updated at vertical blank rather than
2257          * horizontal blank
2258          */
2259         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2260         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2261                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2262         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2263
2264         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2265                upper_32_bits(fb_location));
2266         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2267                upper_32_bits(fb_location));
2268         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2269                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2270         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2271                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2272         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2273         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2274
2275         /*
2276          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2277          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2278          * retain the full precision throughout the pipeline.
2279          */
2280         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2281         if (bypass_lut)
2282                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2283         else
2284                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2285         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2286
2287         if (bypass_lut)
2288                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2289
2290         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2291         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2292         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2293         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2294         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2295         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2296
2297         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2298         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2299
2300         dce_v10_0_grph_enable(crtc, true);
2301
2302         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2303                target_fb->height);
2304
2305         x &= ~3;
2306         y &= ~1;
2307         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2308                (x << 16) | y);
2309         viewport_w = crtc->mode.hdisplay;
2310         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2311         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2312                (viewport_w << 16) | viewport_h);
2313
2314         /* set pageflip to happen anywhere in vblank interval */
2315         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2316
2317         if (!atomic && fb && fb != crtc->primary->fb) {
2318                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2319                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2320                 r = amdgpu_bo_reserve(abo, false);
2321                 if (unlikely(r != 0))
2322                         return r;
2323                 amdgpu_bo_unpin(abo);
2324                 amdgpu_bo_unreserve(abo);
2325         }
2326
2327         /* Bytes per pixel may have changed */
2328         dce_v10_0_bandwidth_update(adev);
2329
2330         return 0;
2331 }
2332
2333 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2334                                      struct drm_display_mode *mode)
2335 {
2336         struct drm_device *dev = crtc->dev;
2337         struct amdgpu_device *adev = dev->dev_private;
2338         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2339         u32 tmp;
2340
2341         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2342         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2343                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2344         else
2345                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2346         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2347 }
2348
2349 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2350 {
2351         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2352         struct drm_device *dev = crtc->dev;
2353         struct amdgpu_device *adev = dev->dev_private;
2354         int i;
2355         u32 tmp;
2356
2357         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2358
2359         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2360         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2361         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2362         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2363
2364         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2365         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2366         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2367
2368         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2369         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2370         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2371
2372         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2373         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2374         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2375         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2376
2377         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2378
2379         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2380         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2381         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2382
2383         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2384         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2385         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2386
2387         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2388         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2389
2390         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2391         for (i = 0; i < 256; i++) {
2392                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2393                        (amdgpu_crtc->lut_r[i] << 20) |
2394                        (amdgpu_crtc->lut_g[i] << 10) |
2395                        (amdgpu_crtc->lut_b[i] << 0));
2396         }
2397
2398         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2399         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2400         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2401         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2402         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2403
2404         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2405         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2406         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2407         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2408
2409         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2410         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2411         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2412         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2413
2414         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2415         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2416         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2417         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2418
2419         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2420         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2421         /* XXX this only needs to be programmed once per crtc at startup,
2422          * not sure where the best place for it is
2423          */
2424         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2425         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2426         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2427 }
2428
2429 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2430 {
2431         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2432         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2433
2434         switch (amdgpu_encoder->encoder_id) {
2435         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2436                 if (dig->linkb)
2437                         return 1;
2438                 else
2439                         return 0;
2440                 break;
2441         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2442                 if (dig->linkb)
2443                         return 3;
2444                 else
2445                         return 2;
2446                 break;
2447         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2448                 if (dig->linkb)
2449                         return 5;
2450                 else
2451                         return 4;
2452                 break;
2453         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2454                 return 6;
2455                 break;
2456         default:
2457                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2458                 return 0;
2459         }
2460 }
2461
2462 /**
2463  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2464  *
2465  * @crtc: drm crtc
2466  *
2467  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2468  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2469  * monitors a dedicated PPLL must be used.  If a particular board has
2470  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2471  * as there is no need to program the PLL itself.  If we are not able to
2472  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2473  * avoid messing up an existing monitor.
2474  *
2475  * Asic specific PLL information
2476  *
2477  * DCE 10.x
2478  * Tonga
2479  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2480  * CI
2481  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2482  *
2483  */
2484 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2485 {
2486         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2487         struct drm_device *dev = crtc->dev;
2488         struct amdgpu_device *adev = dev->dev_private;
2489         u32 pll_in_use;
2490         int pll;
2491
2492         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2493                 if (adev->clock.dp_extclk)
2494                         /* skip PPLL programming if using ext clock */
2495                         return ATOM_PPLL_INVALID;
2496                 else {
2497                         /* use the same PPLL for all DP monitors */
2498                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2499                         if (pll != ATOM_PPLL_INVALID)
2500                                 return pll;
2501                 }
2502         } else {
2503                 /* use the same PPLL for all monitors with the same clock */
2504                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2505                 if (pll != ATOM_PPLL_INVALID)
2506                         return pll;
2507         }
2508
2509         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2510         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2511         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2512                 return ATOM_PPLL2;
2513         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2514                 return ATOM_PPLL1;
2515         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2516                 return ATOM_PPLL0;
2517         DRM_ERROR("unable to allocate a PPLL\n");
2518         return ATOM_PPLL_INVALID;
2519 }
2520
2521 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2522 {
2523         struct amdgpu_device *adev = crtc->dev->dev_private;
2524         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2525         uint32_t cur_lock;
2526
2527         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2528         if (lock)
2529                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2530         else
2531                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2532         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2533 }
2534
2535 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2536 {
2537         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2538         struct amdgpu_device *adev = crtc->dev->dev_private;
2539         u32 tmp;
2540
2541         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2542         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2543         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2544 }
2545
2546 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2547 {
2548         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2549         struct amdgpu_device *adev = crtc->dev->dev_private;
2550         u32 tmp;
2551
2552         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2553                upper_32_bits(amdgpu_crtc->cursor_addr));
2554         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2555                lower_32_bits(amdgpu_crtc->cursor_addr));
2556
2557         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2558         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2559         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2560         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2561 }
2562
2563 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2564                                         int x, int y)
2565 {
2566         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2567         struct amdgpu_device *adev = crtc->dev->dev_private;
2568         int xorigin = 0, yorigin = 0;
2569
2570         amdgpu_crtc->cursor_x = x;
2571         amdgpu_crtc->cursor_y = y;
2572
2573         /* avivo cursor are offset into the total surface */
2574         x += crtc->x;
2575         y += crtc->y;
2576         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2577
2578         if (x < 0) {
2579                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2580                 x = 0;
2581         }
2582         if (y < 0) {
2583                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2584                 y = 0;
2585         }
2586
2587         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2588         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2589         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2590                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2591
2592         return 0;
2593 }
2594
2595 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2596                                       int x, int y)
2597 {
2598         int ret;
2599
2600         dce_v10_0_lock_cursor(crtc, true);
2601         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2602         dce_v10_0_lock_cursor(crtc, false);
2603
2604         return ret;
2605 }
2606
2607 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2608                                       struct drm_file *file_priv,
2609                                       uint32_t handle,
2610                                       uint32_t width,
2611                                       uint32_t height,
2612                                       int32_t hot_x,
2613                                       int32_t hot_y)
2614 {
2615         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2616         struct drm_gem_object *obj;
2617         struct amdgpu_bo *aobj;
2618         int ret;
2619
2620         if (!handle) {
2621                 /* turn off cursor */
2622                 dce_v10_0_hide_cursor(crtc);
2623                 obj = NULL;
2624                 goto unpin;
2625         }
2626
2627         if ((width > amdgpu_crtc->max_cursor_width) ||
2628             (height > amdgpu_crtc->max_cursor_height)) {
2629                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2630                 return -EINVAL;
2631         }
2632
2633         obj = drm_gem_object_lookup(file_priv, handle);
2634         if (!obj) {
2635                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2636                 return -ENOENT;
2637         }
2638
2639         aobj = gem_to_amdgpu_bo(obj);
2640         ret = amdgpu_bo_reserve(aobj, false);
2641         if (ret != 0) {
2642                 drm_gem_object_unreference_unlocked(obj);
2643                 return ret;
2644         }
2645
2646         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2647         amdgpu_bo_unreserve(aobj);
2648         if (ret) {
2649                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2650                 drm_gem_object_unreference_unlocked(obj);
2651                 return ret;
2652         }
2653
2654         dce_v10_0_lock_cursor(crtc, true);
2655
2656         if (width != amdgpu_crtc->cursor_width ||
2657             height != amdgpu_crtc->cursor_height ||
2658             hot_x != amdgpu_crtc->cursor_hot_x ||
2659             hot_y != amdgpu_crtc->cursor_hot_y) {
2660                 int x, y;
2661
2662                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2663                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2664
2665                 dce_v10_0_cursor_move_locked(crtc, x, y);
2666
2667                 amdgpu_crtc->cursor_width = width;
2668                 amdgpu_crtc->cursor_height = height;
2669                 amdgpu_crtc->cursor_hot_x = hot_x;
2670                 amdgpu_crtc->cursor_hot_y = hot_y;
2671         }
2672
2673         dce_v10_0_show_cursor(crtc);
2674         dce_v10_0_lock_cursor(crtc, false);
2675
2676 unpin:
2677         if (amdgpu_crtc->cursor_bo) {
2678                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2679                 ret = amdgpu_bo_reserve(aobj, false);
2680                 if (likely(ret == 0)) {
2681                         amdgpu_bo_unpin(aobj);
2682                         amdgpu_bo_unreserve(aobj);
2683                 }
2684                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2685         }
2686
2687         amdgpu_crtc->cursor_bo = obj;
2688         return 0;
2689 }
2690
2691 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2692 {
2693         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2694
2695         if (amdgpu_crtc->cursor_bo) {
2696                 dce_v10_0_lock_cursor(crtc, true);
2697
2698                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2699                                              amdgpu_crtc->cursor_y);
2700
2701                 dce_v10_0_show_cursor(crtc);
2702
2703                 dce_v10_0_lock_cursor(crtc, false);
2704         }
2705 }
2706
2707 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2708                                     u16 *blue, uint32_t size)
2709 {
2710         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2711         int i;
2712
2713         /* userspace palettes are always correct as is */
2714         for (i = 0; i < size; i++) {
2715                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2716                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2717                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2718         }
2719         dce_v10_0_crtc_load_lut(crtc);
2720
2721         return 0;
2722 }
2723
2724 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2725 {
2726         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2727
2728         drm_crtc_cleanup(crtc);
2729         kfree(amdgpu_crtc);
2730 }
2731
2732 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2733         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2734         .cursor_move = dce_v10_0_crtc_cursor_move,
2735         .gamma_set = dce_v10_0_crtc_gamma_set,
2736         .set_config = amdgpu_crtc_set_config,
2737         .destroy = dce_v10_0_crtc_destroy,
2738         .page_flip_target = amdgpu_crtc_page_flip_target,
2739 };
2740
2741 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2742 {
2743         struct drm_device *dev = crtc->dev;
2744         struct amdgpu_device *adev = dev->dev_private;
2745         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2746         unsigned type;
2747
2748         switch (mode) {
2749         case DRM_MODE_DPMS_ON:
2750                 amdgpu_crtc->enabled = true;
2751                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2752                 dce_v10_0_vga_enable(crtc, true);
2753                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2754                 dce_v10_0_vga_enable(crtc, false);
2755                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2756                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2757                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2758                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2759                 drm_crtc_vblank_on(crtc);
2760                 dce_v10_0_crtc_load_lut(crtc);
2761                 break;
2762         case DRM_MODE_DPMS_STANDBY:
2763         case DRM_MODE_DPMS_SUSPEND:
2764         case DRM_MODE_DPMS_OFF:
2765                 drm_crtc_vblank_off(crtc);
2766                 if (amdgpu_crtc->enabled) {
2767                         dce_v10_0_vga_enable(crtc, true);
2768                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2769                         dce_v10_0_vga_enable(crtc, false);
2770                 }
2771                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2772                 amdgpu_crtc->enabled = false;
2773                 break;
2774         }
2775         /* adjust pm to dpms */
2776         amdgpu_pm_compute_clocks(adev);
2777 }
2778
2779 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2780 {
2781         /* disable crtc pair power gating before programming */
2782         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2783         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2784         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2785 }
2786
2787 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2788 {
2789         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2790         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2791 }
2792
2793 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2794 {
2795         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2796         struct drm_device *dev = crtc->dev;
2797         struct amdgpu_device *adev = dev->dev_private;
2798         struct amdgpu_atom_ss ss;
2799         int i;
2800
2801         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2802         if (crtc->primary->fb) {
2803                 int r;
2804                 struct amdgpu_framebuffer *amdgpu_fb;
2805                 struct amdgpu_bo *abo;
2806
2807                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2808                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2809                 r = amdgpu_bo_reserve(abo, false);
2810                 if (unlikely(r))
2811                         DRM_ERROR("failed to reserve abo before unpin\n");
2812                 else {
2813                         amdgpu_bo_unpin(abo);
2814                         amdgpu_bo_unreserve(abo);
2815                 }
2816         }
2817         /* disable the GRPH */
2818         dce_v10_0_grph_enable(crtc, false);
2819
2820         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2821
2822         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2823                 if (adev->mode_info.crtcs[i] &&
2824                     adev->mode_info.crtcs[i]->enabled &&
2825                     i != amdgpu_crtc->crtc_id &&
2826                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2827                         /* one other crtc is using this pll don't turn
2828                          * off the pll
2829                          */
2830                         goto done;
2831                 }
2832         }
2833
2834         switch (amdgpu_crtc->pll_id) {
2835         case ATOM_PPLL0:
2836         case ATOM_PPLL1:
2837         case ATOM_PPLL2:
2838                 /* disable the ppll */
2839                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2840                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2841                 break;
2842         default:
2843                 break;
2844         }
2845 done:
2846         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2847         amdgpu_crtc->adjusted_clock = 0;
2848         amdgpu_crtc->encoder = NULL;
2849         amdgpu_crtc->connector = NULL;
2850 }
2851
2852 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2853                                   struct drm_display_mode *mode,
2854                                   struct drm_display_mode *adjusted_mode,
2855                                   int x, int y, struct drm_framebuffer *old_fb)
2856 {
2857         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2858
2859         if (!amdgpu_crtc->adjusted_clock)
2860                 return -EINVAL;
2861
2862         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2863         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2864         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2865         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2866         amdgpu_atombios_crtc_scaler_setup(crtc);
2867         dce_v10_0_cursor_reset(crtc);
2868         /* update the hw version fpr dpm */
2869         amdgpu_crtc->hw_mode = *adjusted_mode;
2870
2871         return 0;
2872 }
2873
2874 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2875                                      const struct drm_display_mode *mode,
2876                                      struct drm_display_mode *adjusted_mode)
2877 {
2878         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2879         struct drm_device *dev = crtc->dev;
2880         struct drm_encoder *encoder;
2881
2882         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2883         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2884                 if (encoder->crtc == crtc) {
2885                         amdgpu_crtc->encoder = encoder;
2886                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2887                         break;
2888                 }
2889         }
2890         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2891                 amdgpu_crtc->encoder = NULL;
2892                 amdgpu_crtc->connector = NULL;
2893                 return false;
2894         }
2895         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2896                 return false;
2897         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2898                 return false;
2899         /* pick pll */
2900         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2901         /* if we can't get a PPLL for a non-DP encoder, fail */
2902         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2903             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2904                 return false;
2905
2906         return true;
2907 }
2908
2909 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2910                                   struct drm_framebuffer *old_fb)
2911 {
2912         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2913 }
2914
2915 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2916                                          struct drm_framebuffer *fb,
2917                                          int x, int y, enum mode_set_atomic state)
2918 {
2919        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2920 }
2921
2922 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2923         .dpms = dce_v10_0_crtc_dpms,
2924         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2925         .mode_set = dce_v10_0_crtc_mode_set,
2926         .mode_set_base = dce_v10_0_crtc_set_base,
2927         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2928         .prepare = dce_v10_0_crtc_prepare,
2929         .commit = dce_v10_0_crtc_commit,
2930         .load_lut = dce_v10_0_crtc_load_lut,
2931         .disable = dce_v10_0_crtc_disable,
2932 };
2933
2934 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2935 {
2936         struct amdgpu_crtc *amdgpu_crtc;
2937         int i;
2938
2939         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2940                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2941         if (amdgpu_crtc == NULL)
2942                 return -ENOMEM;
2943
2944         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2945
2946         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2947         amdgpu_crtc->crtc_id = index;
2948         adev->mode_info.crtcs[index] = amdgpu_crtc;
2949
2950         amdgpu_crtc->max_cursor_width = 128;
2951         amdgpu_crtc->max_cursor_height = 128;
2952         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2953         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2954
2955         for (i = 0; i < 256; i++) {
2956                 amdgpu_crtc->lut_r[i] = i << 2;
2957                 amdgpu_crtc->lut_g[i] = i << 2;
2958                 amdgpu_crtc->lut_b[i] = i << 2;
2959         }
2960
2961         switch (amdgpu_crtc->crtc_id) {
2962         case 0:
2963         default:
2964                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2965                 break;
2966         case 1:
2967                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2968                 break;
2969         case 2:
2970                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2971                 break;
2972         case 3:
2973                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2974                 break;
2975         case 4:
2976                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2977                 break;
2978         case 5:
2979                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2980                 break;
2981         }
2982
2983         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2984         amdgpu_crtc->adjusted_clock = 0;
2985         amdgpu_crtc->encoder = NULL;
2986         amdgpu_crtc->connector = NULL;
2987         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2988
2989         return 0;
2990 }
2991
2992 static int dce_v10_0_early_init(void *handle)
2993 {
2994         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2995
2996         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2997         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2998
2999         dce_v10_0_set_display_funcs(adev);
3000         dce_v10_0_set_irq_funcs(adev);
3001
3002         adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
3003
3004         switch (adev->asic_type) {
3005         case CHIP_FIJI:
3006         case CHIP_TONGA:
3007                 adev->mode_info.num_hpd = 6;
3008                 adev->mode_info.num_dig = 7;
3009                 break;
3010         default:
3011                 /* FIXME: not supported yet */
3012                 return -EINVAL;
3013         }
3014
3015         return 0;
3016 }
3017
3018 static int dce_v10_0_sw_init(void *handle)
3019 {
3020         int r, i;
3021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3022
3023         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3024                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3025                 if (r)
3026                         return r;
3027         }
3028
3029         for (i = 8; i < 20; i += 2) {
3030                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3031                 if (r)
3032                         return r;
3033         }
3034
3035         /* HPD hotplug */
3036         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3037         if (r)
3038                 return r;
3039
3040         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3041
3042         adev->ddev->mode_config.async_page_flip = true;
3043
3044         adev->ddev->mode_config.max_width = 16384;
3045         adev->ddev->mode_config.max_height = 16384;
3046
3047         adev->ddev->mode_config.preferred_depth = 24;
3048         adev->ddev->mode_config.prefer_shadow = 1;
3049
3050         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3051
3052         r = amdgpu_modeset_create_props(adev);
3053         if (r)
3054                 return r;
3055
3056         adev->ddev->mode_config.max_width = 16384;
3057         adev->ddev->mode_config.max_height = 16384;
3058
3059         /* allocate crtcs */
3060         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3061                 r = dce_v10_0_crtc_init(adev, i);
3062                 if (r)
3063                         return r;
3064         }
3065
3066         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3067                 amdgpu_print_display_setup(adev->ddev);
3068         else
3069                 return -EINVAL;
3070
3071         /* setup afmt */
3072         r = dce_v10_0_afmt_init(adev);
3073         if (r)
3074                 return r;
3075
3076         r = dce_v10_0_audio_init(adev);
3077         if (r)
3078                 return r;
3079
3080         drm_kms_helper_poll_init(adev->ddev);
3081
3082         adev->mode_info.mode_config_initialized = true;
3083         return 0;
3084 }
3085
3086 static int dce_v10_0_sw_fini(void *handle)
3087 {
3088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3089
3090         kfree(adev->mode_info.bios_hardcoded_edid);
3091
3092         drm_kms_helper_poll_fini(adev->ddev);
3093
3094         dce_v10_0_audio_fini(adev);
3095
3096         dce_v10_0_afmt_fini(adev);
3097
3098         drm_mode_config_cleanup(adev->ddev);
3099         adev->mode_info.mode_config_initialized = false;
3100
3101         return 0;
3102 }
3103
3104 static int dce_v10_0_hw_init(void *handle)
3105 {
3106         int i;
3107         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3108
3109         dce_v10_0_init_golden_registers(adev);
3110
3111         /* init dig PHYs, disp eng pll */
3112         amdgpu_atombios_encoder_init_dig(adev);
3113         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3114
3115         /* initialize hpd */
3116         dce_v10_0_hpd_init(adev);
3117
3118         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3119                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3120         }
3121
3122         dce_v10_0_pageflip_interrupt_init(adev);
3123
3124         return 0;
3125 }
3126
3127 static int dce_v10_0_hw_fini(void *handle)
3128 {
3129         int i;
3130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3131
3132         dce_v10_0_hpd_fini(adev);
3133
3134         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3135                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3136         }
3137
3138         dce_v10_0_pageflip_interrupt_fini(adev);
3139
3140         return 0;
3141 }
3142
3143 static int dce_v10_0_suspend(void *handle)
3144 {
3145         return dce_v10_0_hw_fini(handle);
3146 }
3147
3148 static int dce_v10_0_resume(void *handle)
3149 {
3150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3151         int ret;
3152
3153         ret = dce_v10_0_hw_init(handle);
3154
3155         /* turn on the BL */
3156         if (adev->mode_info.bl_encoder) {
3157                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3158                                                                   adev->mode_info.bl_encoder);
3159                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3160                                                     bl_level);
3161         }
3162
3163         return ret;
3164 }
3165
3166 static bool dce_v10_0_is_idle(void *handle)
3167 {
3168         return true;
3169 }
3170
3171 static int dce_v10_0_wait_for_idle(void *handle)
3172 {
3173         return 0;
3174 }
3175
3176 static bool dce_v10_0_check_soft_reset(void *handle)
3177 {
3178         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3179
3180         return dce_v10_0_is_display_hung(adev);
3181 }
3182
3183 static int dce_v10_0_soft_reset(void *handle)
3184 {
3185         u32 srbm_soft_reset = 0, tmp;
3186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3187
3188         if (dce_v10_0_is_display_hung(adev))
3189                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3190
3191         if (srbm_soft_reset) {
3192                 tmp = RREG32(mmSRBM_SOFT_RESET);
3193                 tmp |= srbm_soft_reset;
3194                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3195                 WREG32(mmSRBM_SOFT_RESET, tmp);
3196                 tmp = RREG32(mmSRBM_SOFT_RESET);
3197
3198                 udelay(50);
3199
3200                 tmp &= ~srbm_soft_reset;
3201                 WREG32(mmSRBM_SOFT_RESET, tmp);
3202                 tmp = RREG32(mmSRBM_SOFT_RESET);
3203
3204                 /* Wait a little for things to settle down */
3205                 udelay(50);
3206         }
3207         return 0;
3208 }
3209
3210 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3211                                                      int crtc,
3212                                                      enum amdgpu_interrupt_state state)
3213 {
3214         u32 lb_interrupt_mask;
3215
3216         if (crtc >= adev->mode_info.num_crtc) {
3217                 DRM_DEBUG("invalid crtc %d\n", crtc);
3218                 return;
3219         }
3220
3221         switch (state) {
3222         case AMDGPU_IRQ_STATE_DISABLE:
3223                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3224                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3225                                                   VBLANK_INTERRUPT_MASK, 0);
3226                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3227                 break;
3228         case AMDGPU_IRQ_STATE_ENABLE:
3229                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3230                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3231                                                   VBLANK_INTERRUPT_MASK, 1);
3232                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3233                 break;
3234         default:
3235                 break;
3236         }
3237 }
3238
3239 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3240                                                     int crtc,
3241                                                     enum amdgpu_interrupt_state state)
3242 {
3243         u32 lb_interrupt_mask;
3244
3245         if (crtc >= adev->mode_info.num_crtc) {
3246                 DRM_DEBUG("invalid crtc %d\n", crtc);
3247                 return;
3248         }
3249
3250         switch (state) {
3251         case AMDGPU_IRQ_STATE_DISABLE:
3252                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3253                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3254                                                   VLINE_INTERRUPT_MASK, 0);
3255                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3256                 break;
3257         case AMDGPU_IRQ_STATE_ENABLE:
3258                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3259                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3260                                                   VLINE_INTERRUPT_MASK, 1);
3261                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3262                 break;
3263         default:
3264                 break;
3265         }
3266 }
3267
3268 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3269                                        struct amdgpu_irq_src *source,
3270                                        unsigned hpd,
3271                                        enum amdgpu_interrupt_state state)
3272 {
3273         u32 tmp;
3274
3275         if (hpd >= adev->mode_info.num_hpd) {
3276                 DRM_DEBUG("invalid hdp %d\n", hpd);
3277                 return 0;
3278         }
3279
3280         switch (state) {
3281         case AMDGPU_IRQ_STATE_DISABLE:
3282                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3283                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3284                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3285                 break;
3286         case AMDGPU_IRQ_STATE_ENABLE:
3287                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3288                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3289                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3290                 break;
3291         default:
3292                 break;
3293         }
3294
3295         return 0;
3296 }
3297
3298 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3299                                         struct amdgpu_irq_src *source,
3300                                         unsigned type,
3301                                         enum amdgpu_interrupt_state state)
3302 {
3303         switch (type) {
3304         case AMDGPU_CRTC_IRQ_VBLANK1:
3305                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3306                 break;
3307         case AMDGPU_CRTC_IRQ_VBLANK2:
3308                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3309                 break;
3310         case AMDGPU_CRTC_IRQ_VBLANK3:
3311                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3312                 break;
3313         case AMDGPU_CRTC_IRQ_VBLANK4:
3314                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3315                 break;
3316         case AMDGPU_CRTC_IRQ_VBLANK5:
3317                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3318                 break;
3319         case AMDGPU_CRTC_IRQ_VBLANK6:
3320                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3321                 break;
3322         case AMDGPU_CRTC_IRQ_VLINE1:
3323                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3324                 break;
3325         case AMDGPU_CRTC_IRQ_VLINE2:
3326                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3327                 break;
3328         case AMDGPU_CRTC_IRQ_VLINE3:
3329                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3330                 break;
3331         case AMDGPU_CRTC_IRQ_VLINE4:
3332                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3333                 break;
3334         case AMDGPU_CRTC_IRQ_VLINE5:
3335                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3336                 break;
3337         case AMDGPU_CRTC_IRQ_VLINE6:
3338                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3339                 break;
3340         default:
3341                 break;
3342         }
3343         return 0;
3344 }
3345
3346 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3347                                             struct amdgpu_irq_src *src,
3348                                             unsigned type,
3349                                             enum amdgpu_interrupt_state state)
3350 {
3351         u32 reg;
3352
3353         if (type >= adev->mode_info.num_crtc) {
3354                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3355                 return -EINVAL;
3356         }
3357
3358         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3359         if (state == AMDGPU_IRQ_STATE_DISABLE)
3360                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3361                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3362         else
3363                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3364                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3365
3366         return 0;
3367 }
3368
3369 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3370                                   struct amdgpu_irq_src *source,
3371                                   struct amdgpu_iv_entry *entry)
3372 {
3373         unsigned long flags;
3374         unsigned crtc_id;
3375         struct amdgpu_crtc *amdgpu_crtc;
3376         struct amdgpu_flip_work *works;
3377
3378         crtc_id = (entry->src_id - 8) >> 1;
3379         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3380
3381         if (crtc_id >= adev->mode_info.num_crtc) {
3382                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3383                 return -EINVAL;
3384         }
3385
3386         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3387             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3388                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3389                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3390
3391         /* IRQ could occur when in initial stage */
3392         if (amdgpu_crtc == NULL)
3393                 return 0;
3394
3395         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3396         works = amdgpu_crtc->pflip_works;
3397         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3398                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3399                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3400                                                  amdgpu_crtc->pflip_status,
3401                                                  AMDGPU_FLIP_SUBMITTED);
3402                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3403                 return 0;
3404         }
3405
3406         /* page flip completed. clean up */
3407         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3408         amdgpu_crtc->pflip_works = NULL;
3409
3410         /* wakeup usersapce */
3411         if (works->event)
3412                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3413
3414         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3415
3416         drm_crtc_vblank_put(&amdgpu_crtc->base);
3417         schedule_work(&works->unpin_work);
3418
3419         return 0;
3420 }
3421
3422 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3423                                   int hpd)
3424 {
3425         u32 tmp;
3426
3427         if (hpd >= adev->mode_info.num_hpd) {
3428                 DRM_DEBUG("invalid hdp %d\n", hpd);
3429                 return;
3430         }
3431
3432         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3433         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3434         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3435 }
3436
3437 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3438                                           int crtc)
3439 {
3440         u32 tmp;
3441
3442         if (crtc >= adev->mode_info.num_crtc) {
3443                 DRM_DEBUG("invalid crtc %d\n", crtc);
3444                 return;
3445         }
3446
3447         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3448         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3449         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3450 }
3451
3452 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3453                                          int crtc)
3454 {
3455         u32 tmp;
3456
3457         if (crtc >= adev->mode_info.num_crtc) {
3458                 DRM_DEBUG("invalid crtc %d\n", crtc);
3459                 return;
3460         }
3461
3462         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3463         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3464         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3465 }
3466
3467 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3468                               struct amdgpu_irq_src *source,
3469                               struct amdgpu_iv_entry *entry)
3470 {
3471         unsigned crtc = entry->src_id - 1;
3472         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3473         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3474
3475         switch (entry->src_data) {
3476         case 0: /* vblank */
3477                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3478                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3479                 else
3480                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3481
3482                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3483                         drm_handle_vblank(adev->ddev, crtc);
3484                 }
3485                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3486
3487                 break;
3488         case 1: /* vline */
3489                 if (disp_int & interrupt_status_offsets[crtc].vline)
3490                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3491                 else
3492                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3493
3494                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3495
3496                 break;
3497         default:
3498                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3499                 break;
3500         }
3501
3502         return 0;
3503 }
3504
3505 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3506                              struct amdgpu_irq_src *source,
3507                              struct amdgpu_iv_entry *entry)
3508 {
3509         uint32_t disp_int, mask;
3510         unsigned hpd;
3511
3512         if (entry->src_data >= adev->mode_info.num_hpd) {
3513                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3514                 return 0;
3515         }
3516
3517         hpd = entry->src_data;
3518         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3519         mask = interrupt_status_offsets[hpd].hpd;
3520
3521         if (disp_int & mask) {
3522                 dce_v10_0_hpd_int_ack(adev, hpd);
3523                 schedule_work(&adev->hotplug_work);
3524                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3525         }
3526
3527         return 0;
3528 }
3529
3530 static int dce_v10_0_set_clockgating_state(void *handle,
3531                                           enum amd_clockgating_state state)
3532 {
3533         return 0;
3534 }
3535
3536 static int dce_v10_0_set_powergating_state(void *handle,
3537                                           enum amd_powergating_state state)
3538 {
3539         return 0;
3540 }
3541
3542 const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3543         .name = "dce_v10_0",
3544         .early_init = dce_v10_0_early_init,
3545         .late_init = NULL,
3546         .sw_init = dce_v10_0_sw_init,
3547         .sw_fini = dce_v10_0_sw_fini,
3548         .hw_init = dce_v10_0_hw_init,
3549         .hw_fini = dce_v10_0_hw_fini,
3550         .suspend = dce_v10_0_suspend,
3551         .resume = dce_v10_0_resume,
3552         .is_idle = dce_v10_0_is_idle,
3553         .wait_for_idle = dce_v10_0_wait_for_idle,
3554         .check_soft_reset = dce_v10_0_check_soft_reset,
3555         .soft_reset = dce_v10_0_soft_reset,
3556         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3557         .set_powergating_state = dce_v10_0_set_powergating_state,
3558 };
3559
3560 static void
3561 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3562                           struct drm_display_mode *mode,
3563                           struct drm_display_mode *adjusted_mode)
3564 {
3565         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3566
3567         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3568
3569         /* need to call this here rather than in prepare() since we need some crtc info */
3570         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3571
3572         /* set scaler clears this on some chips */
3573         dce_v10_0_set_interleave(encoder->crtc, mode);
3574
3575         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3576                 dce_v10_0_afmt_enable(encoder, true);
3577                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3578         }
3579 }
3580
3581 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3582 {
3583         struct amdgpu_device *adev = encoder->dev->dev_private;
3584         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3585         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3586
3587         if ((amdgpu_encoder->active_device &
3588              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3589             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3590              ENCODER_OBJECT_ID_NONE)) {
3591                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3592                 if (dig) {
3593                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3594                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3595                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3596                 }
3597         }
3598
3599         amdgpu_atombios_scratch_regs_lock(adev, true);
3600
3601         if (connector) {
3602                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3603
3604                 /* select the clock/data port if it uses a router */
3605                 if (amdgpu_connector->router.cd_valid)
3606                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3607
3608                 /* turn eDP panel on for mode set */
3609                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3610                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3611                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3612         }
3613
3614         /* this is needed for the pll/ss setup to work correctly in some cases */
3615         amdgpu_atombios_encoder_set_crtc_source(encoder);
3616         /* set up the FMT blocks */
3617         dce_v10_0_program_fmt(encoder);
3618 }
3619
3620 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3621 {
3622         struct drm_device *dev = encoder->dev;
3623         struct amdgpu_device *adev = dev->dev_private;
3624
3625         /* need to call this here as we need the crtc set up */
3626         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3627         amdgpu_atombios_scratch_regs_lock(adev, false);
3628 }
3629
3630 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3631 {
3632         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3633         struct amdgpu_encoder_atom_dig *dig;
3634
3635         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3636
3637         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3638                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3639                         dce_v10_0_afmt_enable(encoder, false);
3640                 dig = amdgpu_encoder->enc_priv;
3641                 dig->dig_encoder = -1;
3642         }
3643         amdgpu_encoder->active_device = 0;
3644 }
3645
3646 /* these are handled by the primary encoders */
3647 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3648 {
3649
3650 }
3651
3652 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3653 {
3654
3655 }
3656
3657 static void
3658 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3659                       struct drm_display_mode *mode,
3660                       struct drm_display_mode *adjusted_mode)
3661 {
3662
3663 }
3664
3665 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3666 {
3667
3668 }
3669
3670 static void
3671 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3672 {
3673
3674 }
3675
3676 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3677         .dpms = dce_v10_0_ext_dpms,
3678         .prepare = dce_v10_0_ext_prepare,
3679         .mode_set = dce_v10_0_ext_mode_set,
3680         .commit = dce_v10_0_ext_commit,
3681         .disable = dce_v10_0_ext_disable,
3682         /* no detect for TMDS/LVDS yet */
3683 };
3684
3685 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3686         .dpms = amdgpu_atombios_encoder_dpms,
3687         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3688         .prepare = dce_v10_0_encoder_prepare,
3689         .mode_set = dce_v10_0_encoder_mode_set,
3690         .commit = dce_v10_0_encoder_commit,
3691         .disable = dce_v10_0_encoder_disable,
3692         .detect = amdgpu_atombios_encoder_dig_detect,
3693 };
3694
3695 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3696         .dpms = amdgpu_atombios_encoder_dpms,
3697         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3698         .prepare = dce_v10_0_encoder_prepare,
3699         .mode_set = dce_v10_0_encoder_mode_set,
3700         .commit = dce_v10_0_encoder_commit,
3701         .detect = amdgpu_atombios_encoder_dac_detect,
3702 };
3703
3704 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3705 {
3706         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3707         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3708                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3709         kfree(amdgpu_encoder->enc_priv);
3710         drm_encoder_cleanup(encoder);
3711         kfree(amdgpu_encoder);
3712 }
3713
3714 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3715         .destroy = dce_v10_0_encoder_destroy,
3716 };
3717
3718 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3719                                  uint32_t encoder_enum,
3720                                  uint32_t supported_device,
3721                                  u16 caps)
3722 {
3723         struct drm_device *dev = adev->ddev;
3724         struct drm_encoder *encoder;
3725         struct amdgpu_encoder *amdgpu_encoder;
3726
3727         /* see if we already added it */
3728         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3729                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3730                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3731                         amdgpu_encoder->devices |= supported_device;
3732                         return;
3733                 }
3734
3735         }
3736
3737         /* add a new one */
3738         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3739         if (!amdgpu_encoder)
3740                 return;
3741
3742         encoder = &amdgpu_encoder->base;
3743         switch (adev->mode_info.num_crtc) {
3744         case 1:
3745                 encoder->possible_crtcs = 0x1;
3746                 break;
3747         case 2:
3748         default:
3749                 encoder->possible_crtcs = 0x3;
3750                 break;
3751         case 4:
3752                 encoder->possible_crtcs = 0xf;
3753                 break;
3754         case 6:
3755                 encoder->possible_crtcs = 0x3f;
3756                 break;
3757         }
3758
3759         amdgpu_encoder->enc_priv = NULL;
3760
3761         amdgpu_encoder->encoder_enum = encoder_enum;
3762         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3763         amdgpu_encoder->devices = supported_device;
3764         amdgpu_encoder->rmx_type = RMX_OFF;
3765         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3766         amdgpu_encoder->is_ext_encoder = false;
3767         amdgpu_encoder->caps = caps;
3768
3769         switch (amdgpu_encoder->encoder_id) {
3770         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3771         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3772                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3773                                  DRM_MODE_ENCODER_DAC, NULL);
3774                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3775                 break;
3776         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3777         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3778         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3779         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3780         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3781                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3782                         amdgpu_encoder->rmx_type = RMX_FULL;
3783                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3784                                          DRM_MODE_ENCODER_LVDS, NULL);
3785                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3786                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3787                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3788                                          DRM_MODE_ENCODER_DAC, NULL);
3789                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3790                 } else {
3791                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3792                                          DRM_MODE_ENCODER_TMDS, NULL);
3793                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3794                 }
3795                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3796                 break;
3797         case ENCODER_OBJECT_ID_SI170B:
3798         case ENCODER_OBJECT_ID_CH7303:
3799         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3800         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3801         case ENCODER_OBJECT_ID_TITFP513:
3802         case ENCODER_OBJECT_ID_VT1623:
3803         case ENCODER_OBJECT_ID_HDMI_SI1930:
3804         case ENCODER_OBJECT_ID_TRAVIS:
3805         case ENCODER_OBJECT_ID_NUTMEG:
3806                 /* these are handled by the primary encoders */
3807                 amdgpu_encoder->is_ext_encoder = true;
3808                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3809                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3810                                          DRM_MODE_ENCODER_LVDS, NULL);
3811                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3812                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3813                                          DRM_MODE_ENCODER_DAC, NULL);
3814                 else
3815                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3816                                          DRM_MODE_ENCODER_TMDS, NULL);
3817                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3818                 break;
3819         }
3820 }
3821
3822 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3823         .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3824         .bandwidth_update = &dce_v10_0_bandwidth_update,
3825         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3826         .vblank_wait = &dce_v10_0_vblank_wait,
3827         .is_display_hung = &dce_v10_0_is_display_hung,
3828         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3829         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3830         .hpd_sense = &dce_v10_0_hpd_sense,
3831         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3832         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3833         .page_flip = &dce_v10_0_page_flip,
3834         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3835         .add_encoder = &dce_v10_0_encoder_add,
3836         .add_connector = &amdgpu_connector_add,
3837         .stop_mc_access = &dce_v10_0_stop_mc_access,
3838         .resume_mc_access = &dce_v10_0_resume_mc_access,
3839 };
3840
3841 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3842 {
3843         if (adev->mode_info.funcs == NULL)
3844                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3845 }
3846
3847 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3848         .set = dce_v10_0_set_crtc_irq_state,
3849         .process = dce_v10_0_crtc_irq,
3850 };
3851
3852 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3853         .set = dce_v10_0_set_pageflip_irq_state,
3854         .process = dce_v10_0_pageflip_irq,
3855 };
3856
3857 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3858         .set = dce_v10_0_set_hpd_irq_state,
3859         .process = dce_v10_0_hpd_irq,
3860 };
3861
3862 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3863 {
3864         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3865         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3866
3867         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3868         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3869
3870         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3871         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3872 }