2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_10_0_d.h"
36 #include "dce/dce_10_0_sh_mask.h"
37 #include "dce/dce_10_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
46 static const u32 crtc_offsets[] =
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
57 static const u32 hpd_offsets[] =
67 static const uint32_t dig_offsets[] = {
83 } interrupt_status_offsets[] = { {
84 .reg = mmDISP_INTERRUPT_STATUS,
85 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
86 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
87 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
89 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
90 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
91 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
92 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
96 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
101 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115 static const u32 golden_settings_tonga_a11[] =
117 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
118 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
119 mmFBC_MISC, 0x1f311fff, 0x12300000,
120 mmHDMI_CONTROL, 0x31000111, 0x00000011,
123 static const u32 tonga_mgcg_cgcg_init[] =
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
129 static const u32 golden_settings_fiji_a10[] =
131 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
132 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
133 mmFBC_MISC, 0x1f311fff, 0x12300000,
134 mmHDMI_CONTROL, 0x31000111, 0x00000011,
137 static const u32 fiji_mgcg_cgcg_init[] =
139 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
140 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
145 switch (adev->asic_type) {
147 amdgpu_program_register_sequence(adev,
149 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
150 amdgpu_program_register_sequence(adev,
151 golden_settings_fiji_a10,
152 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
155 amdgpu_program_register_sequence(adev,
156 tonga_mgcg_cgcg_init,
157 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
158 amdgpu_program_register_sequence(adev,
159 golden_settings_tonga_a11,
160 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
168 u32 block_offset, u32 reg)
173 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
174 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
175 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
176 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
182 u32 block_offset, u32 reg, u32 v)
186 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
187 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
189 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
195 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
215 * dce_v10_0_vblank_wait - vblank wait asic callback.
217 * @adev: amdgpu_device pointer
218 * @crtc: crtc to wait for vblank on
220 * Wait for vblank on the requested crtc (evergreen+).
222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
226 if (crtc >= adev->mode_info.num_crtc)
229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
232 /* depending on when we hit vblank, we may be close to active; if so,
233 * wait for another frame.
235 while (dce_v10_0_is_in_vblank(adev, crtc)) {
238 if (!dce_v10_0_is_counter_moving(adev, crtc))
243 while (!dce_v10_0_is_in_vblank(adev, crtc)) {
246 if (!dce_v10_0_is_counter_moving(adev, crtc))
252 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
254 if (crtc >= adev->mode_info.num_crtc)
257 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
260 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
264 /* Enable pflip interrupts */
265 for (i = 0; i < adev->mode_info.num_crtc; i++)
266 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
269 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
273 /* Disable pflip interrupts */
274 for (i = 0; i < adev->mode_info.num_crtc; i++)
275 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
279 * dce_v10_0_page_flip - pageflip callback.
281 * @adev: amdgpu_device pointer
282 * @crtc_id: crtc to cleanup pageflip on
283 * @crtc_base: new address of the crtc (GPU MC address)
285 * Triggers the actual pageflip by updating the primary
286 * surface base address.
288 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
289 int crtc_id, u64 crtc_base, bool async)
291 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
294 /* flip at hsync for async, default is vsync */
295 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
296 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
297 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
298 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
299 /* update the primary scanout address */
300 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
301 upper_32_bits(crtc_base));
302 /* writing to the low address triggers the update */
303 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
304 lower_32_bits(crtc_base));
306 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
309 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
310 u32 *vbl, u32 *position)
312 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
315 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
316 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
322 * dce_v10_0_hpd_sense - hpd sense callback.
324 * @adev: amdgpu_device pointer
325 * @hpd: hpd (hotplug detect) pin
327 * Checks if a digital monitor is connected (evergreen+).
328 * Returns true if connected, false if not connected.
330 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
331 enum amdgpu_hpd_id hpd)
334 bool connected = false;
359 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
360 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
367 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
369 * @adev: amdgpu_device pointer
370 * @hpd: hpd (hotplug detect) pin
372 * Set the polarity of the hpd pin (evergreen+).
374 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
375 enum amdgpu_hpd_id hpd)
378 bool connected = dce_v10_0_hpd_sense(adev, hpd);
404 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
406 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
408 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
409 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
413 * dce_v10_0_hpd_init - hpd setup callback.
415 * @adev: amdgpu_device pointer
417 * Setup the hpd pins used by the card (evergreen+).
418 * Enable the pin, set the polarity, and enable the hpd interrupts.
420 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
422 struct drm_device *dev = adev->ddev;
423 struct drm_connector *connector;
427 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
428 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
430 switch (amdgpu_connector->hpd.hpd) {
453 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
454 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
455 /* don't try to enable hpd on eDP or LVDS avoid breaking the
456 * aux dp channel on imac and help (but not completely fix)
457 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
458 * also avoid interrupt storms during dpms.
460 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
461 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
462 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
466 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
467 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
468 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
470 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
471 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
472 DC_HPD_CONNECT_INT_DELAY,
473 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
474 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
475 DC_HPD_DISCONNECT_INT_DELAY,
476 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
477 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
479 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
480 amdgpu_irq_get(adev, &adev->hpd_irq,
481 amdgpu_connector->hpd.hpd);
486 * dce_v10_0_hpd_fini - hpd tear down callback.
488 * @adev: amdgpu_device pointer
490 * Tear down the hpd pins used by the card (evergreen+).
491 * Disable the hpd interrupts.
493 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
495 struct drm_device *dev = adev->ddev;
496 struct drm_connector *connector;
500 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
501 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
503 switch (amdgpu_connector->hpd.hpd) {
526 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
527 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
528 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
530 amdgpu_irq_put(adev, &adev->hpd_irq,
531 amdgpu_connector->hpd.hpd);
535 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
537 return mmDC_GPIO_HPD_A;
540 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
546 for (i = 0; i < adev->mode_info.num_crtc; i++) {
547 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
548 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
549 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
550 crtc_hung |= (1 << i);
554 for (j = 0; j < 10; j++) {
555 for (i = 0; i < adev->mode_info.num_crtc; i++) {
556 if (crtc_hung & (1 << i)) {
557 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
558 if (tmp != crtc_status[i])
559 crtc_hung &= ~(1 << i);
570 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
571 struct amdgpu_mode_mc_save *save)
573 u32 crtc_enabled, tmp;
576 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
577 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
579 /* disable VGA render */
580 tmp = RREG32(mmVGA_RENDER_CONTROL);
581 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
582 WREG32(mmVGA_RENDER_CONTROL, tmp);
584 /* blank the display controllers */
585 for (i = 0; i < adev->mode_info.num_crtc; i++) {
586 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
587 CRTC_CONTROL, CRTC_MASTER_EN);
593 save->crtc_enabled[i] = true;
594 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
595 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
596 amdgpu_display_vblank_wait(adev, i);
597 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
598 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
599 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
600 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
602 /* wait for the next frame */
603 frame_count = amdgpu_display_vblank_get_counter(adev, i);
604 for (j = 0; j < adev->usec_timeout; j++) {
605 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
609 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
610 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
611 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
612 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
614 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
615 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
616 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
617 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
620 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
621 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
622 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
623 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
624 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
625 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
626 save->crtc_enabled[i] = false;
630 save->crtc_enabled[i] = false;
635 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
636 struct amdgpu_mode_mc_save *save)
638 u32 tmp, frame_count;
641 /* update crtc base addresses */
642 for (i = 0; i < adev->mode_info.num_crtc; i++) {
643 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
644 upper_32_bits(adev->mc.vram_start));
645 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
646 upper_32_bits(adev->mc.vram_start));
647 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
648 (u32)adev->mc.vram_start);
649 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
650 (u32)adev->mc.vram_start);
652 if (save->crtc_enabled[i]) {
653 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
654 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
655 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
656 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
658 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
659 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
660 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
661 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
663 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
664 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
665 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
666 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
668 for (j = 0; j < adev->usec_timeout; j++) {
669 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
670 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
674 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
675 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
676 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
677 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
678 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
679 /* wait for the next frame */
680 frame_count = amdgpu_display_vblank_get_counter(adev, i);
681 for (j = 0; j < adev->usec_timeout; j++) {
682 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
689 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
690 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
692 /* Unlock vga access */
693 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
695 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
698 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
703 /* Lockout access through VGA aperture*/
704 tmp = RREG32(mmVGA_HDP_CONTROL);
706 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
708 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
709 WREG32(mmVGA_HDP_CONTROL, tmp);
711 /* disable VGA render */
712 tmp = RREG32(mmVGA_RENDER_CONTROL);
714 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
716 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
717 WREG32(mmVGA_RENDER_CONTROL, tmp);
720 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
724 switch (adev->asic_type) {
735 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
737 /*Disable VGA render and enabled crtc, if has DCE engine*/
738 if (amdgpu_atombios_has_dce_engine_info(adev)) {
742 dce_v10_0_set_vga_render_state(adev, false);
745 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
746 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
747 CRTC_CONTROL, CRTC_MASTER_EN);
749 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
750 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
751 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
752 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
753 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
759 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
761 struct drm_device *dev = encoder->dev;
762 struct amdgpu_device *adev = dev->dev_private;
763 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
764 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
765 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
768 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
771 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
772 bpc = amdgpu_connector_get_monitor_bpc(connector);
773 dither = amdgpu_connector->dither;
776 /* LVDS/eDP FMT is set up by atom */
777 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
780 /* not needed for analog */
781 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
782 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
790 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
791 /* XXX sort out optimal dither settings */
792 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
793 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
794 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
795 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
797 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
798 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
802 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
803 /* XXX sort out optimal dither settings */
804 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
805 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
806 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
807 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
808 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
810 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
811 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
815 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
816 /* XXX sort out optimal dither settings */
817 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
818 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
819 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
820 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
821 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
823 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
824 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
832 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
836 /* display watermark setup */
838 * dce_v10_0_line_buffer_adjust - Set up the line buffer
840 * @adev: amdgpu_device pointer
841 * @amdgpu_crtc: the selected display controller
842 * @mode: the current display mode on the selected display
845 * Setup up the line buffer allocation for
846 * the selected display controller (CIK).
847 * Returns the line buffer size in pixels.
849 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
850 struct amdgpu_crtc *amdgpu_crtc,
851 struct drm_display_mode *mode)
853 u32 tmp, buffer_alloc, i, mem_cfg;
854 u32 pipe_offset = amdgpu_crtc->crtc_id;
857 * There are 6 line buffers, one for each display controllers.
858 * There are 3 partitions per LB. Select the number of partitions
859 * to enable based on the display width. For display widths larger
860 * than 4096, you need use to use 2 display controllers and combine
861 * them using the stereo blender.
863 if (amdgpu_crtc->base.enabled && mode) {
864 if (mode->crtc_hdisplay < 1920) {
867 } else if (mode->crtc_hdisplay < 2560) {
870 } else if (mode->crtc_hdisplay < 4096) {
872 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
874 DRM_DEBUG_KMS("Mode too big for LB!\n");
876 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
883 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
884 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
885 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
887 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
888 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
889 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
891 for (i = 0; i < adev->usec_timeout; i++) {
892 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
893 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
898 if (amdgpu_crtc->base.enabled && mode) {
910 /* controller not enabled, so no lb used */
915 * cik_get_number_of_dram_channels - get the number of dram channels
917 * @adev: amdgpu_device pointer
919 * Look up the number of video ram channels (CIK).
920 * Used for display watermark bandwidth calculations
921 * Returns the number of dram channels
923 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
925 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
927 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
950 struct dce10_wm_params {
951 u32 dram_channels; /* number of dram channels */
952 u32 yclk; /* bandwidth per dram data pin in kHz */
953 u32 sclk; /* engine clock in kHz */
954 u32 disp_clk; /* display clock in kHz */
955 u32 src_width; /* viewport width */
956 u32 active_time; /* active display time in ns */
957 u32 blank_time; /* blank time in ns */
958 bool interlaced; /* mode is interlaced */
959 fixed20_12 vsc; /* vertical scale ratio */
960 u32 num_heads; /* number of active crtcs */
961 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
962 u32 lb_size; /* line buffer allocated to pipe */
963 u32 vtaps; /* vertical scaler taps */
967 * dce_v10_0_dram_bandwidth - get the dram bandwidth
969 * @wm: watermark calculation data
971 * Calculate the raw dram bandwidth (CIK).
972 * Used for display watermark bandwidth calculations
973 * Returns the dram bandwidth in MBytes/s
975 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
977 /* Calculate raw DRAM Bandwidth */
978 fixed20_12 dram_efficiency; /* 0.7 */
979 fixed20_12 yclk, dram_channels, bandwidth;
982 a.full = dfixed_const(1000);
983 yclk.full = dfixed_const(wm->yclk);
984 yclk.full = dfixed_div(yclk, a);
985 dram_channels.full = dfixed_const(wm->dram_channels * 4);
986 a.full = dfixed_const(10);
987 dram_efficiency.full = dfixed_const(7);
988 dram_efficiency.full = dfixed_div(dram_efficiency, a);
989 bandwidth.full = dfixed_mul(dram_channels, yclk);
990 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
992 return dfixed_trunc(bandwidth);
996 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
998 * @wm: watermark calculation data
1000 * Calculate the dram bandwidth used for display (CIK).
1001 * Used for display watermark bandwidth calculations
1002 * Returns the dram bandwidth for display in MBytes/s
1004 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1006 /* Calculate DRAM Bandwidth and the part allocated to display. */
1007 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1008 fixed20_12 yclk, dram_channels, bandwidth;
1011 a.full = dfixed_const(1000);
1012 yclk.full = dfixed_const(wm->yclk);
1013 yclk.full = dfixed_div(yclk, a);
1014 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1015 a.full = dfixed_const(10);
1016 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1017 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1018 bandwidth.full = dfixed_mul(dram_channels, yclk);
1019 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1021 return dfixed_trunc(bandwidth);
1025 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
1027 * @wm: watermark calculation data
1029 * Calculate the data return bandwidth used for display (CIK).
1030 * Used for display watermark bandwidth calculations
1031 * Returns the data return bandwidth in MBytes/s
1033 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
1035 /* Calculate the display Data return Bandwidth */
1036 fixed20_12 return_efficiency; /* 0.8 */
1037 fixed20_12 sclk, bandwidth;
1040 a.full = dfixed_const(1000);
1041 sclk.full = dfixed_const(wm->sclk);
1042 sclk.full = dfixed_div(sclk, a);
1043 a.full = dfixed_const(10);
1044 return_efficiency.full = dfixed_const(8);
1045 return_efficiency.full = dfixed_div(return_efficiency, a);
1046 a.full = dfixed_const(32);
1047 bandwidth.full = dfixed_mul(a, sclk);
1048 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1050 return dfixed_trunc(bandwidth);
1054 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1056 * @wm: watermark calculation data
1058 * Calculate the dmif bandwidth used for display (CIK).
1059 * Used for display watermark bandwidth calculations
1060 * Returns the dmif bandwidth in MBytes/s
1062 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1064 /* Calculate the DMIF Request Bandwidth */
1065 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1066 fixed20_12 disp_clk, bandwidth;
1069 a.full = dfixed_const(1000);
1070 disp_clk.full = dfixed_const(wm->disp_clk);
1071 disp_clk.full = dfixed_div(disp_clk, a);
1072 a.full = dfixed_const(32);
1073 b.full = dfixed_mul(a, disp_clk);
1075 a.full = dfixed_const(10);
1076 disp_clk_request_efficiency.full = dfixed_const(8);
1077 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1079 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1081 return dfixed_trunc(bandwidth);
1085 * dce_v10_0_available_bandwidth - get the min available bandwidth
1087 * @wm: watermark calculation data
1089 * Calculate the min available bandwidth used for display (CIK).
1090 * Used for display watermark bandwidth calculations
1091 * Returns the min available bandwidth in MBytes/s
1093 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1095 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1096 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1097 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1098 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1100 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1104 * dce_v10_0_average_bandwidth - get the average available bandwidth
1106 * @wm: watermark calculation data
1108 * Calculate the average available bandwidth used for display (CIK).
1109 * Used for display watermark bandwidth calculations
1110 * Returns the average available bandwidth in MBytes/s
1112 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1114 /* Calculate the display mode Average Bandwidth
1115 * DisplayMode should contain the source and destination dimensions,
1119 fixed20_12 line_time;
1120 fixed20_12 src_width;
1121 fixed20_12 bandwidth;
1124 a.full = dfixed_const(1000);
1125 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1126 line_time.full = dfixed_div(line_time, a);
1127 bpp.full = dfixed_const(wm->bytes_per_pixel);
1128 src_width.full = dfixed_const(wm->src_width);
1129 bandwidth.full = dfixed_mul(src_width, bpp);
1130 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1131 bandwidth.full = dfixed_div(bandwidth, line_time);
1133 return dfixed_trunc(bandwidth);
1137 * dce_v10_0_latency_watermark - get the latency watermark
1139 * @wm: watermark calculation data
1141 * Calculate the latency watermark (CIK).
1142 * Used for display watermark bandwidth calculations
1143 * Returns the latency watermark in ns
1145 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1147 /* First calculate the latency in ns */
1148 u32 mc_latency = 2000; /* 2000 ns. */
1149 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1150 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1151 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1152 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1153 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1154 (wm->num_heads * cursor_line_pair_return_time);
1155 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1156 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1157 u32 tmp, dmif_size = 12288;
1160 if (wm->num_heads == 0)
1163 a.full = dfixed_const(2);
1164 b.full = dfixed_const(1);
1165 if ((wm->vsc.full > a.full) ||
1166 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1168 ((wm->vsc.full >= a.full) && wm->interlaced))
1169 max_src_lines_per_dst_line = 4;
1171 max_src_lines_per_dst_line = 2;
1173 a.full = dfixed_const(available_bandwidth);
1174 b.full = dfixed_const(wm->num_heads);
1175 a.full = dfixed_div(a, b);
1176 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1177 tmp = min(dfixed_trunc(a), tmp);
1179 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1181 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1182 b.full = dfixed_const(1000);
1183 c.full = dfixed_const(lb_fill_bw);
1184 b.full = dfixed_div(c, b);
1185 a.full = dfixed_div(a, b);
1186 line_fill_time = dfixed_trunc(a);
1188 if (line_fill_time < wm->active_time)
1191 return latency + (line_fill_time - wm->active_time);
1196 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1197 * average and available dram bandwidth
1199 * @wm: watermark calculation data
1201 * Check if the display average bandwidth fits in the display
1202 * dram bandwidth (CIK).
1203 * Used for display watermark bandwidth calculations
1204 * Returns true if the display fits, false if not.
1206 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1208 if (dce_v10_0_average_bandwidth(wm) <=
1209 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1216 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1217 * average and available bandwidth
1219 * @wm: watermark calculation data
1221 * Check if the display average bandwidth fits in the display
1222 * available bandwidth (CIK).
1223 * Used for display watermark bandwidth calculations
1224 * Returns true if the display fits, false if not.
1226 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1228 if (dce_v10_0_average_bandwidth(wm) <=
1229 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1236 * dce_v10_0_check_latency_hiding - check latency hiding
1238 * @wm: watermark calculation data
1240 * Check latency hiding (CIK).
1241 * Used for display watermark bandwidth calculations
1242 * Returns true if the display fits, false if not.
1244 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1246 u32 lb_partitions = wm->lb_size / wm->src_width;
1247 u32 line_time = wm->active_time + wm->blank_time;
1248 u32 latency_tolerant_lines;
1252 a.full = dfixed_const(1);
1253 if (wm->vsc.full > a.full)
1254 latency_tolerant_lines = 1;
1256 if (lb_partitions <= (wm->vtaps + 1))
1257 latency_tolerant_lines = 1;
1259 latency_tolerant_lines = 2;
1262 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1264 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1271 * dce_v10_0_program_watermarks - program display watermarks
1273 * @adev: amdgpu_device pointer
1274 * @amdgpu_crtc: the selected display controller
1275 * @lb_size: line buffer size
1276 * @num_heads: number of display controllers in use
1278 * Calculate and program the display watermarks for the
1279 * selected display controller (CIK).
1281 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1282 struct amdgpu_crtc *amdgpu_crtc,
1283 u32 lb_size, u32 num_heads)
1285 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1286 struct dce10_wm_params wm_low, wm_high;
1289 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1290 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1292 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1293 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1295 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1297 line_time = min(line_time, (u32)65535);
1299 /* watermark for high clocks */
1300 if (adev->pm.dpm_enabled) {
1302 amdgpu_dpm_get_mclk(adev, false) * 10;
1304 amdgpu_dpm_get_sclk(adev, false) * 10;
1306 wm_high.yclk = adev->pm.current_mclk * 10;
1307 wm_high.sclk = adev->pm.current_sclk * 10;
1310 wm_high.disp_clk = mode->clock;
1311 wm_high.src_width = mode->crtc_hdisplay;
1312 wm_high.active_time = active_time;
1313 wm_high.blank_time = line_time - wm_high.active_time;
1314 wm_high.interlaced = false;
1315 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1316 wm_high.interlaced = true;
1317 wm_high.vsc = amdgpu_crtc->vsc;
1319 if (amdgpu_crtc->rmx_type != RMX_OFF)
1321 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1322 wm_high.lb_size = lb_size;
1323 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1324 wm_high.num_heads = num_heads;
1326 /* set for high clocks */
1327 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1329 /* possibly force display priority to high */
1330 /* should really do this at mode validation time... */
1331 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1332 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1333 !dce_v10_0_check_latency_hiding(&wm_high) ||
1334 (adev->mode_info.disp_priority == 2)) {
1335 DRM_DEBUG_KMS("force priority to high\n");
1338 /* watermark for low clocks */
1339 if (adev->pm.dpm_enabled) {
1341 amdgpu_dpm_get_mclk(adev, true) * 10;
1343 amdgpu_dpm_get_sclk(adev, true) * 10;
1345 wm_low.yclk = adev->pm.current_mclk * 10;
1346 wm_low.sclk = adev->pm.current_sclk * 10;
1349 wm_low.disp_clk = mode->clock;
1350 wm_low.src_width = mode->crtc_hdisplay;
1351 wm_low.active_time = active_time;
1352 wm_low.blank_time = line_time - wm_low.active_time;
1353 wm_low.interlaced = false;
1354 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1355 wm_low.interlaced = true;
1356 wm_low.vsc = amdgpu_crtc->vsc;
1358 if (amdgpu_crtc->rmx_type != RMX_OFF)
1360 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1361 wm_low.lb_size = lb_size;
1362 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1363 wm_low.num_heads = num_heads;
1365 /* set for low clocks */
1366 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1368 /* possibly force display priority to high */
1369 /* should really do this at mode validation time... */
1370 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1371 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1372 !dce_v10_0_check_latency_hiding(&wm_low) ||
1373 (adev->mode_info.disp_priority == 2)) {
1374 DRM_DEBUG_KMS("force priority to high\n");
1376 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1380 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1381 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1382 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1383 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1384 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1385 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1386 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1388 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1389 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1390 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1391 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1392 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1393 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1394 /* restore original selection */
1395 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1397 /* save values for DPM */
1398 amdgpu_crtc->line_time = line_time;
1399 amdgpu_crtc->wm_high = latency_watermark_a;
1400 amdgpu_crtc->wm_low = latency_watermark_b;
1401 /* Save number of lines the linebuffer leads before the scanout */
1402 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1406 * dce_v10_0_bandwidth_update - program display watermarks
1408 * @adev: amdgpu_device pointer
1410 * Calculate and program the display watermarks and line
1411 * buffer allocation (CIK).
1413 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1415 struct drm_display_mode *mode = NULL;
1416 u32 num_heads = 0, lb_size;
1419 amdgpu_update_display_priority(adev);
1421 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1422 if (adev->mode_info.crtcs[i]->base.enabled)
1425 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1426 mode = &adev->mode_info.crtcs[i]->base.mode;
1427 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1428 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1429 lb_size, num_heads);
1433 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1438 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1439 offset = adev->mode_info.audio.pin[i].offset;
1440 tmp = RREG32_AUDIO_ENDPT(offset,
1441 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1443 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1444 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1445 adev->mode_info.audio.pin[i].connected = false;
1447 adev->mode_info.audio.pin[i].connected = true;
1451 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1455 dce_v10_0_audio_get_connected_pins(adev);
1457 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1458 if (adev->mode_info.audio.pin[i].connected)
1459 return &adev->mode_info.audio.pin[i];
1461 DRM_ERROR("No connected audio pins found!\n");
1465 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1467 struct amdgpu_device *adev = encoder->dev->dev_private;
1468 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1469 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1472 if (!dig || !dig->afmt || !dig->afmt->pin)
1475 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1476 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1477 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1480 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1481 struct drm_display_mode *mode)
1483 struct amdgpu_device *adev = encoder->dev->dev_private;
1484 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1485 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1486 struct drm_connector *connector;
1487 struct amdgpu_connector *amdgpu_connector = NULL;
1491 if (!dig || !dig->afmt || !dig->afmt->pin)
1494 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1495 if (connector->encoder == encoder) {
1496 amdgpu_connector = to_amdgpu_connector(connector);
1501 if (!amdgpu_connector) {
1502 DRM_ERROR("Couldn't find encoder's connector\n");
1506 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1508 if (connector->latency_present[interlace]) {
1509 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1510 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1511 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1512 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1514 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1516 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1519 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1520 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1523 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1525 struct amdgpu_device *adev = encoder->dev->dev_private;
1526 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1527 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1528 struct drm_connector *connector;
1529 struct amdgpu_connector *amdgpu_connector = NULL;
1534 if (!dig || !dig->afmt || !dig->afmt->pin)
1537 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1538 if (connector->encoder == encoder) {
1539 amdgpu_connector = to_amdgpu_connector(connector);
1544 if (!amdgpu_connector) {
1545 DRM_ERROR("Couldn't find encoder's connector\n");
1549 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1550 if (sad_count < 0) {
1551 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1555 /* program the speaker allocation */
1556 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1557 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1558 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1561 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1562 HDMI_CONNECTION, 1);
1564 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1565 SPEAKER_ALLOCATION, sadb[0]);
1567 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1568 SPEAKER_ALLOCATION, 5); /* stereo */
1569 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1570 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1575 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1577 struct amdgpu_device *adev = encoder->dev->dev_private;
1578 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1579 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1580 struct drm_connector *connector;
1581 struct amdgpu_connector *amdgpu_connector = NULL;
1582 struct cea_sad *sads;
1585 static const u16 eld_reg_to_type[][2] = {
1586 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1587 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1588 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1589 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1590 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1591 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1592 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1593 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1594 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1595 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1596 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1597 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1600 if (!dig || !dig->afmt || !dig->afmt->pin)
1603 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1604 if (connector->encoder == encoder) {
1605 amdgpu_connector = to_amdgpu_connector(connector);
1610 if (!amdgpu_connector) {
1611 DRM_ERROR("Couldn't find encoder's connector\n");
1615 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1616 if (sad_count <= 0) {
1617 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1622 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1624 u8 stereo_freqs = 0;
1625 int max_channels = -1;
1628 for (j = 0; j < sad_count; j++) {
1629 struct cea_sad *sad = &sads[j];
1631 if (sad->format == eld_reg_to_type[i][1]) {
1632 if (sad->channels > max_channels) {
1633 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1634 MAX_CHANNELS, sad->channels);
1635 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1636 DESCRIPTOR_BYTE_2, sad->byte2);
1637 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1638 SUPPORTED_FREQUENCIES, sad->freq);
1639 max_channels = sad->channels;
1642 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1643 stereo_freqs |= sad->freq;
1649 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1650 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1651 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1657 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1658 struct amdgpu_audio_pin *pin,
1664 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1665 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1668 static const u32 pin_offsets[] =
1670 AUD0_REGISTER_OFFSET,
1671 AUD1_REGISTER_OFFSET,
1672 AUD2_REGISTER_OFFSET,
1673 AUD3_REGISTER_OFFSET,
1674 AUD4_REGISTER_OFFSET,
1675 AUD5_REGISTER_OFFSET,
1676 AUD6_REGISTER_OFFSET,
1679 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1686 adev->mode_info.audio.enabled = true;
1688 adev->mode_info.audio.num_pins = 7;
1690 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1691 adev->mode_info.audio.pin[i].channels = -1;
1692 adev->mode_info.audio.pin[i].rate = -1;
1693 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1694 adev->mode_info.audio.pin[i].status_bits = 0;
1695 adev->mode_info.audio.pin[i].category_code = 0;
1696 adev->mode_info.audio.pin[i].connected = false;
1697 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1698 adev->mode_info.audio.pin[i].id = i;
1699 /* disable audio. it will be set up later */
1700 /* XXX remove once we switch to ip funcs */
1701 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1707 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1714 if (!adev->mode_info.audio.enabled)
1717 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1718 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1720 adev->mode_info.audio.enabled = false;
1724 * update the N and CTS parameters for a given pixel clock rate
1726 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1728 struct drm_device *dev = encoder->dev;
1729 struct amdgpu_device *adev = dev->dev_private;
1730 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1731 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1732 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1735 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1736 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1737 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1738 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1739 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1740 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1742 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1743 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1744 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1745 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1746 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1747 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1749 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1750 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1751 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1752 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1753 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1754 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1759 * build a HDMI Video Info Frame
1761 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1762 void *buffer, size_t size)
1764 struct drm_device *dev = encoder->dev;
1765 struct amdgpu_device *adev = dev->dev_private;
1766 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1767 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1768 uint8_t *frame = buffer + 3;
1769 uint8_t *header = buffer;
1771 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1772 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1773 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1774 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1775 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1776 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1777 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1778 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1781 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1783 struct drm_device *dev = encoder->dev;
1784 struct amdgpu_device *adev = dev->dev_private;
1785 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1786 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1787 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1788 u32 dto_phase = 24 * 1000;
1789 u32 dto_modulo = clock;
1792 if (!dig || !dig->afmt)
1795 /* XXX two dtos; generally use dto0 for hdmi */
1796 /* Express [24MHz / target pixel clock] as an exact rational
1797 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1798 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1800 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1801 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1802 amdgpu_crtc->crtc_id);
1803 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1804 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1805 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1809 * update the info frames with the data from the current display mode
1811 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1812 struct drm_display_mode *mode)
1814 struct drm_device *dev = encoder->dev;
1815 struct amdgpu_device *adev = dev->dev_private;
1816 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1817 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1818 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1819 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1820 struct hdmi_avi_infoframe frame;
1825 if (!dig || !dig->afmt)
1828 /* Silent, r600_hdmi_enable will raise WARN for us */
1829 if (!dig->afmt->enabled)
1832 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1833 if (encoder->crtc) {
1834 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1835 bpc = amdgpu_crtc->bpc;
1838 /* disable audio prior to setting up hw */
1839 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1840 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1842 dce_v10_0_audio_set_dto(encoder, mode->clock);
1844 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1845 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1846 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1848 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1850 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1857 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1858 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1859 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1860 connector->name, bpc);
1863 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1864 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1865 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1869 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1870 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1871 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1875 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1877 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1878 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1879 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1880 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1881 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1883 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1884 /* enable audio info frames (frames won't be set until audio is enabled) */
1885 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1886 /* required for audio info values to be updated */
1887 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1888 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1890 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1891 /* required for audio info values to be updated */
1892 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1893 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1895 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1896 /* anything other than 0 */
1897 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1898 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1900 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1902 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1903 /* set the default audio delay */
1904 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1905 /* should be suffient for all audio modes and small enough for all hblanks */
1906 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1907 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1909 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1910 /* allow 60958 channel status fields to be updated */
1911 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1912 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1914 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1916 /* clear SW CTS value */
1917 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1919 /* select SW CTS value */
1920 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1921 /* allow hw to sent ACR packets when required */
1922 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1923 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1925 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1927 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1928 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1929 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1931 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1932 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1933 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1935 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1936 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1937 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1938 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1939 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1940 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1941 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1942 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1944 dce_v10_0_audio_write_speaker_allocation(encoder);
1946 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1947 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1949 dce_v10_0_afmt_audio_select_pin(encoder);
1950 dce_v10_0_audio_write_sad_regs(encoder);
1951 dce_v10_0_audio_write_latency_fields(encoder, mode);
1953 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1955 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1959 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1961 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1965 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1967 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1968 /* enable AVI info frames */
1969 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1970 /* required for audio info values to be updated */
1971 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1972 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1974 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1975 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1976 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1978 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1979 /* send audio packets */
1980 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1981 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1983 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1984 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1985 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1986 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1988 /* enable audio after to setting up hw */
1989 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1992 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1994 struct drm_device *dev = encoder->dev;
1995 struct amdgpu_device *adev = dev->dev_private;
1996 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1997 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1999 if (!dig || !dig->afmt)
2002 /* Silent, r600_hdmi_enable will raise WARN for us */
2003 if (enable && dig->afmt->enabled)
2005 if (!enable && !dig->afmt->enabled)
2008 if (!enable && dig->afmt->pin) {
2009 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
2010 dig->afmt->pin = NULL;
2013 dig->afmt->enabled = enable;
2015 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
2016 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
2019 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
2023 for (i = 0; i < adev->mode_info.num_dig; i++)
2024 adev->mode_info.afmt[i] = NULL;
2026 /* DCE10 has audio blocks tied to DIG encoders */
2027 for (i = 0; i < adev->mode_info.num_dig; i++) {
2028 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
2029 if (adev->mode_info.afmt[i]) {
2030 adev->mode_info.afmt[i]->offset = dig_offsets[i];
2031 adev->mode_info.afmt[i]->id = i;
2034 for (j = 0; j < i; j++) {
2035 kfree(adev->mode_info.afmt[j]);
2036 adev->mode_info.afmt[j] = NULL;
2044 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
2048 for (i = 0; i < adev->mode_info.num_dig; i++) {
2049 kfree(adev->mode_info.afmt[i]);
2050 adev->mode_info.afmt[i] = NULL;
2054 static const u32 vga_control_regs[6] =
2064 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2066 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2067 struct drm_device *dev = crtc->dev;
2068 struct amdgpu_device *adev = dev->dev_private;
2071 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2073 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2075 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2078 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2080 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2081 struct drm_device *dev = crtc->dev;
2082 struct amdgpu_device *adev = dev->dev_private;
2085 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2087 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2090 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2091 struct drm_framebuffer *fb,
2092 int x, int y, int atomic)
2094 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2095 struct drm_device *dev = crtc->dev;
2096 struct amdgpu_device *adev = dev->dev_private;
2097 struct amdgpu_framebuffer *amdgpu_fb;
2098 struct drm_framebuffer *target_fb;
2099 struct drm_gem_object *obj;
2100 struct amdgpu_bo *abo;
2101 uint64_t fb_location, tiling_flags;
2102 uint32_t fb_format, fb_pitch_pixels;
2103 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2105 u32 tmp, viewport_w, viewport_h;
2107 bool bypass_lut = false;
2111 if (!atomic && !crtc->primary->fb) {
2112 DRM_DEBUG_KMS("No FB bound\n");
2117 amdgpu_fb = to_amdgpu_framebuffer(fb);
2120 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2121 target_fb = crtc->primary->fb;
2124 /* If atomic, assume fb object is pinned & idle & fenced and
2125 * just update base pointers
2127 obj = amdgpu_fb->obj;
2128 abo = gem_to_amdgpu_bo(obj);
2129 r = amdgpu_bo_reserve(abo, false);
2130 if (unlikely(r != 0))
2134 fb_location = amdgpu_bo_gpu_offset(abo);
2136 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2137 if (unlikely(r != 0)) {
2138 amdgpu_bo_unreserve(abo);
2143 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2144 amdgpu_bo_unreserve(abo);
2146 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2148 switch (target_fb->pixel_format) {
2150 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2151 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2153 case DRM_FORMAT_XRGB4444:
2154 case DRM_FORMAT_ARGB4444:
2155 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2156 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2158 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2162 case DRM_FORMAT_XRGB1555:
2163 case DRM_FORMAT_ARGB1555:
2164 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2165 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2167 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2171 case DRM_FORMAT_BGRX5551:
2172 case DRM_FORMAT_BGRA5551:
2173 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2174 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2176 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2180 case DRM_FORMAT_RGB565:
2181 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2182 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2184 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2188 case DRM_FORMAT_XRGB8888:
2189 case DRM_FORMAT_ARGB8888:
2190 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2191 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2193 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2197 case DRM_FORMAT_XRGB2101010:
2198 case DRM_FORMAT_ARGB2101010:
2199 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2200 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2202 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2205 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2208 case DRM_FORMAT_BGRX1010102:
2209 case DRM_FORMAT_BGRA1010102:
2210 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2211 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2213 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2216 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2220 format_name = drm_get_format_name(target_fb->pixel_format);
2221 DRM_ERROR("Unsupported screen format %s\n", format_name);
2226 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2227 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2229 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2230 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2231 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2232 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2233 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2235 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2236 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2237 ARRAY_2D_TILED_THIN1);
2238 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2240 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2241 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2242 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2244 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2245 ADDR_SURF_MICRO_TILING_DISPLAY);
2246 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2247 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2248 ARRAY_1D_TILED_THIN1);
2251 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2254 dce_v10_0_vga_enable(crtc, false);
2256 /* Make sure surface address is updated at vertical blank rather than
2259 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2260 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2261 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2262 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2264 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2265 upper_32_bits(fb_location));
2266 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2267 upper_32_bits(fb_location));
2268 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2269 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2270 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2271 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2272 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2273 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2276 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2277 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2278 * retain the full precision throughout the pipeline.
2280 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2282 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2284 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2285 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2288 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2290 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2291 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2292 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2293 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2294 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2295 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2297 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2298 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2300 dce_v10_0_grph_enable(crtc, true);
2302 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2307 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2309 viewport_w = crtc->mode.hdisplay;
2310 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2311 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2312 (viewport_w << 16) | viewport_h);
2314 /* set pageflip to happen anywhere in vblank interval */
2315 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2317 if (!atomic && fb && fb != crtc->primary->fb) {
2318 amdgpu_fb = to_amdgpu_framebuffer(fb);
2319 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2320 r = amdgpu_bo_reserve(abo, false);
2321 if (unlikely(r != 0))
2323 amdgpu_bo_unpin(abo);
2324 amdgpu_bo_unreserve(abo);
2327 /* Bytes per pixel may have changed */
2328 dce_v10_0_bandwidth_update(adev);
2333 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2334 struct drm_display_mode *mode)
2336 struct drm_device *dev = crtc->dev;
2337 struct amdgpu_device *adev = dev->dev_private;
2338 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2341 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2342 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2343 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2345 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2346 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2349 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2351 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2352 struct drm_device *dev = crtc->dev;
2353 struct amdgpu_device *adev = dev->dev_private;
2357 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2359 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2360 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2361 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2362 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2364 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2365 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2366 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2368 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2369 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2370 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2372 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2373 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2374 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2375 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2377 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2379 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2380 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2381 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2383 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2384 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2385 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2387 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2388 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2390 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2391 for (i = 0; i < 256; i++) {
2392 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2393 (amdgpu_crtc->lut_r[i] << 20) |
2394 (amdgpu_crtc->lut_g[i] << 10) |
2395 (amdgpu_crtc->lut_b[i] << 0));
2398 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2399 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2400 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2401 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2402 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2404 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2405 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2406 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2407 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2409 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2410 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2411 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2412 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2414 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2415 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2416 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2417 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2419 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2420 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2421 /* XXX this only needs to be programmed once per crtc at startup,
2422 * not sure where the best place for it is
2424 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2425 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2426 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2429 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2431 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2432 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2434 switch (amdgpu_encoder->encoder_id) {
2435 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2441 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2447 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2453 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2457 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2463 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2467 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2468 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2469 * monitors a dedicated PPLL must be used. If a particular board has
2470 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2471 * as there is no need to program the PLL itself. If we are not able to
2472 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2473 * avoid messing up an existing monitor.
2475 * Asic specific PLL information
2479 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2481 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2484 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2486 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2487 struct drm_device *dev = crtc->dev;
2488 struct amdgpu_device *adev = dev->dev_private;
2492 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2493 if (adev->clock.dp_extclk)
2494 /* skip PPLL programming if using ext clock */
2495 return ATOM_PPLL_INVALID;
2497 /* use the same PPLL for all DP monitors */
2498 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2499 if (pll != ATOM_PPLL_INVALID)
2503 /* use the same PPLL for all monitors with the same clock */
2504 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2505 if (pll != ATOM_PPLL_INVALID)
2509 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2510 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2511 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2513 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2515 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2517 DRM_ERROR("unable to allocate a PPLL\n");
2518 return ATOM_PPLL_INVALID;
2521 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2523 struct amdgpu_device *adev = crtc->dev->dev_private;
2524 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2527 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2529 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2531 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2532 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2535 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2537 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2538 struct amdgpu_device *adev = crtc->dev->dev_private;
2541 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2542 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2543 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2546 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2548 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2549 struct amdgpu_device *adev = crtc->dev->dev_private;
2552 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2553 upper_32_bits(amdgpu_crtc->cursor_addr));
2554 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2555 lower_32_bits(amdgpu_crtc->cursor_addr));
2557 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2558 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2559 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2560 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2563 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2566 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2567 struct amdgpu_device *adev = crtc->dev->dev_private;
2568 int xorigin = 0, yorigin = 0;
2570 amdgpu_crtc->cursor_x = x;
2571 amdgpu_crtc->cursor_y = y;
2573 /* avivo cursor are offset into the total surface */
2576 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2579 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2583 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2587 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2588 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2589 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2590 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2595 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2600 dce_v10_0_lock_cursor(crtc, true);
2601 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2602 dce_v10_0_lock_cursor(crtc, false);
2607 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2608 struct drm_file *file_priv,
2615 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2616 struct drm_gem_object *obj;
2617 struct amdgpu_bo *aobj;
2621 /* turn off cursor */
2622 dce_v10_0_hide_cursor(crtc);
2627 if ((width > amdgpu_crtc->max_cursor_width) ||
2628 (height > amdgpu_crtc->max_cursor_height)) {
2629 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2633 obj = drm_gem_object_lookup(file_priv, handle);
2635 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2639 aobj = gem_to_amdgpu_bo(obj);
2640 ret = amdgpu_bo_reserve(aobj, false);
2642 drm_gem_object_unreference_unlocked(obj);
2646 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2647 amdgpu_bo_unreserve(aobj);
2649 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2650 drm_gem_object_unreference_unlocked(obj);
2654 dce_v10_0_lock_cursor(crtc, true);
2656 if (width != amdgpu_crtc->cursor_width ||
2657 height != amdgpu_crtc->cursor_height ||
2658 hot_x != amdgpu_crtc->cursor_hot_x ||
2659 hot_y != amdgpu_crtc->cursor_hot_y) {
2662 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2663 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2665 dce_v10_0_cursor_move_locked(crtc, x, y);
2667 amdgpu_crtc->cursor_width = width;
2668 amdgpu_crtc->cursor_height = height;
2669 amdgpu_crtc->cursor_hot_x = hot_x;
2670 amdgpu_crtc->cursor_hot_y = hot_y;
2673 dce_v10_0_show_cursor(crtc);
2674 dce_v10_0_lock_cursor(crtc, false);
2677 if (amdgpu_crtc->cursor_bo) {
2678 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2679 ret = amdgpu_bo_reserve(aobj, false);
2680 if (likely(ret == 0)) {
2681 amdgpu_bo_unpin(aobj);
2682 amdgpu_bo_unreserve(aobj);
2684 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2687 amdgpu_crtc->cursor_bo = obj;
2691 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2693 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2695 if (amdgpu_crtc->cursor_bo) {
2696 dce_v10_0_lock_cursor(crtc, true);
2698 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2699 amdgpu_crtc->cursor_y);
2701 dce_v10_0_show_cursor(crtc);
2703 dce_v10_0_lock_cursor(crtc, false);
2707 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2708 u16 *blue, uint32_t size)
2710 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2713 /* userspace palettes are always correct as is */
2714 for (i = 0; i < size; i++) {
2715 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2716 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2717 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2719 dce_v10_0_crtc_load_lut(crtc);
2724 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2726 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2728 drm_crtc_cleanup(crtc);
2732 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2733 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2734 .cursor_move = dce_v10_0_crtc_cursor_move,
2735 .gamma_set = dce_v10_0_crtc_gamma_set,
2736 .set_config = amdgpu_crtc_set_config,
2737 .destroy = dce_v10_0_crtc_destroy,
2738 .page_flip_target = amdgpu_crtc_page_flip_target,
2741 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2743 struct drm_device *dev = crtc->dev;
2744 struct amdgpu_device *adev = dev->dev_private;
2745 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2749 case DRM_MODE_DPMS_ON:
2750 amdgpu_crtc->enabled = true;
2751 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2752 dce_v10_0_vga_enable(crtc, true);
2753 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2754 dce_v10_0_vga_enable(crtc, false);
2755 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2756 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2757 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2758 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2759 drm_crtc_vblank_on(crtc);
2760 dce_v10_0_crtc_load_lut(crtc);
2762 case DRM_MODE_DPMS_STANDBY:
2763 case DRM_MODE_DPMS_SUSPEND:
2764 case DRM_MODE_DPMS_OFF:
2765 drm_crtc_vblank_off(crtc);
2766 if (amdgpu_crtc->enabled) {
2767 dce_v10_0_vga_enable(crtc, true);
2768 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2769 dce_v10_0_vga_enable(crtc, false);
2771 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2772 amdgpu_crtc->enabled = false;
2775 /* adjust pm to dpms */
2776 amdgpu_pm_compute_clocks(adev);
2779 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2781 /* disable crtc pair power gating before programming */
2782 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2783 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2784 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2787 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2789 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2790 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2793 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2795 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2796 struct drm_device *dev = crtc->dev;
2797 struct amdgpu_device *adev = dev->dev_private;
2798 struct amdgpu_atom_ss ss;
2801 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2802 if (crtc->primary->fb) {
2804 struct amdgpu_framebuffer *amdgpu_fb;
2805 struct amdgpu_bo *abo;
2807 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2808 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2809 r = amdgpu_bo_reserve(abo, false);
2811 DRM_ERROR("failed to reserve abo before unpin\n");
2813 amdgpu_bo_unpin(abo);
2814 amdgpu_bo_unreserve(abo);
2817 /* disable the GRPH */
2818 dce_v10_0_grph_enable(crtc, false);
2820 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2822 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2823 if (adev->mode_info.crtcs[i] &&
2824 adev->mode_info.crtcs[i]->enabled &&
2825 i != amdgpu_crtc->crtc_id &&
2826 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2827 /* one other crtc is using this pll don't turn
2834 switch (amdgpu_crtc->pll_id) {
2838 /* disable the ppll */
2839 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2840 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2846 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2847 amdgpu_crtc->adjusted_clock = 0;
2848 amdgpu_crtc->encoder = NULL;
2849 amdgpu_crtc->connector = NULL;
2852 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2853 struct drm_display_mode *mode,
2854 struct drm_display_mode *adjusted_mode,
2855 int x, int y, struct drm_framebuffer *old_fb)
2857 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2859 if (!amdgpu_crtc->adjusted_clock)
2862 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2863 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2864 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2865 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2866 amdgpu_atombios_crtc_scaler_setup(crtc);
2867 dce_v10_0_cursor_reset(crtc);
2868 /* update the hw version fpr dpm */
2869 amdgpu_crtc->hw_mode = *adjusted_mode;
2874 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2875 const struct drm_display_mode *mode,
2876 struct drm_display_mode *adjusted_mode)
2878 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2879 struct drm_device *dev = crtc->dev;
2880 struct drm_encoder *encoder;
2882 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2883 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2884 if (encoder->crtc == crtc) {
2885 amdgpu_crtc->encoder = encoder;
2886 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2890 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2891 amdgpu_crtc->encoder = NULL;
2892 amdgpu_crtc->connector = NULL;
2895 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2897 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2900 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2901 /* if we can't get a PPLL for a non-DP encoder, fail */
2902 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2903 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2909 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2910 struct drm_framebuffer *old_fb)
2912 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2915 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2916 struct drm_framebuffer *fb,
2917 int x, int y, enum mode_set_atomic state)
2919 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2922 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2923 .dpms = dce_v10_0_crtc_dpms,
2924 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2925 .mode_set = dce_v10_0_crtc_mode_set,
2926 .mode_set_base = dce_v10_0_crtc_set_base,
2927 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2928 .prepare = dce_v10_0_crtc_prepare,
2929 .commit = dce_v10_0_crtc_commit,
2930 .load_lut = dce_v10_0_crtc_load_lut,
2931 .disable = dce_v10_0_crtc_disable,
2934 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2936 struct amdgpu_crtc *amdgpu_crtc;
2939 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2940 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2941 if (amdgpu_crtc == NULL)
2944 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2946 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2947 amdgpu_crtc->crtc_id = index;
2948 adev->mode_info.crtcs[index] = amdgpu_crtc;
2950 amdgpu_crtc->max_cursor_width = 128;
2951 amdgpu_crtc->max_cursor_height = 128;
2952 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2953 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2955 for (i = 0; i < 256; i++) {
2956 amdgpu_crtc->lut_r[i] = i << 2;
2957 amdgpu_crtc->lut_g[i] = i << 2;
2958 amdgpu_crtc->lut_b[i] = i << 2;
2961 switch (amdgpu_crtc->crtc_id) {
2964 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2967 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2970 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2973 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2976 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2979 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2983 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2984 amdgpu_crtc->adjusted_clock = 0;
2985 amdgpu_crtc->encoder = NULL;
2986 amdgpu_crtc->connector = NULL;
2987 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2992 static int dce_v10_0_early_init(void *handle)
2994 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2996 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2997 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2999 dce_v10_0_set_display_funcs(adev);
3000 dce_v10_0_set_irq_funcs(adev);
3002 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
3004 switch (adev->asic_type) {
3007 adev->mode_info.num_hpd = 6;
3008 adev->mode_info.num_dig = 7;
3011 /* FIXME: not supported yet */
3018 static int dce_v10_0_sw_init(void *handle)
3021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3023 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3024 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3029 for (i = 8; i < 20; i += 2) {
3030 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3036 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3040 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3042 adev->ddev->mode_config.async_page_flip = true;
3044 adev->ddev->mode_config.max_width = 16384;
3045 adev->ddev->mode_config.max_height = 16384;
3047 adev->ddev->mode_config.preferred_depth = 24;
3048 adev->ddev->mode_config.prefer_shadow = 1;
3050 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3052 r = amdgpu_modeset_create_props(adev);
3056 adev->ddev->mode_config.max_width = 16384;
3057 adev->ddev->mode_config.max_height = 16384;
3059 /* allocate crtcs */
3060 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3061 r = dce_v10_0_crtc_init(adev, i);
3066 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3067 amdgpu_print_display_setup(adev->ddev);
3072 r = dce_v10_0_afmt_init(adev);
3076 r = dce_v10_0_audio_init(adev);
3080 drm_kms_helper_poll_init(adev->ddev);
3082 adev->mode_info.mode_config_initialized = true;
3086 static int dce_v10_0_sw_fini(void *handle)
3088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3090 kfree(adev->mode_info.bios_hardcoded_edid);
3092 drm_kms_helper_poll_fini(adev->ddev);
3094 dce_v10_0_audio_fini(adev);
3096 dce_v10_0_afmt_fini(adev);
3098 drm_mode_config_cleanup(adev->ddev);
3099 adev->mode_info.mode_config_initialized = false;
3104 static int dce_v10_0_hw_init(void *handle)
3107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3109 dce_v10_0_init_golden_registers(adev);
3111 /* init dig PHYs, disp eng pll */
3112 amdgpu_atombios_encoder_init_dig(adev);
3113 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3115 /* initialize hpd */
3116 dce_v10_0_hpd_init(adev);
3118 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3119 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3122 dce_v10_0_pageflip_interrupt_init(adev);
3127 static int dce_v10_0_hw_fini(void *handle)
3130 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3132 dce_v10_0_hpd_fini(adev);
3134 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3135 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3138 dce_v10_0_pageflip_interrupt_fini(adev);
3143 static int dce_v10_0_suspend(void *handle)
3145 return dce_v10_0_hw_fini(handle);
3148 static int dce_v10_0_resume(void *handle)
3150 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3153 ret = dce_v10_0_hw_init(handle);
3155 /* turn on the BL */
3156 if (adev->mode_info.bl_encoder) {
3157 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3158 adev->mode_info.bl_encoder);
3159 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3166 static bool dce_v10_0_is_idle(void *handle)
3171 static int dce_v10_0_wait_for_idle(void *handle)
3176 static bool dce_v10_0_check_soft_reset(void *handle)
3178 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3180 return dce_v10_0_is_display_hung(adev);
3183 static int dce_v10_0_soft_reset(void *handle)
3185 u32 srbm_soft_reset = 0, tmp;
3186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3188 if (dce_v10_0_is_display_hung(adev))
3189 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3191 if (srbm_soft_reset) {
3192 tmp = RREG32(mmSRBM_SOFT_RESET);
3193 tmp |= srbm_soft_reset;
3194 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3195 WREG32(mmSRBM_SOFT_RESET, tmp);
3196 tmp = RREG32(mmSRBM_SOFT_RESET);
3200 tmp &= ~srbm_soft_reset;
3201 WREG32(mmSRBM_SOFT_RESET, tmp);
3202 tmp = RREG32(mmSRBM_SOFT_RESET);
3204 /* Wait a little for things to settle down */
3210 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3212 enum amdgpu_interrupt_state state)
3214 u32 lb_interrupt_mask;
3216 if (crtc >= adev->mode_info.num_crtc) {
3217 DRM_DEBUG("invalid crtc %d\n", crtc);
3222 case AMDGPU_IRQ_STATE_DISABLE:
3223 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3224 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3225 VBLANK_INTERRUPT_MASK, 0);
3226 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3228 case AMDGPU_IRQ_STATE_ENABLE:
3229 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3230 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3231 VBLANK_INTERRUPT_MASK, 1);
3232 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3239 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3241 enum amdgpu_interrupt_state state)
3243 u32 lb_interrupt_mask;
3245 if (crtc >= adev->mode_info.num_crtc) {
3246 DRM_DEBUG("invalid crtc %d\n", crtc);
3251 case AMDGPU_IRQ_STATE_DISABLE:
3252 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3253 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3254 VLINE_INTERRUPT_MASK, 0);
3255 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3257 case AMDGPU_IRQ_STATE_ENABLE:
3258 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3259 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3260 VLINE_INTERRUPT_MASK, 1);
3261 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3268 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3269 struct amdgpu_irq_src *source,
3271 enum amdgpu_interrupt_state state)
3275 if (hpd >= adev->mode_info.num_hpd) {
3276 DRM_DEBUG("invalid hdp %d\n", hpd);
3281 case AMDGPU_IRQ_STATE_DISABLE:
3282 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3283 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3284 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3286 case AMDGPU_IRQ_STATE_ENABLE:
3287 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3288 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3289 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3298 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3299 struct amdgpu_irq_src *source,
3301 enum amdgpu_interrupt_state state)
3304 case AMDGPU_CRTC_IRQ_VBLANK1:
3305 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3307 case AMDGPU_CRTC_IRQ_VBLANK2:
3308 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3310 case AMDGPU_CRTC_IRQ_VBLANK3:
3311 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3313 case AMDGPU_CRTC_IRQ_VBLANK4:
3314 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3316 case AMDGPU_CRTC_IRQ_VBLANK5:
3317 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3319 case AMDGPU_CRTC_IRQ_VBLANK6:
3320 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3322 case AMDGPU_CRTC_IRQ_VLINE1:
3323 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3325 case AMDGPU_CRTC_IRQ_VLINE2:
3326 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3328 case AMDGPU_CRTC_IRQ_VLINE3:
3329 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3331 case AMDGPU_CRTC_IRQ_VLINE4:
3332 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3334 case AMDGPU_CRTC_IRQ_VLINE5:
3335 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3337 case AMDGPU_CRTC_IRQ_VLINE6:
3338 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3346 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3347 struct amdgpu_irq_src *src,
3349 enum amdgpu_interrupt_state state)
3353 if (type >= adev->mode_info.num_crtc) {
3354 DRM_ERROR("invalid pageflip crtc %d\n", type);
3358 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3359 if (state == AMDGPU_IRQ_STATE_DISABLE)
3360 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3361 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3363 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3364 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3369 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3370 struct amdgpu_irq_src *source,
3371 struct amdgpu_iv_entry *entry)
3373 unsigned long flags;
3375 struct amdgpu_crtc *amdgpu_crtc;
3376 struct amdgpu_flip_work *works;
3378 crtc_id = (entry->src_id - 8) >> 1;
3379 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3381 if (crtc_id >= adev->mode_info.num_crtc) {
3382 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3386 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3387 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3388 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3389 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3391 /* IRQ could occur when in initial stage */
3392 if (amdgpu_crtc == NULL)
3395 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3396 works = amdgpu_crtc->pflip_works;
3397 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3398 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3399 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3400 amdgpu_crtc->pflip_status,
3401 AMDGPU_FLIP_SUBMITTED);
3402 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3406 /* page flip completed. clean up */
3407 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3408 amdgpu_crtc->pflip_works = NULL;
3410 /* wakeup usersapce */
3412 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3414 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3416 drm_crtc_vblank_put(&amdgpu_crtc->base);
3417 schedule_work(&works->unpin_work);
3422 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3427 if (hpd >= adev->mode_info.num_hpd) {
3428 DRM_DEBUG("invalid hdp %d\n", hpd);
3432 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3433 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3434 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3437 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3442 if (crtc >= adev->mode_info.num_crtc) {
3443 DRM_DEBUG("invalid crtc %d\n", crtc);
3447 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3448 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3449 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3452 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3457 if (crtc >= adev->mode_info.num_crtc) {
3458 DRM_DEBUG("invalid crtc %d\n", crtc);
3462 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3463 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3464 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3467 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3468 struct amdgpu_irq_src *source,
3469 struct amdgpu_iv_entry *entry)
3471 unsigned crtc = entry->src_id - 1;
3472 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3473 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3475 switch (entry->src_data) {
3476 case 0: /* vblank */
3477 if (disp_int & interrupt_status_offsets[crtc].vblank)
3478 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3480 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3482 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3483 drm_handle_vblank(adev->ddev, crtc);
3485 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3489 if (disp_int & interrupt_status_offsets[crtc].vline)
3490 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3492 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3494 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3498 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3505 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3506 struct amdgpu_irq_src *source,
3507 struct amdgpu_iv_entry *entry)
3509 uint32_t disp_int, mask;
3512 if (entry->src_data >= adev->mode_info.num_hpd) {
3513 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3517 hpd = entry->src_data;
3518 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3519 mask = interrupt_status_offsets[hpd].hpd;
3521 if (disp_int & mask) {
3522 dce_v10_0_hpd_int_ack(adev, hpd);
3523 schedule_work(&adev->hotplug_work);
3524 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3530 static int dce_v10_0_set_clockgating_state(void *handle,
3531 enum amd_clockgating_state state)
3536 static int dce_v10_0_set_powergating_state(void *handle,
3537 enum amd_powergating_state state)
3542 const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3543 .name = "dce_v10_0",
3544 .early_init = dce_v10_0_early_init,
3546 .sw_init = dce_v10_0_sw_init,
3547 .sw_fini = dce_v10_0_sw_fini,
3548 .hw_init = dce_v10_0_hw_init,
3549 .hw_fini = dce_v10_0_hw_fini,
3550 .suspend = dce_v10_0_suspend,
3551 .resume = dce_v10_0_resume,
3552 .is_idle = dce_v10_0_is_idle,
3553 .wait_for_idle = dce_v10_0_wait_for_idle,
3554 .check_soft_reset = dce_v10_0_check_soft_reset,
3555 .soft_reset = dce_v10_0_soft_reset,
3556 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3557 .set_powergating_state = dce_v10_0_set_powergating_state,
3561 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3562 struct drm_display_mode *mode,
3563 struct drm_display_mode *adjusted_mode)
3565 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3567 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3569 /* need to call this here rather than in prepare() since we need some crtc info */
3570 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3572 /* set scaler clears this on some chips */
3573 dce_v10_0_set_interleave(encoder->crtc, mode);
3575 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3576 dce_v10_0_afmt_enable(encoder, true);
3577 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3581 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3583 struct amdgpu_device *adev = encoder->dev->dev_private;
3584 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3585 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3587 if ((amdgpu_encoder->active_device &
3588 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3589 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3590 ENCODER_OBJECT_ID_NONE)) {
3591 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3593 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3594 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3595 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3599 amdgpu_atombios_scratch_regs_lock(adev, true);
3602 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3604 /* select the clock/data port if it uses a router */
3605 if (amdgpu_connector->router.cd_valid)
3606 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3608 /* turn eDP panel on for mode set */
3609 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3610 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3611 ATOM_TRANSMITTER_ACTION_POWER_ON);
3614 /* this is needed for the pll/ss setup to work correctly in some cases */
3615 amdgpu_atombios_encoder_set_crtc_source(encoder);
3616 /* set up the FMT blocks */
3617 dce_v10_0_program_fmt(encoder);
3620 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3622 struct drm_device *dev = encoder->dev;
3623 struct amdgpu_device *adev = dev->dev_private;
3625 /* need to call this here as we need the crtc set up */
3626 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3627 amdgpu_atombios_scratch_regs_lock(adev, false);
3630 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3632 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3633 struct amdgpu_encoder_atom_dig *dig;
3635 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3637 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3638 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3639 dce_v10_0_afmt_enable(encoder, false);
3640 dig = amdgpu_encoder->enc_priv;
3641 dig->dig_encoder = -1;
3643 amdgpu_encoder->active_device = 0;
3646 /* these are handled by the primary encoders */
3647 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3652 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3658 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3659 struct drm_display_mode *mode,
3660 struct drm_display_mode *adjusted_mode)
3665 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3671 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3676 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3677 .dpms = dce_v10_0_ext_dpms,
3678 .prepare = dce_v10_0_ext_prepare,
3679 .mode_set = dce_v10_0_ext_mode_set,
3680 .commit = dce_v10_0_ext_commit,
3681 .disable = dce_v10_0_ext_disable,
3682 /* no detect for TMDS/LVDS yet */
3685 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3686 .dpms = amdgpu_atombios_encoder_dpms,
3687 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3688 .prepare = dce_v10_0_encoder_prepare,
3689 .mode_set = dce_v10_0_encoder_mode_set,
3690 .commit = dce_v10_0_encoder_commit,
3691 .disable = dce_v10_0_encoder_disable,
3692 .detect = amdgpu_atombios_encoder_dig_detect,
3695 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3696 .dpms = amdgpu_atombios_encoder_dpms,
3697 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3698 .prepare = dce_v10_0_encoder_prepare,
3699 .mode_set = dce_v10_0_encoder_mode_set,
3700 .commit = dce_v10_0_encoder_commit,
3701 .detect = amdgpu_atombios_encoder_dac_detect,
3704 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3706 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3707 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3708 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3709 kfree(amdgpu_encoder->enc_priv);
3710 drm_encoder_cleanup(encoder);
3711 kfree(amdgpu_encoder);
3714 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3715 .destroy = dce_v10_0_encoder_destroy,
3718 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3719 uint32_t encoder_enum,
3720 uint32_t supported_device,
3723 struct drm_device *dev = adev->ddev;
3724 struct drm_encoder *encoder;
3725 struct amdgpu_encoder *amdgpu_encoder;
3727 /* see if we already added it */
3728 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3729 amdgpu_encoder = to_amdgpu_encoder(encoder);
3730 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3731 amdgpu_encoder->devices |= supported_device;
3738 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3739 if (!amdgpu_encoder)
3742 encoder = &amdgpu_encoder->base;
3743 switch (adev->mode_info.num_crtc) {
3745 encoder->possible_crtcs = 0x1;
3749 encoder->possible_crtcs = 0x3;
3752 encoder->possible_crtcs = 0xf;
3755 encoder->possible_crtcs = 0x3f;
3759 amdgpu_encoder->enc_priv = NULL;
3761 amdgpu_encoder->encoder_enum = encoder_enum;
3762 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3763 amdgpu_encoder->devices = supported_device;
3764 amdgpu_encoder->rmx_type = RMX_OFF;
3765 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3766 amdgpu_encoder->is_ext_encoder = false;
3767 amdgpu_encoder->caps = caps;
3769 switch (amdgpu_encoder->encoder_id) {
3770 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3771 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3772 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3773 DRM_MODE_ENCODER_DAC, NULL);
3774 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3776 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3777 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3778 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3779 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3780 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3781 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3782 amdgpu_encoder->rmx_type = RMX_FULL;
3783 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3784 DRM_MODE_ENCODER_LVDS, NULL);
3785 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3786 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3787 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3788 DRM_MODE_ENCODER_DAC, NULL);
3789 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3791 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3792 DRM_MODE_ENCODER_TMDS, NULL);
3793 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3795 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3797 case ENCODER_OBJECT_ID_SI170B:
3798 case ENCODER_OBJECT_ID_CH7303:
3799 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3800 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3801 case ENCODER_OBJECT_ID_TITFP513:
3802 case ENCODER_OBJECT_ID_VT1623:
3803 case ENCODER_OBJECT_ID_HDMI_SI1930:
3804 case ENCODER_OBJECT_ID_TRAVIS:
3805 case ENCODER_OBJECT_ID_NUTMEG:
3806 /* these are handled by the primary encoders */
3807 amdgpu_encoder->is_ext_encoder = true;
3808 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3809 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3810 DRM_MODE_ENCODER_LVDS, NULL);
3811 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3812 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3813 DRM_MODE_ENCODER_DAC, NULL);
3815 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3816 DRM_MODE_ENCODER_TMDS, NULL);
3817 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3822 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3823 .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3824 .bandwidth_update = &dce_v10_0_bandwidth_update,
3825 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3826 .vblank_wait = &dce_v10_0_vblank_wait,
3827 .is_display_hung = &dce_v10_0_is_display_hung,
3828 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3829 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3830 .hpd_sense = &dce_v10_0_hpd_sense,
3831 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3832 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3833 .page_flip = &dce_v10_0_page_flip,
3834 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3835 .add_encoder = &dce_v10_0_encoder_add,
3836 .add_connector = &amdgpu_connector_add,
3837 .stop_mc_access = &dce_v10_0_stop_mc_access,
3838 .resume_mc_access = &dce_v10_0_resume_mc_access,
3841 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3843 if (adev->mode_info.funcs == NULL)
3844 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3847 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3848 .set = dce_v10_0_set_crtc_irq_state,
3849 .process = dce_v10_0_crtc_irq,
3852 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3853 .set = dce_v10_0_set_pageflip_irq_state,
3854 .process = dce_v10_0_pageflip_irq,
3857 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3858 .set = dce_v10_0_set_hpd_irq_state,
3859 .process = dce_v10_0_hpd_irq,
3862 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3864 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3865 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3867 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3868 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3870 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3871 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;