drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34 #include "dce_v10_0.h"
  35
  36 #include "dce/dce_10_0_d.h"
  37 #include "dce/dce_10_0_sh_mask.h"
  38 #include "dce/dce_10_0_enum.h"
  39 #include "oss/oss_3_0_d.h"
  40 #include "oss/oss_3_0_sh_mask.h"
  41 #include "gmc/gmc_8_1_d.h"
  42 #include "gmc/gmc_8_1_sh_mask.h"
  43
  44 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  45 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  46
  47 static const u32 crtc_offsets[] =
  48 {
  49         CRTC0_REGISTER_OFFSET,
  50         CRTC1_REGISTER_OFFSET,
  51         CRTC2_REGISTER_OFFSET,
  52         CRTC3_REGISTER_OFFSET,
  53         CRTC4_REGISTER_OFFSET,
  54         CRTC5_REGISTER_OFFSET,
  55         CRTC6_REGISTER_OFFSET
  56 };
  57
  58 static const u32 hpd_offsets[] =
  59 {
  60         HPD0_REGISTER_OFFSET,
  61         HPD1_REGISTER_OFFSET,
  62         HPD2_REGISTER_OFFSET,
  63         HPD3_REGISTER_OFFSET,
  64         HPD4_REGISTER_OFFSET,
  65         HPD5_REGISTER_OFFSET
  66 };
  67
  68 static const uint32_t dig_offsets[] = {
  69         DIG0_REGISTER_OFFSET,
  70         DIG1_REGISTER_OFFSET,
  71         DIG2_REGISTER_OFFSET,
  72         DIG3_REGISTER_OFFSET,
  73         DIG4_REGISTER_OFFSET,
  74         DIG5_REGISTER_OFFSET,
  75         DIG6_REGISTER_OFFSET
  76 };
  77
  78 static const struct {
  79         uint32_t        reg;
  80         uint32_t        vblank;
  81         uint32_t        vline;
  82         uint32_t        hpd;
  83
  84 } interrupt_status_offsets[] = { {
  85         .reg = mmDISP_INTERRUPT_STATUS,
  86         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  87         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  88         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  89 }, {
  90         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  91         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  92         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  93         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  94 }, {
  95         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  96         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  97         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  98         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  99 }, {
 100         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 101         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 102         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 103         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 104 }, {
 105         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 106         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 107         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 108         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 109 }, {
 110         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 111         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 112         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 113         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 114 } };
 115
 116 static const u32 golden_settings_tonga_a11[] =
 117 {
 118         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 119         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 120         mmFBC_MISC, 0x1f311fff, 0x12300000,
 121         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 122 };
 123
 124 static const u32 tonga_mgcg_cgcg_init[] =
 125 {
 126         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 127         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 128 };
 129
 130 static const u32 golden_settings_fiji_a10[] =
 131 {
 132         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 133         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 134         mmFBC_MISC, 0x1f311fff, 0x12300000,
 135         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 136 };
 137
 138 static const u32 fiji_mgcg_cgcg_init[] =
 139 {
 140         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 141         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 142 };
 143
 144 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 145 {
 146         switch (adev->asic_type) {
 147         case CHIP_FIJI:
 148                 amdgpu_program_register_sequence(adev,
 149                                                  fiji_mgcg_cgcg_init,
 150                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 151                 amdgpu_program_register_sequence(adev,
 152                                                  golden_settings_fiji_a10,
 153                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 154                 break;
 155         case CHIP_TONGA:
 156                 amdgpu_program_register_sequence(adev,
 157                                                  tonga_mgcg_cgcg_init,
 158                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 159                 amdgpu_program_register_sequence(adev,
 160                                                  golden_settings_tonga_a11,
 161                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 162                 break;
 163         default:
 164                 break;
 165         }
 166 }
 167
 168 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 169                                      u32 block_offset, u32 reg)
 170 {
 171         unsigned long flags;
 172         u32 r;
 173
 174         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 175         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 176         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 177         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 178
 179         return r;
 180 }
 181
 182 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 183                                       u32 block_offset, u32 reg, u32 v)
 184 {
 185         unsigned long flags;
 186
 187         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 188         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 189         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 190         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 191 }
 192
 193 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 194 {
 195         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 196                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 197                 return true;
 198         else
 199                 return false;
 200 }
 201
 202 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 203 {
 204         u32 pos1, pos2;
 205
 206         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 207         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 208
 209         if (pos1 != pos2)
 210                 return true;
 211         else
 212                 return false;
 213 }
 214
 215 /**
 216  * dce_v10_0_vblank_wait - vblank wait asic callback.
 217  *
 218  * @adev: amdgpu_device pointer
 219  * @crtc: crtc to wait for vblank on
 220  *
 221  * Wait for vblank on the requested crtc (evergreen+).
 222  */
 223 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 224 {
 225         unsigned i = 100;
 226
 227         if (crtc >= adev->mode_info.num_crtc)
 228                 return;
 229
 230         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 231                 return;
 232
 233         /* depending on when we hit vblank, we may be close to active; if so,
 234          * wait for another frame.
 235          */
 236         while (dce_v10_0_is_in_vblank(adev, crtc)) {
 237                 if (i++ == 100) {
 238                         i = 0;
 239                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 240                                 break;
 241                 }
 242         }
 243
 244         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
 245                 if (i++ == 100) {
 246                         i = 0;
 247                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 248                                 break;
 249                 }
 250         }
 251 }
 252
 253 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 254 {
 255         if (crtc >= adev->mode_info.num_crtc)
 256                 return 0;
 257         else
 258                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 259 }
 260
 261 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 262 {
 263         unsigned i;
 264
 265         /* Enable pflip interrupts */
 266         for (i = 0; i < adev->mode_info.num_crtc; i++)
 267                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 268 }
 269
 270 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 271 {
 272         unsigned i;
 273
 274         /* Disable pflip interrupts */
 275         for (i = 0; i < adev->mode_info.num_crtc; i++)
 276                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 277 }
 278
 279 /**
 280  * dce_v10_0_page_flip - pageflip callback.
 281  *
 282  * @adev: amdgpu_device pointer
 283  * @crtc_id: crtc to cleanup pageflip on
 284  * @crtc_base: new address of the crtc (GPU MC address)
 285  *
 286  * Triggers the actual pageflip by updating the primary
 287  * surface base address.
 288  */
 289 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 290                                 int crtc_id, u64 crtc_base, bool async)
 291 {
 292         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 293         u32 tmp;
 294
 295         /* flip at hsync for async, default is vsync */
 296         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 297         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 298                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
 299         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 300         /* update the primary scanout address */
 301         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 302                upper_32_bits(crtc_base));
 303         /* writing to the low address triggers the update */
 304         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 305                lower_32_bits(crtc_base));
 306         /* post the write */
 307         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 308 }
 309
 310 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 311                                         u32 *vbl, u32 *position)
 312 {
 313         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 314                 return -EINVAL;
 315
 316         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 317         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 318
 319         return 0;
 320 }
 321
 322 /**
 323  * dce_v10_0_hpd_sense - hpd sense callback.
 324  *
 325  * @adev: amdgpu_device pointer
 326  * @hpd: hpd (hotplug detect) pin
 327  *
 328  * Checks if a digital monitor is connected (evergreen+).
 329  * Returns true if connected, false if not connected.
 330  */
 331 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 332                                enum amdgpu_hpd_id hpd)
 333 {
 334         bool connected = false;
 335
 336         if (hpd >= adev->mode_info.num_hpd)
 337                 return connected;
 338
 339         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
 340             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 341                 connected = true;
 342
 343         return connected;
 344 }
 345
 346 /**
 347  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 348  *
 349  * @adev: amdgpu_device pointer
 350  * @hpd: hpd (hotplug detect) pin
 351  *
 352  * Set the polarity of the hpd pin (evergreen+).
 353  */
 354 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 355                                       enum amdgpu_hpd_id hpd)
 356 {
 357         u32 tmp;
 358         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 359
 360         if (hpd >= adev->mode_info.num_hpd)
 361                 return;
 362
 363         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
 364         if (connected)
 365                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 366         else
 367                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 368         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
 369 }
 370
 371 /**
 372  * dce_v10_0_hpd_init - hpd setup callback.
 373  *
 374  * @adev: amdgpu_device pointer
 375  *
 376  * Setup the hpd pins used by the card (evergreen+).
 377  * Enable the pin, set the polarity, and enable the hpd interrupts.
 378  */
 379 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 380 {
 381         struct drm_device *dev = adev->ddev;
 382         struct drm_connector *connector;
 383         u32 tmp;
 384
 385         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 386                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 387
 388                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 389                         continue;
 390
 391                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 392                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 393                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 394                          * aux dp channel on imac and help (but not completely fix)
 395                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 396                          * also avoid interrupt storms during dpms.
 397                          */
 398                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 399                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 400                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 401                         continue;
 402                 }
 403
 404                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 405                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 406                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 407
 408                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 409                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 410                                     DC_HPD_CONNECT_INT_DELAY,
 411                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 412                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 413                                     DC_HPD_DISCONNECT_INT_DELAY,
 414                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 415                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 416
 417                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 418                 amdgpu_irq_get(adev, &adev->hpd_irq,
 419                                amdgpu_connector->hpd.hpd);
 420         }
 421 }
 422
 423 /**
 424  * dce_v10_0_hpd_fini - hpd tear down callback.
 425  *
 426  * @adev: amdgpu_device pointer
 427  *
 428  * Tear down the hpd pins used by the card (evergreen+).
 429  * Disable the hpd interrupts.
 430  */
 431 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 432 {
 433         struct drm_device *dev = adev->ddev;
 434         struct drm_connector *connector;
 435         u32 tmp;
 436
 437         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 438                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 439
 440                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 441                         continue;
 442
 443                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 444                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 445                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 446
 447                 amdgpu_irq_put(adev, &adev->hpd_irq,
 448                                amdgpu_connector->hpd.hpd);
 449         }
 450 }
 451
 452 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 453 {
 454         return mmDC_GPIO_HPD_A;
 455 }
 456
 457 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 458 {
 459         u32 crtc_hung = 0;
 460         u32 crtc_status[6];
 461         u32 i, j, tmp;
 462
 463         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 464                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 465                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 466                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 467                         crtc_hung |= (1 << i);
 468                 }
 469         }
 470
 471         for (j = 0; j < 10; j++) {
 472                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 473                         if (crtc_hung & (1 << i)) {
 474                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 475                                 if (tmp != crtc_status[i])
 476                                         crtc_hung &= ~(1 << i);
 477                         }
 478                 }
 479                 if (crtc_hung == 0)
 480                         return false;
 481                 udelay(100);
 482         }
 483
 484         return true;
 485 }
 486
 487 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 488                                            bool render)
 489 {
 490         u32 tmp;
 491
 492         /* Lockout access through VGA aperture*/
 493         tmp = RREG32(mmVGA_HDP_CONTROL);
 494         if (render)
 495                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 496         else
 497                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 498         WREG32(mmVGA_HDP_CONTROL, tmp);
 499
 500         /* disable VGA render */
 501         tmp = RREG32(mmVGA_RENDER_CONTROL);
 502         if (render)
 503                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 504         else
 505                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 506         WREG32(mmVGA_RENDER_CONTROL, tmp);
 507 }
 508
 509 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
 510 {
 511         int num_crtc = 0;
 512
 513         switch (adev->asic_type) {
 514         case CHIP_FIJI:
 515         case CHIP_TONGA:
 516                 num_crtc = 6;
 517                 break;
 518         default:
 519                 num_crtc = 0;
 520         }
 521         return num_crtc;
 522 }
 523
 524 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
 525 {
 526         /*Disable VGA render and enabled crtc, if has DCE engine*/
 527         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 528                 u32 tmp;
 529                 int crtc_enabled, i;
 530
 531                 dce_v10_0_set_vga_render_state(adev, false);
 532
 533                 /*Disable crtc*/
 534                 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
 535                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 536                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 537                         if (crtc_enabled) {
 538                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 539                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 540                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 541                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 542                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 543                         }
 544                 }
 545         }
 546 }
 547
 548 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 549 {
 550         struct drm_device *dev = encoder->dev;
 551         struct amdgpu_device *adev = dev->dev_private;
 552         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 553         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 554         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 555         int bpc = 0;
 556         u32 tmp = 0;
 557         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 558
 559         if (connector) {
 560                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 561                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 562                 dither = amdgpu_connector->dither;
 563         }
 564
 565         /* LVDS/eDP FMT is set up by atom */
 566         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 567                 return;
 568
 569         /* not needed for analog */
 570         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 571             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 572                 return;
 573
 574         if (bpc == 0)
 575                 return;
 576
 577         switch (bpc) {
 578         case 6:
 579                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 580                         /* XXX sort out optimal dither settings */
 581                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 582                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 583                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 584                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 585                 } else {
 586                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 587                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 588                 }
 589                 break;
 590         case 8:
 591                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 592                         /* XXX sort out optimal dither settings */
 593                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 594                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 595                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 596                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 597                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 598                 } else {
 599                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 600                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 601                 }
 602                 break;
 603         case 10:
 604                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 605                         /* XXX sort out optimal dither settings */
 606                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 607                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 608                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 609                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 610                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 611                 } else {
 612                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 613                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 614                 }
 615                 break;
 616         default:
 617                 /* not needed */
 618                 break;
 619         }
 620
 621         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 622 }
 623
 624
 625 /* display watermark setup */
 626 /**
 627  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 628  *
 629  * @adev: amdgpu_device pointer
 630  * @amdgpu_crtc: the selected display controller
 631  * @mode: the current display mode on the selected display
 632  * controller
 633  *
 634  * Setup up the line buffer allocation for
 635  * the selected display controller (CIK).
 636  * Returns the line buffer size in pixels.
 637  */
 638 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 639                                        struct amdgpu_crtc *amdgpu_crtc,
 640                                        struct drm_display_mode *mode)
 641 {
 642         u32 tmp, buffer_alloc, i, mem_cfg;
 643         u32 pipe_offset = amdgpu_crtc->crtc_id;
 644         /*
 645          * Line Buffer Setup
 646          * There are 6 line buffers, one for each display controllers.
 647          * There are 3 partitions per LB. Select the number of partitions
 648          * to enable based on the display width.  For display widths larger
 649          * than 4096, you need use to use 2 display controllers and combine
 650          * them using the stereo blender.
 651          */
 652         if (amdgpu_crtc->base.enabled && mode) {
 653                 if (mode->crtc_hdisplay < 1920) {
 654                         mem_cfg = 1;
 655                         buffer_alloc = 2;
 656                 } else if (mode->crtc_hdisplay < 2560) {
 657                         mem_cfg = 2;
 658                         buffer_alloc = 2;
 659                 } else if (mode->crtc_hdisplay < 4096) {
 660                         mem_cfg = 0;
 661                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 662                 } else {
 663                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 664                         mem_cfg = 0;
 665                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 666                 }
 667         } else {
 668                 mem_cfg = 1;
 669                 buffer_alloc = 0;
 670         }
 671
 672         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 673         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 674         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 675
 676         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 677         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 678         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 679
 680         for (i = 0; i < adev->usec_timeout; i++) {
 681                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 682                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 683                         break;
 684                 udelay(1);
 685         }
 686
 687         if (amdgpu_crtc->base.enabled && mode) {
 688                 switch (mem_cfg) {
 689                 case 0:
 690                 default:
 691                         return 4096 * 2;
 692                 case 1:
 693                         return 1920 * 2;
 694                 case 2:
 695                         return 2560 * 2;
 696                 }
 697         }
 698
 699         /* controller not enabled, so no lb used */
 700         return 0;
 701 }
 702
 703 /**
 704  * cik_get_number_of_dram_channels - get the number of dram channels
 705  *
 706  * @adev: amdgpu_device pointer
 707  *
 708  * Look up the number of video ram channels (CIK).
 709  * Used for display watermark bandwidth calculations
 710  * Returns the number of dram channels
 711  */
 712 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 713 {
 714         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 715
 716         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 717         case 0:
 718         default:
 719                 return 1;
 720         case 1:
 721                 return 2;
 722         case 2:
 723                 return 4;
 724         case 3:
 725                 return 8;
 726         case 4:
 727                 return 3;
 728         case 5:
 729                 return 6;
 730         case 6:
 731                 return 10;
 732         case 7:
 733                 return 12;
 734         case 8:
 735                 return 16;
 736         }
 737 }
 738
 739 struct dce10_wm_params {
 740         u32 dram_channels; /* number of dram channels */
 741         u32 yclk;          /* bandwidth per dram data pin in kHz */
 742         u32 sclk;          /* engine clock in kHz */
 743         u32 disp_clk;      /* display clock in kHz */
 744         u32 src_width;     /* viewport width */
 745         u32 active_time;   /* active display time in ns */
 746         u32 blank_time;    /* blank time in ns */
 747         bool interlaced;    /* mode is interlaced */
 748         fixed20_12 vsc;    /* vertical scale ratio */
 749         u32 num_heads;     /* number of active crtcs */
 750         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 751         u32 lb_size;       /* line buffer allocated to pipe */
 752         u32 vtaps;         /* vertical scaler taps */
 753 };
 754
 755 /**
 756  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 757  *
 758  * @wm: watermark calculation data
 759  *
 760  * Calculate the raw dram bandwidth (CIK).
 761  * Used for display watermark bandwidth calculations
 762  * Returns the dram bandwidth in MBytes/s
 763  */
 764 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 765 {
 766         /* Calculate raw DRAM Bandwidth */
 767         fixed20_12 dram_efficiency; /* 0.7 */
 768         fixed20_12 yclk, dram_channels, bandwidth;
 769         fixed20_12 a;
 770
 771         a.full = dfixed_const(1000);
 772         yclk.full = dfixed_const(wm->yclk);
 773         yclk.full = dfixed_div(yclk, a);
 774         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 775         a.full = dfixed_const(10);
 776         dram_efficiency.full = dfixed_const(7);
 777         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 778         bandwidth.full = dfixed_mul(dram_channels, yclk);
 779         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 780
 781         return dfixed_trunc(bandwidth);
 782 }
 783
 784 /**
 785  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 786  *
 787  * @wm: watermark calculation data
 788  *
 789  * Calculate the dram bandwidth used for display (CIK).
 790  * Used for display watermark bandwidth calculations
 791  * Returns the dram bandwidth for display in MBytes/s
 792  */
 793 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 794 {
 795         /* Calculate DRAM Bandwidth and the part allocated to display. */
 796         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 797         fixed20_12 yclk, dram_channels, bandwidth;
 798         fixed20_12 a;
 799
 800         a.full = dfixed_const(1000);
 801         yclk.full = dfixed_const(wm->yclk);
 802         yclk.full = dfixed_div(yclk, a);
 803         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 804         a.full = dfixed_const(10);
 805         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 806         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 807         bandwidth.full = dfixed_mul(dram_channels, yclk);
 808         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 809
 810         return dfixed_trunc(bandwidth);
 811 }
 812
 813 /**
 814  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 815  *
 816  * @wm: watermark calculation data
 817  *
 818  * Calculate the data return bandwidth used for display (CIK).
 819  * Used for display watermark bandwidth calculations
 820  * Returns the data return bandwidth in MBytes/s
 821  */
 822 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 823 {
 824         /* Calculate the display Data return Bandwidth */
 825         fixed20_12 return_efficiency; /* 0.8 */
 826         fixed20_12 sclk, bandwidth;
 827         fixed20_12 a;
 828
 829         a.full = dfixed_const(1000);
 830         sclk.full = dfixed_const(wm->sclk);
 831         sclk.full = dfixed_div(sclk, a);
 832         a.full = dfixed_const(10);
 833         return_efficiency.full = dfixed_const(8);
 834         return_efficiency.full = dfixed_div(return_efficiency, a);
 835         a.full = dfixed_const(32);
 836         bandwidth.full = dfixed_mul(a, sclk);
 837         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 838
 839         return dfixed_trunc(bandwidth);
 840 }
 841
 842 /**
 843  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
 844  *
 845  * @wm: watermark calculation data
 846  *
 847  * Calculate the dmif bandwidth used for display (CIK).
 848  * Used for display watermark bandwidth calculations
 849  * Returns the dmif bandwidth in MBytes/s
 850  */
 851 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 852 {
 853         /* Calculate the DMIF Request Bandwidth */
 854         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 855         fixed20_12 disp_clk, bandwidth;
 856         fixed20_12 a, b;
 857
 858         a.full = dfixed_const(1000);
 859         disp_clk.full = dfixed_const(wm->disp_clk);
 860         disp_clk.full = dfixed_div(disp_clk, a);
 861         a.full = dfixed_const(32);
 862         b.full = dfixed_mul(a, disp_clk);
 863
 864         a.full = dfixed_const(10);
 865         disp_clk_request_efficiency.full = dfixed_const(8);
 866         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 867
 868         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 869
 870         return dfixed_trunc(bandwidth);
 871 }
 872
 873 /**
 874  * dce_v10_0_available_bandwidth - get the min available bandwidth
 875  *
 876  * @wm: watermark calculation data
 877  *
 878  * Calculate the min available bandwidth used for display (CIK).
 879  * Used for display watermark bandwidth calculations
 880  * Returns the min available bandwidth in MBytes/s
 881  */
 882 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
 883 {
 884         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 885         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
 886         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
 887         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
 888
 889         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 890 }
 891
 892 /**
 893  * dce_v10_0_average_bandwidth - get the average available bandwidth
 894  *
 895  * @wm: watermark calculation data
 896  *
 897  * Calculate the average available bandwidth used for display (CIK).
 898  * Used for display watermark bandwidth calculations
 899  * Returns the average available bandwidth in MBytes/s
 900  */
 901 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
 902 {
 903         /* Calculate the display mode Average Bandwidth
 904          * DisplayMode should contain the source and destination dimensions,
 905          * timing, etc.
 906          */
 907         fixed20_12 bpp;
 908         fixed20_12 line_time;
 909         fixed20_12 src_width;
 910         fixed20_12 bandwidth;
 911         fixed20_12 a;
 912
 913         a.full = dfixed_const(1000);
 914         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 915         line_time.full = dfixed_div(line_time, a);
 916         bpp.full = dfixed_const(wm->bytes_per_pixel);
 917         src_width.full = dfixed_const(wm->src_width);
 918         bandwidth.full = dfixed_mul(src_width, bpp);
 919         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 920         bandwidth.full = dfixed_div(bandwidth, line_time);
 921
 922         return dfixed_trunc(bandwidth);
 923 }
 924
 925 /**
 926  * dce_v10_0_latency_watermark - get the latency watermark
 927  *
 928  * @wm: watermark calculation data
 929  *
 930  * Calculate the latency watermark (CIK).
 931  * Used for display watermark bandwidth calculations
 932  * Returns the latency watermark in ns
 933  */
 934 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
 935 {
 936         /* First calculate the latency in ns */
 937         u32 mc_latency = 2000; /* 2000 ns. */
 938         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
 939         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 940         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 941         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 942         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 943                 (wm->num_heads * cursor_line_pair_return_time);
 944         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 945         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 946         u32 tmp, dmif_size = 12288;
 947         fixed20_12 a, b, c;
 948
 949         if (wm->num_heads == 0)
 950                 return 0;
 951
 952         a.full = dfixed_const(2);
 953         b.full = dfixed_const(1);
 954         if ((wm->vsc.full > a.full) ||
 955             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 956             (wm->vtaps >= 5) ||
 957             ((wm->vsc.full >= a.full) && wm->interlaced))
 958                 max_src_lines_per_dst_line = 4;
 959         else
 960                 max_src_lines_per_dst_line = 2;
 961
 962         a.full = dfixed_const(available_bandwidth);
 963         b.full = dfixed_const(wm->num_heads);
 964         a.full = dfixed_div(a, b);
 965         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 966         tmp = min(dfixed_trunc(a), tmp);
 967
 968         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 969
 970         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 971         b.full = dfixed_const(1000);
 972         c.full = dfixed_const(lb_fill_bw);
 973         b.full = dfixed_div(c, b);
 974         a.full = dfixed_div(a, b);
 975         line_fill_time = dfixed_trunc(a);
 976
 977         if (line_fill_time < wm->active_time)
 978                 return latency;
 979         else
 980                 return latency + (line_fill_time - wm->active_time);
 981
 982 }
 983
 984 /**
 985  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 986  * average and available dram bandwidth
 987  *
 988  * @wm: watermark calculation data
 989  *
 990  * Check if the display average bandwidth fits in the display
 991  * dram bandwidth (CIK).
 992  * Used for display watermark bandwidth calculations
 993  * Returns true if the display fits, false if not.
 994  */
 995 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 996 {
 997         if (dce_v10_0_average_bandwidth(wm) <=
 998             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 999                 return true;
1000         else
1001                 return false;
1002 }
1003
1004 /**
1005  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1006  * average and available bandwidth
1007  *
1008  * @wm: watermark calculation data
1009  *
1010  * Check if the display average bandwidth fits in the display
1011  * available bandwidth (CIK).
1012  * Used for display watermark bandwidth calculations
1013  * Returns true if the display fits, false if not.
1014  */
1015 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1016 {
1017         if (dce_v10_0_average_bandwidth(wm) <=
1018             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1019                 return true;
1020         else
1021                 return false;
1022 }
1023
1024 /**
1025  * dce_v10_0_check_latency_hiding - check latency hiding
1026  *
1027  * @wm: watermark calculation data
1028  *
1029  * Check latency hiding (CIK).
1030  * Used for display watermark bandwidth calculations
1031  * Returns true if the display fits, false if not.
1032  */
1033 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1034 {
1035         u32 lb_partitions = wm->lb_size / wm->src_width;
1036         u32 line_time = wm->active_time + wm->blank_time;
1037         u32 latency_tolerant_lines;
1038         u32 latency_hiding;
1039         fixed20_12 a;
1040
1041         a.full = dfixed_const(1);
1042         if (wm->vsc.full > a.full)
1043                 latency_tolerant_lines = 1;
1044         else {
1045                 if (lb_partitions <= (wm->vtaps + 1))
1046                         latency_tolerant_lines = 1;
1047                 else
1048                         latency_tolerant_lines = 2;
1049         }
1050
1051         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1052
1053         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1054                 return true;
1055         else
1056                 return false;
1057 }
1058
1059 /**
1060  * dce_v10_0_program_watermarks - program display watermarks
1061  *
1062  * @adev: amdgpu_device pointer
1063  * @amdgpu_crtc: the selected display controller
1064  * @lb_size: line buffer size
1065  * @num_heads: number of display controllers in use
1066  *
1067  * Calculate and program the display watermarks for the
1068  * selected display controller (CIK).
1069  */
1070 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1071                                         struct amdgpu_crtc *amdgpu_crtc,
1072                                         u32 lb_size, u32 num_heads)
1073 {
1074         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1075         struct dce10_wm_params wm_low, wm_high;
1076         u32 active_time;
1077         u32 line_time = 0;
1078         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1079         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1080
1081         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1082                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1083                                             (u32)mode->clock);
1084                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1085                                           (u32)mode->clock);
1086                 line_time = min(line_time, (u32)65535);
1087
1088                 /* watermark for high clocks */
1089                 if (adev->pm.dpm_enabled) {
1090                         wm_high.yclk =
1091                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1092                         wm_high.sclk =
1093                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1094                 } else {
1095                         wm_high.yclk = adev->pm.current_mclk * 10;
1096                         wm_high.sclk = adev->pm.current_sclk * 10;
1097                 }
1098
1099                 wm_high.disp_clk = mode->clock;
1100                 wm_high.src_width = mode->crtc_hdisplay;
1101                 wm_high.active_time = active_time;
1102                 wm_high.blank_time = line_time - wm_high.active_time;
1103                 wm_high.interlaced = false;
1104                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1105                         wm_high.interlaced = true;
1106                 wm_high.vsc = amdgpu_crtc->vsc;
1107                 wm_high.vtaps = 1;
1108                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1109                         wm_high.vtaps = 2;
1110                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1111                 wm_high.lb_size = lb_size;
1112                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1113                 wm_high.num_heads = num_heads;
1114
1115                 /* set for high clocks */
1116                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1117
1118                 /* possibly force display priority to high */
1119                 /* should really do this at mode validation time... */
1120                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1121                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1122                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1123                     (adev->mode_info.disp_priority == 2)) {
1124                         DRM_DEBUG_KMS("force priority to high\n");
1125                 }
1126
1127                 /* watermark for low clocks */
1128                 if (adev->pm.dpm_enabled) {
1129                         wm_low.yclk =
1130                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1131                         wm_low.sclk =
1132                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1133                 } else {
1134                         wm_low.yclk = adev->pm.current_mclk * 10;
1135                         wm_low.sclk = adev->pm.current_sclk * 10;
1136                 }
1137
1138                 wm_low.disp_clk = mode->clock;
1139                 wm_low.src_width = mode->crtc_hdisplay;
1140                 wm_low.active_time = active_time;
1141                 wm_low.blank_time = line_time - wm_low.active_time;
1142                 wm_low.interlaced = false;
1143                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1144                         wm_low.interlaced = true;
1145                 wm_low.vsc = amdgpu_crtc->vsc;
1146                 wm_low.vtaps = 1;
1147                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1148                         wm_low.vtaps = 2;
1149                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1150                 wm_low.lb_size = lb_size;
1151                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1152                 wm_low.num_heads = num_heads;
1153
1154                 /* set for low clocks */
1155                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1156
1157                 /* possibly force display priority to high */
1158                 /* should really do this at mode validation time... */
1159                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1160                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1161                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1162                     (adev->mode_info.disp_priority == 2)) {
1163                         DRM_DEBUG_KMS("force priority to high\n");
1164                 }
1165                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1166         }
1167
1168         /* select wm A */
1169         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1170         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1171         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1172         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1173         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1174         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1175         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1176         /* select wm B */
1177         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1178         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1179         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1180         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1181         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1182         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1183         /* restore original selection */
1184         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1185
1186         /* save values for DPM */
1187         amdgpu_crtc->line_time = line_time;
1188         amdgpu_crtc->wm_high = latency_watermark_a;
1189         amdgpu_crtc->wm_low = latency_watermark_b;
1190         /* Save number of lines the linebuffer leads before the scanout */
1191         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1192 }
1193
1194 /**
1195  * dce_v10_0_bandwidth_update - program display watermarks
1196  *
1197  * @adev: amdgpu_device pointer
1198  *
1199  * Calculate and program the display watermarks and line
1200  * buffer allocation (CIK).
1201  */
1202 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1203 {
1204         struct drm_display_mode *mode = NULL;
1205         u32 num_heads = 0, lb_size;
1206         int i;
1207
1208         amdgpu_update_display_priority(adev);
1209
1210         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1211                 if (adev->mode_info.crtcs[i]->base.enabled)
1212                         num_heads++;
1213         }
1214         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1215                 mode = &adev->mode_info.crtcs[i]->base.mode;
1216                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1217                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1218                                             lb_size, num_heads);
1219         }
1220 }
1221
1222 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1223 {
1224         int i;
1225         u32 offset, tmp;
1226
1227         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1228                 offset = adev->mode_info.audio.pin[i].offset;
1229                 tmp = RREG32_AUDIO_ENDPT(offset,
1230                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1231                 if (((tmp &
1232                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1233                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1234                         adev->mode_info.audio.pin[i].connected = false;
1235                 else
1236                         adev->mode_info.audio.pin[i].connected = true;
1237         }
1238 }
1239
1240 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1241 {
1242         int i;
1243
1244         dce_v10_0_audio_get_connected_pins(adev);
1245
1246         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1247                 if (adev->mode_info.audio.pin[i].connected)
1248                         return &adev->mode_info.audio.pin[i];
1249         }
1250         DRM_ERROR("No connected audio pins found!\n");
1251         return NULL;
1252 }
1253
1254 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1255 {
1256         struct amdgpu_device *adev = encoder->dev->dev_private;
1257         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1258         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1259         u32 tmp;
1260
1261         if (!dig || !dig->afmt || !dig->afmt->pin)
1262                 return;
1263
1264         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1265         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1266         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1267 }
1268
1269 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1270                                                 struct drm_display_mode *mode)
1271 {
1272         struct amdgpu_device *adev = encoder->dev->dev_private;
1273         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1274         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1275         struct drm_connector *connector;
1276         struct amdgpu_connector *amdgpu_connector = NULL;
1277         u32 tmp;
1278         int interlace = 0;
1279
1280         if (!dig || !dig->afmt || !dig->afmt->pin)
1281                 return;
1282
1283         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1284                 if (connector->encoder == encoder) {
1285                         amdgpu_connector = to_amdgpu_connector(connector);
1286                         break;
1287                 }
1288         }
1289
1290         if (!amdgpu_connector) {
1291                 DRM_ERROR("Couldn't find encoder's connector\n");
1292                 return;
1293         }
1294
1295         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1296                 interlace = 1;
1297         if (connector->latency_present[interlace]) {
1298                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1299                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1300                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1301                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1302         } else {
1303                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1304                                     VIDEO_LIPSYNC, 0);
1305                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1306                                     AUDIO_LIPSYNC, 0);
1307         }
1308         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1309                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1310 }
1311
1312 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1313 {
1314         struct amdgpu_device *adev = encoder->dev->dev_private;
1315         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1316         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1317         struct drm_connector *connector;
1318         struct amdgpu_connector *amdgpu_connector = NULL;
1319         u32 tmp;
1320         u8 *sadb = NULL;
1321         int sad_count;
1322
1323         if (!dig || !dig->afmt || !dig->afmt->pin)
1324                 return;
1325
1326         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1327                 if (connector->encoder == encoder) {
1328                         amdgpu_connector = to_amdgpu_connector(connector);
1329                         break;
1330                 }
1331         }
1332
1333         if (!amdgpu_connector) {
1334                 DRM_ERROR("Couldn't find encoder's connector\n");
1335                 return;
1336         }
1337
1338         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1339         if (sad_count < 0) {
1340                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1341                 sad_count = 0;
1342         }
1343
1344         /* program the speaker allocation */
1345         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1346                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1347         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1348                             DP_CONNECTION, 0);
1349         /* set HDMI mode */
1350         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1351                             HDMI_CONNECTION, 1);
1352         if (sad_count)
1353                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1354                                     SPEAKER_ALLOCATION, sadb[0]);
1355         else
1356                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1357                                     SPEAKER_ALLOCATION, 5); /* stereo */
1358         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1359                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1360
1361         kfree(sadb);
1362 }
1363
1364 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1365 {
1366         struct amdgpu_device *adev = encoder->dev->dev_private;
1367         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1368         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1369         struct drm_connector *connector;
1370         struct amdgpu_connector *amdgpu_connector = NULL;
1371         struct cea_sad *sads;
1372         int i, sad_count;
1373
1374         static const u16 eld_reg_to_type[][2] = {
1375                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1376                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1377                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1378                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1379                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1380                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1381                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1382                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1383                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1384                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1385                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1386                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1387         };
1388
1389         if (!dig || !dig->afmt || !dig->afmt->pin)
1390                 return;
1391
1392         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1393                 if (connector->encoder == encoder) {
1394                         amdgpu_connector = to_amdgpu_connector(connector);
1395                         break;
1396                 }
1397         }
1398
1399         if (!amdgpu_connector) {
1400                 DRM_ERROR("Couldn't find encoder's connector\n");
1401                 return;
1402         }
1403
1404         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1405         if (sad_count <= 0) {
1406                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1407                 return;
1408         }
1409         BUG_ON(!sads);
1410
1411         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1412                 u32 tmp = 0;
1413                 u8 stereo_freqs = 0;
1414                 int max_channels = -1;
1415                 int j;
1416
1417                 for (j = 0; j < sad_count; j++) {
1418                         struct cea_sad *sad = &sads[j];
1419
1420                         if (sad->format == eld_reg_to_type[i][1]) {
1421                                 if (sad->channels > max_channels) {
1422                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1423                                                             MAX_CHANNELS, sad->channels);
1424                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1425                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1426                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1427                                                             SUPPORTED_FREQUENCIES, sad->freq);
1428                                         max_channels = sad->channels;
1429                                 }
1430
1431                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1432                                         stereo_freqs |= sad->freq;
1433                                 else
1434                                         break;
1435                         }
1436                 }
1437
1438                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1439                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1440                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1441         }
1442
1443         kfree(sads);
1444 }
1445
1446 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1447                                   struct amdgpu_audio_pin *pin,
1448                                   bool enable)
1449 {
1450         if (!pin)
1451                 return;
1452
1453         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1454                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1455 }
1456
1457 static const u32 pin_offsets[] =
1458 {
1459         AUD0_REGISTER_OFFSET,
1460         AUD1_REGISTER_OFFSET,
1461         AUD2_REGISTER_OFFSET,
1462         AUD3_REGISTER_OFFSET,
1463         AUD4_REGISTER_OFFSET,
1464         AUD5_REGISTER_OFFSET,
1465         AUD6_REGISTER_OFFSET,
1466 };
1467
1468 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1469 {
1470         int i;
1471
1472         if (!amdgpu_audio)
1473                 return 0;
1474
1475         adev->mode_info.audio.enabled = true;
1476
1477         adev->mode_info.audio.num_pins = 7;
1478
1479         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1480                 adev->mode_info.audio.pin[i].channels = -1;
1481                 adev->mode_info.audio.pin[i].rate = -1;
1482                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1483                 adev->mode_info.audio.pin[i].status_bits = 0;
1484                 adev->mode_info.audio.pin[i].category_code = 0;
1485                 adev->mode_info.audio.pin[i].connected = false;
1486                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1487                 adev->mode_info.audio.pin[i].id = i;
1488                 /* disable audio.  it will be set up later */
1489                 /* XXX remove once we switch to ip funcs */
1490                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1491         }
1492
1493         return 0;
1494 }
1495
1496 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1497 {
1498         int i;
1499
1500         if (!amdgpu_audio)
1501                 return;
1502
1503         if (!adev->mode_info.audio.enabled)
1504                 return;
1505
1506         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1507                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1508
1509         adev->mode_info.audio.enabled = false;
1510 }
1511
1512 /*
1513  * update the N and CTS parameters for a given pixel clock rate
1514  */
1515 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1516 {
1517         struct drm_device *dev = encoder->dev;
1518         struct amdgpu_device *adev = dev->dev_private;
1519         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1520         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1521         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1522         u32 tmp;
1523
1524         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1525         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1526         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1527         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1528         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1529         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1530
1531         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1532         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1533         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1534         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1535         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1536         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1537
1538         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1539         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1540         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1541         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1542         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1543         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1544
1545 }
1546
1547 /*
1548  * build a HDMI Video Info Frame
1549  */
1550 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1551                                                void *buffer, size_t size)
1552 {
1553         struct drm_device *dev = encoder->dev;
1554         struct amdgpu_device *adev = dev->dev_private;
1555         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1556         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1557         uint8_t *frame = buffer + 3;
1558         uint8_t *header = buffer;
1559
1560         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1561                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1562         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1563                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1564         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1565                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1566         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1567                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1568 }
1569
1570 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1571 {
1572         struct drm_device *dev = encoder->dev;
1573         struct amdgpu_device *adev = dev->dev_private;
1574         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1575         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1576         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1577         u32 dto_phase = 24 * 1000;
1578         u32 dto_modulo = clock;
1579         u32 tmp;
1580
1581         if (!dig || !dig->afmt)
1582                 return;
1583
1584         /* XXX two dtos; generally use dto0 for hdmi */
1585         /* Express [24MHz / target pixel clock] as an exact rational
1586          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1587          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1588          */
1589         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1590         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1591                             amdgpu_crtc->crtc_id);
1592         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1593         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1594         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1595 }
1596
1597 /*
1598  * update the info frames with the data from the current display mode
1599  */
1600 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1601                                   struct drm_display_mode *mode)
1602 {
1603         struct drm_device *dev = encoder->dev;
1604         struct amdgpu_device *adev = dev->dev_private;
1605         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1606         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1607         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1608         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1609         struct hdmi_avi_infoframe frame;
1610         ssize_t err;
1611         u32 tmp;
1612         int bpc = 8;
1613
1614         if (!dig || !dig->afmt)
1615                 return;
1616
1617         /* Silent, r600_hdmi_enable will raise WARN for us */
1618         if (!dig->afmt->enabled)
1619                 return;
1620
1621         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1622         if (encoder->crtc) {
1623                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1624                 bpc = amdgpu_crtc->bpc;
1625         }
1626
1627         /* disable audio prior to setting up hw */
1628         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1629         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1630
1631         dce_v10_0_audio_set_dto(encoder, mode->clock);
1632
1633         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1634         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1635         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1636
1637         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1638
1639         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1640         switch (bpc) {
1641         case 0:
1642         case 6:
1643         case 8:
1644         case 16:
1645         default:
1646                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1647                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1648                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1649                           connector->name, bpc);
1650                 break;
1651         case 10:
1652                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1653                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1654                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1655                           connector->name);
1656                 break;
1657         case 12:
1658                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1659                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1660                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1661                           connector->name);
1662                 break;
1663         }
1664         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1665
1666         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1667         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1668         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1669         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1670         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1671
1672         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1673         /* enable audio info frames (frames won't be set until audio is enabled) */
1674         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1675         /* required for audio info values to be updated */
1676         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1677         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1678
1679         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1680         /* required for audio info values to be updated */
1681         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1682         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1683
1684         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1685         /* anything other than 0 */
1686         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1687         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1688
1689         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1690
1691         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1692         /* set the default audio delay */
1693         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1694         /* should be suffient for all audio modes and small enough for all hblanks */
1695         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1696         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1697
1698         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1699         /* allow 60958 channel status fields to be updated */
1700         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1701         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1702
1703         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1704         if (bpc > 8)
1705                 /* clear SW CTS value */
1706                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1707         else
1708                 /* select SW CTS value */
1709                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1710         /* allow hw to sent ACR packets when required */
1711         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1712         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1713
1714         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1715
1716         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1717         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1718         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1719
1720         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1721         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1722         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1723
1724         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1725         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1726         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1727         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1728         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1729         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1730         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1731         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1732
1733         dce_v10_0_audio_write_speaker_allocation(encoder);
1734
1735         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1736                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1737
1738         dce_v10_0_afmt_audio_select_pin(encoder);
1739         dce_v10_0_audio_write_sad_regs(encoder);
1740         dce_v10_0_audio_write_latency_fields(encoder, mode);
1741
1742         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1743         if (err < 0) {
1744                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1745                 return;
1746         }
1747
1748         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1749         if (err < 0) {
1750                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1751                 return;
1752         }
1753
1754         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1755
1756         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1757         /* enable AVI info frames */
1758         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1759         /* required for audio info values to be updated */
1760         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1761         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1762
1763         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1764         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1765         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1766
1767         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1768         /* send audio packets */
1769         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1770         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1771
1772         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1773         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1774         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1775         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1776
1777         /* enable audio after to setting up hw */
1778         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1779 }
1780
1781 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1782 {
1783         struct drm_device *dev = encoder->dev;
1784         struct amdgpu_device *adev = dev->dev_private;
1785         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1786         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1787
1788         if (!dig || !dig->afmt)
1789                 return;
1790
1791         /* Silent, r600_hdmi_enable will raise WARN for us */
1792         if (enable && dig->afmt->enabled)
1793                 return;
1794         if (!enable && !dig->afmt->enabled)
1795                 return;
1796
1797         if (!enable && dig->afmt->pin) {
1798                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1799                 dig->afmt->pin = NULL;
1800         }
1801
1802         dig->afmt->enabled = enable;
1803
1804         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1805                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1806 }
1807
1808 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1809 {
1810         int i;
1811
1812         for (i = 0; i < adev->mode_info.num_dig; i++)
1813                 adev->mode_info.afmt[i] = NULL;
1814
1815         /* DCE10 has audio blocks tied to DIG encoders */
1816         for (i = 0; i < adev->mode_info.num_dig; i++) {
1817                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1818                 if (adev->mode_info.afmt[i]) {
1819                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1820                         adev->mode_info.afmt[i]->id = i;
1821                 } else {
1822                         int j;
1823                         for (j = 0; j < i; j++) {
1824                                 kfree(adev->mode_info.afmt[j]);
1825                                 adev->mode_info.afmt[j] = NULL;
1826                         }
1827                         return -ENOMEM;
1828                 }
1829         }
1830         return 0;
1831 }
1832
1833 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1834 {
1835         int i;
1836
1837         for (i = 0; i < adev->mode_info.num_dig; i++) {
1838                 kfree(adev->mode_info.afmt[i]);
1839                 adev->mode_info.afmt[i] = NULL;
1840         }
1841 }
1842
1843 static const u32 vga_control_regs[6] =
1844 {
1845         mmD1VGA_CONTROL,
1846         mmD2VGA_CONTROL,
1847         mmD3VGA_CONTROL,
1848         mmD4VGA_CONTROL,
1849         mmD5VGA_CONTROL,
1850         mmD6VGA_CONTROL,
1851 };
1852
1853 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1854 {
1855         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1856         struct drm_device *dev = crtc->dev;
1857         struct amdgpu_device *adev = dev->dev_private;
1858         u32 vga_control;
1859
1860         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1861         if (enable)
1862                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1863         else
1864                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1865 }
1866
1867 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1868 {
1869         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1870         struct drm_device *dev = crtc->dev;
1871         struct amdgpu_device *adev = dev->dev_private;
1872
1873         if (enable)
1874                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1875         else
1876                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1877 }
1878
1879 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1880                                      struct drm_framebuffer *fb,
1881                                      int x, int y, int atomic)
1882 {
1883         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1884         struct drm_device *dev = crtc->dev;
1885         struct amdgpu_device *adev = dev->dev_private;
1886         struct amdgpu_framebuffer *amdgpu_fb;
1887         struct drm_framebuffer *target_fb;
1888         struct drm_gem_object *obj;
1889         struct amdgpu_bo *abo;
1890         uint64_t fb_location, tiling_flags;
1891         uint32_t fb_format, fb_pitch_pixels;
1892         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1893         u32 pipe_config;
1894         u32 tmp, viewport_w, viewport_h;
1895         int r;
1896         bool bypass_lut = false;
1897         struct drm_format_name_buf format_name;
1898
1899         /* no fb bound */
1900         if (!atomic && !crtc->primary->fb) {
1901                 DRM_DEBUG_KMS("No FB bound\n");
1902                 return 0;
1903         }
1904
1905         if (atomic) {
1906                 amdgpu_fb = to_amdgpu_framebuffer(fb);
1907                 target_fb = fb;
1908         } else {
1909                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1910                 target_fb = crtc->primary->fb;
1911         }
1912
1913         /* If atomic, assume fb object is pinned & idle & fenced and
1914          * just update base pointers
1915          */
1916         obj = amdgpu_fb->obj;
1917         abo = gem_to_amdgpu_bo(obj);
1918         r = amdgpu_bo_reserve(abo, false);
1919         if (unlikely(r != 0))
1920                 return r;
1921
1922         if (atomic) {
1923                 fb_location = amdgpu_bo_gpu_offset(abo);
1924         } else {
1925                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1926                 if (unlikely(r != 0)) {
1927                         amdgpu_bo_unreserve(abo);
1928                         return -EINVAL;
1929                 }
1930         }
1931
1932         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1933         amdgpu_bo_unreserve(abo);
1934
1935         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1936
1937         switch (target_fb->format->format) {
1938         case DRM_FORMAT_C8:
1939                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1940                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1941                 break;
1942         case DRM_FORMAT_XRGB4444:
1943         case DRM_FORMAT_ARGB4444:
1944                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1945                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1946 #ifdef __BIG_ENDIAN
1947                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1948                                         ENDIAN_8IN16);
1949 #endif
1950                 break;
1951         case DRM_FORMAT_XRGB1555:
1952         case DRM_FORMAT_ARGB1555:
1953                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1954                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1955 #ifdef __BIG_ENDIAN
1956                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1957                                         ENDIAN_8IN16);
1958 #endif
1959                 break;
1960         case DRM_FORMAT_BGRX5551:
1961         case DRM_FORMAT_BGRA5551:
1962                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1963                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1964 #ifdef __BIG_ENDIAN
1965                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1966                                         ENDIAN_8IN16);
1967 #endif
1968                 break;
1969         case DRM_FORMAT_RGB565:
1970                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1971                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1972 #ifdef __BIG_ENDIAN
1973                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1974                                         ENDIAN_8IN16);
1975 #endif
1976                 break;
1977         case DRM_FORMAT_XRGB8888:
1978         case DRM_FORMAT_ARGB8888:
1979                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1980                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1981 #ifdef __BIG_ENDIAN
1982                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1983                                         ENDIAN_8IN32);
1984 #endif
1985                 break;
1986         case DRM_FORMAT_XRGB2101010:
1987         case DRM_FORMAT_ARGB2101010:
1988                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1989                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1990 #ifdef __BIG_ENDIAN
1991                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1992                                         ENDIAN_8IN32);
1993 #endif
1994                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1995                 bypass_lut = true;
1996                 break;
1997         case DRM_FORMAT_BGRX1010102:
1998         case DRM_FORMAT_BGRA1010102:
1999                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2000                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2001 #ifdef __BIG_ENDIAN
2002                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2003                                         ENDIAN_8IN32);
2004 #endif
2005                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2006                 bypass_lut = true;
2007                 break;
2008         default:
2009                 DRM_ERROR("Unsupported screen format %s\n",
2010                           drm_get_format_name(target_fb->format->format, &format_name));
2011                 return -EINVAL;
2012         }
2013
2014         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2015                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2016
2017                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2018                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2019                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2020                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2021                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2022
2023                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2024                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2025                                           ARRAY_2D_TILED_THIN1);
2026                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2027                                           tile_split);
2028                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2029                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2030                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2031                                           mtaspect);
2032                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2033                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2034         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2035                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2036                                           ARRAY_1D_TILED_THIN1);
2037         }
2038
2039         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2040                                   pipe_config);
2041
2042         dce_v10_0_vga_enable(crtc, false);
2043
2044         /* Make sure surface address is updated at vertical blank rather than
2045          * horizontal blank
2046          */
2047         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2048         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2049                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2050         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2051
2052         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2053                upper_32_bits(fb_location));
2054         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2055                upper_32_bits(fb_location));
2056         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2057                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2058         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2059                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2060         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2061         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2062
2063         /*
2064          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2065          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2066          * retain the full precision throughout the pipeline.
2067          */
2068         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2069         if (bypass_lut)
2070                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2071         else
2072                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2073         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2074
2075         if (bypass_lut)
2076                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2077
2078         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2079         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2080         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2081         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2082         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2083         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2084
2085         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2086         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2087
2088         dce_v10_0_grph_enable(crtc, true);
2089
2090         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2091                target_fb->height);
2092
2093         x &= ~3;
2094         y &= ~1;
2095         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2096                (x << 16) | y);
2097         viewport_w = crtc->mode.hdisplay;
2098         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2099         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2100                (viewport_w << 16) | viewport_h);
2101
2102         /* set pageflip to happen anywhere in vblank interval */
2103         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2104
2105         if (!atomic && fb && fb != crtc->primary->fb) {
2106                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2107                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2108                 r = amdgpu_bo_reserve(abo, true);
2109                 if (unlikely(r != 0))
2110                         return r;
2111                 amdgpu_bo_unpin(abo);
2112                 amdgpu_bo_unreserve(abo);
2113         }
2114
2115         /* Bytes per pixel may have changed */
2116         dce_v10_0_bandwidth_update(adev);
2117
2118         return 0;
2119 }
2120
2121 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2122                                      struct drm_display_mode *mode)
2123 {
2124         struct drm_device *dev = crtc->dev;
2125         struct amdgpu_device *adev = dev->dev_private;
2126         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2127         u32 tmp;
2128
2129         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2130         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2131                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2132         else
2133                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2134         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2135 }
2136
2137 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2138 {
2139         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2140         struct drm_device *dev = crtc->dev;
2141         struct amdgpu_device *adev = dev->dev_private;
2142         u16 *r, *g, *b;
2143         int i;
2144         u32 tmp;
2145
2146         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2147
2148         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2149         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2150         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2151         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2152
2153         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2154         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2155         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2156
2157         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2158         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2159         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2160
2161         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2162         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2163         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2164         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2165
2166         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2167
2168         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2169         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2170         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2171
2172         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2173         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2174         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2175
2176         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2177         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2178
2179         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2180         r = crtc->gamma_store;
2181         g = r + crtc->gamma_size;
2182         b = g + crtc->gamma_size;
2183         for (i = 0; i < 256; i++) {
2184                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2185                        ((*r++ & 0xffc0) << 14) |
2186                        ((*g++ & 0xffc0) << 4) |
2187                        (*b++ >> 6));
2188         }
2189
2190         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2191         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2192         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2193         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2194         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2195
2196         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2197         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2198         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2199         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2200
2201         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2202         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2203         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2204         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2205
2206         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2207         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2208         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2209         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2210
2211         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2212         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2213         /* XXX this only needs to be programmed once per crtc at startup,
2214          * not sure where the best place for it is
2215          */
2216         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2217         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2218         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2219 }
2220
2221 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2222 {
2223         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2224         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2225
2226         switch (amdgpu_encoder->encoder_id) {
2227         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2228                 if (dig->linkb)
2229                         return 1;
2230                 else
2231                         return 0;
2232                 break;
2233         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2234                 if (dig->linkb)
2235                         return 3;
2236                 else
2237                         return 2;
2238                 break;
2239         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2240                 if (dig->linkb)
2241                         return 5;
2242                 else
2243                         return 4;
2244                 break;
2245         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2246                 return 6;
2247                 break;
2248         default:
2249                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2250                 return 0;
2251         }
2252 }
2253
2254 /**
2255  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2256  *
2257  * @crtc: drm crtc
2258  *
2259  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2260  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2261  * monitors a dedicated PPLL must be used.  If a particular board has
2262  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2263  * as there is no need to program the PLL itself.  If we are not able to
2264  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2265  * avoid messing up an existing monitor.
2266  *
2267  * Asic specific PLL information
2268  *
2269  * DCE 10.x
2270  * Tonga
2271  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2272  * CI
2273  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2274  *
2275  */
2276 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2277 {
2278         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2279         struct drm_device *dev = crtc->dev;
2280         struct amdgpu_device *adev = dev->dev_private;
2281         u32 pll_in_use;
2282         int pll;
2283
2284         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2285                 if (adev->clock.dp_extclk)
2286                         /* skip PPLL programming if using ext clock */
2287                         return ATOM_PPLL_INVALID;
2288                 else {
2289                         /* use the same PPLL for all DP monitors */
2290                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2291                         if (pll != ATOM_PPLL_INVALID)
2292                                 return pll;
2293                 }
2294         } else {
2295                 /* use the same PPLL for all monitors with the same clock */
2296                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2297                 if (pll != ATOM_PPLL_INVALID)
2298                         return pll;
2299         }
2300
2301         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2302         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2303         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2304                 return ATOM_PPLL2;
2305         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2306                 return ATOM_PPLL1;
2307         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2308                 return ATOM_PPLL0;
2309         DRM_ERROR("unable to allocate a PPLL\n");
2310         return ATOM_PPLL_INVALID;
2311 }
2312
2313 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2314 {
2315         struct amdgpu_device *adev = crtc->dev->dev_private;
2316         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2317         uint32_t cur_lock;
2318
2319         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2320         if (lock)
2321                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2322         else
2323                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2324         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2325 }
2326
2327 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2328 {
2329         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2330         struct amdgpu_device *adev = crtc->dev->dev_private;
2331         u32 tmp;
2332
2333         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2334         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2335         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2336 }
2337
2338 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2339 {
2340         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2341         struct amdgpu_device *adev = crtc->dev->dev_private;
2342         u32 tmp;
2343
2344         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2345                upper_32_bits(amdgpu_crtc->cursor_addr));
2346         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2347                lower_32_bits(amdgpu_crtc->cursor_addr));
2348
2349         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2350         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2351         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2352         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2353 }
2354
2355 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2356                                         int x, int y)
2357 {
2358         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2359         struct amdgpu_device *adev = crtc->dev->dev_private;
2360         int xorigin = 0, yorigin = 0;
2361
2362         amdgpu_crtc->cursor_x = x;
2363         amdgpu_crtc->cursor_y = y;
2364
2365         /* avivo cursor are offset into the total surface */
2366         x += crtc->x;
2367         y += crtc->y;
2368         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2369
2370         if (x < 0) {
2371                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2372                 x = 0;
2373         }
2374         if (y < 0) {
2375                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2376                 y = 0;
2377         }
2378
2379         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2380         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2381         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2382                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2383
2384         return 0;
2385 }
2386
2387 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2388                                       int x, int y)
2389 {
2390         int ret;
2391
2392         dce_v10_0_lock_cursor(crtc, true);
2393         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2394         dce_v10_0_lock_cursor(crtc, false);
2395
2396         return ret;
2397 }
2398
2399 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2400                                       struct drm_file *file_priv,
2401                                       uint32_t handle,
2402                                       uint32_t width,
2403                                       uint32_t height,
2404                                       int32_t hot_x,
2405                                       int32_t hot_y)
2406 {
2407         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2408         struct drm_gem_object *obj;
2409         struct amdgpu_bo *aobj;
2410         int ret;
2411
2412         if (!handle) {
2413                 /* turn off cursor */
2414                 dce_v10_0_hide_cursor(crtc);
2415                 obj = NULL;
2416                 goto unpin;
2417         }
2418
2419         if ((width > amdgpu_crtc->max_cursor_width) ||
2420             (height > amdgpu_crtc->max_cursor_height)) {
2421                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2422                 return -EINVAL;
2423         }
2424
2425         obj = drm_gem_object_lookup(file_priv, handle);
2426         if (!obj) {
2427                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2428                 return -ENOENT;
2429         }
2430
2431         aobj = gem_to_amdgpu_bo(obj);
2432         ret = amdgpu_bo_reserve(aobj, false);
2433         if (ret != 0) {
2434                 drm_gem_object_put_unlocked(obj);
2435                 return ret;
2436         }
2437
2438         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2439         amdgpu_bo_unreserve(aobj);
2440         if (ret) {
2441                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2442                 drm_gem_object_put_unlocked(obj);
2443                 return ret;
2444         }
2445
2446         dce_v10_0_lock_cursor(crtc, true);
2447
2448         if (width != amdgpu_crtc->cursor_width ||
2449             height != amdgpu_crtc->cursor_height ||
2450             hot_x != amdgpu_crtc->cursor_hot_x ||
2451             hot_y != amdgpu_crtc->cursor_hot_y) {
2452                 int x, y;
2453
2454                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2455                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2456
2457                 dce_v10_0_cursor_move_locked(crtc, x, y);
2458
2459                 amdgpu_crtc->cursor_width = width;
2460                 amdgpu_crtc->cursor_height = height;
2461                 amdgpu_crtc->cursor_hot_x = hot_x;
2462                 amdgpu_crtc->cursor_hot_y = hot_y;
2463         }
2464
2465         dce_v10_0_show_cursor(crtc);
2466         dce_v10_0_lock_cursor(crtc, false);
2467
2468 unpin:
2469         if (amdgpu_crtc->cursor_bo) {
2470                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2471                 ret = amdgpu_bo_reserve(aobj, true);
2472                 if (likely(ret == 0)) {
2473                         amdgpu_bo_unpin(aobj);
2474                         amdgpu_bo_unreserve(aobj);
2475                 }
2476                 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2477         }
2478
2479         amdgpu_crtc->cursor_bo = obj;
2480         return 0;
2481 }
2482
2483 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2484 {
2485         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2486
2487         if (amdgpu_crtc->cursor_bo) {
2488                 dce_v10_0_lock_cursor(crtc, true);
2489
2490                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2491                                              amdgpu_crtc->cursor_y);
2492
2493                 dce_v10_0_show_cursor(crtc);
2494
2495                 dce_v10_0_lock_cursor(crtc, false);
2496         }
2497 }
2498
2499 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2500                                     u16 *blue, uint32_t size,
2501                                     struct drm_modeset_acquire_ctx *ctx)
2502 {
2503         dce_v10_0_crtc_load_lut(crtc);
2504
2505         return 0;
2506 }
2507
2508 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2509 {
2510         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2511
2512         drm_crtc_cleanup(crtc);
2513         kfree(amdgpu_crtc);
2514 }
2515
2516 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2517         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2518         .cursor_move = dce_v10_0_crtc_cursor_move,
2519         .gamma_set = dce_v10_0_crtc_gamma_set,
2520         .set_config = amdgpu_crtc_set_config,
2521         .destroy = dce_v10_0_crtc_destroy,
2522         .page_flip_target = amdgpu_crtc_page_flip_target,
2523 };
2524
2525 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2526 {
2527         struct drm_device *dev = crtc->dev;
2528         struct amdgpu_device *adev = dev->dev_private;
2529         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2530         unsigned type;
2531
2532         switch (mode) {
2533         case DRM_MODE_DPMS_ON:
2534                 amdgpu_crtc->enabled = true;
2535                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2536                 dce_v10_0_vga_enable(crtc, true);
2537                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2538                 dce_v10_0_vga_enable(crtc, false);
2539                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2540                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2541                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2542                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2543                 drm_crtc_vblank_on(crtc);
2544                 dce_v10_0_crtc_load_lut(crtc);
2545                 break;
2546         case DRM_MODE_DPMS_STANDBY:
2547         case DRM_MODE_DPMS_SUSPEND:
2548         case DRM_MODE_DPMS_OFF:
2549                 drm_crtc_vblank_off(crtc);
2550                 if (amdgpu_crtc->enabled) {
2551                         dce_v10_0_vga_enable(crtc, true);
2552                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2553                         dce_v10_0_vga_enable(crtc, false);
2554                 }
2555                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2556                 amdgpu_crtc->enabled = false;
2557                 break;
2558         }
2559         /* adjust pm to dpms */
2560         amdgpu_pm_compute_clocks(adev);
2561 }
2562
2563 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2564 {
2565         /* disable crtc pair power gating before programming */
2566         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2567         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2568         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2569 }
2570
2571 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2572 {
2573         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2574         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2575 }
2576
2577 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2578 {
2579         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2580         struct drm_device *dev = crtc->dev;
2581         struct amdgpu_device *adev = dev->dev_private;
2582         struct amdgpu_atom_ss ss;
2583         int i;
2584
2585         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2586         if (crtc->primary->fb) {
2587                 int r;
2588                 struct amdgpu_framebuffer *amdgpu_fb;
2589                 struct amdgpu_bo *abo;
2590
2591                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2592                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2593                 r = amdgpu_bo_reserve(abo, true);
2594                 if (unlikely(r))
2595                         DRM_ERROR("failed to reserve abo before unpin\n");
2596                 else {
2597                         amdgpu_bo_unpin(abo);
2598                         amdgpu_bo_unreserve(abo);
2599                 }
2600         }
2601         /* disable the GRPH */
2602         dce_v10_0_grph_enable(crtc, false);
2603
2604         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2605
2606         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2607                 if (adev->mode_info.crtcs[i] &&
2608                     adev->mode_info.crtcs[i]->enabled &&
2609                     i != amdgpu_crtc->crtc_id &&
2610                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2611                         /* one other crtc is using this pll don't turn
2612                          * off the pll
2613                          */
2614                         goto done;
2615                 }
2616         }
2617
2618         switch (amdgpu_crtc->pll_id) {
2619         case ATOM_PPLL0:
2620         case ATOM_PPLL1:
2621         case ATOM_PPLL2:
2622                 /* disable the ppll */
2623                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2624                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2625                 break;
2626         default:
2627                 break;
2628         }
2629 done:
2630         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2631         amdgpu_crtc->adjusted_clock = 0;
2632         amdgpu_crtc->encoder = NULL;
2633         amdgpu_crtc->connector = NULL;
2634 }
2635
2636 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2637                                   struct drm_display_mode *mode,
2638                                   struct drm_display_mode *adjusted_mode,
2639                                   int x, int y, struct drm_framebuffer *old_fb)
2640 {
2641         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2642
2643         if (!amdgpu_crtc->adjusted_clock)
2644                 return -EINVAL;
2645
2646         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2647         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2648         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2649         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2650         amdgpu_atombios_crtc_scaler_setup(crtc);
2651         dce_v10_0_cursor_reset(crtc);
2652         /* update the hw version fpr dpm */
2653         amdgpu_crtc->hw_mode = *adjusted_mode;
2654
2655         return 0;
2656 }
2657
2658 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2659                                      const struct drm_display_mode *mode,
2660                                      struct drm_display_mode *adjusted_mode)
2661 {
2662         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2663         struct drm_device *dev = crtc->dev;
2664         struct drm_encoder *encoder;
2665
2666         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2667         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2668                 if (encoder->crtc == crtc) {
2669                         amdgpu_crtc->encoder = encoder;
2670                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2671                         break;
2672                 }
2673         }
2674         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2675                 amdgpu_crtc->encoder = NULL;
2676                 amdgpu_crtc->connector = NULL;
2677                 return false;
2678         }
2679         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2680                 return false;
2681         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2682                 return false;
2683         /* pick pll */
2684         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2685         /* if we can't get a PPLL for a non-DP encoder, fail */
2686         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2687             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2688                 return false;
2689
2690         return true;
2691 }
2692
2693 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2694                                   struct drm_framebuffer *old_fb)
2695 {
2696         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2697 }
2698
2699 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2700                                          struct drm_framebuffer *fb,
2701                                          int x, int y, enum mode_set_atomic state)
2702 {
2703        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2704 }
2705
2706 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2707         .dpms = dce_v10_0_crtc_dpms,
2708         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2709         .mode_set = dce_v10_0_crtc_mode_set,
2710         .mode_set_base = dce_v10_0_crtc_set_base,
2711         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2712         .prepare = dce_v10_0_crtc_prepare,
2713         .commit = dce_v10_0_crtc_commit,
2714         .disable = dce_v10_0_crtc_disable,
2715 };
2716
2717 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2718 {
2719         struct amdgpu_crtc *amdgpu_crtc;
2720
2721         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2722                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2723         if (amdgpu_crtc == NULL)
2724                 return -ENOMEM;
2725
2726         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2727
2728         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2729         amdgpu_crtc->crtc_id = index;
2730         adev->mode_info.crtcs[index] = amdgpu_crtc;
2731
2732         amdgpu_crtc->max_cursor_width = 128;
2733         amdgpu_crtc->max_cursor_height = 128;
2734         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2735         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2736
2737         switch (amdgpu_crtc->crtc_id) {
2738         case 0:
2739         default:
2740                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2741                 break;
2742         case 1:
2743                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2744                 break;
2745         case 2:
2746                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2747                 break;
2748         case 3:
2749                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2750                 break;
2751         case 4:
2752                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2753                 break;
2754         case 5:
2755                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2756                 break;
2757         }
2758
2759         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2760         amdgpu_crtc->adjusted_clock = 0;
2761         amdgpu_crtc->encoder = NULL;
2762         amdgpu_crtc->connector = NULL;
2763         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2764
2765         return 0;
2766 }
2767
2768 static int dce_v10_0_early_init(void *handle)
2769 {
2770         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2771
2772         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2773         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2774
2775         dce_v10_0_set_display_funcs(adev);
2776         dce_v10_0_set_irq_funcs(adev);
2777
2778         adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2779
2780         switch (adev->asic_type) {
2781         case CHIP_FIJI:
2782         case CHIP_TONGA:
2783                 adev->mode_info.num_hpd = 6;
2784                 adev->mode_info.num_dig = 7;
2785                 break;
2786         default:
2787                 /* FIXME: not supported yet */
2788                 return -EINVAL;
2789         }
2790
2791         return 0;
2792 }
2793
2794 static int dce_v10_0_sw_init(void *handle)
2795 {
2796         int r, i;
2797         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2798
2799         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2800                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2801                 if (r)
2802                         return r;
2803         }
2804
2805         for (i = 8; i < 20; i += 2) {
2806                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2807                 if (r)
2808                         return r;
2809         }
2810
2811         /* HPD hotplug */
2812         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2813         if (r)
2814                 return r;
2815
2816         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2817
2818         adev->ddev->mode_config.async_page_flip = true;
2819
2820         adev->ddev->mode_config.max_width = 16384;
2821         adev->ddev->mode_config.max_height = 16384;
2822
2823         adev->ddev->mode_config.preferred_depth = 24;
2824         adev->ddev->mode_config.prefer_shadow = 1;
2825
2826         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2827
2828         r = amdgpu_modeset_create_props(adev);
2829         if (r)
2830                 return r;
2831
2832         adev->ddev->mode_config.max_width = 16384;
2833         adev->ddev->mode_config.max_height = 16384;
2834
2835         /* allocate crtcs */
2836         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2837                 r = dce_v10_0_crtc_init(adev, i);
2838                 if (r)
2839                         return r;
2840         }
2841
2842         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2843                 amdgpu_print_display_setup(adev->ddev);
2844         else
2845                 return -EINVAL;
2846
2847         /* setup afmt */
2848         r = dce_v10_0_afmt_init(adev);
2849         if (r)
2850                 return r;
2851
2852         r = dce_v10_0_audio_init(adev);
2853         if (r)
2854                 return r;
2855
2856         drm_kms_helper_poll_init(adev->ddev);
2857
2858         adev->mode_info.mode_config_initialized = true;
2859         return 0;
2860 }
2861
2862 static int dce_v10_0_sw_fini(void *handle)
2863 {
2864         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2865
2866         kfree(adev->mode_info.bios_hardcoded_edid);
2867
2868         drm_kms_helper_poll_fini(adev->ddev);
2869
2870         dce_v10_0_audio_fini(adev);
2871
2872         dce_v10_0_afmt_fini(adev);
2873
2874         drm_mode_config_cleanup(adev->ddev);
2875         adev->mode_info.mode_config_initialized = false;
2876
2877         return 0;
2878 }
2879
2880 static int dce_v10_0_hw_init(void *handle)
2881 {
2882         int i;
2883         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2884
2885         dce_v10_0_init_golden_registers(adev);
2886
2887         /* disable vga render */
2888         dce_v10_0_set_vga_render_state(adev, false);
2889         /* init dig PHYs, disp eng pll */
2890         amdgpu_atombios_encoder_init_dig(adev);
2891         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2892
2893         /* initialize hpd */
2894         dce_v10_0_hpd_init(adev);
2895
2896         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2897                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2898         }
2899
2900         dce_v10_0_pageflip_interrupt_init(adev);
2901
2902         return 0;
2903 }
2904
2905 static int dce_v10_0_hw_fini(void *handle)
2906 {
2907         int i;
2908         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2909
2910         dce_v10_0_hpd_fini(adev);
2911
2912         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2913                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2914         }
2915
2916         dce_v10_0_pageflip_interrupt_fini(adev);
2917
2918         return 0;
2919 }
2920
2921 static int dce_v10_0_suspend(void *handle)
2922 {
2923         return dce_v10_0_hw_fini(handle);
2924 }
2925
2926 static int dce_v10_0_resume(void *handle)
2927 {
2928         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2929         int ret;
2930
2931         ret = dce_v10_0_hw_init(handle);
2932
2933         /* turn on the BL */
2934         if (adev->mode_info.bl_encoder) {
2935                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2936                                                                   adev->mode_info.bl_encoder);
2937                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2938                                                     bl_level);
2939         }
2940
2941         return ret;
2942 }
2943
2944 static bool dce_v10_0_is_idle(void *handle)
2945 {
2946         return true;
2947 }
2948
2949 static int dce_v10_0_wait_for_idle(void *handle)
2950 {
2951         return 0;
2952 }
2953
2954 static bool dce_v10_0_check_soft_reset(void *handle)
2955 {
2956         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2957
2958         return dce_v10_0_is_display_hung(adev);
2959 }
2960
2961 static int dce_v10_0_soft_reset(void *handle)
2962 {
2963         u32 srbm_soft_reset = 0, tmp;
2964         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2965
2966         if (dce_v10_0_is_display_hung(adev))
2967                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2968
2969         if (srbm_soft_reset) {
2970                 tmp = RREG32(mmSRBM_SOFT_RESET);
2971                 tmp |= srbm_soft_reset;
2972                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2973                 WREG32(mmSRBM_SOFT_RESET, tmp);
2974                 tmp = RREG32(mmSRBM_SOFT_RESET);
2975
2976                 udelay(50);
2977
2978                 tmp &= ~srbm_soft_reset;
2979                 WREG32(mmSRBM_SOFT_RESET, tmp);
2980                 tmp = RREG32(mmSRBM_SOFT_RESET);
2981
2982                 /* Wait a little for things to settle down */
2983                 udelay(50);
2984         }
2985         return 0;
2986 }
2987
2988 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2989                                                      int crtc,
2990                                                      enum amdgpu_interrupt_state state)
2991 {
2992         u32 lb_interrupt_mask;
2993
2994         if (crtc >= adev->mode_info.num_crtc) {
2995                 DRM_DEBUG("invalid crtc %d\n", crtc);
2996                 return;
2997         }
2998
2999         switch (state) {
3000         case AMDGPU_IRQ_STATE_DISABLE:
3001                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3002                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3003                                                   VBLANK_INTERRUPT_MASK, 0);
3004                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3005                 break;
3006         case AMDGPU_IRQ_STATE_ENABLE:
3007                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3008                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3009                                                   VBLANK_INTERRUPT_MASK, 1);
3010                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3011                 break;
3012         default:
3013                 break;
3014         }
3015 }
3016
3017 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3018                                                     int crtc,
3019                                                     enum amdgpu_interrupt_state state)
3020 {
3021         u32 lb_interrupt_mask;
3022
3023         if (crtc >= adev->mode_info.num_crtc) {
3024                 DRM_DEBUG("invalid crtc %d\n", crtc);
3025                 return;
3026         }
3027
3028         switch (state) {
3029         case AMDGPU_IRQ_STATE_DISABLE:
3030                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3031                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3032                                                   VLINE_INTERRUPT_MASK, 0);
3033                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3034                 break;
3035         case AMDGPU_IRQ_STATE_ENABLE:
3036                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3037                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3038                                                   VLINE_INTERRUPT_MASK, 1);
3039                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3040                 break;
3041         default:
3042                 break;
3043         }
3044 }
3045
3046 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3047                                        struct amdgpu_irq_src *source,
3048                                        unsigned hpd,
3049                                        enum amdgpu_interrupt_state state)
3050 {
3051         u32 tmp;
3052
3053         if (hpd >= adev->mode_info.num_hpd) {
3054                 DRM_DEBUG("invalid hdp %d\n", hpd);
3055                 return 0;
3056         }
3057
3058         switch (state) {
3059         case AMDGPU_IRQ_STATE_DISABLE:
3060                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3061                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3062                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3063                 break;
3064         case AMDGPU_IRQ_STATE_ENABLE:
3065                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3066                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3067                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3068                 break;
3069         default:
3070                 break;
3071         }
3072
3073         return 0;
3074 }
3075
3076 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3077                                         struct amdgpu_irq_src *source,
3078                                         unsigned type,
3079                                         enum amdgpu_interrupt_state state)
3080 {
3081         switch (type) {
3082         case AMDGPU_CRTC_IRQ_VBLANK1:
3083                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3084                 break;
3085         case AMDGPU_CRTC_IRQ_VBLANK2:
3086                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3087                 break;
3088         case AMDGPU_CRTC_IRQ_VBLANK3:
3089                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3090                 break;
3091         case AMDGPU_CRTC_IRQ_VBLANK4:
3092                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3093                 break;
3094         case AMDGPU_CRTC_IRQ_VBLANK5:
3095                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3096                 break;
3097         case AMDGPU_CRTC_IRQ_VBLANK6:
3098                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3099                 break;
3100         case AMDGPU_CRTC_IRQ_VLINE1:
3101                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3102                 break;
3103         case AMDGPU_CRTC_IRQ_VLINE2:
3104                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3105                 break;
3106         case AMDGPU_CRTC_IRQ_VLINE3:
3107                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3108                 break;
3109         case AMDGPU_CRTC_IRQ_VLINE4:
3110                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3111                 break;
3112         case AMDGPU_CRTC_IRQ_VLINE5:
3113                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3114                 break;
3115         case AMDGPU_CRTC_IRQ_VLINE6:
3116                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3117                 break;
3118         default:
3119                 break;
3120         }
3121         return 0;
3122 }
3123
3124 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3125                                             struct amdgpu_irq_src *src,
3126                                             unsigned type,
3127                                             enum amdgpu_interrupt_state state)
3128 {
3129         u32 reg;
3130
3131         if (type >= adev->mode_info.num_crtc) {
3132                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3133                 return -EINVAL;
3134         }
3135
3136         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3137         if (state == AMDGPU_IRQ_STATE_DISABLE)
3138                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3139                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3140         else
3141                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3142                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3143
3144         return 0;
3145 }
3146
3147 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3148                                   struct amdgpu_irq_src *source,
3149                                   struct amdgpu_iv_entry *entry)
3150 {
3151         unsigned long flags;
3152         unsigned crtc_id;
3153         struct amdgpu_crtc *amdgpu_crtc;
3154         struct amdgpu_flip_work *works;
3155
3156         crtc_id = (entry->src_id - 8) >> 1;
3157         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3158
3159         if (crtc_id >= adev->mode_info.num_crtc) {
3160                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3161                 return -EINVAL;
3162         }
3163
3164         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3165             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3166                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3167                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3168
3169         /* IRQ could occur when in initial stage */
3170         if (amdgpu_crtc == NULL)
3171                 return 0;
3172
3173         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3174         works = amdgpu_crtc->pflip_works;
3175         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3176                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3177                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3178                                                  amdgpu_crtc->pflip_status,
3179                                                  AMDGPU_FLIP_SUBMITTED);
3180                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3181                 return 0;
3182         }
3183
3184         /* page flip completed. clean up */
3185         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3186         amdgpu_crtc->pflip_works = NULL;
3187
3188         /* wakeup usersapce */
3189         if (works->event)
3190                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3191
3192         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3193
3194         drm_crtc_vblank_put(&amdgpu_crtc->base);
3195         schedule_work(&works->unpin_work);
3196
3197         return 0;
3198 }
3199
3200 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3201                                   int hpd)
3202 {
3203         u32 tmp;
3204
3205         if (hpd >= adev->mode_info.num_hpd) {
3206                 DRM_DEBUG("invalid hdp %d\n", hpd);
3207                 return;
3208         }
3209
3210         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3211         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3212         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3213 }
3214
3215 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3216                                           int crtc)
3217 {
3218         u32 tmp;
3219
3220         if (crtc >= adev->mode_info.num_crtc) {
3221                 DRM_DEBUG("invalid crtc %d\n", crtc);
3222                 return;
3223         }
3224
3225         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3226         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3227         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3228 }
3229
3230 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3231                                          int crtc)
3232 {
3233         u32 tmp;
3234
3235         if (crtc >= adev->mode_info.num_crtc) {
3236                 DRM_DEBUG("invalid crtc %d\n", crtc);
3237                 return;
3238         }
3239
3240         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3241         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3242         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3243 }
3244
3245 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3246                               struct amdgpu_irq_src *source,
3247                               struct amdgpu_iv_entry *entry)
3248 {
3249         unsigned crtc = entry->src_id - 1;
3250         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3251         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3252
3253         switch (entry->src_data[0]) {
3254         case 0: /* vblank */
3255                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3256                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3257                 else
3258                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3259
3260                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3261                         drm_handle_vblank(adev->ddev, crtc);
3262                 }
3263                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3264
3265                 break;
3266         case 1: /* vline */
3267                 if (disp_int & interrupt_status_offsets[crtc].vline)
3268                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3269                 else
3270                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3271
3272                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3273
3274                 break;
3275         default:
3276                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3277                 break;
3278         }
3279
3280         return 0;
3281 }
3282
3283 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3284                              struct amdgpu_irq_src *source,
3285                              struct amdgpu_iv_entry *entry)
3286 {
3287         uint32_t disp_int, mask;
3288         unsigned hpd;
3289
3290         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3291                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3292                 return 0;
3293         }
3294
3295         hpd = entry->src_data[0];
3296         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3297         mask = interrupt_status_offsets[hpd].hpd;
3298
3299         if (disp_int & mask) {
3300                 dce_v10_0_hpd_int_ack(adev, hpd);
3301                 schedule_work(&adev->hotplug_work);
3302                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3303         }
3304
3305         return 0;
3306 }
3307
3308 static int dce_v10_0_set_clockgating_state(void *handle,
3309                                           enum amd_clockgating_state state)
3310 {
3311         return 0;
3312 }
3313
3314 static int dce_v10_0_set_powergating_state(void *handle,
3315                                           enum amd_powergating_state state)
3316 {
3317         return 0;
3318 }
3319
3320 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3321         .name = "dce_v10_0",
3322         .early_init = dce_v10_0_early_init,
3323         .late_init = NULL,
3324         .sw_init = dce_v10_0_sw_init,
3325         .sw_fini = dce_v10_0_sw_fini,
3326         .hw_init = dce_v10_0_hw_init,
3327         .hw_fini = dce_v10_0_hw_fini,
3328         .suspend = dce_v10_0_suspend,
3329         .resume = dce_v10_0_resume,
3330         .is_idle = dce_v10_0_is_idle,
3331         .wait_for_idle = dce_v10_0_wait_for_idle,
3332         .check_soft_reset = dce_v10_0_check_soft_reset,
3333         .soft_reset = dce_v10_0_soft_reset,
3334         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3335         .set_powergating_state = dce_v10_0_set_powergating_state,
3336 };
3337
3338 static void
3339 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3340                           struct drm_display_mode *mode,
3341                           struct drm_display_mode *adjusted_mode)
3342 {
3343         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3344
3345         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3346
3347         /* need to call this here rather than in prepare() since we need some crtc info */
3348         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3349
3350         /* set scaler clears this on some chips */
3351         dce_v10_0_set_interleave(encoder->crtc, mode);
3352
3353         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3354                 dce_v10_0_afmt_enable(encoder, true);
3355                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3356         }
3357 }
3358
3359 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3360 {
3361         struct amdgpu_device *adev = encoder->dev->dev_private;
3362         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3363         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3364
3365         if ((amdgpu_encoder->active_device &
3366              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3367             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3368              ENCODER_OBJECT_ID_NONE)) {
3369                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3370                 if (dig) {
3371                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3372                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3373                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3374                 }
3375         }
3376
3377         amdgpu_atombios_scratch_regs_lock(adev, true);
3378
3379         if (connector) {
3380                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3381
3382                 /* select the clock/data port if it uses a router */
3383                 if (amdgpu_connector->router.cd_valid)
3384                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3385
3386                 /* turn eDP panel on for mode set */
3387                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3388                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3389                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3390         }
3391
3392         /* this is needed for the pll/ss setup to work correctly in some cases */
3393         amdgpu_atombios_encoder_set_crtc_source(encoder);
3394         /* set up the FMT blocks */
3395         dce_v10_0_program_fmt(encoder);
3396 }
3397
3398 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3399 {
3400         struct drm_device *dev = encoder->dev;
3401         struct amdgpu_device *adev = dev->dev_private;
3402
3403         /* need to call this here as we need the crtc set up */
3404         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3405         amdgpu_atombios_scratch_regs_lock(adev, false);
3406 }
3407
3408 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3409 {
3410         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3411         struct amdgpu_encoder_atom_dig *dig;
3412
3413         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3414
3415         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3416                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3417                         dce_v10_0_afmt_enable(encoder, false);
3418                 dig = amdgpu_encoder->enc_priv;
3419                 dig->dig_encoder = -1;
3420         }
3421         amdgpu_encoder->active_device = 0;
3422 }
3423
3424 /* these are handled by the primary encoders */
3425 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3426 {
3427
3428 }
3429
3430 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3431 {
3432
3433 }
3434
3435 static void
3436 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3437                       struct drm_display_mode *mode,
3438                       struct drm_display_mode *adjusted_mode)
3439 {
3440
3441 }
3442
3443 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3444 {
3445
3446 }
3447
3448 static void
3449 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3450 {
3451
3452 }
3453
3454 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3455         .dpms = dce_v10_0_ext_dpms,
3456         .prepare = dce_v10_0_ext_prepare,
3457         .mode_set = dce_v10_0_ext_mode_set,
3458         .commit = dce_v10_0_ext_commit,
3459         .disable = dce_v10_0_ext_disable,
3460         /* no detect for TMDS/LVDS yet */
3461 };
3462
3463 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3464         .dpms = amdgpu_atombios_encoder_dpms,
3465         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3466         .prepare = dce_v10_0_encoder_prepare,
3467         .mode_set = dce_v10_0_encoder_mode_set,
3468         .commit = dce_v10_0_encoder_commit,
3469         .disable = dce_v10_0_encoder_disable,
3470         .detect = amdgpu_atombios_encoder_dig_detect,
3471 };
3472
3473 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3474         .dpms = amdgpu_atombios_encoder_dpms,
3475         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3476         .prepare = dce_v10_0_encoder_prepare,
3477         .mode_set = dce_v10_0_encoder_mode_set,
3478         .commit = dce_v10_0_encoder_commit,
3479         .detect = amdgpu_atombios_encoder_dac_detect,
3480 };
3481
3482 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3483 {
3484         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3485         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3486                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3487         kfree(amdgpu_encoder->enc_priv);
3488         drm_encoder_cleanup(encoder);
3489         kfree(amdgpu_encoder);
3490 }
3491
3492 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3493         .destroy = dce_v10_0_encoder_destroy,
3494 };
3495
3496 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3497                                  uint32_t encoder_enum,
3498                                  uint32_t supported_device,
3499                                  u16 caps)
3500 {
3501         struct drm_device *dev = adev->ddev;
3502         struct drm_encoder *encoder;
3503         struct amdgpu_encoder *amdgpu_encoder;
3504
3505         /* see if we already added it */
3506         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3507                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3508                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3509                         amdgpu_encoder->devices |= supported_device;
3510                         return;
3511                 }
3512
3513         }
3514
3515         /* add a new one */
3516         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3517         if (!amdgpu_encoder)
3518                 return;
3519
3520         encoder = &amdgpu_encoder->base;
3521         switch (adev->mode_info.num_crtc) {
3522         case 1:
3523                 encoder->possible_crtcs = 0x1;
3524                 break;
3525         case 2:
3526         default:
3527                 encoder->possible_crtcs = 0x3;
3528                 break;
3529         case 4:
3530                 encoder->possible_crtcs = 0xf;
3531                 break;
3532         case 6:
3533                 encoder->possible_crtcs = 0x3f;
3534                 break;
3535         }
3536
3537         amdgpu_encoder->enc_priv = NULL;
3538
3539         amdgpu_encoder->encoder_enum = encoder_enum;
3540         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3541         amdgpu_encoder->devices = supported_device;
3542         amdgpu_encoder->rmx_type = RMX_OFF;
3543         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3544         amdgpu_encoder->is_ext_encoder = false;
3545         amdgpu_encoder->caps = caps;
3546
3547         switch (amdgpu_encoder->encoder_id) {
3548         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3549         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3550                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3551                                  DRM_MODE_ENCODER_DAC, NULL);
3552                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3553                 break;
3554         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3555         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3556         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3557         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3558         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3559                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3560                         amdgpu_encoder->rmx_type = RMX_FULL;
3561                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3562                                          DRM_MODE_ENCODER_LVDS, NULL);
3563                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3564                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3565                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3566                                          DRM_MODE_ENCODER_DAC, NULL);
3567                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3568                 } else {
3569                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3570                                          DRM_MODE_ENCODER_TMDS, NULL);
3571                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3572                 }
3573                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3574                 break;
3575         case ENCODER_OBJECT_ID_SI170B:
3576         case ENCODER_OBJECT_ID_CH7303:
3577         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3578         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3579         case ENCODER_OBJECT_ID_TITFP513:
3580         case ENCODER_OBJECT_ID_VT1623:
3581         case ENCODER_OBJECT_ID_HDMI_SI1930:
3582         case ENCODER_OBJECT_ID_TRAVIS:
3583         case ENCODER_OBJECT_ID_NUTMEG:
3584                 /* these are handled by the primary encoders */
3585                 amdgpu_encoder->is_ext_encoder = true;
3586                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3587                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3588                                          DRM_MODE_ENCODER_LVDS, NULL);
3589                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3590                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3591                                          DRM_MODE_ENCODER_DAC, NULL);
3592                 else
3593                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3594                                          DRM_MODE_ENCODER_TMDS, NULL);
3595                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3596                 break;
3597         }
3598 }
3599
3600 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3601         .bandwidth_update = &dce_v10_0_bandwidth_update,
3602         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3603         .vblank_wait = &dce_v10_0_vblank_wait,
3604         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3605         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3606         .hpd_sense = &dce_v10_0_hpd_sense,
3607         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3608         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3609         .page_flip = &dce_v10_0_page_flip,
3610         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3611         .add_encoder = &dce_v10_0_encoder_add,
3612         .add_connector = &amdgpu_connector_add,
3613 };
3614
3615 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3616 {
3617         if (adev->mode_info.funcs == NULL)
3618                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3619 }
3620
3621 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3622         .set = dce_v10_0_set_crtc_irq_state,
3623         .process = dce_v10_0_crtc_irq,
3624 };
3625
3626 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3627         .set = dce_v10_0_set_pageflip_irq_state,
3628         .process = dce_v10_0_pageflip_irq,
3629 };
3630
3631 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3632         .set = dce_v10_0_set_hpd_irq_state,
3633         .process = dce_v10_0_hpd_irq,
3634 };
3635
3636 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3637 {
3638         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3639         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3640
3641         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3642         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3643
3644         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3645         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3646 }
3647
3648 const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3649 {
3650         .type = AMD_IP_BLOCK_TYPE_DCE,
3651         .major = 10,
3652         .minor = 0,
3653         .rev = 0,
3654         .funcs = &dce_v10_0_ip_funcs,
3655 };
3656
3657 const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3658 {
3659         .type = AMD_IP_BLOCK_TYPE_DCE,
3660         .major = 10,
3661         .minor = 1,
3662         .rev = 0,
3663         .funcs = &dce_v10_0_ip_funcs,
3664 };