drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_10_0_d.h"
  36 #include "dce/dce_10_0_sh_mask.h"
  37 #include "dce/dce_10_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET
  75 };
  76
  77 static const struct {
  78         uint32_t        reg;
  79         uint32_t        vblank;
  80         uint32_t        vline;
  81         uint32_t        hpd;
  82
  83 } interrupt_status_offsets[] = { {
  84         .reg = mmDISP_INTERRUPT_STATUS,
  85         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  86         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  87         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  88 }, {
  89         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  90         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  91         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  92         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  93 }, {
  94         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  95         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 113 } };
 114
 115 static const u32 golden_settings_tonga_a11[] =
 116 {
 117         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 118         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 119         mmFBC_MISC, 0x1f311fff, 0x12300000,
 120         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 121 };
 122
 123 static const u32 tonga_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 golden_settings_fiji_a10[] =
 130 {
 131         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 132         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 133         mmFBC_MISC, 0x1f311fff, 0x12300000,
 134         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 135 };
 136
 137 static const u32 fiji_mgcg_cgcg_init[] =
 138 {
 139         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 140         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 141 };
 142
 143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 144 {
 145         switch (adev->asic_type) {
 146         case CHIP_FIJI:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  fiji_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 150                 amdgpu_program_register_sequence(adev,
 151                                                  golden_settings_fiji_a10,
 152                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 153                 break;
 154         case CHIP_TONGA:
 155                 amdgpu_program_register_sequence(adev,
 156                                                  tonga_mgcg_cgcg_init,
 157                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 158                 amdgpu_program_register_sequence(adev,
 159                                                  golden_settings_tonga_a11,
 160                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 168                                      u32 block_offset, u32 reg)
 169 {
 170         unsigned long flags;
 171         u32 r;
 172
 173         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 174         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 175         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 176         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 177
 178         return r;
 179 }
 180
 181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 182                                       u32 block_offset, u32 reg, u32 v)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 187         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 188         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 189         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 190 }
 191
 192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 193 {
 194         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 195                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 196                 return true;
 197         else
 198                 return false;
 199 }
 200
 201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 202 {
 203         u32 pos1, pos2;
 204
 205         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 206         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 207
 208         if (pos1 != pos2)
 209                 return true;
 210         else
 211                 return false;
 212 }
 213
 214 /**
 215  * dce_v10_0_vblank_wait - vblank wait asic callback.
 216  *
 217  * @adev: amdgpu_device pointer
 218  * @crtc: crtc to wait for vblank on
 219  *
 220  * Wait for vblank on the requested crtc (evergreen+).
 221  */
 222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 223 {
 224         unsigned i = 0;
 225
 226         if (crtc >= adev->mode_info.num_crtc)
 227                 return;
 228
 229         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 230                 return;
 231
 232         /* depending on when we hit vblank, we may be close to active; if so,
 233          * wait for another frame.
 234          */
 235         while (dce_v10_0_is_in_vblank(adev, crtc)) {
 236                 if (i++ % 100 == 0) {
 237                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 238                                 break;
 239                 }
 240         }
 241
 242         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
 243                 if (i++ % 100 == 0) {
 244                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 245                                 break;
 246                 }
 247         }
 248 }
 249
 250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 251 {
 252         if (crtc >= adev->mode_info.num_crtc)
 253                 return 0;
 254         else
 255                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 256 }
 257
 258 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 259 {
 260         unsigned i;
 261
 262         /* Enable pflip interrupts */
 263         for (i = 0; i < adev->mode_info.num_crtc; i++)
 264                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 265 }
 266
 267 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 268 {
 269         unsigned i;
 270
 271         /* Disable pflip interrupts */
 272         for (i = 0; i < adev->mode_info.num_crtc; i++)
 273                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 274 }
 275
 276 /**
 277  * dce_v10_0_page_flip - pageflip callback.
 278  *
 279  * @adev: amdgpu_device pointer
 280  * @crtc_id: crtc to cleanup pageflip on
 281  * @crtc_base: new address of the crtc (GPU MC address)
 282  *
 283  * Triggers the actual pageflip by updating the primary
 284  * surface base address.
 285  */
 286 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 287                               int crtc_id, u64 crtc_base)
 288 {
 289         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 290
 291         /* update the primary scanout address */
 292         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 293                upper_32_bits(crtc_base));
 294         /* writing to the low address triggers the update */
 295         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 296                lower_32_bits(crtc_base));
 297         /* post the write */
 298         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 299 }
 300
 301 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 302                                         u32 *vbl, u32 *position)
 303 {
 304         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 305                 return -EINVAL;
 306
 307         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 308         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 309
 310         return 0;
 311 }
 312
 313 /**
 314  * dce_v10_0_hpd_sense - hpd sense callback.
 315  *
 316  * @adev: amdgpu_device pointer
 317  * @hpd: hpd (hotplug detect) pin
 318  *
 319  * Checks if a digital monitor is connected (evergreen+).
 320  * Returns true if connected, false if not connected.
 321  */
 322 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 323                                enum amdgpu_hpd_id hpd)
 324 {
 325         int idx;
 326         bool connected = false;
 327
 328         switch (hpd) {
 329         case AMDGPU_HPD_1:
 330                 idx = 0;
 331                 break;
 332         case AMDGPU_HPD_2:
 333                 idx = 1;
 334                 break;
 335         case AMDGPU_HPD_3:
 336                 idx = 2;
 337                 break;
 338         case AMDGPU_HPD_4:
 339                 idx = 3;
 340                 break;
 341         case AMDGPU_HPD_5:
 342                 idx = 4;
 343                 break;
 344         case AMDGPU_HPD_6:
 345                 idx = 5;
 346                 break;
 347         default:
 348                 return connected;
 349         }
 350
 351         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 352             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 353                 connected = true;
 354
 355         return connected;
 356 }
 357
 358 /**
 359  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 360  *
 361  * @adev: amdgpu_device pointer
 362  * @hpd: hpd (hotplug detect) pin
 363  *
 364  * Set the polarity of the hpd pin (evergreen+).
 365  */
 366 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 367                                       enum amdgpu_hpd_id hpd)
 368 {
 369         u32 tmp;
 370         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 371         int idx;
 372
 373         switch (hpd) {
 374         case AMDGPU_HPD_1:
 375                 idx = 0;
 376                 break;
 377         case AMDGPU_HPD_2:
 378                 idx = 1;
 379                 break;
 380         case AMDGPU_HPD_3:
 381                 idx = 2;
 382                 break;
 383         case AMDGPU_HPD_4:
 384                 idx = 3;
 385                 break;
 386         case AMDGPU_HPD_5:
 387                 idx = 4;
 388                 break;
 389         case AMDGPU_HPD_6:
 390                 idx = 5;
 391                 break;
 392         default:
 393                 return;
 394         }
 395
 396         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 397         if (connected)
 398                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 399         else
 400                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 401         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 402 }
 403
 404 /**
 405  * dce_v10_0_hpd_init - hpd setup callback.
 406  *
 407  * @adev: amdgpu_device pointer
 408  *
 409  * Setup the hpd pins used by the card (evergreen+).
 410  * Enable the pin, set the polarity, and enable the hpd interrupts.
 411  */
 412 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 413 {
 414         struct drm_device *dev = adev->ddev;
 415         struct drm_connector *connector;
 416         u32 tmp;
 417         int idx;
 418
 419         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 420                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 421
 422                 switch (amdgpu_connector->hpd.hpd) {
 423                 case AMDGPU_HPD_1:
 424                         idx = 0;
 425                         break;
 426                 case AMDGPU_HPD_2:
 427                         idx = 1;
 428                         break;
 429                 case AMDGPU_HPD_3:
 430                         idx = 2;
 431                         break;
 432                 case AMDGPU_HPD_4:
 433                         idx = 3;
 434                         break;
 435                 case AMDGPU_HPD_5:
 436                         idx = 4;
 437                         break;
 438                 case AMDGPU_HPD_6:
 439                         idx = 5;
 440                         break;
 441                 default:
 442                         continue;
 443                 }
 444
 445                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 446                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 447                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 448                          * aux dp channel on imac and help (but not completely fix)
 449                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 450                          * also avoid interrupt storms during dpms.
 451                          */
 452                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 453                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 454                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 455                         continue;
 456                 }
 457
 458                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 459                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 460                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 461
 462                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 463                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 464                                     DC_HPD_CONNECT_INT_DELAY,
 465                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 466                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 467                                     DC_HPD_DISCONNECT_INT_DELAY,
 468                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 469                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 470
 471                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 472                 amdgpu_irq_get(adev, &adev->hpd_irq,
 473                                amdgpu_connector->hpd.hpd);
 474         }
 475 }
 476
 477 /**
 478  * dce_v10_0_hpd_fini - hpd tear down callback.
 479  *
 480  * @adev: amdgpu_device pointer
 481  *
 482  * Tear down the hpd pins used by the card (evergreen+).
 483  * Disable the hpd interrupts.
 484  */
 485 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 486 {
 487         struct drm_device *dev = adev->ddev;
 488         struct drm_connector *connector;
 489         u32 tmp;
 490         int idx;
 491
 492         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 493                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 494
 495                 switch (amdgpu_connector->hpd.hpd) {
 496                 case AMDGPU_HPD_1:
 497                         idx = 0;
 498                         break;
 499                 case AMDGPU_HPD_2:
 500                         idx = 1;
 501                         break;
 502                 case AMDGPU_HPD_3:
 503                         idx = 2;
 504                         break;
 505                 case AMDGPU_HPD_4:
 506                         idx = 3;
 507                         break;
 508                 case AMDGPU_HPD_5:
 509                         idx = 4;
 510                         break;
 511                 case AMDGPU_HPD_6:
 512                         idx = 5;
 513                         break;
 514                 default:
 515                         continue;
 516                 }
 517
 518                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 519                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 520                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 521
 522                 amdgpu_irq_put(adev, &adev->hpd_irq,
 523                                amdgpu_connector->hpd.hpd);
 524         }
 525 }
 526
 527 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 528 {
 529         return mmDC_GPIO_HPD_A;
 530 }
 531
 532 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 533 {
 534         u32 crtc_hung = 0;
 535         u32 crtc_status[6];
 536         u32 i, j, tmp;
 537
 538         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 539                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 540                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 541                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 542                         crtc_hung |= (1 << i);
 543                 }
 544         }
 545
 546         for (j = 0; j < 10; j++) {
 547                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 548                         if (crtc_hung & (1 << i)) {
 549                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 550                                 if (tmp != crtc_status[i])
 551                                         crtc_hung &= ~(1 << i);
 552                         }
 553                 }
 554                 if (crtc_hung == 0)
 555                         return false;
 556                 udelay(100);
 557         }
 558
 559         return true;
 560 }
 561
 562 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
 563                                      struct amdgpu_mode_mc_save *save)
 564 {
 565         u32 crtc_enabled, tmp;
 566         int i;
 567
 568         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 569         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 570
 571         /* disable VGA render */
 572         tmp = RREG32(mmVGA_RENDER_CONTROL);
 573         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 574         WREG32(mmVGA_RENDER_CONTROL, tmp);
 575
 576         /* blank the display controllers */
 577         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 578                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 579                                              CRTC_CONTROL, CRTC_MASTER_EN);
 580                 if (crtc_enabled) {
 581 #if 0
 582                         u32 frame_count;
 583                         int j;
 584
 585                         save->crtc_enabled[i] = true;
 586                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 587                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 588                                 amdgpu_display_vblank_wait(adev, i);
 589                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 590                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 591                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 592                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 593                         }
 594                         /* wait for the next frame */
 595                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 596                         for (j = 0; j < adev->usec_timeout; j++) {
 597                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 598                                         break;
 599                                 udelay(1);
 600                         }
 601                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 602                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 603                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 604                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 605                         }
 606                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 607                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 608                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 609                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 610                         }
 611 #else
 612                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 613                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 614                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 615                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 616                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 617                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 618                         save->crtc_enabled[i] = false;
 619                         /* ***** */
 620 #endif
 621                 } else {
 622                         save->crtc_enabled[i] = false;
 623                 }
 624         }
 625 }
 626
 627 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
 628                                        struct amdgpu_mode_mc_save *save)
 629 {
 630         u32 tmp, frame_count;
 631         int i, j;
 632
 633         /* update crtc base addresses */
 634         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 635                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 636                        upper_32_bits(adev->mc.vram_start));
 637                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 638                        upper_32_bits(adev->mc.vram_start));
 639                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 640                        (u32)adev->mc.vram_start);
 641                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 642                        (u32)adev->mc.vram_start);
 643
 644                 if (save->crtc_enabled[i]) {
 645                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 646                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 647                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 648                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 649                         }
 650                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 651                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 652                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 653                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 654                         }
 655                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 656                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 657                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 658                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 659                         }
 660                         for (j = 0; j < adev->usec_timeout; j++) {
 661                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 662                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 663                                         break;
 664                                 udelay(1);
 665                         }
 666                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 667                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 668                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 669                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 670                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 671                         /* wait for the next frame */
 672                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 673                         for (j = 0; j < adev->usec_timeout; j++) {
 674                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 675                                         break;
 676                                 udelay(1);
 677                         }
 678                 }
 679         }
 680
 681         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 682         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 683
 684         /* Unlock vga access */
 685         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 686         mdelay(1);
 687         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 688 }
 689
 690 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 691                                            bool render)
 692 {
 693         u32 tmp;
 694
 695         /* Lockout access through VGA aperture*/
 696         tmp = RREG32(mmVGA_HDP_CONTROL);
 697         if (render)
 698                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 699         else
 700                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 701         WREG32(mmVGA_HDP_CONTROL, tmp);
 702
 703         /* disable VGA render */
 704         tmp = RREG32(mmVGA_RENDER_CONTROL);
 705         if (render)
 706                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 707         else
 708                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 709         WREG32(mmVGA_RENDER_CONTROL, tmp);
 710 }
 711
 712 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 713 {
 714         struct drm_device *dev = encoder->dev;
 715         struct amdgpu_device *adev = dev->dev_private;
 716         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 717         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 718         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 719         int bpc = 0;
 720         u32 tmp = 0;
 721         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 722
 723         if (connector) {
 724                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 725                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 726                 dither = amdgpu_connector->dither;
 727         }
 728
 729         /* LVDS/eDP FMT is set up by atom */
 730         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 731                 return;
 732
 733         /* not needed for analog */
 734         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 735             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 736                 return;
 737
 738         if (bpc == 0)
 739                 return;
 740
 741         switch (bpc) {
 742         case 6:
 743                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 744                         /* XXX sort out optimal dither settings */
 745                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 746                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 747                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 748                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 749                 } else {
 750                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 751                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 752                 }
 753                 break;
 754         case 8:
 755                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 756                         /* XXX sort out optimal dither settings */
 757                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 758                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 759                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 760                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 761                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 762                 } else {
 763                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 764                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 765                 }
 766                 break;
 767         case 10:
 768                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 769                         /* XXX sort out optimal dither settings */
 770                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 771                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 772                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 773                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 774                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 775                 } else {
 776                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 777                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 778                 }
 779                 break;
 780         default:
 781                 /* not needed */
 782                 break;
 783         }
 784
 785         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 786 }
 787
 788
 789 /* display watermark setup */
 790 /**
 791  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 792  *
 793  * @adev: amdgpu_device pointer
 794  * @amdgpu_crtc: the selected display controller
 795  * @mode: the current display mode on the selected display
 796  * controller
 797  *
 798  * Setup up the line buffer allocation for
 799  * the selected display controller (CIK).
 800  * Returns the line buffer size in pixels.
 801  */
 802 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 803                                        struct amdgpu_crtc *amdgpu_crtc,
 804                                        struct drm_display_mode *mode)
 805 {
 806         u32 tmp, buffer_alloc, i, mem_cfg;
 807         u32 pipe_offset = amdgpu_crtc->crtc_id;
 808         /*
 809          * Line Buffer Setup
 810          * There are 6 line buffers, one for each display controllers.
 811          * There are 3 partitions per LB. Select the number of partitions
 812          * to enable based on the display width.  For display widths larger
 813          * than 4096, you need use to use 2 display controllers and combine
 814          * them using the stereo blender.
 815          */
 816         if (amdgpu_crtc->base.enabled && mode) {
 817                 if (mode->crtc_hdisplay < 1920) {
 818                         mem_cfg = 1;
 819                         buffer_alloc = 2;
 820                 } else if (mode->crtc_hdisplay < 2560) {
 821                         mem_cfg = 2;
 822                         buffer_alloc = 2;
 823                 } else if (mode->crtc_hdisplay < 4096) {
 824                         mem_cfg = 0;
 825                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 826                 } else {
 827                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 828                         mem_cfg = 0;
 829                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 830                 }
 831         } else {
 832                 mem_cfg = 1;
 833                 buffer_alloc = 0;
 834         }
 835
 836         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 837         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 838         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 839
 840         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 841         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 842         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 843
 844         for (i = 0; i < adev->usec_timeout; i++) {
 845                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 846                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 847                         break;
 848                 udelay(1);
 849         }
 850
 851         if (amdgpu_crtc->base.enabled && mode) {
 852                 switch (mem_cfg) {
 853                 case 0:
 854                 default:
 855                         return 4096 * 2;
 856                 case 1:
 857                         return 1920 * 2;
 858                 case 2:
 859                         return 2560 * 2;
 860                 }
 861         }
 862
 863         /* controller not enabled, so no lb used */
 864         return 0;
 865 }
 866
 867 /**
 868  * cik_get_number_of_dram_channels - get the number of dram channels
 869  *
 870  * @adev: amdgpu_device pointer
 871  *
 872  * Look up the number of video ram channels (CIK).
 873  * Used for display watermark bandwidth calculations
 874  * Returns the number of dram channels
 875  */
 876 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 877 {
 878         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 879
 880         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 881         case 0:
 882         default:
 883                 return 1;
 884         case 1:
 885                 return 2;
 886         case 2:
 887                 return 4;
 888         case 3:
 889                 return 8;
 890         case 4:
 891                 return 3;
 892         case 5:
 893                 return 6;
 894         case 6:
 895                 return 10;
 896         case 7:
 897                 return 12;
 898         case 8:
 899                 return 16;
 900         }
 901 }
 902
 903 struct dce10_wm_params {
 904         u32 dram_channels; /* number of dram channels */
 905         u32 yclk;          /* bandwidth per dram data pin in kHz */
 906         u32 sclk;          /* engine clock in kHz */
 907         u32 disp_clk;      /* display clock in kHz */
 908         u32 src_width;     /* viewport width */
 909         u32 active_time;   /* active display time in ns */
 910         u32 blank_time;    /* blank time in ns */
 911         bool interlaced;    /* mode is interlaced */
 912         fixed20_12 vsc;    /* vertical scale ratio */
 913         u32 num_heads;     /* number of active crtcs */
 914         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 915         u32 lb_size;       /* line buffer allocated to pipe */
 916         u32 vtaps;         /* vertical scaler taps */
 917 };
 918
 919 /**
 920  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 921  *
 922  * @wm: watermark calculation data
 923  *
 924  * Calculate the raw dram bandwidth (CIK).
 925  * Used for display watermark bandwidth calculations
 926  * Returns the dram bandwidth in MBytes/s
 927  */
 928 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 929 {
 930         /* Calculate raw DRAM Bandwidth */
 931         fixed20_12 dram_efficiency; /* 0.7 */
 932         fixed20_12 yclk, dram_channels, bandwidth;
 933         fixed20_12 a;
 934
 935         a.full = dfixed_const(1000);
 936         yclk.full = dfixed_const(wm->yclk);
 937         yclk.full = dfixed_div(yclk, a);
 938         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 939         a.full = dfixed_const(10);
 940         dram_efficiency.full = dfixed_const(7);
 941         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 942         bandwidth.full = dfixed_mul(dram_channels, yclk);
 943         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 944
 945         return dfixed_trunc(bandwidth);
 946 }
 947
 948 /**
 949  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 950  *
 951  * @wm: watermark calculation data
 952  *
 953  * Calculate the dram bandwidth used for display (CIK).
 954  * Used for display watermark bandwidth calculations
 955  * Returns the dram bandwidth for display in MBytes/s
 956  */
 957 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 958 {
 959         /* Calculate DRAM Bandwidth and the part allocated to display. */
 960         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 961         fixed20_12 yclk, dram_channels, bandwidth;
 962         fixed20_12 a;
 963
 964         a.full = dfixed_const(1000);
 965         yclk.full = dfixed_const(wm->yclk);
 966         yclk.full = dfixed_div(yclk, a);
 967         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 968         a.full = dfixed_const(10);
 969         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 970         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 971         bandwidth.full = dfixed_mul(dram_channels, yclk);
 972         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 973
 974         return dfixed_trunc(bandwidth);
 975 }
 976
 977 /**
 978  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 979  *
 980  * @wm: watermark calculation data
 981  *
 982  * Calculate the data return bandwidth used for display (CIK).
 983  * Used for display watermark bandwidth calculations
 984  * Returns the data return bandwidth in MBytes/s
 985  */
 986 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 987 {
 988         /* Calculate the display Data return Bandwidth */
 989         fixed20_12 return_efficiency; /* 0.8 */
 990         fixed20_12 sclk, bandwidth;
 991         fixed20_12 a;
 992
 993         a.full = dfixed_const(1000);
 994         sclk.full = dfixed_const(wm->sclk);
 995         sclk.full = dfixed_div(sclk, a);
 996         a.full = dfixed_const(10);
 997         return_efficiency.full = dfixed_const(8);
 998         return_efficiency.full = dfixed_div(return_efficiency, a);
 999         a.full = dfixed_const(32);
1000         bandwidth.full = dfixed_mul(a, sclk);
1001         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1002
1003         return dfixed_trunc(bandwidth);
1004 }
1005
1006 /**
1007  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1008  *
1009  * @wm: watermark calculation data
1010  *
1011  * Calculate the dmif bandwidth used for display (CIK).
1012  * Used for display watermark bandwidth calculations
1013  * Returns the dmif bandwidth in MBytes/s
1014  */
1015 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1016 {
1017         /* Calculate the DMIF Request Bandwidth */
1018         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1019         fixed20_12 disp_clk, bandwidth;
1020         fixed20_12 a, b;
1021
1022         a.full = dfixed_const(1000);
1023         disp_clk.full = dfixed_const(wm->disp_clk);
1024         disp_clk.full = dfixed_div(disp_clk, a);
1025         a.full = dfixed_const(32);
1026         b.full = dfixed_mul(a, disp_clk);
1027
1028         a.full = dfixed_const(10);
1029         disp_clk_request_efficiency.full = dfixed_const(8);
1030         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1031
1032         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1033
1034         return dfixed_trunc(bandwidth);
1035 }
1036
1037 /**
1038  * dce_v10_0_available_bandwidth - get the min available bandwidth
1039  *
1040  * @wm: watermark calculation data
1041  *
1042  * Calculate the min available bandwidth used for display (CIK).
1043  * Used for display watermark bandwidth calculations
1044  * Returns the min available bandwidth in MBytes/s
1045  */
1046 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1047 {
1048         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1049         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1050         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1051         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1052
1053         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1054 }
1055
1056 /**
1057  * dce_v10_0_average_bandwidth - get the average available bandwidth
1058  *
1059  * @wm: watermark calculation data
1060  *
1061  * Calculate the average available bandwidth used for display (CIK).
1062  * Used for display watermark bandwidth calculations
1063  * Returns the average available bandwidth in MBytes/s
1064  */
1065 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1066 {
1067         /* Calculate the display mode Average Bandwidth
1068          * DisplayMode should contain the source and destination dimensions,
1069          * timing, etc.
1070          */
1071         fixed20_12 bpp;
1072         fixed20_12 line_time;
1073         fixed20_12 src_width;
1074         fixed20_12 bandwidth;
1075         fixed20_12 a;
1076
1077         a.full = dfixed_const(1000);
1078         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1079         line_time.full = dfixed_div(line_time, a);
1080         bpp.full = dfixed_const(wm->bytes_per_pixel);
1081         src_width.full = dfixed_const(wm->src_width);
1082         bandwidth.full = dfixed_mul(src_width, bpp);
1083         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1084         bandwidth.full = dfixed_div(bandwidth, line_time);
1085
1086         return dfixed_trunc(bandwidth);
1087 }
1088
1089 /**
1090  * dce_v10_0_latency_watermark - get the latency watermark
1091  *
1092  * @wm: watermark calculation data
1093  *
1094  * Calculate the latency watermark (CIK).
1095  * Used for display watermark bandwidth calculations
1096  * Returns the latency watermark in ns
1097  */
1098 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1099 {
1100         /* First calculate the latency in ns */
1101         u32 mc_latency = 2000; /* 2000 ns. */
1102         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1103         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1104         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1105         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1106         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1107                 (wm->num_heads * cursor_line_pair_return_time);
1108         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1109         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1110         u32 tmp, dmif_size = 12288;
1111         fixed20_12 a, b, c;
1112
1113         if (wm->num_heads == 0)
1114                 return 0;
1115
1116         a.full = dfixed_const(2);
1117         b.full = dfixed_const(1);
1118         if ((wm->vsc.full > a.full) ||
1119             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1120             (wm->vtaps >= 5) ||
1121             ((wm->vsc.full >= a.full) && wm->interlaced))
1122                 max_src_lines_per_dst_line = 4;
1123         else
1124                 max_src_lines_per_dst_line = 2;
1125
1126         a.full = dfixed_const(available_bandwidth);
1127         b.full = dfixed_const(wm->num_heads);
1128         a.full = dfixed_div(a, b);
1129         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1130         tmp = min(dfixed_trunc(a), tmp);
1131
1132         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1133
1134         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1135         b.full = dfixed_const(1000);
1136         c.full = dfixed_const(lb_fill_bw);
1137         b.full = dfixed_div(c, b);
1138         a.full = dfixed_div(a, b);
1139         line_fill_time = dfixed_trunc(a);
1140
1141         if (line_fill_time < wm->active_time)
1142                 return latency;
1143         else
1144                 return latency + (line_fill_time - wm->active_time);
1145
1146 }
1147
1148 /**
1149  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1150  * average and available dram bandwidth
1151  *
1152  * @wm: watermark calculation data
1153  *
1154  * Check if the display average bandwidth fits in the display
1155  * dram bandwidth (CIK).
1156  * Used for display watermark bandwidth calculations
1157  * Returns true if the display fits, false if not.
1158  */
1159 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1160 {
1161         if (dce_v10_0_average_bandwidth(wm) <=
1162             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1163                 return true;
1164         else
1165                 return false;
1166 }
1167
1168 /**
1169  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1170  * average and available bandwidth
1171  *
1172  * @wm: watermark calculation data
1173  *
1174  * Check if the display average bandwidth fits in the display
1175  * available bandwidth (CIK).
1176  * Used for display watermark bandwidth calculations
1177  * Returns true if the display fits, false if not.
1178  */
1179 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1180 {
1181         if (dce_v10_0_average_bandwidth(wm) <=
1182             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1183                 return true;
1184         else
1185                 return false;
1186 }
1187
1188 /**
1189  * dce_v10_0_check_latency_hiding - check latency hiding
1190  *
1191  * @wm: watermark calculation data
1192  *
1193  * Check latency hiding (CIK).
1194  * Used for display watermark bandwidth calculations
1195  * Returns true if the display fits, false if not.
1196  */
1197 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1198 {
1199         u32 lb_partitions = wm->lb_size / wm->src_width;
1200         u32 line_time = wm->active_time + wm->blank_time;
1201         u32 latency_tolerant_lines;
1202         u32 latency_hiding;
1203         fixed20_12 a;
1204
1205         a.full = dfixed_const(1);
1206         if (wm->vsc.full > a.full)
1207                 latency_tolerant_lines = 1;
1208         else {
1209                 if (lb_partitions <= (wm->vtaps + 1))
1210                         latency_tolerant_lines = 1;
1211                 else
1212                         latency_tolerant_lines = 2;
1213         }
1214
1215         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1216
1217         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1218                 return true;
1219         else
1220                 return false;
1221 }
1222
1223 /**
1224  * dce_v10_0_program_watermarks - program display watermarks
1225  *
1226  * @adev: amdgpu_device pointer
1227  * @amdgpu_crtc: the selected display controller
1228  * @lb_size: line buffer size
1229  * @num_heads: number of display controllers in use
1230  *
1231  * Calculate and program the display watermarks for the
1232  * selected display controller (CIK).
1233  */
1234 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1235                                         struct amdgpu_crtc *amdgpu_crtc,
1236                                         u32 lb_size, u32 num_heads)
1237 {
1238         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1239         struct dce10_wm_params wm_low, wm_high;
1240         u32 active_time;
1241         u32 line_time = 0;
1242         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1243         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1244
1245         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1246                 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1247                 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1248
1249                 /* watermark for high clocks */
1250                 if (adev->pm.dpm_enabled) {
1251                         wm_high.yclk =
1252                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1253                         wm_high.sclk =
1254                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1255                 } else {
1256                         wm_high.yclk = adev->pm.current_mclk * 10;
1257                         wm_high.sclk = adev->pm.current_sclk * 10;
1258                 }
1259
1260                 wm_high.disp_clk = mode->clock;
1261                 wm_high.src_width = mode->crtc_hdisplay;
1262                 wm_high.active_time = active_time;
1263                 wm_high.blank_time = line_time - wm_high.active_time;
1264                 wm_high.interlaced = false;
1265                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1266                         wm_high.interlaced = true;
1267                 wm_high.vsc = amdgpu_crtc->vsc;
1268                 wm_high.vtaps = 1;
1269                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1270                         wm_high.vtaps = 2;
1271                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1272                 wm_high.lb_size = lb_size;
1273                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1274                 wm_high.num_heads = num_heads;
1275
1276                 /* set for high clocks */
1277                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1278
1279                 /* possibly force display priority to high */
1280                 /* should really do this at mode validation time... */
1281                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1282                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1283                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1284                     (adev->mode_info.disp_priority == 2)) {
1285                         DRM_DEBUG_KMS("force priority to high\n");
1286                 }
1287
1288                 /* watermark for low clocks */
1289                 if (adev->pm.dpm_enabled) {
1290                         wm_low.yclk =
1291                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1292                         wm_low.sclk =
1293                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1294                 } else {
1295                         wm_low.yclk = adev->pm.current_mclk * 10;
1296                         wm_low.sclk = adev->pm.current_sclk * 10;
1297                 }
1298
1299                 wm_low.disp_clk = mode->clock;
1300                 wm_low.src_width = mode->crtc_hdisplay;
1301                 wm_low.active_time = active_time;
1302                 wm_low.blank_time = line_time - wm_low.active_time;
1303                 wm_low.interlaced = false;
1304                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1305                         wm_low.interlaced = true;
1306                 wm_low.vsc = amdgpu_crtc->vsc;
1307                 wm_low.vtaps = 1;
1308                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1309                         wm_low.vtaps = 2;
1310                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1311                 wm_low.lb_size = lb_size;
1312                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1313                 wm_low.num_heads = num_heads;
1314
1315                 /* set for low clocks */
1316                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1317
1318                 /* possibly force display priority to high */
1319                 /* should really do this at mode validation time... */
1320                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1321                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1322                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1323                     (adev->mode_info.disp_priority == 2)) {
1324                         DRM_DEBUG_KMS("force priority to high\n");
1325                 }
1326                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1327         }
1328
1329         /* select wm A */
1330         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1331         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1332         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1333         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1334         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1335         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1336         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1337         /* select wm B */
1338         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1339         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1340         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1341         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1342         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1343         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1344         /* restore original selection */
1345         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1346
1347         /* save values for DPM */
1348         amdgpu_crtc->line_time = line_time;
1349         amdgpu_crtc->wm_high = latency_watermark_a;
1350         amdgpu_crtc->wm_low = latency_watermark_b;
1351         /* Save number of lines the linebuffer leads before the scanout */
1352         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1353 }
1354
1355 /**
1356  * dce_v10_0_bandwidth_update - program display watermarks
1357  *
1358  * @adev: amdgpu_device pointer
1359  *
1360  * Calculate and program the display watermarks and line
1361  * buffer allocation (CIK).
1362  */
1363 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1364 {
1365         struct drm_display_mode *mode = NULL;
1366         u32 num_heads = 0, lb_size;
1367         int i;
1368
1369         amdgpu_update_display_priority(adev);
1370
1371         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1372                 if (adev->mode_info.crtcs[i]->base.enabled)
1373                         num_heads++;
1374         }
1375         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1376                 mode = &adev->mode_info.crtcs[i]->base.mode;
1377                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1378                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1379                                             lb_size, num_heads);
1380         }
1381 }
1382
1383 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1384 {
1385         int i;
1386         u32 offset, tmp;
1387
1388         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1389                 offset = adev->mode_info.audio.pin[i].offset;
1390                 tmp = RREG32_AUDIO_ENDPT(offset,
1391                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1392                 if (((tmp &
1393                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1394                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1395                         adev->mode_info.audio.pin[i].connected = false;
1396                 else
1397                         adev->mode_info.audio.pin[i].connected = true;
1398         }
1399 }
1400
1401 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1402 {
1403         int i;
1404
1405         dce_v10_0_audio_get_connected_pins(adev);
1406
1407         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1408                 if (adev->mode_info.audio.pin[i].connected)
1409                         return &adev->mode_info.audio.pin[i];
1410         }
1411         DRM_ERROR("No connected audio pins found!\n");
1412         return NULL;
1413 }
1414
1415 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1416 {
1417         struct amdgpu_device *adev = encoder->dev->dev_private;
1418         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1419         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1420         u32 tmp;
1421
1422         if (!dig || !dig->afmt || !dig->afmt->pin)
1423                 return;
1424
1425         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1426         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1427         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1428 }
1429
1430 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1431                                                 struct drm_display_mode *mode)
1432 {
1433         struct amdgpu_device *adev = encoder->dev->dev_private;
1434         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1435         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1436         struct drm_connector *connector;
1437         struct amdgpu_connector *amdgpu_connector = NULL;
1438         u32 tmp;
1439         int interlace = 0;
1440
1441         if (!dig || !dig->afmt || !dig->afmt->pin)
1442                 return;
1443
1444         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1445                 if (connector->encoder == encoder) {
1446                         amdgpu_connector = to_amdgpu_connector(connector);
1447                         break;
1448                 }
1449         }
1450
1451         if (!amdgpu_connector) {
1452                 DRM_ERROR("Couldn't find encoder's connector\n");
1453                 return;
1454         }
1455
1456         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1457                 interlace = 1;
1458         if (connector->latency_present[interlace]) {
1459                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1460                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1461                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1462                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1463         } else {
1464                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1465                                     VIDEO_LIPSYNC, 0);
1466                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1467                                     AUDIO_LIPSYNC, 0);
1468         }
1469         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1470                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1471 }
1472
1473 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1474 {
1475         struct amdgpu_device *adev = encoder->dev->dev_private;
1476         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1477         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1478         struct drm_connector *connector;
1479         struct amdgpu_connector *amdgpu_connector = NULL;
1480         u32 tmp;
1481         u8 *sadb = NULL;
1482         int sad_count;
1483
1484         if (!dig || !dig->afmt || !dig->afmt->pin)
1485                 return;
1486
1487         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1488                 if (connector->encoder == encoder) {
1489                         amdgpu_connector = to_amdgpu_connector(connector);
1490                         break;
1491                 }
1492         }
1493
1494         if (!amdgpu_connector) {
1495                 DRM_ERROR("Couldn't find encoder's connector\n");
1496                 return;
1497         }
1498
1499         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1500         if (sad_count < 0) {
1501                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1502                 sad_count = 0;
1503         }
1504
1505         /* program the speaker allocation */
1506         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1507                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1508         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1509                             DP_CONNECTION, 0);
1510         /* set HDMI mode */
1511         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1512                             HDMI_CONNECTION, 1);
1513         if (sad_count)
1514                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1515                                     SPEAKER_ALLOCATION, sadb[0]);
1516         else
1517                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1518                                     SPEAKER_ALLOCATION, 5); /* stereo */
1519         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1520                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1521
1522         kfree(sadb);
1523 }
1524
1525 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1526 {
1527         struct amdgpu_device *adev = encoder->dev->dev_private;
1528         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1529         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1530         struct drm_connector *connector;
1531         struct amdgpu_connector *amdgpu_connector = NULL;
1532         struct cea_sad *sads;
1533         int i, sad_count;
1534
1535         static const u16 eld_reg_to_type[][2] = {
1536                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1537                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1538                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1539                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1540                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1541                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1542                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1543                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1544                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1545                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1546                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1547                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1548         };
1549
1550         if (!dig || !dig->afmt || !dig->afmt->pin)
1551                 return;
1552
1553         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1554                 if (connector->encoder == encoder) {
1555                         amdgpu_connector = to_amdgpu_connector(connector);
1556                         break;
1557                 }
1558         }
1559
1560         if (!amdgpu_connector) {
1561                 DRM_ERROR("Couldn't find encoder's connector\n");
1562                 return;
1563         }
1564
1565         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1566         if (sad_count <= 0) {
1567                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1568                 return;
1569         }
1570         BUG_ON(!sads);
1571
1572         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1573                 u32 tmp = 0;
1574                 u8 stereo_freqs = 0;
1575                 int max_channels = -1;
1576                 int j;
1577
1578                 for (j = 0; j < sad_count; j++) {
1579                         struct cea_sad *sad = &sads[j];
1580
1581                         if (sad->format == eld_reg_to_type[i][1]) {
1582                                 if (sad->channels > max_channels) {
1583                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1584                                                             MAX_CHANNELS, sad->channels);
1585                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1586                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1587                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1588                                                             SUPPORTED_FREQUENCIES, sad->freq);
1589                                         max_channels = sad->channels;
1590                                 }
1591
1592                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1593                                         stereo_freqs |= sad->freq;
1594                                 else
1595                                         break;
1596                         }
1597                 }
1598
1599                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1600                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1601                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1602         }
1603
1604         kfree(sads);
1605 }
1606
1607 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1608                                   struct amdgpu_audio_pin *pin,
1609                                   bool enable)
1610 {
1611         if (!pin)
1612                 return;
1613
1614         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1615                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1616 }
1617
1618 static const u32 pin_offsets[] =
1619 {
1620         AUD0_REGISTER_OFFSET,
1621         AUD1_REGISTER_OFFSET,
1622         AUD2_REGISTER_OFFSET,
1623         AUD3_REGISTER_OFFSET,
1624         AUD4_REGISTER_OFFSET,
1625         AUD5_REGISTER_OFFSET,
1626         AUD6_REGISTER_OFFSET,
1627 };
1628
1629 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1630 {
1631         int i;
1632
1633         if (!amdgpu_audio)
1634                 return 0;
1635
1636         adev->mode_info.audio.enabled = true;
1637
1638         adev->mode_info.audio.num_pins = 7;
1639
1640         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1641                 adev->mode_info.audio.pin[i].channels = -1;
1642                 adev->mode_info.audio.pin[i].rate = -1;
1643                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1644                 adev->mode_info.audio.pin[i].status_bits = 0;
1645                 adev->mode_info.audio.pin[i].category_code = 0;
1646                 adev->mode_info.audio.pin[i].connected = false;
1647                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1648                 adev->mode_info.audio.pin[i].id = i;
1649                 /* disable audio.  it will be set up later */
1650                 /* XXX remove once we switch to ip funcs */
1651                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1652         }
1653
1654         return 0;
1655 }
1656
1657 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1658 {
1659         int i;
1660
1661         if (!adev->mode_info.audio.enabled)
1662                 return;
1663
1664         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1665                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1666
1667         adev->mode_info.audio.enabled = false;
1668 }
1669
1670 /*
1671  * update the N and CTS parameters for a given pixel clock rate
1672  */
1673 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1674 {
1675         struct drm_device *dev = encoder->dev;
1676         struct amdgpu_device *adev = dev->dev_private;
1677         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1678         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1679         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1680         u32 tmp;
1681
1682         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1683         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1684         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1685         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1686         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1687         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1688
1689         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1690         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1691         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1692         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1693         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1694         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1695
1696         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1697         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1698         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1699         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1700         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1701         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1702
1703 }
1704
1705 /*
1706  * build a HDMI Video Info Frame
1707  */
1708 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1709                                                void *buffer, size_t size)
1710 {
1711         struct drm_device *dev = encoder->dev;
1712         struct amdgpu_device *adev = dev->dev_private;
1713         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1714         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1715         uint8_t *frame = buffer + 3;
1716         uint8_t *header = buffer;
1717
1718         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1719                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1720         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1721                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1722         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1723                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1724         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1725                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1726 }
1727
1728 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1729 {
1730         struct drm_device *dev = encoder->dev;
1731         struct amdgpu_device *adev = dev->dev_private;
1732         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1733         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1734         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1735         u32 dto_phase = 24 * 1000;
1736         u32 dto_modulo = clock;
1737         u32 tmp;
1738
1739         if (!dig || !dig->afmt)
1740                 return;
1741
1742         /* XXX two dtos; generally use dto0 for hdmi */
1743         /* Express [24MHz / target pixel clock] as an exact rational
1744          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1745          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1746          */
1747         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1748         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1749                             amdgpu_crtc->crtc_id);
1750         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1751         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1752         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1753 }
1754
1755 /*
1756  * update the info frames with the data from the current display mode
1757  */
1758 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1759                                   struct drm_display_mode *mode)
1760 {
1761         struct drm_device *dev = encoder->dev;
1762         struct amdgpu_device *adev = dev->dev_private;
1763         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1764         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1765         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1766         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1767         struct hdmi_avi_infoframe frame;
1768         ssize_t err;
1769         u32 tmp;
1770         int bpc = 8;
1771
1772         if (!dig || !dig->afmt)
1773                 return;
1774
1775         /* Silent, r600_hdmi_enable will raise WARN for us */
1776         if (!dig->afmt->enabled)
1777                 return;
1778
1779         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1780         if (encoder->crtc) {
1781                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1782                 bpc = amdgpu_crtc->bpc;
1783         }
1784
1785         /* disable audio prior to setting up hw */
1786         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1787         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1788
1789         dce_v10_0_audio_set_dto(encoder, mode->clock);
1790
1791         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1792         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1793         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1794
1795         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1796
1797         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1798         switch (bpc) {
1799         case 0:
1800         case 6:
1801         case 8:
1802         case 16:
1803         default:
1804                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1805                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1806                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1807                           connector->name, bpc);
1808                 break;
1809         case 10:
1810                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1811                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1812                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1813                           connector->name);
1814                 break;
1815         case 12:
1816                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1817                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1818                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1819                           connector->name);
1820                 break;
1821         }
1822         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1823
1824         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1825         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1826         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1827         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1828         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1829
1830         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1831         /* enable audio info frames (frames won't be set until audio is enabled) */
1832         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1833         /* required for audio info values to be updated */
1834         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1835         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1836
1837         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1838         /* required for audio info values to be updated */
1839         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1840         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1841
1842         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1843         /* anything other than 0 */
1844         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1845         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1846
1847         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1848
1849         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1850         /* set the default audio delay */
1851         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1852         /* should be suffient for all audio modes and small enough for all hblanks */
1853         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1854         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1855
1856         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1857         /* allow 60958 channel status fields to be updated */
1858         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1859         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1860
1861         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1862         if (bpc > 8)
1863                 /* clear SW CTS value */
1864                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1865         else
1866                 /* select SW CTS value */
1867                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1868         /* allow hw to sent ACR packets when required */
1869         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1870         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1871
1872         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1873
1874         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1875         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1876         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1877
1878         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1879         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1880         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1881
1882         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1883         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1884         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1885         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1886         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1887         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1888         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1889         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1890
1891         dce_v10_0_audio_write_speaker_allocation(encoder);
1892
1893         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1894                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1895
1896         dce_v10_0_afmt_audio_select_pin(encoder);
1897         dce_v10_0_audio_write_sad_regs(encoder);
1898         dce_v10_0_audio_write_latency_fields(encoder, mode);
1899
1900         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1901         if (err < 0) {
1902                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1903                 return;
1904         }
1905
1906         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1907         if (err < 0) {
1908                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1909                 return;
1910         }
1911
1912         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1913
1914         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1915         /* enable AVI info frames */
1916         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1917         /* required for audio info values to be updated */
1918         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1919         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1920
1921         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1922         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1923         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1924
1925         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1926         /* send audio packets */
1927         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1928         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1929
1930         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1931         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1932         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1933         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1934
1935         /* enable audio after to setting up hw */
1936         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1937 }
1938
1939 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1940 {
1941         struct drm_device *dev = encoder->dev;
1942         struct amdgpu_device *adev = dev->dev_private;
1943         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1944         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1945
1946         if (!dig || !dig->afmt)
1947                 return;
1948
1949         /* Silent, r600_hdmi_enable will raise WARN for us */
1950         if (enable && dig->afmt->enabled)
1951                 return;
1952         if (!enable && !dig->afmt->enabled)
1953                 return;
1954
1955         if (!enable && dig->afmt->pin) {
1956                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1957                 dig->afmt->pin = NULL;
1958         }
1959
1960         dig->afmt->enabled = enable;
1961
1962         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1963                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1964 }
1965
1966 static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
1967 {
1968         int i;
1969
1970         for (i = 0; i < adev->mode_info.num_dig; i++)
1971                 adev->mode_info.afmt[i] = NULL;
1972
1973         /* DCE10 has audio blocks tied to DIG encoders */
1974         for (i = 0; i < adev->mode_info.num_dig; i++) {
1975                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1976                 if (adev->mode_info.afmt[i]) {
1977                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1978                         adev->mode_info.afmt[i]->id = i;
1979                 }
1980         }
1981 }
1982
1983 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1984 {
1985         int i;
1986
1987         for (i = 0; i < adev->mode_info.num_dig; i++) {
1988                 kfree(adev->mode_info.afmt[i]);
1989                 adev->mode_info.afmt[i] = NULL;
1990         }
1991 }
1992
1993 static const u32 vga_control_regs[6] =
1994 {
1995         mmD1VGA_CONTROL,
1996         mmD2VGA_CONTROL,
1997         mmD3VGA_CONTROL,
1998         mmD4VGA_CONTROL,
1999         mmD5VGA_CONTROL,
2000         mmD6VGA_CONTROL,
2001 };
2002
2003 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2004 {
2005         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2006         struct drm_device *dev = crtc->dev;
2007         struct amdgpu_device *adev = dev->dev_private;
2008         u32 vga_control;
2009
2010         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2011         if (enable)
2012                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2013         else
2014                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2015 }
2016
2017 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2018 {
2019         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2020         struct drm_device *dev = crtc->dev;
2021         struct amdgpu_device *adev = dev->dev_private;
2022
2023         if (enable)
2024                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2025         else
2026                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2027 }
2028
2029 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2030                                      struct drm_framebuffer *fb,
2031                                      int x, int y, int atomic)
2032 {
2033         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2034         struct drm_device *dev = crtc->dev;
2035         struct amdgpu_device *adev = dev->dev_private;
2036         struct amdgpu_framebuffer *amdgpu_fb;
2037         struct drm_framebuffer *target_fb;
2038         struct drm_gem_object *obj;
2039         struct amdgpu_bo *rbo;
2040         uint64_t fb_location, tiling_flags;
2041         uint32_t fb_format, fb_pitch_pixels;
2042         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2043         u32 pipe_config;
2044         u32 tmp, viewport_w, viewport_h;
2045         int r;
2046         bool bypass_lut = false;
2047
2048         /* no fb bound */
2049         if (!atomic && !crtc->primary->fb) {
2050                 DRM_DEBUG_KMS("No FB bound\n");
2051                 return 0;
2052         }
2053
2054         if (atomic) {
2055                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2056                 target_fb = fb;
2057         }
2058         else {
2059                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2060                 target_fb = crtc->primary->fb;
2061         }
2062
2063         /* If atomic, assume fb object is pinned & idle & fenced and
2064          * just update base pointers
2065          */
2066         obj = amdgpu_fb->obj;
2067         rbo = gem_to_amdgpu_bo(obj);
2068         r = amdgpu_bo_reserve(rbo, false);
2069         if (unlikely(r != 0))
2070                 return r;
2071
2072         if (atomic)
2073                 fb_location = amdgpu_bo_gpu_offset(rbo);
2074         else {
2075                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2076                 if (unlikely(r != 0)) {
2077                         amdgpu_bo_unreserve(rbo);
2078                         return -EINVAL;
2079                 }
2080         }
2081
2082         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2083         amdgpu_bo_unreserve(rbo);
2084
2085         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2086
2087         switch (target_fb->pixel_format) {
2088         case DRM_FORMAT_C8:
2089                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2090                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2091                 break;
2092         case DRM_FORMAT_XRGB4444:
2093         case DRM_FORMAT_ARGB4444:
2094                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2095                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2096 #ifdef __BIG_ENDIAN
2097                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2098                                         ENDIAN_8IN16);
2099 #endif
2100                 break;
2101         case DRM_FORMAT_XRGB1555:
2102         case DRM_FORMAT_ARGB1555:
2103                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2104                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2105 #ifdef __BIG_ENDIAN
2106                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2107                                         ENDIAN_8IN16);
2108 #endif
2109                 break;
2110         case DRM_FORMAT_BGRX5551:
2111         case DRM_FORMAT_BGRA5551:
2112                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2113                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2114 #ifdef __BIG_ENDIAN
2115                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2116                                         ENDIAN_8IN16);
2117 #endif
2118                 break;
2119         case DRM_FORMAT_RGB565:
2120                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2121                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2122 #ifdef __BIG_ENDIAN
2123                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2124                                         ENDIAN_8IN16);
2125 #endif
2126                 break;
2127         case DRM_FORMAT_XRGB8888:
2128         case DRM_FORMAT_ARGB8888:
2129                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2130                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2131 #ifdef __BIG_ENDIAN
2132                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2133                                         ENDIAN_8IN32);
2134 #endif
2135                 break;
2136         case DRM_FORMAT_XRGB2101010:
2137         case DRM_FORMAT_ARGB2101010:
2138                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2139                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2140 #ifdef __BIG_ENDIAN
2141                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2142                                         ENDIAN_8IN32);
2143 #endif
2144                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2145                 bypass_lut = true;
2146                 break;
2147         case DRM_FORMAT_BGRX1010102:
2148         case DRM_FORMAT_BGRA1010102:
2149                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2150                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2151 #ifdef __BIG_ENDIAN
2152                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2153                                         ENDIAN_8IN32);
2154 #endif
2155                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2156                 bypass_lut = true;
2157                 break;
2158         default:
2159                 DRM_ERROR("Unsupported screen format %s\n",
2160                         drm_get_format_name(target_fb->pixel_format));
2161                 return -EINVAL;
2162         }
2163
2164         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2165                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2166
2167                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2168                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2169                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2170                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2171                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2172
2173                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2174                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2175                                           ARRAY_2D_TILED_THIN1);
2176                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2177                                           tile_split);
2178                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2179                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2180                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2181                                           mtaspect);
2182                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2183                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2184         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2185                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2186                                           ARRAY_1D_TILED_THIN1);
2187         }
2188
2189         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2190                                   pipe_config);
2191
2192         dce_v10_0_vga_enable(crtc, false);
2193
2194         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2195                upper_32_bits(fb_location));
2196         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2197                upper_32_bits(fb_location));
2198         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2199                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2200         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2201                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2202         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2203         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2204
2205         /*
2206          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2207          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2208          * retain the full precision throughout the pipeline.
2209          */
2210         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2211         if (bypass_lut)
2212                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2213         else
2214                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2215         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2216
2217         if (bypass_lut)
2218                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2219
2220         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2221         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2222         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2223         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2224         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2225         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2226
2227         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2228         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2229
2230         dce_v10_0_grph_enable(crtc, true);
2231
2232         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2233                target_fb->height);
2234
2235         x &= ~3;
2236         y &= ~1;
2237         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2238                (x << 16) | y);
2239         viewport_w = crtc->mode.hdisplay;
2240         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2241         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2242                (viewport_w << 16) | viewport_h);
2243
2244         /* pageflip setup */
2245         /* make sure flip is at vb rather than hb */
2246         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2247         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2248                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2249         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2250
2251         /* set pageflip to happen only at start of vblank interval (front porch) */
2252         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2253
2254         if (!atomic && fb && fb != crtc->primary->fb) {
2255                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2256                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2257                 r = amdgpu_bo_reserve(rbo, false);
2258                 if (unlikely(r != 0))
2259                         return r;
2260                 amdgpu_bo_unpin(rbo);
2261                 amdgpu_bo_unreserve(rbo);
2262         }
2263
2264         /* Bytes per pixel may have changed */
2265         dce_v10_0_bandwidth_update(adev);
2266
2267         return 0;
2268 }
2269
2270 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2271                                      struct drm_display_mode *mode)
2272 {
2273         struct drm_device *dev = crtc->dev;
2274         struct amdgpu_device *adev = dev->dev_private;
2275         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2276         u32 tmp;
2277
2278         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2279         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2280                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2281         else
2282                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2283         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2284 }
2285
2286 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2287 {
2288         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2289         struct drm_device *dev = crtc->dev;
2290         struct amdgpu_device *adev = dev->dev_private;
2291         int i;
2292         u32 tmp;
2293
2294         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2295
2296         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2297         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2298         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2299         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2300
2301         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2302         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2303         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2304
2305         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2306         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2307         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2308
2309         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2310         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2311         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2312         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2313
2314         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2315
2316         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2317         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2318         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2319
2320         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2321         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2322         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2323
2324         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2325         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2326
2327         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2328         for (i = 0; i < 256; i++) {
2329                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2330                        (amdgpu_crtc->lut_r[i] << 20) |
2331                        (amdgpu_crtc->lut_g[i] << 10) |
2332                        (amdgpu_crtc->lut_b[i] << 0));
2333         }
2334
2335         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2336         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2337         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2338         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2339         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2340
2341         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2342         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2343         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2344         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2345
2346         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2347         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2348         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2349         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2350
2351         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2352         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2353         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2354         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2355
2356         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2357         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2358         /* XXX this only needs to be programmed once per crtc at startup,
2359          * not sure where the best place for it is
2360          */
2361         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2362         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2363         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2364 }
2365
2366 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2367 {
2368         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2369         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2370
2371         switch (amdgpu_encoder->encoder_id) {
2372         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2373                 if (dig->linkb)
2374                         return 1;
2375                 else
2376                         return 0;
2377                 break;
2378         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2379                 if (dig->linkb)
2380                         return 3;
2381                 else
2382                         return 2;
2383                 break;
2384         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2385                 if (dig->linkb)
2386                         return 5;
2387                 else
2388                         return 4;
2389                 break;
2390         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2391                 return 6;
2392                 break;
2393         default:
2394                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2395                 return 0;
2396         }
2397 }
2398
2399 /**
2400  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2401  *
2402  * @crtc: drm crtc
2403  *
2404  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2405  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2406  * monitors a dedicated PPLL must be used.  If a particular board has
2407  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2408  * as there is no need to program the PLL itself.  If we are not able to
2409  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2410  * avoid messing up an existing monitor.
2411  *
2412  * Asic specific PLL information
2413  *
2414  * DCE 10.x
2415  * Tonga
2416  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2417  * CI
2418  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2419  *
2420  */
2421 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2422 {
2423         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2424         struct drm_device *dev = crtc->dev;
2425         struct amdgpu_device *adev = dev->dev_private;
2426         u32 pll_in_use;
2427         int pll;
2428
2429         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2430                 if (adev->clock.dp_extclk)
2431                         /* skip PPLL programming if using ext clock */
2432                         return ATOM_PPLL_INVALID;
2433                 else {
2434                         /* use the same PPLL for all DP monitors */
2435                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2436                         if (pll != ATOM_PPLL_INVALID)
2437                                 return pll;
2438                 }
2439         } else {
2440                 /* use the same PPLL for all monitors with the same clock */
2441                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2442                 if (pll != ATOM_PPLL_INVALID)
2443                         return pll;
2444         }
2445
2446         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2447         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2448         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2449                 return ATOM_PPLL2;
2450         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2451                 return ATOM_PPLL1;
2452         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2453                 return ATOM_PPLL0;
2454         DRM_ERROR("unable to allocate a PPLL\n");
2455         return ATOM_PPLL_INVALID;
2456 }
2457
2458 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2459 {
2460         struct amdgpu_device *adev = crtc->dev->dev_private;
2461         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2462         uint32_t cur_lock;
2463
2464         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2465         if (lock)
2466                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2467         else
2468                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2469         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2470 }
2471
2472 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2473 {
2474         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2475         struct amdgpu_device *adev = crtc->dev->dev_private;
2476         u32 tmp;
2477
2478         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2479         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2480         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2481 }
2482
2483 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2484 {
2485         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2486         struct amdgpu_device *adev = crtc->dev->dev_private;
2487         u32 tmp;
2488
2489         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2490                upper_32_bits(amdgpu_crtc->cursor_addr));
2491         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2492                lower_32_bits(amdgpu_crtc->cursor_addr));
2493
2494         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2495         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2496         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2497         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2498 }
2499
2500 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2501                                         int x, int y)
2502 {
2503         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2504         struct amdgpu_device *adev = crtc->dev->dev_private;
2505         int xorigin = 0, yorigin = 0;
2506
2507         /* avivo cursor are offset into the total surface */
2508         x += crtc->x;
2509         y += crtc->y;
2510         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2511
2512         if (x < 0) {
2513                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2514                 x = 0;
2515         }
2516         if (y < 0) {
2517                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2518                 y = 0;
2519         }
2520
2521         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2522         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2523         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2524                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2525
2526         amdgpu_crtc->cursor_x = x;
2527         amdgpu_crtc->cursor_y = y;
2528
2529         return 0;
2530 }
2531
2532 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2533                                       int x, int y)
2534 {
2535         int ret;
2536
2537         dce_v10_0_lock_cursor(crtc, true);
2538         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2539         dce_v10_0_lock_cursor(crtc, false);
2540
2541         return ret;
2542 }
2543
2544 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2545                                       struct drm_file *file_priv,
2546                                       uint32_t handle,
2547                                       uint32_t width,
2548                                       uint32_t height,
2549                                       int32_t hot_x,
2550                                       int32_t hot_y)
2551 {
2552         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2553         struct drm_gem_object *obj;
2554         struct amdgpu_bo *aobj;
2555         int ret;
2556
2557         if (!handle) {
2558                 /* turn off cursor */
2559                 dce_v10_0_hide_cursor(crtc);
2560                 obj = NULL;
2561                 goto unpin;
2562         }
2563
2564         if ((width > amdgpu_crtc->max_cursor_width) ||
2565             (height > amdgpu_crtc->max_cursor_height)) {
2566                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2567                 return -EINVAL;
2568         }
2569
2570         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2571         if (!obj) {
2572                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2573                 return -ENOENT;
2574         }
2575
2576         aobj = gem_to_amdgpu_bo(obj);
2577         ret = amdgpu_bo_reserve(aobj, false);
2578         if (ret != 0) {
2579                 drm_gem_object_unreference_unlocked(obj);
2580                 return ret;
2581         }
2582
2583         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2584         amdgpu_bo_unreserve(aobj);
2585         if (ret) {
2586                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2587                 drm_gem_object_unreference_unlocked(obj);
2588                 return ret;
2589         }
2590
2591         amdgpu_crtc->cursor_width = width;
2592         amdgpu_crtc->cursor_height = height;
2593
2594         dce_v10_0_lock_cursor(crtc, true);
2595
2596         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2597             hot_y != amdgpu_crtc->cursor_hot_y) {
2598                 int x, y;
2599
2600                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2601                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2602
2603                 dce_v10_0_cursor_move_locked(crtc, x, y);
2604
2605                 amdgpu_crtc->cursor_hot_x = hot_x;
2606                 amdgpu_crtc->cursor_hot_y = hot_y;
2607         }
2608
2609         dce_v10_0_show_cursor(crtc);
2610         dce_v10_0_lock_cursor(crtc, false);
2611
2612 unpin:
2613         if (amdgpu_crtc->cursor_bo) {
2614                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2615                 ret = amdgpu_bo_reserve(aobj, false);
2616                 if (likely(ret == 0)) {
2617                         amdgpu_bo_unpin(aobj);
2618                         amdgpu_bo_unreserve(aobj);
2619                 }
2620                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2621         }
2622
2623         amdgpu_crtc->cursor_bo = obj;
2624         return 0;
2625 }
2626
2627 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2628 {
2629         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2630
2631         if (amdgpu_crtc->cursor_bo) {
2632                 dce_v10_0_lock_cursor(crtc, true);
2633
2634                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2635                                              amdgpu_crtc->cursor_y);
2636
2637                 dce_v10_0_show_cursor(crtc);
2638
2639                 dce_v10_0_lock_cursor(crtc, false);
2640         }
2641 }
2642
2643 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2644                                     u16 *blue, uint32_t start, uint32_t size)
2645 {
2646         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2647         int end = (start + size > 256) ? 256 : start + size, i;
2648
2649         /* userspace palettes are always correct as is */
2650         for (i = start; i < end; i++) {
2651                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2652                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2653                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2654         }
2655         dce_v10_0_crtc_load_lut(crtc);
2656 }
2657
2658 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2659 {
2660         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2661
2662         drm_crtc_cleanup(crtc);
2663         destroy_workqueue(amdgpu_crtc->pflip_queue);
2664         kfree(amdgpu_crtc);
2665 }
2666
2667 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2668         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2669         .cursor_move = dce_v10_0_crtc_cursor_move,
2670         .gamma_set = dce_v10_0_crtc_gamma_set,
2671         .set_config = amdgpu_crtc_set_config,
2672         .destroy = dce_v10_0_crtc_destroy,
2673         .page_flip = amdgpu_crtc_page_flip,
2674 };
2675
2676 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2677 {
2678         struct drm_device *dev = crtc->dev;
2679         struct amdgpu_device *adev = dev->dev_private;
2680         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2681         unsigned type;
2682
2683         switch (mode) {
2684         case DRM_MODE_DPMS_ON:
2685                 amdgpu_crtc->enabled = true;
2686                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2687                 dce_v10_0_vga_enable(crtc, true);
2688                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2689                 dce_v10_0_vga_enable(crtc, false);
2690                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2691                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2692                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2693                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2694                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2695                 dce_v10_0_crtc_load_lut(crtc);
2696                 break;
2697         case DRM_MODE_DPMS_STANDBY:
2698         case DRM_MODE_DPMS_SUSPEND:
2699         case DRM_MODE_DPMS_OFF:
2700                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2701                 if (amdgpu_crtc->enabled) {
2702                         dce_v10_0_vga_enable(crtc, true);
2703                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2704                         dce_v10_0_vga_enable(crtc, false);
2705                 }
2706                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2707                 amdgpu_crtc->enabled = false;
2708                 break;
2709         }
2710         /* adjust pm to dpms */
2711         amdgpu_pm_compute_clocks(adev);
2712 }
2713
2714 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2715 {
2716         /* disable crtc pair power gating before programming */
2717         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2718         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2719         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2720 }
2721
2722 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2723 {
2724         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2725         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2726 }
2727
2728 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2729 {
2730         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2731         struct drm_device *dev = crtc->dev;
2732         struct amdgpu_device *adev = dev->dev_private;
2733         struct amdgpu_atom_ss ss;
2734         int i;
2735
2736         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2737         if (crtc->primary->fb) {
2738                 int r;
2739                 struct amdgpu_framebuffer *amdgpu_fb;
2740                 struct amdgpu_bo *rbo;
2741
2742                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2743                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2744                 r = amdgpu_bo_reserve(rbo, false);
2745                 if (unlikely(r))
2746                         DRM_ERROR("failed to reserve rbo before unpin\n");
2747                 else {
2748                         amdgpu_bo_unpin(rbo);
2749                         amdgpu_bo_unreserve(rbo);
2750                 }
2751         }
2752         /* disable the GRPH */
2753         dce_v10_0_grph_enable(crtc, false);
2754
2755         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2756
2757         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2758                 if (adev->mode_info.crtcs[i] &&
2759                     adev->mode_info.crtcs[i]->enabled &&
2760                     i != amdgpu_crtc->crtc_id &&
2761                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2762                         /* one other crtc is using this pll don't turn
2763                          * off the pll
2764                          */
2765                         goto done;
2766                 }
2767         }
2768
2769         switch (amdgpu_crtc->pll_id) {
2770         case ATOM_PPLL0:
2771         case ATOM_PPLL1:
2772         case ATOM_PPLL2:
2773                 /* disable the ppll */
2774                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2775                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2776                 break;
2777         default:
2778                 break;
2779         }
2780 done:
2781         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2782         amdgpu_crtc->adjusted_clock = 0;
2783         amdgpu_crtc->encoder = NULL;
2784         amdgpu_crtc->connector = NULL;
2785 }
2786
2787 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2788                                   struct drm_display_mode *mode,
2789                                   struct drm_display_mode *adjusted_mode,
2790                                   int x, int y, struct drm_framebuffer *old_fb)
2791 {
2792         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2793
2794         if (!amdgpu_crtc->adjusted_clock)
2795                 return -EINVAL;
2796
2797         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2798         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2799         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2800         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2801         amdgpu_atombios_crtc_scaler_setup(crtc);
2802         dce_v10_0_cursor_reset(crtc);
2803         /* update the hw version fpr dpm */
2804         amdgpu_crtc->hw_mode = *adjusted_mode;
2805
2806         return 0;
2807 }
2808
2809 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2810                                      const struct drm_display_mode *mode,
2811                                      struct drm_display_mode *adjusted_mode)
2812 {
2813         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2814         struct drm_device *dev = crtc->dev;
2815         struct drm_encoder *encoder;
2816
2817         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2818         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2819                 if (encoder->crtc == crtc) {
2820                         amdgpu_crtc->encoder = encoder;
2821                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2822                         break;
2823                 }
2824         }
2825         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2826                 amdgpu_crtc->encoder = NULL;
2827                 amdgpu_crtc->connector = NULL;
2828                 return false;
2829         }
2830         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2831                 return false;
2832         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2833                 return false;
2834         /* pick pll */
2835         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2836         /* if we can't get a PPLL for a non-DP encoder, fail */
2837         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2838             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2839                 return false;
2840
2841         return true;
2842 }
2843
2844 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2845                                   struct drm_framebuffer *old_fb)
2846 {
2847         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2848 }
2849
2850 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2851                                          struct drm_framebuffer *fb,
2852                                          int x, int y, enum mode_set_atomic state)
2853 {
2854        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2855 }
2856
2857 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2858         .dpms = dce_v10_0_crtc_dpms,
2859         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2860         .mode_set = dce_v10_0_crtc_mode_set,
2861         .mode_set_base = dce_v10_0_crtc_set_base,
2862         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2863         .prepare = dce_v10_0_crtc_prepare,
2864         .commit = dce_v10_0_crtc_commit,
2865         .load_lut = dce_v10_0_crtc_load_lut,
2866         .disable = dce_v10_0_crtc_disable,
2867 };
2868
2869 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2870 {
2871         struct amdgpu_crtc *amdgpu_crtc;
2872         int i;
2873
2874         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2875                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2876         if (amdgpu_crtc == NULL)
2877                 return -ENOMEM;
2878
2879         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2880
2881         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2882         amdgpu_crtc->crtc_id = index;
2883         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2884         adev->mode_info.crtcs[index] = amdgpu_crtc;
2885
2886         amdgpu_crtc->max_cursor_width = 128;
2887         amdgpu_crtc->max_cursor_height = 128;
2888         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2889         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2890
2891         for (i = 0; i < 256; i++) {
2892                 amdgpu_crtc->lut_r[i] = i << 2;
2893                 amdgpu_crtc->lut_g[i] = i << 2;
2894                 amdgpu_crtc->lut_b[i] = i << 2;
2895         }
2896
2897         switch (amdgpu_crtc->crtc_id) {
2898         case 0:
2899         default:
2900                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2901                 break;
2902         case 1:
2903                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2904                 break;
2905         case 2:
2906                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2907                 break;
2908         case 3:
2909                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2910                 break;
2911         case 4:
2912                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2913                 break;
2914         case 5:
2915                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2916                 break;
2917         }
2918
2919         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2920         amdgpu_crtc->adjusted_clock = 0;
2921         amdgpu_crtc->encoder = NULL;
2922         amdgpu_crtc->connector = NULL;
2923         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2924
2925         return 0;
2926 }
2927
2928 static int dce_v10_0_early_init(void *handle)
2929 {
2930         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2931
2932         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2933         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2934
2935         dce_v10_0_set_display_funcs(adev);
2936         dce_v10_0_set_irq_funcs(adev);
2937
2938         switch (adev->asic_type) {
2939         case CHIP_FIJI:
2940         case CHIP_TONGA:
2941                 adev->mode_info.num_crtc = 6; /* XXX 7??? */
2942                 adev->mode_info.num_hpd = 6;
2943                 adev->mode_info.num_dig = 7;
2944                 break;
2945         default:
2946                 /* FIXME: not supported yet */
2947                 return -EINVAL;
2948         }
2949
2950         return 0;
2951 }
2952
2953 static int dce_v10_0_sw_init(void *handle)
2954 {
2955         int r, i;
2956         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2957
2958         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2959                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2960                 if (r)
2961                         return r;
2962         }
2963
2964         for (i = 8; i < 20; i += 2) {
2965                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2966                 if (r)
2967                         return r;
2968         }
2969
2970         /* HPD hotplug */
2971         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2972         if (r)
2973                 return r;
2974
2975         adev->mode_info.mode_config_initialized = true;
2976
2977         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2978
2979         adev->ddev->mode_config.max_width = 16384;
2980         adev->ddev->mode_config.max_height = 16384;
2981
2982         adev->ddev->mode_config.preferred_depth = 24;
2983         adev->ddev->mode_config.prefer_shadow = 1;
2984
2985         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2986
2987         r = amdgpu_modeset_create_props(adev);
2988         if (r)
2989                 return r;
2990
2991         adev->ddev->mode_config.max_width = 16384;
2992         adev->ddev->mode_config.max_height = 16384;
2993
2994         /* allocate crtcs */
2995         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2996                 r = dce_v10_0_crtc_init(adev, i);
2997                 if (r)
2998                         return r;
2999         }
3000
3001         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3002                 amdgpu_print_display_setup(adev->ddev);
3003         else
3004                 return -EINVAL;
3005
3006         /* setup afmt */
3007         dce_v10_0_afmt_init(adev);
3008
3009         r = dce_v10_0_audio_init(adev);
3010         if (r)
3011                 return r;
3012
3013         drm_kms_helper_poll_init(adev->ddev);
3014
3015         return r;
3016 }
3017
3018 static int dce_v10_0_sw_fini(void *handle)
3019 {
3020         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3021
3022         kfree(adev->mode_info.bios_hardcoded_edid);
3023
3024         drm_kms_helper_poll_fini(adev->ddev);
3025
3026         dce_v10_0_audio_fini(adev);
3027
3028         dce_v10_0_afmt_fini(adev);
3029
3030         drm_mode_config_cleanup(adev->ddev);
3031         adev->mode_info.mode_config_initialized = false;
3032
3033         return 0;
3034 }
3035
3036 static int dce_v10_0_hw_init(void *handle)
3037 {
3038         int i;
3039         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3040
3041         dce_v10_0_init_golden_registers(adev);
3042
3043         /* init dig PHYs, disp eng pll */
3044         amdgpu_atombios_encoder_init_dig(adev);
3045         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3046
3047         /* initialize hpd */
3048         dce_v10_0_hpd_init(adev);
3049
3050         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3051                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3052         }
3053
3054         dce_v10_0_pageflip_interrupt_init(adev);
3055
3056         return 0;
3057 }
3058
3059 static int dce_v10_0_hw_fini(void *handle)
3060 {
3061         int i;
3062         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3063
3064         dce_v10_0_hpd_fini(adev);
3065
3066         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3067                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3068         }
3069
3070         dce_v10_0_pageflip_interrupt_fini(adev);
3071
3072         return 0;
3073 }
3074
3075 static int dce_v10_0_suspend(void *handle)
3076 {
3077         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3078
3079         amdgpu_atombios_scratch_regs_save(adev);
3080
3081         return dce_v10_0_hw_fini(handle);
3082 }
3083
3084 static int dce_v10_0_resume(void *handle)
3085 {
3086         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3087         int ret;
3088
3089         ret = dce_v10_0_hw_init(handle);
3090
3091         amdgpu_atombios_scratch_regs_restore(adev);
3092
3093         /* turn on the BL */
3094         if (adev->mode_info.bl_encoder) {
3095                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3096                                                                   adev->mode_info.bl_encoder);
3097                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3098                                                     bl_level);
3099         }
3100
3101         return ret;
3102 }
3103
3104 static bool dce_v10_0_is_idle(void *handle)
3105 {
3106         return true;
3107 }
3108
3109 static int dce_v10_0_wait_for_idle(void *handle)
3110 {
3111         return 0;
3112 }
3113
3114 static void dce_v10_0_print_status(void *handle)
3115 {
3116         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3117
3118         dev_info(adev->dev, "DCE 10.x registers\n");
3119         /* XXX todo */
3120 }
3121
3122 static int dce_v10_0_soft_reset(void *handle)
3123 {
3124         u32 srbm_soft_reset = 0, tmp;
3125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3126
3127         if (dce_v10_0_is_display_hung(adev))
3128                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3129
3130         if (srbm_soft_reset) {
3131                 dce_v10_0_print_status((void *)adev);
3132
3133                 tmp = RREG32(mmSRBM_SOFT_RESET);
3134                 tmp |= srbm_soft_reset;
3135                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3136                 WREG32(mmSRBM_SOFT_RESET, tmp);
3137                 tmp = RREG32(mmSRBM_SOFT_RESET);
3138
3139                 udelay(50);
3140
3141                 tmp &= ~srbm_soft_reset;
3142                 WREG32(mmSRBM_SOFT_RESET, tmp);
3143                 tmp = RREG32(mmSRBM_SOFT_RESET);
3144
3145                 /* Wait a little for things to settle down */
3146                 udelay(50);
3147                 dce_v10_0_print_status((void *)adev);
3148         }
3149         return 0;
3150 }
3151
3152 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3153                                                      int crtc,
3154                                                      enum amdgpu_interrupt_state state)
3155 {
3156         u32 lb_interrupt_mask;
3157
3158         if (crtc >= adev->mode_info.num_crtc) {
3159                 DRM_DEBUG("invalid crtc %d\n", crtc);
3160                 return;
3161         }
3162
3163         switch (state) {
3164         case AMDGPU_IRQ_STATE_DISABLE:
3165                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3166                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3167                                                   VBLANK_INTERRUPT_MASK, 0);
3168                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3169                 break;
3170         case AMDGPU_IRQ_STATE_ENABLE:
3171                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3172                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3173                                                   VBLANK_INTERRUPT_MASK, 1);
3174                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3175                 break;
3176         default:
3177                 break;
3178         }
3179 }
3180
3181 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3182                                                     int crtc,
3183                                                     enum amdgpu_interrupt_state state)
3184 {
3185         u32 lb_interrupt_mask;
3186
3187         if (crtc >= adev->mode_info.num_crtc) {
3188                 DRM_DEBUG("invalid crtc %d\n", crtc);
3189                 return;
3190         }
3191
3192         switch (state) {
3193         case AMDGPU_IRQ_STATE_DISABLE:
3194                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3195                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3196                                                   VLINE_INTERRUPT_MASK, 0);
3197                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3198                 break;
3199         case AMDGPU_IRQ_STATE_ENABLE:
3200                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3201                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3202                                                   VLINE_INTERRUPT_MASK, 1);
3203                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3204                 break;
3205         default:
3206                 break;
3207         }
3208 }
3209
3210 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3211                                        struct amdgpu_irq_src *source,
3212                                        unsigned hpd,
3213                                        enum amdgpu_interrupt_state state)
3214 {
3215         u32 tmp;
3216
3217         if (hpd >= adev->mode_info.num_hpd) {
3218                 DRM_DEBUG("invalid hdp %d\n", hpd);
3219                 return 0;
3220         }
3221
3222         switch (state) {
3223         case AMDGPU_IRQ_STATE_DISABLE:
3224                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3225                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3226                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3227                 break;
3228         case AMDGPU_IRQ_STATE_ENABLE:
3229                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3230                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3231                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3232                 break;
3233         default:
3234                 break;
3235         }
3236
3237         return 0;
3238 }
3239
3240 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3241                                         struct amdgpu_irq_src *source,
3242                                         unsigned type,
3243                                         enum amdgpu_interrupt_state state)
3244 {
3245         switch (type) {
3246         case AMDGPU_CRTC_IRQ_VBLANK1:
3247                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3248                 break;
3249         case AMDGPU_CRTC_IRQ_VBLANK2:
3250                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3251                 break;
3252         case AMDGPU_CRTC_IRQ_VBLANK3:
3253                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3254                 break;
3255         case AMDGPU_CRTC_IRQ_VBLANK4:
3256                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3257                 break;
3258         case AMDGPU_CRTC_IRQ_VBLANK5:
3259                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3260                 break;
3261         case AMDGPU_CRTC_IRQ_VBLANK6:
3262                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3263                 break;
3264         case AMDGPU_CRTC_IRQ_VLINE1:
3265                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3266                 break;
3267         case AMDGPU_CRTC_IRQ_VLINE2:
3268                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3269                 break;
3270         case AMDGPU_CRTC_IRQ_VLINE3:
3271                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3272                 break;
3273         case AMDGPU_CRTC_IRQ_VLINE4:
3274                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3275                 break;
3276         case AMDGPU_CRTC_IRQ_VLINE5:
3277                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3278                 break;
3279         case AMDGPU_CRTC_IRQ_VLINE6:
3280                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3281                 break;
3282         default:
3283                 break;
3284         }
3285         return 0;
3286 }
3287
3288 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3289                                             struct amdgpu_irq_src *src,
3290                                             unsigned type,
3291                                             enum amdgpu_interrupt_state state)
3292 {
3293         u32 reg;
3294
3295         if (type >= adev->mode_info.num_crtc) {
3296                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3297                 return -EINVAL;
3298         }
3299
3300         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3301         if (state == AMDGPU_IRQ_STATE_DISABLE)
3302                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3303                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3304         else
3305                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3306                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3307
3308         return 0;
3309 }
3310
3311 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3312                                   struct amdgpu_irq_src *source,
3313                                   struct amdgpu_iv_entry *entry)
3314 {
3315         unsigned long flags;
3316         unsigned crtc_id;
3317         struct amdgpu_crtc *amdgpu_crtc;
3318         struct amdgpu_flip_work *works;
3319
3320         crtc_id = (entry->src_id - 8) >> 1;
3321         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3322
3323         if (crtc_id >= adev->mode_info.num_crtc) {
3324                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3325                 return -EINVAL;
3326         }
3327
3328         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3329             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3330                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3331                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3332
3333         /* IRQ could occur when in initial stage */
3334         if (amdgpu_crtc == NULL)
3335                 return 0;
3336
3337         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3338         works = amdgpu_crtc->pflip_works;
3339         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3340                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3341                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3342                                                  amdgpu_crtc->pflip_status,
3343                                                  AMDGPU_FLIP_SUBMITTED);
3344                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3345                 return 0;
3346         }
3347
3348         /* page flip completed. clean up */
3349         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3350         amdgpu_crtc->pflip_works = NULL;
3351
3352         /* wakeup usersapce */
3353         if (works->event)
3354                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3355
3356         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3357
3358         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3359         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3360
3361         return 0;
3362 }
3363
3364 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3365                                   int hpd)
3366 {
3367         u32 tmp;
3368
3369         if (hpd >= adev->mode_info.num_hpd) {
3370                 DRM_DEBUG("invalid hdp %d\n", hpd);
3371                 return;
3372         }
3373
3374         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3375         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3376         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3377 }
3378
3379 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3380                                           int crtc)
3381 {
3382         u32 tmp;
3383
3384         if (crtc >= adev->mode_info.num_crtc) {
3385                 DRM_DEBUG("invalid crtc %d\n", crtc);
3386                 return;
3387         }
3388
3389         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3390         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3391         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3392 }
3393
3394 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3395                                          int crtc)
3396 {
3397         u32 tmp;
3398
3399         if (crtc >= adev->mode_info.num_crtc) {
3400                 DRM_DEBUG("invalid crtc %d\n", crtc);
3401                 return;
3402         }
3403
3404         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3405         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3406         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3407 }
3408
3409 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3410                               struct amdgpu_irq_src *source,
3411                               struct amdgpu_iv_entry *entry)
3412 {
3413         unsigned crtc = entry->src_id - 1;
3414         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3415         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3416
3417         switch (entry->src_data) {
3418         case 0: /* vblank */
3419                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3420                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3421                 else
3422                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3423
3424                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3425                         drm_handle_vblank(adev->ddev, crtc);
3426                 }
3427                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3428
3429                 break;
3430         case 1: /* vline */
3431                 if (disp_int & interrupt_status_offsets[crtc].vline)
3432                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3433                 else
3434                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3435
3436                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3437
3438                 break;
3439         default:
3440                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3441                 break;
3442         }
3443
3444         return 0;
3445 }
3446
3447 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3448                              struct amdgpu_irq_src *source,
3449                              struct amdgpu_iv_entry *entry)
3450 {
3451         uint32_t disp_int, mask;
3452         unsigned hpd;
3453
3454         if (entry->src_data >= adev->mode_info.num_hpd) {
3455                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3456                 return 0;
3457         }
3458
3459         hpd = entry->src_data;
3460         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3461         mask = interrupt_status_offsets[hpd].hpd;
3462
3463         if (disp_int & mask) {
3464                 dce_v10_0_hpd_int_ack(adev, hpd);
3465                 schedule_work(&adev->hotplug_work);
3466                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3467         }
3468
3469         return 0;
3470 }
3471
3472 static int dce_v10_0_set_clockgating_state(void *handle,
3473                                           enum amd_clockgating_state state)
3474 {
3475         return 0;
3476 }
3477
3478 static int dce_v10_0_set_powergating_state(void *handle,
3479                                           enum amd_powergating_state state)
3480 {
3481         return 0;
3482 }
3483
3484 const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3485         .early_init = dce_v10_0_early_init,
3486         .late_init = NULL,
3487         .sw_init = dce_v10_0_sw_init,
3488         .sw_fini = dce_v10_0_sw_fini,
3489         .hw_init = dce_v10_0_hw_init,
3490         .hw_fini = dce_v10_0_hw_fini,
3491         .suspend = dce_v10_0_suspend,
3492         .resume = dce_v10_0_resume,
3493         .is_idle = dce_v10_0_is_idle,
3494         .wait_for_idle = dce_v10_0_wait_for_idle,
3495         .soft_reset = dce_v10_0_soft_reset,
3496         .print_status = dce_v10_0_print_status,
3497         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3498         .set_powergating_state = dce_v10_0_set_powergating_state,
3499 };
3500
3501 static void
3502 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3503                           struct drm_display_mode *mode,
3504                           struct drm_display_mode *adjusted_mode)
3505 {
3506         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3507
3508         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3509
3510         /* need to call this here rather than in prepare() since we need some crtc info */
3511         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3512
3513         /* set scaler clears this on some chips */
3514         dce_v10_0_set_interleave(encoder->crtc, mode);
3515
3516         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3517                 dce_v10_0_afmt_enable(encoder, true);
3518                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3519         }
3520 }
3521
3522 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3523 {
3524         struct amdgpu_device *adev = encoder->dev->dev_private;
3525         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3526         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3527
3528         if ((amdgpu_encoder->active_device &
3529              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3530             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3531              ENCODER_OBJECT_ID_NONE)) {
3532                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3533                 if (dig) {
3534                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3535                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3536                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3537                 }
3538         }
3539
3540         amdgpu_atombios_scratch_regs_lock(adev, true);
3541
3542         if (connector) {
3543                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3544
3545                 /* select the clock/data port if it uses a router */
3546                 if (amdgpu_connector->router.cd_valid)
3547                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3548
3549                 /* turn eDP panel on for mode set */
3550                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3551                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3552                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3553         }
3554
3555         /* this is needed for the pll/ss setup to work correctly in some cases */
3556         amdgpu_atombios_encoder_set_crtc_source(encoder);
3557         /* set up the FMT blocks */
3558         dce_v10_0_program_fmt(encoder);
3559 }
3560
3561 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3562 {
3563         struct drm_device *dev = encoder->dev;
3564         struct amdgpu_device *adev = dev->dev_private;
3565
3566         /* need to call this here as we need the crtc set up */
3567         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3568         amdgpu_atombios_scratch_regs_lock(adev, false);
3569 }
3570
3571 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3572 {
3573         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3574         struct amdgpu_encoder_atom_dig *dig;
3575
3576         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3577
3578         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3579                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3580                         dce_v10_0_afmt_enable(encoder, false);
3581                 dig = amdgpu_encoder->enc_priv;
3582                 dig->dig_encoder = -1;
3583         }
3584         amdgpu_encoder->active_device = 0;
3585 }
3586
3587 /* these are handled by the primary encoders */
3588 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3589 {
3590
3591 }
3592
3593 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3594 {
3595
3596 }
3597
3598 static void
3599 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3600                       struct drm_display_mode *mode,
3601                       struct drm_display_mode *adjusted_mode)
3602 {
3603
3604 }
3605
3606 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3607 {
3608
3609 }
3610
3611 static void
3612 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3613 {
3614
3615 }
3616
3617 static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder,
3618                                     const struct drm_display_mode *mode,
3619                                     struct drm_display_mode *adjusted_mode)
3620 {
3621         return true;
3622 }
3623
3624 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3625         .dpms = dce_v10_0_ext_dpms,
3626         .mode_fixup = dce_v10_0_ext_mode_fixup,
3627         .prepare = dce_v10_0_ext_prepare,
3628         .mode_set = dce_v10_0_ext_mode_set,
3629         .commit = dce_v10_0_ext_commit,
3630         .disable = dce_v10_0_ext_disable,
3631         /* no detect for TMDS/LVDS yet */
3632 };
3633
3634 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3635         .dpms = amdgpu_atombios_encoder_dpms,
3636         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3637         .prepare = dce_v10_0_encoder_prepare,
3638         .mode_set = dce_v10_0_encoder_mode_set,
3639         .commit = dce_v10_0_encoder_commit,
3640         .disable = dce_v10_0_encoder_disable,
3641         .detect = amdgpu_atombios_encoder_dig_detect,
3642 };
3643
3644 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3645         .dpms = amdgpu_atombios_encoder_dpms,
3646         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3647         .prepare = dce_v10_0_encoder_prepare,
3648         .mode_set = dce_v10_0_encoder_mode_set,
3649         .commit = dce_v10_0_encoder_commit,
3650         .detect = amdgpu_atombios_encoder_dac_detect,
3651 };
3652
3653 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3654 {
3655         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3656         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3657                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3658         kfree(amdgpu_encoder->enc_priv);
3659         drm_encoder_cleanup(encoder);
3660         kfree(amdgpu_encoder);
3661 }
3662
3663 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3664         .destroy = dce_v10_0_encoder_destroy,
3665 };
3666
3667 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3668                                  uint32_t encoder_enum,
3669                                  uint32_t supported_device,
3670                                  u16 caps)
3671 {
3672         struct drm_device *dev = adev->ddev;
3673         struct drm_encoder *encoder;
3674         struct amdgpu_encoder *amdgpu_encoder;
3675
3676         /* see if we already added it */
3677         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3678                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3679                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3680                         amdgpu_encoder->devices |= supported_device;
3681                         return;
3682                 }
3683
3684         }
3685
3686         /* add a new one */
3687         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3688         if (!amdgpu_encoder)
3689                 return;
3690
3691         encoder = &amdgpu_encoder->base;
3692         switch (adev->mode_info.num_crtc) {
3693         case 1:
3694                 encoder->possible_crtcs = 0x1;
3695                 break;
3696         case 2:
3697         default:
3698                 encoder->possible_crtcs = 0x3;
3699                 break;
3700         case 4:
3701                 encoder->possible_crtcs = 0xf;
3702                 break;
3703         case 6:
3704                 encoder->possible_crtcs = 0x3f;
3705                 break;
3706         }
3707
3708         amdgpu_encoder->enc_priv = NULL;
3709
3710         amdgpu_encoder->encoder_enum = encoder_enum;
3711         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3712         amdgpu_encoder->devices = supported_device;
3713         amdgpu_encoder->rmx_type = RMX_OFF;
3714         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3715         amdgpu_encoder->is_ext_encoder = false;
3716         amdgpu_encoder->caps = caps;
3717
3718         switch (amdgpu_encoder->encoder_id) {
3719         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3720         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3721                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3722                                  DRM_MODE_ENCODER_DAC);
3723                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3724                 break;
3725         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3726         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3727         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3728         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3729         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3730                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3731                         amdgpu_encoder->rmx_type = RMX_FULL;
3732                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3733                                          DRM_MODE_ENCODER_LVDS);
3734                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3735                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3736                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3737                                          DRM_MODE_ENCODER_DAC);
3738                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3739                 } else {
3740                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3741                                          DRM_MODE_ENCODER_TMDS);
3742                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3743                 }
3744                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3745                 break;
3746         case ENCODER_OBJECT_ID_SI170B:
3747         case ENCODER_OBJECT_ID_CH7303:
3748         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3749         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3750         case ENCODER_OBJECT_ID_TITFP513:
3751         case ENCODER_OBJECT_ID_VT1623:
3752         case ENCODER_OBJECT_ID_HDMI_SI1930:
3753         case ENCODER_OBJECT_ID_TRAVIS:
3754         case ENCODER_OBJECT_ID_NUTMEG:
3755                 /* these are handled by the primary encoders */
3756                 amdgpu_encoder->is_ext_encoder = true;
3757                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3758                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3759                                          DRM_MODE_ENCODER_LVDS);
3760                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3761                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3762                                          DRM_MODE_ENCODER_DAC);
3763                 else
3764                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3765                                          DRM_MODE_ENCODER_TMDS);
3766                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3767                 break;
3768         }
3769 }
3770
3771 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3772         .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3773         .bandwidth_update = &dce_v10_0_bandwidth_update,
3774         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3775         .vblank_wait = &dce_v10_0_vblank_wait,
3776         .is_display_hung = &dce_v10_0_is_display_hung,
3777         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3778         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3779         .hpd_sense = &dce_v10_0_hpd_sense,
3780         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3781         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3782         .page_flip = &dce_v10_0_page_flip,
3783         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3784         .add_encoder = &dce_v10_0_encoder_add,
3785         .add_connector = &amdgpu_connector_add,
3786         .stop_mc_access = &dce_v10_0_stop_mc_access,
3787         .resume_mc_access = &dce_v10_0_resume_mc_access,
3788 };
3789
3790 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3791 {
3792         if (adev->mode_info.funcs == NULL)
3793                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3794 }
3795
3796 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3797         .set = dce_v10_0_set_crtc_irq_state,
3798         .process = dce_v10_0_crtc_irq,
3799 };
3800
3801 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3802         .set = dce_v10_0_set_pageflip_irq_state,
3803         .process = dce_v10_0_pageflip_irq,
3804 };
3805
3806 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3807         .set = dce_v10_0_set_hpd_irq_state,
3808         .process = dce_v10_0_hpd_irq,
3809 };
3810
3811 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3812 {
3813         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3814         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3815
3816         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3817         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3818
3819         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3820         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3821 }