drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34 #include "dce_v10_0.h"
  35
  36 #include "dce/dce_10_0_d.h"
  37 #include "dce/dce_10_0_sh_mask.h"
  38 #include "dce/dce_10_0_enum.h"
  39 #include "oss/oss_3_0_d.h"
  40 #include "oss/oss_3_0_sh_mask.h"
  41 #include "gmc/gmc_8_1_d.h"
  42 #include "gmc/gmc_8_1_sh_mask.h"
  43
  44 #include "ivsrcid/ivsrcid_vislands30.h"
  45
  46 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  47 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  48
  49 static const u32 crtc_offsets[] =
  50 {
  51         CRTC0_REGISTER_OFFSET,
  52         CRTC1_REGISTER_OFFSET,
  53         CRTC2_REGISTER_OFFSET,
  54         CRTC3_REGISTER_OFFSET,
  55         CRTC4_REGISTER_OFFSET,
  56         CRTC5_REGISTER_OFFSET,
  57         CRTC6_REGISTER_OFFSET
  58 };
  59
  60 static const u32 hpd_offsets[] =
  61 {
  62         HPD0_REGISTER_OFFSET,
  63         HPD1_REGISTER_OFFSET,
  64         HPD2_REGISTER_OFFSET,
  65         HPD3_REGISTER_OFFSET,
  66         HPD4_REGISTER_OFFSET,
  67         HPD5_REGISTER_OFFSET
  68 };
  69
  70 static const uint32_t dig_offsets[] = {
  71         DIG0_REGISTER_OFFSET,
  72         DIG1_REGISTER_OFFSET,
  73         DIG2_REGISTER_OFFSET,
  74         DIG3_REGISTER_OFFSET,
  75         DIG4_REGISTER_OFFSET,
  76         DIG5_REGISTER_OFFSET,
  77         DIG6_REGISTER_OFFSET
  78 };
  79
  80 static const struct {
  81         uint32_t        reg;
  82         uint32_t        vblank;
  83         uint32_t        vline;
  84         uint32_t        hpd;
  85
  86 } interrupt_status_offsets[] = { {
  87         .reg = mmDISP_INTERRUPT_STATUS,
  88         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  89         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  90         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  91 }, {
  92         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  93         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  94         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  95         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  96 }, {
  97         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  98         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  99         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 100         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 101 }, {
 102         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 103         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 104         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 105         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 106 }, {
 107         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 108         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 109         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 110         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 111 }, {
 112         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 113         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 114         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 115         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 116 } };
 117
 118 static const u32 golden_settings_tonga_a11[] =
 119 {
 120         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 121         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 122         mmFBC_MISC, 0x1f311fff, 0x12300000,
 123         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 124 };
 125
 126 static const u32 tonga_mgcg_cgcg_init[] =
 127 {
 128         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 129         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 130 };
 131
 132 static const u32 golden_settings_fiji_a10[] =
 133 {
 134         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 135         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 136         mmFBC_MISC, 0x1f311fff, 0x12300000,
 137         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 138 };
 139
 140 static const u32 fiji_mgcg_cgcg_init[] =
 141 {
 142         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 143         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 144 };
 145
 146 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 147 {
 148         switch (adev->asic_type) {
 149         case CHIP_FIJI:
 150                 amdgpu_device_program_register_sequence(adev,
 151                                                         fiji_mgcg_cgcg_init,
 152                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 153                 amdgpu_device_program_register_sequence(adev,
 154                                                         golden_settings_fiji_a10,
 155                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 156                 break;
 157         case CHIP_TONGA:
 158                 amdgpu_device_program_register_sequence(adev,
 159                                                         tonga_mgcg_cgcg_init,
 160                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 161                 amdgpu_device_program_register_sequence(adev,
 162                                                         golden_settings_tonga_a11,
 163                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 164                 break;
 165         default:
 166                 break;
 167         }
 168 }
 169
 170 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 171                                      u32 block_offset, u32 reg)
 172 {
 173         unsigned long flags;
 174         u32 r;
 175
 176         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 177         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 178         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 179         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 180
 181         return r;
 182 }
 183
 184 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 185                                       u32 block_offset, u32 reg, u32 v)
 186 {
 187         unsigned long flags;
 188
 189         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 190         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 191         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 192         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 193 }
 194
 195 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 196 {
 197         if (crtc >= adev->mode_info.num_crtc)
 198                 return 0;
 199         else
 200                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 201 }
 202
 203 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 204 {
 205         unsigned i;
 206
 207         /* Enable pflip interrupts */
 208         for (i = 0; i < adev->mode_info.num_crtc; i++)
 209                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 210 }
 211
 212 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 213 {
 214         unsigned i;
 215
 216         /* Disable pflip interrupts */
 217         for (i = 0; i < adev->mode_info.num_crtc; i++)
 218                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 219 }
 220
 221 /**
 222  * dce_v10_0_page_flip - pageflip callback.
 223  *
 224  * @adev: amdgpu_device pointer
 225  * @crtc_id: crtc to cleanup pageflip on
 226  * @crtc_base: new address of the crtc (GPU MC address)
 227  *
 228  * Triggers the actual pageflip by updating the primary
 229  * surface base address.
 230  */
 231 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 232                                 int crtc_id, u64 crtc_base, bool async)
 233 {
 234         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 235         u32 tmp;
 236
 237         /* flip at hsync for async, default is vsync */
 238         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 239         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 240                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
 241         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 242         /* update the primary scanout address */
 243         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 244                upper_32_bits(crtc_base));
 245         /* writing to the low address triggers the update */
 246         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 247                lower_32_bits(crtc_base));
 248         /* post the write */
 249         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 250 }
 251
 252 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 253                                         u32 *vbl, u32 *position)
 254 {
 255         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 256                 return -EINVAL;
 257
 258         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 259         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 260
 261         return 0;
 262 }
 263
 264 /**
 265  * dce_v10_0_hpd_sense - hpd sense callback.
 266  *
 267  * @adev: amdgpu_device pointer
 268  * @hpd: hpd (hotplug detect) pin
 269  *
 270  * Checks if a digital monitor is connected (evergreen+).
 271  * Returns true if connected, false if not connected.
 272  */
 273 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 274                                enum amdgpu_hpd_id hpd)
 275 {
 276         bool connected = false;
 277
 278         if (hpd >= adev->mode_info.num_hpd)
 279                 return connected;
 280
 281         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
 282             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 283                 connected = true;
 284
 285         return connected;
 286 }
 287
 288 /**
 289  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 290  *
 291  * @adev: amdgpu_device pointer
 292  * @hpd: hpd (hotplug detect) pin
 293  *
 294  * Set the polarity of the hpd pin (evergreen+).
 295  */
 296 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 297                                       enum amdgpu_hpd_id hpd)
 298 {
 299         u32 tmp;
 300         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 301
 302         if (hpd >= adev->mode_info.num_hpd)
 303                 return;
 304
 305         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
 306         if (connected)
 307                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 308         else
 309                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 310         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
 311 }
 312
 313 /**
 314  * dce_v10_0_hpd_init - hpd setup callback.
 315  *
 316  * @adev: amdgpu_device pointer
 317  *
 318  * Setup the hpd pins used by the card (evergreen+).
 319  * Enable the pin, set the polarity, and enable the hpd interrupts.
 320  */
 321 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 322 {
 323         struct drm_device *dev = adev->ddev;
 324         struct drm_connector *connector;
 325         u32 tmp;
 326
 327         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 328                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 329
 330                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 331                         continue;
 332
 333                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 334                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 335                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 336                          * aux dp channel on imac and help (but not completely fix)
 337                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 338                          * also avoid interrupt storms during dpms.
 339                          */
 340                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 341                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 342                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 343                         continue;
 344                 }
 345
 346                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 347                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 348                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 349
 350                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 351                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 352                                     DC_HPD_CONNECT_INT_DELAY,
 353                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 354                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 355                                     DC_HPD_DISCONNECT_INT_DELAY,
 356                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 357                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 358
 359                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 360                 amdgpu_irq_get(adev, &adev->hpd_irq,
 361                                amdgpu_connector->hpd.hpd);
 362         }
 363 }
 364
 365 /**
 366  * dce_v10_0_hpd_fini - hpd tear down callback.
 367  *
 368  * @adev: amdgpu_device pointer
 369  *
 370  * Tear down the hpd pins used by the card (evergreen+).
 371  * Disable the hpd interrupts.
 372  */
 373 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 374 {
 375         struct drm_device *dev = adev->ddev;
 376         struct drm_connector *connector;
 377         u32 tmp;
 378
 379         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 380                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 381
 382                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 383                         continue;
 384
 385                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 386                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 387                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 388
 389                 amdgpu_irq_put(adev, &adev->hpd_irq,
 390                                amdgpu_connector->hpd.hpd);
 391         }
 392 }
 393
 394 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 395 {
 396         return mmDC_GPIO_HPD_A;
 397 }
 398
 399 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 400 {
 401         u32 crtc_hung = 0;
 402         u32 crtc_status[6];
 403         u32 i, j, tmp;
 404
 405         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 406                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 407                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 408                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 409                         crtc_hung |= (1 << i);
 410                 }
 411         }
 412
 413         for (j = 0; j < 10; j++) {
 414                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 415                         if (crtc_hung & (1 << i)) {
 416                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 417                                 if (tmp != crtc_status[i])
 418                                         crtc_hung &= ~(1 << i);
 419                         }
 420                 }
 421                 if (crtc_hung == 0)
 422                         return false;
 423                 udelay(100);
 424         }
 425
 426         return true;
 427 }
 428
 429 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 430                                            bool render)
 431 {
 432         u32 tmp;
 433
 434         /* Lockout access through VGA aperture*/
 435         tmp = RREG32(mmVGA_HDP_CONTROL);
 436         if (render)
 437                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 438         else
 439                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 440         WREG32(mmVGA_HDP_CONTROL, tmp);
 441
 442         /* disable VGA render */
 443         tmp = RREG32(mmVGA_RENDER_CONTROL);
 444         if (render)
 445                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 446         else
 447                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 448         WREG32(mmVGA_RENDER_CONTROL, tmp);
 449 }
 450
 451 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
 452 {
 453         int num_crtc = 0;
 454
 455         switch (adev->asic_type) {
 456         case CHIP_FIJI:
 457         case CHIP_TONGA:
 458                 num_crtc = 6;
 459                 break;
 460         default:
 461                 num_crtc = 0;
 462         }
 463         return num_crtc;
 464 }
 465
 466 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
 467 {
 468         /*Disable VGA render and enabled crtc, if has DCE engine*/
 469         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 470                 u32 tmp;
 471                 int crtc_enabled, i;
 472
 473                 dce_v10_0_set_vga_render_state(adev, false);
 474
 475                 /*Disable crtc*/
 476                 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
 477                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 478                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 479                         if (crtc_enabled) {
 480                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 481                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 482                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 483                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 484                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 485                         }
 486                 }
 487         }
 488 }
 489
 490 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 491 {
 492         struct drm_device *dev = encoder->dev;
 493         struct amdgpu_device *adev = dev->dev_private;
 494         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 495         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 496         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 497         int bpc = 0;
 498         u32 tmp = 0;
 499         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 500
 501         if (connector) {
 502                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 503                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 504                 dither = amdgpu_connector->dither;
 505         }
 506
 507         /* LVDS/eDP FMT is set up by atom */
 508         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 509                 return;
 510
 511         /* not needed for analog */
 512         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 513             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 514                 return;
 515
 516         if (bpc == 0)
 517                 return;
 518
 519         switch (bpc) {
 520         case 6:
 521                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 522                         /* XXX sort out optimal dither settings */
 523                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 524                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 525                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 526                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 527                 } else {
 528                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 529                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 530                 }
 531                 break;
 532         case 8:
 533                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 534                         /* XXX sort out optimal dither settings */
 535                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 536                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 537                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 538                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 539                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 540                 } else {
 541                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 542                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 543                 }
 544                 break;
 545         case 10:
 546                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 547                         /* XXX sort out optimal dither settings */
 548                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 549                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 550                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 551                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 552                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 553                 } else {
 554                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 555                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 556                 }
 557                 break;
 558         default:
 559                 /* not needed */
 560                 break;
 561         }
 562
 563         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 564 }
 565
 566
 567 /* display watermark setup */
 568 /**
 569  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 570  *
 571  * @adev: amdgpu_device pointer
 572  * @amdgpu_crtc: the selected display controller
 573  * @mode: the current display mode on the selected display
 574  * controller
 575  *
 576  * Setup up the line buffer allocation for
 577  * the selected display controller (CIK).
 578  * Returns the line buffer size in pixels.
 579  */
 580 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 581                                        struct amdgpu_crtc *amdgpu_crtc,
 582                                        struct drm_display_mode *mode)
 583 {
 584         u32 tmp, buffer_alloc, i, mem_cfg;
 585         u32 pipe_offset = amdgpu_crtc->crtc_id;
 586         /*
 587          * Line Buffer Setup
 588          * There are 6 line buffers, one for each display controllers.
 589          * There are 3 partitions per LB. Select the number of partitions
 590          * to enable based on the display width.  For display widths larger
 591          * than 4096, you need use to use 2 display controllers and combine
 592          * them using the stereo blender.
 593          */
 594         if (amdgpu_crtc->base.enabled && mode) {
 595                 if (mode->crtc_hdisplay < 1920) {
 596                         mem_cfg = 1;
 597                         buffer_alloc = 2;
 598                 } else if (mode->crtc_hdisplay < 2560) {
 599                         mem_cfg = 2;
 600                         buffer_alloc = 2;
 601                 } else if (mode->crtc_hdisplay < 4096) {
 602                         mem_cfg = 0;
 603                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 604                 } else {
 605                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 606                         mem_cfg = 0;
 607                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 608                 }
 609         } else {
 610                 mem_cfg = 1;
 611                 buffer_alloc = 0;
 612         }
 613
 614         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 615         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 616         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 617
 618         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 619         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 620         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 621
 622         for (i = 0; i < adev->usec_timeout; i++) {
 623                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 624                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 625                         break;
 626                 udelay(1);
 627         }
 628
 629         if (amdgpu_crtc->base.enabled && mode) {
 630                 switch (mem_cfg) {
 631                 case 0:
 632                 default:
 633                         return 4096 * 2;
 634                 case 1:
 635                         return 1920 * 2;
 636                 case 2:
 637                         return 2560 * 2;
 638                 }
 639         }
 640
 641         /* controller not enabled, so no lb used */
 642         return 0;
 643 }
 644
 645 /**
 646  * cik_get_number_of_dram_channels - get the number of dram channels
 647  *
 648  * @adev: amdgpu_device pointer
 649  *
 650  * Look up the number of video ram channels (CIK).
 651  * Used for display watermark bandwidth calculations
 652  * Returns the number of dram channels
 653  */
 654 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 655 {
 656         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 657
 658         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 659         case 0:
 660         default:
 661                 return 1;
 662         case 1:
 663                 return 2;
 664         case 2:
 665                 return 4;
 666         case 3:
 667                 return 8;
 668         case 4:
 669                 return 3;
 670         case 5:
 671                 return 6;
 672         case 6:
 673                 return 10;
 674         case 7:
 675                 return 12;
 676         case 8:
 677                 return 16;
 678         }
 679 }
 680
 681 struct dce10_wm_params {
 682         u32 dram_channels; /* number of dram channels */
 683         u32 yclk;          /* bandwidth per dram data pin in kHz */
 684         u32 sclk;          /* engine clock in kHz */
 685         u32 disp_clk;      /* display clock in kHz */
 686         u32 src_width;     /* viewport width */
 687         u32 active_time;   /* active display time in ns */
 688         u32 blank_time;    /* blank time in ns */
 689         bool interlaced;    /* mode is interlaced */
 690         fixed20_12 vsc;    /* vertical scale ratio */
 691         u32 num_heads;     /* number of active crtcs */
 692         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 693         u32 lb_size;       /* line buffer allocated to pipe */
 694         u32 vtaps;         /* vertical scaler taps */
 695 };
 696
 697 /**
 698  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 699  *
 700  * @wm: watermark calculation data
 701  *
 702  * Calculate the raw dram bandwidth (CIK).
 703  * Used for display watermark bandwidth calculations
 704  * Returns the dram bandwidth in MBytes/s
 705  */
 706 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 707 {
 708         /* Calculate raw DRAM Bandwidth */
 709         fixed20_12 dram_efficiency; /* 0.7 */
 710         fixed20_12 yclk, dram_channels, bandwidth;
 711         fixed20_12 a;
 712
 713         a.full = dfixed_const(1000);
 714         yclk.full = dfixed_const(wm->yclk);
 715         yclk.full = dfixed_div(yclk, a);
 716         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 717         a.full = dfixed_const(10);
 718         dram_efficiency.full = dfixed_const(7);
 719         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 720         bandwidth.full = dfixed_mul(dram_channels, yclk);
 721         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 722
 723         return dfixed_trunc(bandwidth);
 724 }
 725
 726 /**
 727  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 728  *
 729  * @wm: watermark calculation data
 730  *
 731  * Calculate the dram bandwidth used for display (CIK).
 732  * Used for display watermark bandwidth calculations
 733  * Returns the dram bandwidth for display in MBytes/s
 734  */
 735 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 736 {
 737         /* Calculate DRAM Bandwidth and the part allocated to display. */
 738         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 739         fixed20_12 yclk, dram_channels, bandwidth;
 740         fixed20_12 a;
 741
 742         a.full = dfixed_const(1000);
 743         yclk.full = dfixed_const(wm->yclk);
 744         yclk.full = dfixed_div(yclk, a);
 745         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 746         a.full = dfixed_const(10);
 747         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 748         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 749         bandwidth.full = dfixed_mul(dram_channels, yclk);
 750         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 751
 752         return dfixed_trunc(bandwidth);
 753 }
 754
 755 /**
 756  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 757  *
 758  * @wm: watermark calculation data
 759  *
 760  * Calculate the data return bandwidth used for display (CIK).
 761  * Used for display watermark bandwidth calculations
 762  * Returns the data return bandwidth in MBytes/s
 763  */
 764 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 765 {
 766         /* Calculate the display Data return Bandwidth */
 767         fixed20_12 return_efficiency; /* 0.8 */
 768         fixed20_12 sclk, bandwidth;
 769         fixed20_12 a;
 770
 771         a.full = dfixed_const(1000);
 772         sclk.full = dfixed_const(wm->sclk);
 773         sclk.full = dfixed_div(sclk, a);
 774         a.full = dfixed_const(10);
 775         return_efficiency.full = dfixed_const(8);
 776         return_efficiency.full = dfixed_div(return_efficiency, a);
 777         a.full = dfixed_const(32);
 778         bandwidth.full = dfixed_mul(a, sclk);
 779         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 780
 781         return dfixed_trunc(bandwidth);
 782 }
 783
 784 /**
 785  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
 786  *
 787  * @wm: watermark calculation data
 788  *
 789  * Calculate the dmif bandwidth used for display (CIK).
 790  * Used for display watermark bandwidth calculations
 791  * Returns the dmif bandwidth in MBytes/s
 792  */
 793 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 794 {
 795         /* Calculate the DMIF Request Bandwidth */
 796         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 797         fixed20_12 disp_clk, bandwidth;
 798         fixed20_12 a, b;
 799
 800         a.full = dfixed_const(1000);
 801         disp_clk.full = dfixed_const(wm->disp_clk);
 802         disp_clk.full = dfixed_div(disp_clk, a);
 803         a.full = dfixed_const(32);
 804         b.full = dfixed_mul(a, disp_clk);
 805
 806         a.full = dfixed_const(10);
 807         disp_clk_request_efficiency.full = dfixed_const(8);
 808         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 809
 810         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 811
 812         return dfixed_trunc(bandwidth);
 813 }
 814
 815 /**
 816  * dce_v10_0_available_bandwidth - get the min available bandwidth
 817  *
 818  * @wm: watermark calculation data
 819  *
 820  * Calculate the min available bandwidth used for display (CIK).
 821  * Used for display watermark bandwidth calculations
 822  * Returns the min available bandwidth in MBytes/s
 823  */
 824 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
 825 {
 826         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 827         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
 828         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
 829         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
 830
 831         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 832 }
 833
 834 /**
 835  * dce_v10_0_average_bandwidth - get the average available bandwidth
 836  *
 837  * @wm: watermark calculation data
 838  *
 839  * Calculate the average available bandwidth used for display (CIK).
 840  * Used for display watermark bandwidth calculations
 841  * Returns the average available bandwidth in MBytes/s
 842  */
 843 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
 844 {
 845         /* Calculate the display mode Average Bandwidth
 846          * DisplayMode should contain the source and destination dimensions,
 847          * timing, etc.
 848          */
 849         fixed20_12 bpp;
 850         fixed20_12 line_time;
 851         fixed20_12 src_width;
 852         fixed20_12 bandwidth;
 853         fixed20_12 a;
 854
 855         a.full = dfixed_const(1000);
 856         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 857         line_time.full = dfixed_div(line_time, a);
 858         bpp.full = dfixed_const(wm->bytes_per_pixel);
 859         src_width.full = dfixed_const(wm->src_width);
 860         bandwidth.full = dfixed_mul(src_width, bpp);
 861         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 862         bandwidth.full = dfixed_div(bandwidth, line_time);
 863
 864         return dfixed_trunc(bandwidth);
 865 }
 866
 867 /**
 868  * dce_v10_0_latency_watermark - get the latency watermark
 869  *
 870  * @wm: watermark calculation data
 871  *
 872  * Calculate the latency watermark (CIK).
 873  * Used for display watermark bandwidth calculations
 874  * Returns the latency watermark in ns
 875  */
 876 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
 877 {
 878         /* First calculate the latency in ns */
 879         u32 mc_latency = 2000; /* 2000 ns. */
 880         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
 881         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 882         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 883         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 884         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 885                 (wm->num_heads * cursor_line_pair_return_time);
 886         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 887         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 888         u32 tmp, dmif_size = 12288;
 889         fixed20_12 a, b, c;
 890
 891         if (wm->num_heads == 0)
 892                 return 0;
 893
 894         a.full = dfixed_const(2);
 895         b.full = dfixed_const(1);
 896         if ((wm->vsc.full > a.full) ||
 897             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 898             (wm->vtaps >= 5) ||
 899             ((wm->vsc.full >= a.full) && wm->interlaced))
 900                 max_src_lines_per_dst_line = 4;
 901         else
 902                 max_src_lines_per_dst_line = 2;
 903
 904         a.full = dfixed_const(available_bandwidth);
 905         b.full = dfixed_const(wm->num_heads);
 906         a.full = dfixed_div(a, b);
 907         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 908         tmp = min(dfixed_trunc(a), tmp);
 909
 910         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 911
 912         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 913         b.full = dfixed_const(1000);
 914         c.full = dfixed_const(lb_fill_bw);
 915         b.full = dfixed_div(c, b);
 916         a.full = dfixed_div(a, b);
 917         line_fill_time = dfixed_trunc(a);
 918
 919         if (line_fill_time < wm->active_time)
 920                 return latency;
 921         else
 922                 return latency + (line_fill_time - wm->active_time);
 923
 924 }
 925
 926 /**
 927  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 928  * average and available dram bandwidth
 929  *
 930  * @wm: watermark calculation data
 931  *
 932  * Check if the display average bandwidth fits in the display
 933  * dram bandwidth (CIK).
 934  * Used for display watermark bandwidth calculations
 935  * Returns true if the display fits, false if not.
 936  */
 937 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 938 {
 939         if (dce_v10_0_average_bandwidth(wm) <=
 940             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 941                 return true;
 942         else
 943                 return false;
 944 }
 945
 946 /**
 947  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
 948  * average and available bandwidth
 949  *
 950  * @wm: watermark calculation data
 951  *
 952  * Check if the display average bandwidth fits in the display
 953  * available bandwidth (CIK).
 954  * Used for display watermark bandwidth calculations
 955  * Returns true if the display fits, false if not.
 956  */
 957 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
 958 {
 959         if (dce_v10_0_average_bandwidth(wm) <=
 960             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
 961                 return true;
 962         else
 963                 return false;
 964 }
 965
 966 /**
 967  * dce_v10_0_check_latency_hiding - check latency hiding
 968  *
 969  * @wm: watermark calculation data
 970  *
 971  * Check latency hiding (CIK).
 972  * Used for display watermark bandwidth calculations
 973  * Returns true if the display fits, false if not.
 974  */
 975 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
 976 {
 977         u32 lb_partitions = wm->lb_size / wm->src_width;
 978         u32 line_time = wm->active_time + wm->blank_time;
 979         u32 latency_tolerant_lines;
 980         u32 latency_hiding;
 981         fixed20_12 a;
 982
 983         a.full = dfixed_const(1);
 984         if (wm->vsc.full > a.full)
 985                 latency_tolerant_lines = 1;
 986         else {
 987                 if (lb_partitions <= (wm->vtaps + 1))
 988                         latency_tolerant_lines = 1;
 989                 else
 990                         latency_tolerant_lines = 2;
 991         }
 992
 993         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 994
 995         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
 996                 return true;
 997         else
 998                 return false;
 999 }
1000
1001 /**
1002  * dce_v10_0_program_watermarks - program display watermarks
1003  *
1004  * @adev: amdgpu_device pointer
1005  * @amdgpu_crtc: the selected display controller
1006  * @lb_size: line buffer size
1007  * @num_heads: number of display controllers in use
1008  *
1009  * Calculate and program the display watermarks for the
1010  * selected display controller (CIK).
1011  */
1012 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1013                                         struct amdgpu_crtc *amdgpu_crtc,
1014                                         u32 lb_size, u32 num_heads)
1015 {
1016         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1017         struct dce10_wm_params wm_low, wm_high;
1018         u32 active_time;
1019         u32 line_time = 0;
1020         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1021         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1022
1023         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1024                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1025                                             (u32)mode->clock);
1026                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1027                                           (u32)mode->clock);
1028                 line_time = min(line_time, (u32)65535);
1029
1030                 /* watermark for high clocks */
1031                 if (adev->pm.dpm_enabled) {
1032                         wm_high.yclk =
1033                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1034                         wm_high.sclk =
1035                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1036                 } else {
1037                         wm_high.yclk = adev->pm.current_mclk * 10;
1038                         wm_high.sclk = adev->pm.current_sclk * 10;
1039                 }
1040
1041                 wm_high.disp_clk = mode->clock;
1042                 wm_high.src_width = mode->crtc_hdisplay;
1043                 wm_high.active_time = active_time;
1044                 wm_high.blank_time = line_time - wm_high.active_time;
1045                 wm_high.interlaced = false;
1046                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1047                         wm_high.interlaced = true;
1048                 wm_high.vsc = amdgpu_crtc->vsc;
1049                 wm_high.vtaps = 1;
1050                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1051                         wm_high.vtaps = 2;
1052                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1053                 wm_high.lb_size = lb_size;
1054                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1055                 wm_high.num_heads = num_heads;
1056
1057                 /* set for high clocks */
1058                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1059
1060                 /* possibly force display priority to high */
1061                 /* should really do this at mode validation time... */
1062                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1063                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1064                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1065                     (adev->mode_info.disp_priority == 2)) {
1066                         DRM_DEBUG_KMS("force priority to high\n");
1067                 }
1068
1069                 /* watermark for low clocks */
1070                 if (adev->pm.dpm_enabled) {
1071                         wm_low.yclk =
1072                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1073                         wm_low.sclk =
1074                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1075                 } else {
1076                         wm_low.yclk = adev->pm.current_mclk * 10;
1077                         wm_low.sclk = adev->pm.current_sclk * 10;
1078                 }
1079
1080                 wm_low.disp_clk = mode->clock;
1081                 wm_low.src_width = mode->crtc_hdisplay;
1082                 wm_low.active_time = active_time;
1083                 wm_low.blank_time = line_time - wm_low.active_time;
1084                 wm_low.interlaced = false;
1085                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1086                         wm_low.interlaced = true;
1087                 wm_low.vsc = amdgpu_crtc->vsc;
1088                 wm_low.vtaps = 1;
1089                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1090                         wm_low.vtaps = 2;
1091                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1092                 wm_low.lb_size = lb_size;
1093                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1094                 wm_low.num_heads = num_heads;
1095
1096                 /* set for low clocks */
1097                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1098
1099                 /* possibly force display priority to high */
1100                 /* should really do this at mode validation time... */
1101                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1102                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1103                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1104                     (adev->mode_info.disp_priority == 2)) {
1105                         DRM_DEBUG_KMS("force priority to high\n");
1106                 }
1107                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1108         }
1109
1110         /* select wm A */
1111         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1112         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1113         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1114         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1115         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1116         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1117         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1118         /* select wm B */
1119         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1120         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1121         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1122         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1123         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1124         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1125         /* restore original selection */
1126         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1127
1128         /* save values for DPM */
1129         amdgpu_crtc->line_time = line_time;
1130         amdgpu_crtc->wm_high = latency_watermark_a;
1131         amdgpu_crtc->wm_low = latency_watermark_b;
1132         /* Save number of lines the linebuffer leads before the scanout */
1133         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1134 }
1135
1136 /**
1137  * dce_v10_0_bandwidth_update - program display watermarks
1138  *
1139  * @adev: amdgpu_device pointer
1140  *
1141  * Calculate and program the display watermarks and line
1142  * buffer allocation (CIK).
1143  */
1144 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1145 {
1146         struct drm_display_mode *mode = NULL;
1147         u32 num_heads = 0, lb_size;
1148         int i;
1149
1150         amdgpu_display_update_priority(adev);
1151
1152         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1153                 if (adev->mode_info.crtcs[i]->base.enabled)
1154                         num_heads++;
1155         }
1156         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1157                 mode = &adev->mode_info.crtcs[i]->base.mode;
1158                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1159                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1160                                             lb_size, num_heads);
1161         }
1162 }
1163
1164 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1165 {
1166         int i;
1167         u32 offset, tmp;
1168
1169         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1170                 offset = adev->mode_info.audio.pin[i].offset;
1171                 tmp = RREG32_AUDIO_ENDPT(offset,
1172                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1173                 if (((tmp &
1174                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1175                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1176                         adev->mode_info.audio.pin[i].connected = false;
1177                 else
1178                         adev->mode_info.audio.pin[i].connected = true;
1179         }
1180 }
1181
1182 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1183 {
1184         int i;
1185
1186         dce_v10_0_audio_get_connected_pins(adev);
1187
1188         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1189                 if (adev->mode_info.audio.pin[i].connected)
1190                         return &adev->mode_info.audio.pin[i];
1191         }
1192         DRM_ERROR("No connected audio pins found!\n");
1193         return NULL;
1194 }
1195
1196 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1197 {
1198         struct amdgpu_device *adev = encoder->dev->dev_private;
1199         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1200         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1201         u32 tmp;
1202
1203         if (!dig || !dig->afmt || !dig->afmt->pin)
1204                 return;
1205
1206         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1207         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1208         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1209 }
1210
1211 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1212                                                 struct drm_display_mode *mode)
1213 {
1214         struct amdgpu_device *adev = encoder->dev->dev_private;
1215         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1216         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1217         struct drm_connector *connector;
1218         struct amdgpu_connector *amdgpu_connector = NULL;
1219         u32 tmp;
1220         int interlace = 0;
1221
1222         if (!dig || !dig->afmt || !dig->afmt->pin)
1223                 return;
1224
1225         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1226                 if (connector->encoder == encoder) {
1227                         amdgpu_connector = to_amdgpu_connector(connector);
1228                         break;
1229                 }
1230         }
1231
1232         if (!amdgpu_connector) {
1233                 DRM_ERROR("Couldn't find encoder's connector\n");
1234                 return;
1235         }
1236
1237         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1238                 interlace = 1;
1239         if (connector->latency_present[interlace]) {
1240                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1241                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1242                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1243                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1244         } else {
1245                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1246                                     VIDEO_LIPSYNC, 0);
1247                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1248                                     AUDIO_LIPSYNC, 0);
1249         }
1250         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1251                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1252 }
1253
1254 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1255 {
1256         struct amdgpu_device *adev = encoder->dev->dev_private;
1257         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1258         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1259         struct drm_connector *connector;
1260         struct amdgpu_connector *amdgpu_connector = NULL;
1261         u32 tmp;
1262         u8 *sadb = NULL;
1263         int sad_count;
1264
1265         if (!dig || !dig->afmt || !dig->afmt->pin)
1266                 return;
1267
1268         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1269                 if (connector->encoder == encoder) {
1270                         amdgpu_connector = to_amdgpu_connector(connector);
1271                         break;
1272                 }
1273         }
1274
1275         if (!amdgpu_connector) {
1276                 DRM_ERROR("Couldn't find encoder's connector\n");
1277                 return;
1278         }
1279
1280         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1281         if (sad_count < 0) {
1282                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1283                 sad_count = 0;
1284         }
1285
1286         /* program the speaker allocation */
1287         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1288                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1289         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1290                             DP_CONNECTION, 0);
1291         /* set HDMI mode */
1292         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1293                             HDMI_CONNECTION, 1);
1294         if (sad_count)
1295                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1296                                     SPEAKER_ALLOCATION, sadb[0]);
1297         else
1298                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1299                                     SPEAKER_ALLOCATION, 5); /* stereo */
1300         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1301                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1302
1303         kfree(sadb);
1304 }
1305
1306 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1307 {
1308         struct amdgpu_device *adev = encoder->dev->dev_private;
1309         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1310         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1311         struct drm_connector *connector;
1312         struct amdgpu_connector *amdgpu_connector = NULL;
1313         struct cea_sad *sads;
1314         int i, sad_count;
1315
1316         static const u16 eld_reg_to_type[][2] = {
1317                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1318                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1319                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1320                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1321                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1322                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1323                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1324                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1325                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1326                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1327                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1328                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1329         };
1330
1331         if (!dig || !dig->afmt || !dig->afmt->pin)
1332                 return;
1333
1334         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1335                 if (connector->encoder == encoder) {
1336                         amdgpu_connector = to_amdgpu_connector(connector);
1337                         break;
1338                 }
1339         }
1340
1341         if (!amdgpu_connector) {
1342                 DRM_ERROR("Couldn't find encoder's connector\n");
1343                 return;
1344         }
1345
1346         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1347         if (sad_count <= 0) {
1348                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1349                 return;
1350         }
1351         BUG_ON(!sads);
1352
1353         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1354                 u32 tmp = 0;
1355                 u8 stereo_freqs = 0;
1356                 int max_channels = -1;
1357                 int j;
1358
1359                 for (j = 0; j < sad_count; j++) {
1360                         struct cea_sad *sad = &sads[j];
1361
1362                         if (sad->format == eld_reg_to_type[i][1]) {
1363                                 if (sad->channels > max_channels) {
1364                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1365                                                             MAX_CHANNELS, sad->channels);
1366                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1367                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1368                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1369                                                             SUPPORTED_FREQUENCIES, sad->freq);
1370                                         max_channels = sad->channels;
1371                                 }
1372
1373                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1374                                         stereo_freqs |= sad->freq;
1375                                 else
1376                                         break;
1377                         }
1378                 }
1379
1380                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1381                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1382                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1383         }
1384
1385         kfree(sads);
1386 }
1387
1388 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1389                                   struct amdgpu_audio_pin *pin,
1390                                   bool enable)
1391 {
1392         if (!pin)
1393                 return;
1394
1395         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1396                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1397 }
1398
1399 static const u32 pin_offsets[] =
1400 {
1401         AUD0_REGISTER_OFFSET,
1402         AUD1_REGISTER_OFFSET,
1403         AUD2_REGISTER_OFFSET,
1404         AUD3_REGISTER_OFFSET,
1405         AUD4_REGISTER_OFFSET,
1406         AUD5_REGISTER_OFFSET,
1407         AUD6_REGISTER_OFFSET,
1408 };
1409
1410 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1411 {
1412         int i;
1413
1414         if (!amdgpu_audio)
1415                 return 0;
1416
1417         adev->mode_info.audio.enabled = true;
1418
1419         adev->mode_info.audio.num_pins = 7;
1420
1421         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1422                 adev->mode_info.audio.pin[i].channels = -1;
1423                 adev->mode_info.audio.pin[i].rate = -1;
1424                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1425                 adev->mode_info.audio.pin[i].status_bits = 0;
1426                 adev->mode_info.audio.pin[i].category_code = 0;
1427                 adev->mode_info.audio.pin[i].connected = false;
1428                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1429                 adev->mode_info.audio.pin[i].id = i;
1430                 /* disable audio.  it will be set up later */
1431                 /* XXX remove once we switch to ip funcs */
1432                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1439 {
1440         int i;
1441
1442         if (!amdgpu_audio)
1443                 return;
1444
1445         if (!adev->mode_info.audio.enabled)
1446                 return;
1447
1448         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1449                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1450
1451         adev->mode_info.audio.enabled = false;
1452 }
1453
1454 /*
1455  * update the N and CTS parameters for a given pixel clock rate
1456  */
1457 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1458 {
1459         struct drm_device *dev = encoder->dev;
1460         struct amdgpu_device *adev = dev->dev_private;
1461         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1462         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1463         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1464         u32 tmp;
1465
1466         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1467         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1468         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1469         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1470         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1471         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1472
1473         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1474         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1475         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1476         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1477         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1478         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1479
1480         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1481         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1482         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1483         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1484         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1485         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1486
1487 }
1488
1489 /*
1490  * build a HDMI Video Info Frame
1491  */
1492 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1493                                                void *buffer, size_t size)
1494 {
1495         struct drm_device *dev = encoder->dev;
1496         struct amdgpu_device *adev = dev->dev_private;
1497         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1498         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1499         uint8_t *frame = buffer + 3;
1500         uint8_t *header = buffer;
1501
1502         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1503                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1504         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1505                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1506         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1507                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1508         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1509                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1510 }
1511
1512 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1513 {
1514         struct drm_device *dev = encoder->dev;
1515         struct amdgpu_device *adev = dev->dev_private;
1516         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1517         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1518         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1519         u32 dto_phase = 24 * 1000;
1520         u32 dto_modulo = clock;
1521         u32 tmp;
1522
1523         if (!dig || !dig->afmt)
1524                 return;
1525
1526         /* XXX two dtos; generally use dto0 for hdmi */
1527         /* Express [24MHz / target pixel clock] as an exact rational
1528          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1529          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1530          */
1531         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1532         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1533                             amdgpu_crtc->crtc_id);
1534         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1535         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1536         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1537 }
1538
1539 /*
1540  * update the info frames with the data from the current display mode
1541  */
1542 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1543                                   struct drm_display_mode *mode)
1544 {
1545         struct drm_device *dev = encoder->dev;
1546         struct amdgpu_device *adev = dev->dev_private;
1547         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1548         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1549         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1550         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1551         struct hdmi_avi_infoframe frame;
1552         ssize_t err;
1553         u32 tmp;
1554         int bpc = 8;
1555
1556         if (!dig || !dig->afmt)
1557                 return;
1558
1559         /* Silent, r600_hdmi_enable will raise WARN for us */
1560         if (!dig->afmt->enabled)
1561                 return;
1562
1563         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1564         if (encoder->crtc) {
1565                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1566                 bpc = amdgpu_crtc->bpc;
1567         }
1568
1569         /* disable audio prior to setting up hw */
1570         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1571         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1572
1573         dce_v10_0_audio_set_dto(encoder, mode->clock);
1574
1575         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1576         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1577         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1578
1579         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1580
1581         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1582         switch (bpc) {
1583         case 0:
1584         case 6:
1585         case 8:
1586         case 16:
1587         default:
1588                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1589                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1590                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1591                           connector->name, bpc);
1592                 break;
1593         case 10:
1594                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1595                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1596                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1597                           connector->name);
1598                 break;
1599         case 12:
1600                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1601                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1602                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1603                           connector->name);
1604                 break;
1605         }
1606         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1607
1608         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1609         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1610         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1611         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1612         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1613
1614         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1615         /* enable audio info frames (frames won't be set until audio is enabled) */
1616         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1617         /* required for audio info values to be updated */
1618         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1619         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1620
1621         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1622         /* required for audio info values to be updated */
1623         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1624         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1625
1626         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1627         /* anything other than 0 */
1628         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1629         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1630
1631         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1632
1633         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1634         /* set the default audio delay */
1635         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1636         /* should be suffient for all audio modes and small enough for all hblanks */
1637         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1638         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1639
1640         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1641         /* allow 60958 channel status fields to be updated */
1642         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1643         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1644
1645         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1646         if (bpc > 8)
1647                 /* clear SW CTS value */
1648                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1649         else
1650                 /* select SW CTS value */
1651                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1652         /* allow hw to sent ACR packets when required */
1653         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1654         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1655
1656         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1657
1658         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1659         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1660         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1661
1662         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1663         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1664         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1665
1666         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1667         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1668         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1669         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1670         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1671         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1672         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1673         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1674
1675         dce_v10_0_audio_write_speaker_allocation(encoder);
1676
1677         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1678                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1679
1680         dce_v10_0_afmt_audio_select_pin(encoder);
1681         dce_v10_0_audio_write_sad_regs(encoder);
1682         dce_v10_0_audio_write_latency_fields(encoder, mode);
1683
1684         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1685         if (err < 0) {
1686                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1687                 return;
1688         }
1689
1690         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1691         if (err < 0) {
1692                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1693                 return;
1694         }
1695
1696         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1697
1698         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1699         /* enable AVI info frames */
1700         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1701         /* required for audio info values to be updated */
1702         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1703         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1704
1705         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1706         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1707         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1708
1709         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1710         /* send audio packets */
1711         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1712         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1713
1714         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1715         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1716         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1717         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1718
1719         /* enable audio after to setting up hw */
1720         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1721 }
1722
1723 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1724 {
1725         struct drm_device *dev = encoder->dev;
1726         struct amdgpu_device *adev = dev->dev_private;
1727         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729
1730         if (!dig || !dig->afmt)
1731                 return;
1732
1733         /* Silent, r600_hdmi_enable will raise WARN for us */
1734         if (enable && dig->afmt->enabled)
1735                 return;
1736         if (!enable && !dig->afmt->enabled)
1737                 return;
1738
1739         if (!enable && dig->afmt->pin) {
1740                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1741                 dig->afmt->pin = NULL;
1742         }
1743
1744         dig->afmt->enabled = enable;
1745
1746         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1747                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1748 }
1749
1750 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1751 {
1752         int i;
1753
1754         for (i = 0; i < adev->mode_info.num_dig; i++)
1755                 adev->mode_info.afmt[i] = NULL;
1756
1757         /* DCE10 has audio blocks tied to DIG encoders */
1758         for (i = 0; i < adev->mode_info.num_dig; i++) {
1759                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1760                 if (adev->mode_info.afmt[i]) {
1761                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1762                         adev->mode_info.afmt[i]->id = i;
1763                 } else {
1764                         int j;
1765                         for (j = 0; j < i; j++) {
1766                                 kfree(adev->mode_info.afmt[j]);
1767                                 adev->mode_info.afmt[j] = NULL;
1768                         }
1769                         return -ENOMEM;
1770                 }
1771         }
1772         return 0;
1773 }
1774
1775 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1776 {
1777         int i;
1778
1779         for (i = 0; i < adev->mode_info.num_dig; i++) {
1780                 kfree(adev->mode_info.afmt[i]);
1781                 adev->mode_info.afmt[i] = NULL;
1782         }
1783 }
1784
1785 static const u32 vga_control_regs[6] =
1786 {
1787         mmD1VGA_CONTROL,
1788         mmD2VGA_CONTROL,
1789         mmD3VGA_CONTROL,
1790         mmD4VGA_CONTROL,
1791         mmD5VGA_CONTROL,
1792         mmD6VGA_CONTROL,
1793 };
1794
1795 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1796 {
1797         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1798         struct drm_device *dev = crtc->dev;
1799         struct amdgpu_device *adev = dev->dev_private;
1800         u32 vga_control;
1801
1802         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1803         if (enable)
1804                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1805         else
1806                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1807 }
1808
1809 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1810 {
1811         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1812         struct drm_device *dev = crtc->dev;
1813         struct amdgpu_device *adev = dev->dev_private;
1814
1815         if (enable)
1816                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1817         else
1818                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1819 }
1820
1821 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1822                                      struct drm_framebuffer *fb,
1823                                      int x, int y, int atomic)
1824 {
1825         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1826         struct drm_device *dev = crtc->dev;
1827         struct amdgpu_device *adev = dev->dev_private;
1828         struct drm_framebuffer *target_fb;
1829         struct drm_gem_object *obj;
1830         struct amdgpu_bo *abo;
1831         uint64_t fb_location, tiling_flags;
1832         uint32_t fb_format, fb_pitch_pixels;
1833         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1834         u32 pipe_config;
1835         u32 tmp, viewport_w, viewport_h;
1836         int r;
1837         bool bypass_lut = false;
1838         struct drm_format_name_buf format_name;
1839
1840         /* no fb bound */
1841         if (!atomic && !crtc->primary->fb) {
1842                 DRM_DEBUG_KMS("No FB bound\n");
1843                 return 0;
1844         }
1845
1846         if (atomic)
1847                 target_fb = fb;
1848         else
1849                 target_fb = crtc->primary->fb;
1850
1851         /* If atomic, assume fb object is pinned & idle & fenced and
1852          * just update base pointers
1853          */
1854         obj = target_fb->obj[0];
1855         abo = gem_to_amdgpu_bo(obj);
1856         r = amdgpu_bo_reserve(abo, false);
1857         if (unlikely(r != 0))
1858                 return r;
1859
1860         if (!atomic) {
1861                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1862                 if (unlikely(r != 0)) {
1863                         amdgpu_bo_unreserve(abo);
1864                         return -EINVAL;
1865                 }
1866         }
1867         fb_location = amdgpu_bo_gpu_offset(abo);
1868
1869         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1870         amdgpu_bo_unreserve(abo);
1871
1872         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1873
1874         switch (target_fb->format->format) {
1875         case DRM_FORMAT_C8:
1876                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1877                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1878                 break;
1879         case DRM_FORMAT_XRGB4444:
1880         case DRM_FORMAT_ARGB4444:
1881                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1882                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1883 #ifdef __BIG_ENDIAN
1884                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1885                                         ENDIAN_8IN16);
1886 #endif
1887                 break;
1888         case DRM_FORMAT_XRGB1555:
1889         case DRM_FORMAT_ARGB1555:
1890                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1891                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1892 #ifdef __BIG_ENDIAN
1893                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1894                                         ENDIAN_8IN16);
1895 #endif
1896                 break;
1897         case DRM_FORMAT_BGRX5551:
1898         case DRM_FORMAT_BGRA5551:
1899                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1900                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1901 #ifdef __BIG_ENDIAN
1902                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1903                                         ENDIAN_8IN16);
1904 #endif
1905                 break;
1906         case DRM_FORMAT_RGB565:
1907                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1908                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1909 #ifdef __BIG_ENDIAN
1910                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1911                                         ENDIAN_8IN16);
1912 #endif
1913                 break;
1914         case DRM_FORMAT_XRGB8888:
1915         case DRM_FORMAT_ARGB8888:
1916                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1917                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1918 #ifdef __BIG_ENDIAN
1919                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1920                                         ENDIAN_8IN32);
1921 #endif
1922                 break;
1923         case DRM_FORMAT_XRGB2101010:
1924         case DRM_FORMAT_ARGB2101010:
1925                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1926                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1927 #ifdef __BIG_ENDIAN
1928                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1929                                         ENDIAN_8IN32);
1930 #endif
1931                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1932                 bypass_lut = true;
1933                 break;
1934         case DRM_FORMAT_BGRX1010102:
1935         case DRM_FORMAT_BGRA1010102:
1936                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1937                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1938 #ifdef __BIG_ENDIAN
1939                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1940                                         ENDIAN_8IN32);
1941 #endif
1942                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1943                 bypass_lut = true;
1944                 break;
1945         default:
1946                 DRM_ERROR("Unsupported screen format %s\n",
1947                           drm_get_format_name(target_fb->format->format, &format_name));
1948                 return -EINVAL;
1949         }
1950
1951         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1952                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1953
1954                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1955                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1956                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1957                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1958                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1959
1960                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1961                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1962                                           ARRAY_2D_TILED_THIN1);
1963                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1964                                           tile_split);
1965                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
1966                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
1967                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
1968                                           mtaspect);
1969                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
1970                                           ADDR_SURF_MICRO_TILING_DISPLAY);
1971         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1972                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1973                                           ARRAY_1D_TILED_THIN1);
1974         }
1975
1976         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
1977                                   pipe_config);
1978
1979         dce_v10_0_vga_enable(crtc, false);
1980
1981         /* Make sure surface address is updated at vertical blank rather than
1982          * horizontal blank
1983          */
1984         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
1985         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
1986                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
1987         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1988
1989         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1990                upper_32_bits(fb_location));
1991         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1992                upper_32_bits(fb_location));
1993         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1994                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1995         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1996                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1997         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1998         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1999
2000         /*
2001          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2002          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2003          * retain the full precision throughout the pipeline.
2004          */
2005         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2006         if (bypass_lut)
2007                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2008         else
2009                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2010         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2011
2012         if (bypass_lut)
2013                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2014
2015         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2016         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2017         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2018         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2019         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2020         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2021
2022         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2023         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2024
2025         dce_v10_0_grph_enable(crtc, true);
2026
2027         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2028                target_fb->height);
2029
2030         x &= ~3;
2031         y &= ~1;
2032         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2033                (x << 16) | y);
2034         viewport_w = crtc->mode.hdisplay;
2035         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2036         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2037                (viewport_w << 16) | viewport_h);
2038
2039         /* set pageflip to happen anywhere in vblank interval */
2040         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2041
2042         if (!atomic && fb && fb != crtc->primary->fb) {
2043                 abo = gem_to_amdgpu_bo(fb->obj[0]);
2044                 r = amdgpu_bo_reserve(abo, true);
2045                 if (unlikely(r != 0))
2046                         return r;
2047                 amdgpu_bo_unpin(abo);
2048                 amdgpu_bo_unreserve(abo);
2049         }
2050
2051         /* Bytes per pixel may have changed */
2052         dce_v10_0_bandwidth_update(adev);
2053
2054         return 0;
2055 }
2056
2057 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2058                                      struct drm_display_mode *mode)
2059 {
2060         struct drm_device *dev = crtc->dev;
2061         struct amdgpu_device *adev = dev->dev_private;
2062         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2063         u32 tmp;
2064
2065         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2066         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2067                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2068         else
2069                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2070         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2071 }
2072
2073 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2074 {
2075         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2076         struct drm_device *dev = crtc->dev;
2077         struct amdgpu_device *adev = dev->dev_private;
2078         u16 *r, *g, *b;
2079         int i;
2080         u32 tmp;
2081
2082         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2083
2084         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2085         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2086         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2087         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2088
2089         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2090         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2091         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2092
2093         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2094         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2095         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2096
2097         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2098         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2099         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2100         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2101
2102         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2103
2104         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2105         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2106         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2107
2108         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2109         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2110         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2111
2112         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2113         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2114
2115         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2116         r = crtc->gamma_store;
2117         g = r + crtc->gamma_size;
2118         b = g + crtc->gamma_size;
2119         for (i = 0; i < 256; i++) {
2120                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2121                        ((*r++ & 0xffc0) << 14) |
2122                        ((*g++ & 0xffc0) << 4) |
2123                        (*b++ >> 6));
2124         }
2125
2126         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2127         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2128         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2129         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2130         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2131
2132         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2133         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2134         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2135         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2136
2137         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2138         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2139         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2140         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2141
2142         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2143         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2144         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2145         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2146
2147         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2148         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2149         /* XXX this only needs to be programmed once per crtc at startup,
2150          * not sure where the best place for it is
2151          */
2152         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2153         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2154         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2155 }
2156
2157 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2158 {
2159         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2160         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2161
2162         switch (amdgpu_encoder->encoder_id) {
2163         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2164                 if (dig->linkb)
2165                         return 1;
2166                 else
2167                         return 0;
2168                 break;
2169         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2170                 if (dig->linkb)
2171                         return 3;
2172                 else
2173                         return 2;
2174                 break;
2175         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2176                 if (dig->linkb)
2177                         return 5;
2178                 else
2179                         return 4;
2180                 break;
2181         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2182                 return 6;
2183                 break;
2184         default:
2185                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2186                 return 0;
2187         }
2188 }
2189
2190 /**
2191  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2192  *
2193  * @crtc: drm crtc
2194  *
2195  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2196  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2197  * monitors a dedicated PPLL must be used.  If a particular board has
2198  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2199  * as there is no need to program the PLL itself.  If we are not able to
2200  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2201  * avoid messing up an existing monitor.
2202  *
2203  * Asic specific PLL information
2204  *
2205  * DCE 10.x
2206  * Tonga
2207  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2208  * CI
2209  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2210  *
2211  */
2212 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2213 {
2214         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2215         struct drm_device *dev = crtc->dev;
2216         struct amdgpu_device *adev = dev->dev_private;
2217         u32 pll_in_use;
2218         int pll;
2219
2220         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2221                 if (adev->clock.dp_extclk)
2222                         /* skip PPLL programming if using ext clock */
2223                         return ATOM_PPLL_INVALID;
2224                 else {
2225                         /* use the same PPLL for all DP monitors */
2226                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2227                         if (pll != ATOM_PPLL_INVALID)
2228                                 return pll;
2229                 }
2230         } else {
2231                 /* use the same PPLL for all monitors with the same clock */
2232                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2233                 if (pll != ATOM_PPLL_INVALID)
2234                         return pll;
2235         }
2236
2237         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2238         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2239         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2240                 return ATOM_PPLL2;
2241         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2242                 return ATOM_PPLL1;
2243         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2244                 return ATOM_PPLL0;
2245         DRM_ERROR("unable to allocate a PPLL\n");
2246         return ATOM_PPLL_INVALID;
2247 }
2248
2249 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2250 {
2251         struct amdgpu_device *adev = crtc->dev->dev_private;
2252         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2253         uint32_t cur_lock;
2254
2255         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2256         if (lock)
2257                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2258         else
2259                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2260         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2261 }
2262
2263 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2264 {
2265         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2266         struct amdgpu_device *adev = crtc->dev->dev_private;
2267         u32 tmp;
2268
2269         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2270         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2271         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2272 }
2273
2274 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2275 {
2276         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2277         struct amdgpu_device *adev = crtc->dev->dev_private;
2278         u32 tmp;
2279
2280         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2281                upper_32_bits(amdgpu_crtc->cursor_addr));
2282         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2283                lower_32_bits(amdgpu_crtc->cursor_addr));
2284
2285         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2286         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2287         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2288         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2289 }
2290
2291 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2292                                         int x, int y)
2293 {
2294         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2295         struct amdgpu_device *adev = crtc->dev->dev_private;
2296         int xorigin = 0, yorigin = 0;
2297
2298         amdgpu_crtc->cursor_x = x;
2299         amdgpu_crtc->cursor_y = y;
2300
2301         /* avivo cursor are offset into the total surface */
2302         x += crtc->x;
2303         y += crtc->y;
2304         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2305
2306         if (x < 0) {
2307                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2308                 x = 0;
2309         }
2310         if (y < 0) {
2311                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2312                 y = 0;
2313         }
2314
2315         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2316         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2317         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2318                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2319
2320         return 0;
2321 }
2322
2323 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2324                                       int x, int y)
2325 {
2326         int ret;
2327
2328         dce_v10_0_lock_cursor(crtc, true);
2329         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2330         dce_v10_0_lock_cursor(crtc, false);
2331
2332         return ret;
2333 }
2334
2335 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2336                                       struct drm_file *file_priv,
2337                                       uint32_t handle,
2338                                       uint32_t width,
2339                                       uint32_t height,
2340                                       int32_t hot_x,
2341                                       int32_t hot_y)
2342 {
2343         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2344         struct drm_gem_object *obj;
2345         struct amdgpu_bo *aobj;
2346         int ret;
2347
2348         if (!handle) {
2349                 /* turn off cursor */
2350                 dce_v10_0_hide_cursor(crtc);
2351                 obj = NULL;
2352                 goto unpin;
2353         }
2354
2355         if ((width > amdgpu_crtc->max_cursor_width) ||
2356             (height > amdgpu_crtc->max_cursor_height)) {
2357                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2358                 return -EINVAL;
2359         }
2360
2361         obj = drm_gem_object_lookup(file_priv, handle);
2362         if (!obj) {
2363                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2364                 return -ENOENT;
2365         }
2366
2367         aobj = gem_to_amdgpu_bo(obj);
2368         ret = amdgpu_bo_reserve(aobj, false);
2369         if (ret != 0) {
2370                 drm_gem_object_put_unlocked(obj);
2371                 return ret;
2372         }
2373
2374         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2375         amdgpu_bo_unreserve(aobj);
2376         if (ret) {
2377                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2378                 drm_gem_object_put_unlocked(obj);
2379                 return ret;
2380         }
2381         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2382
2383         dce_v10_0_lock_cursor(crtc, true);
2384
2385         if (width != amdgpu_crtc->cursor_width ||
2386             height != amdgpu_crtc->cursor_height ||
2387             hot_x != amdgpu_crtc->cursor_hot_x ||
2388             hot_y != amdgpu_crtc->cursor_hot_y) {
2389                 int x, y;
2390
2391                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2392                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2393
2394                 dce_v10_0_cursor_move_locked(crtc, x, y);
2395
2396                 amdgpu_crtc->cursor_width = width;
2397                 amdgpu_crtc->cursor_height = height;
2398                 amdgpu_crtc->cursor_hot_x = hot_x;
2399                 amdgpu_crtc->cursor_hot_y = hot_y;
2400         }
2401
2402         dce_v10_0_show_cursor(crtc);
2403         dce_v10_0_lock_cursor(crtc, false);
2404
2405 unpin:
2406         if (amdgpu_crtc->cursor_bo) {
2407                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2408                 ret = amdgpu_bo_reserve(aobj, true);
2409                 if (likely(ret == 0)) {
2410                         amdgpu_bo_unpin(aobj);
2411                         amdgpu_bo_unreserve(aobj);
2412                 }
2413                 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2414         }
2415
2416         amdgpu_crtc->cursor_bo = obj;
2417         return 0;
2418 }
2419
2420 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2421 {
2422         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2423
2424         if (amdgpu_crtc->cursor_bo) {
2425                 dce_v10_0_lock_cursor(crtc, true);
2426
2427                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2428                                              amdgpu_crtc->cursor_y);
2429
2430                 dce_v10_0_show_cursor(crtc);
2431
2432                 dce_v10_0_lock_cursor(crtc, false);
2433         }
2434 }
2435
2436 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2437                                     u16 *blue, uint32_t size,
2438                                     struct drm_modeset_acquire_ctx *ctx)
2439 {
2440         dce_v10_0_crtc_load_lut(crtc);
2441
2442         return 0;
2443 }
2444
2445 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2446 {
2447         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2448
2449         drm_crtc_cleanup(crtc);
2450         kfree(amdgpu_crtc);
2451 }
2452
2453 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2454         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2455         .cursor_move = dce_v10_0_crtc_cursor_move,
2456         .gamma_set = dce_v10_0_crtc_gamma_set,
2457         .set_config = amdgpu_display_crtc_set_config,
2458         .destroy = dce_v10_0_crtc_destroy,
2459         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2460 };
2461
2462 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2463 {
2464         struct drm_device *dev = crtc->dev;
2465         struct amdgpu_device *adev = dev->dev_private;
2466         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2467         unsigned type;
2468
2469         switch (mode) {
2470         case DRM_MODE_DPMS_ON:
2471                 amdgpu_crtc->enabled = true;
2472                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2473                 dce_v10_0_vga_enable(crtc, true);
2474                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2475                 dce_v10_0_vga_enable(crtc, false);
2476                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2477                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2478                                                 amdgpu_crtc->crtc_id);
2479                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2480                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2481                 drm_crtc_vblank_on(crtc);
2482                 dce_v10_0_crtc_load_lut(crtc);
2483                 break;
2484         case DRM_MODE_DPMS_STANDBY:
2485         case DRM_MODE_DPMS_SUSPEND:
2486         case DRM_MODE_DPMS_OFF:
2487                 drm_crtc_vblank_off(crtc);
2488                 if (amdgpu_crtc->enabled) {
2489                         dce_v10_0_vga_enable(crtc, true);
2490                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2491                         dce_v10_0_vga_enable(crtc, false);
2492                 }
2493                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2494                 amdgpu_crtc->enabled = false;
2495                 break;
2496         }
2497         /* adjust pm to dpms */
2498         amdgpu_pm_compute_clocks(adev);
2499 }
2500
2501 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2502 {
2503         /* disable crtc pair power gating before programming */
2504         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2505         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2506         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2507 }
2508
2509 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2510 {
2511         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2512         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2513 }
2514
2515 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2516 {
2517         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2518         struct drm_device *dev = crtc->dev;
2519         struct amdgpu_device *adev = dev->dev_private;
2520         struct amdgpu_atom_ss ss;
2521         int i;
2522
2523         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2524         if (crtc->primary->fb) {
2525                 int r;
2526                 struct amdgpu_bo *abo;
2527
2528                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2529                 r = amdgpu_bo_reserve(abo, true);
2530                 if (unlikely(r))
2531                         DRM_ERROR("failed to reserve abo before unpin\n");
2532                 else {
2533                         amdgpu_bo_unpin(abo);
2534                         amdgpu_bo_unreserve(abo);
2535                 }
2536         }
2537         /* disable the GRPH */
2538         dce_v10_0_grph_enable(crtc, false);
2539
2540         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2541
2542         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2543                 if (adev->mode_info.crtcs[i] &&
2544                     adev->mode_info.crtcs[i]->enabled &&
2545                     i != amdgpu_crtc->crtc_id &&
2546                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2547                         /* one other crtc is using this pll don't turn
2548                          * off the pll
2549                          */
2550                         goto done;
2551                 }
2552         }
2553
2554         switch (amdgpu_crtc->pll_id) {
2555         case ATOM_PPLL0:
2556         case ATOM_PPLL1:
2557         case ATOM_PPLL2:
2558                 /* disable the ppll */
2559                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2560                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2561                 break;
2562         default:
2563                 break;
2564         }
2565 done:
2566         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2567         amdgpu_crtc->adjusted_clock = 0;
2568         amdgpu_crtc->encoder = NULL;
2569         amdgpu_crtc->connector = NULL;
2570 }
2571
2572 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2573                                   struct drm_display_mode *mode,
2574                                   struct drm_display_mode *adjusted_mode,
2575                                   int x, int y, struct drm_framebuffer *old_fb)
2576 {
2577         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2578
2579         if (!amdgpu_crtc->adjusted_clock)
2580                 return -EINVAL;
2581
2582         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2583         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2584         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2585         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2586         amdgpu_atombios_crtc_scaler_setup(crtc);
2587         dce_v10_0_cursor_reset(crtc);
2588         /* update the hw version fpr dpm */
2589         amdgpu_crtc->hw_mode = *adjusted_mode;
2590
2591         return 0;
2592 }
2593
2594 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2595                                      const struct drm_display_mode *mode,
2596                                      struct drm_display_mode *adjusted_mode)
2597 {
2598         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2599         struct drm_device *dev = crtc->dev;
2600         struct drm_encoder *encoder;
2601
2602         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2603         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2604                 if (encoder->crtc == crtc) {
2605                         amdgpu_crtc->encoder = encoder;
2606                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2607                         break;
2608                 }
2609         }
2610         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2611                 amdgpu_crtc->encoder = NULL;
2612                 amdgpu_crtc->connector = NULL;
2613                 return false;
2614         }
2615         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2616                 return false;
2617         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2618                 return false;
2619         /* pick pll */
2620         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2621         /* if we can't get a PPLL for a non-DP encoder, fail */
2622         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2623             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2624                 return false;
2625
2626         return true;
2627 }
2628
2629 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2630                                   struct drm_framebuffer *old_fb)
2631 {
2632         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2633 }
2634
2635 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2636                                          struct drm_framebuffer *fb,
2637                                          int x, int y, enum mode_set_atomic state)
2638 {
2639        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2640 }
2641
2642 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2643         .dpms = dce_v10_0_crtc_dpms,
2644         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2645         .mode_set = dce_v10_0_crtc_mode_set,
2646         .mode_set_base = dce_v10_0_crtc_set_base,
2647         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2648         .prepare = dce_v10_0_crtc_prepare,
2649         .commit = dce_v10_0_crtc_commit,
2650         .disable = dce_v10_0_crtc_disable,
2651 };
2652
2653 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2654 {
2655         struct amdgpu_crtc *amdgpu_crtc;
2656
2657         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2658                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2659         if (amdgpu_crtc == NULL)
2660                 return -ENOMEM;
2661
2662         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2663
2664         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2665         amdgpu_crtc->crtc_id = index;
2666         adev->mode_info.crtcs[index] = amdgpu_crtc;
2667
2668         amdgpu_crtc->max_cursor_width = 128;
2669         amdgpu_crtc->max_cursor_height = 128;
2670         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2671         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2672
2673         switch (amdgpu_crtc->crtc_id) {
2674         case 0:
2675         default:
2676                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2677                 break;
2678         case 1:
2679                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2680                 break;
2681         case 2:
2682                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2683                 break;
2684         case 3:
2685                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2686                 break;
2687         case 4:
2688                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2689                 break;
2690         case 5:
2691                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2692                 break;
2693         }
2694
2695         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2696         amdgpu_crtc->adjusted_clock = 0;
2697         amdgpu_crtc->encoder = NULL;
2698         amdgpu_crtc->connector = NULL;
2699         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2700
2701         return 0;
2702 }
2703
2704 static int dce_v10_0_early_init(void *handle)
2705 {
2706         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2707
2708         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2709         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2710
2711         dce_v10_0_set_display_funcs(adev);
2712
2713         adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2714
2715         switch (adev->asic_type) {
2716         case CHIP_FIJI:
2717         case CHIP_TONGA:
2718                 adev->mode_info.num_hpd = 6;
2719                 adev->mode_info.num_dig = 7;
2720                 break;
2721         default:
2722                 /* FIXME: not supported yet */
2723                 return -EINVAL;
2724         }
2725
2726         dce_v10_0_set_irq_funcs(adev);
2727
2728         return 0;
2729 }
2730
2731 static int dce_v10_0_sw_init(void *handle)
2732 {
2733         int r, i;
2734         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2735
2736         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2737                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2738                 if (r)
2739                         return r;
2740         }
2741
2742         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2743                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2744                 if (r)
2745                         return r;
2746         }
2747
2748         /* HPD hotplug */
2749         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2750         if (r)
2751                 return r;
2752
2753         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2754
2755         adev->ddev->mode_config.async_page_flip = true;
2756
2757         adev->ddev->mode_config.max_width = 16384;
2758         adev->ddev->mode_config.max_height = 16384;
2759
2760         adev->ddev->mode_config.preferred_depth = 24;
2761         adev->ddev->mode_config.prefer_shadow = 1;
2762
2763         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2764
2765         r = amdgpu_display_modeset_create_props(adev);
2766         if (r)
2767                 return r;
2768
2769         adev->ddev->mode_config.max_width = 16384;
2770         adev->ddev->mode_config.max_height = 16384;
2771
2772         /* allocate crtcs */
2773         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2774                 r = dce_v10_0_crtc_init(adev, i);
2775                 if (r)
2776                         return r;
2777         }
2778
2779         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2780                 amdgpu_display_print_display_setup(adev->ddev);
2781         else
2782                 return -EINVAL;
2783
2784         /* setup afmt */
2785         r = dce_v10_0_afmt_init(adev);
2786         if (r)
2787                 return r;
2788
2789         r = dce_v10_0_audio_init(adev);
2790         if (r)
2791                 return r;
2792
2793         drm_kms_helper_poll_init(adev->ddev);
2794
2795         adev->mode_info.mode_config_initialized = true;
2796         return 0;
2797 }
2798
2799 static int dce_v10_0_sw_fini(void *handle)
2800 {
2801         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2802
2803         kfree(adev->mode_info.bios_hardcoded_edid);
2804
2805         drm_kms_helper_poll_fini(adev->ddev);
2806
2807         dce_v10_0_audio_fini(adev);
2808
2809         dce_v10_0_afmt_fini(adev);
2810
2811         drm_mode_config_cleanup(adev->ddev);
2812         adev->mode_info.mode_config_initialized = false;
2813
2814         return 0;
2815 }
2816
2817 static int dce_v10_0_hw_init(void *handle)
2818 {
2819         int i;
2820         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2821
2822         dce_v10_0_init_golden_registers(adev);
2823
2824         /* disable vga render */
2825         dce_v10_0_set_vga_render_state(adev, false);
2826         /* init dig PHYs, disp eng pll */
2827         amdgpu_atombios_encoder_init_dig(adev);
2828         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2829
2830         /* initialize hpd */
2831         dce_v10_0_hpd_init(adev);
2832
2833         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2834                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2835         }
2836
2837         dce_v10_0_pageflip_interrupt_init(adev);
2838
2839         return 0;
2840 }
2841
2842 static int dce_v10_0_hw_fini(void *handle)
2843 {
2844         int i;
2845         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2846
2847         dce_v10_0_hpd_fini(adev);
2848
2849         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2850                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2851         }
2852
2853         dce_v10_0_pageflip_interrupt_fini(adev);
2854
2855         return 0;
2856 }
2857
2858 static int dce_v10_0_suspend(void *handle)
2859 {
2860         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2861
2862         adev->mode_info.bl_level =
2863                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2864
2865         return dce_v10_0_hw_fini(handle);
2866 }
2867
2868 static int dce_v10_0_resume(void *handle)
2869 {
2870         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2871         int ret;
2872
2873         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2874                                                            adev->mode_info.bl_level);
2875
2876         ret = dce_v10_0_hw_init(handle);
2877
2878         /* turn on the BL */
2879         if (adev->mode_info.bl_encoder) {
2880                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2881                                                                   adev->mode_info.bl_encoder);
2882                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2883                                                     bl_level);
2884         }
2885
2886         return ret;
2887 }
2888
2889 static bool dce_v10_0_is_idle(void *handle)
2890 {
2891         return true;
2892 }
2893
2894 static int dce_v10_0_wait_for_idle(void *handle)
2895 {
2896         return 0;
2897 }
2898
2899 static bool dce_v10_0_check_soft_reset(void *handle)
2900 {
2901         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2902
2903         return dce_v10_0_is_display_hung(adev);
2904 }
2905
2906 static int dce_v10_0_soft_reset(void *handle)
2907 {
2908         u32 srbm_soft_reset = 0, tmp;
2909         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2910
2911         if (dce_v10_0_is_display_hung(adev))
2912                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2913
2914         if (srbm_soft_reset) {
2915                 tmp = RREG32(mmSRBM_SOFT_RESET);
2916                 tmp |= srbm_soft_reset;
2917                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2918                 WREG32(mmSRBM_SOFT_RESET, tmp);
2919                 tmp = RREG32(mmSRBM_SOFT_RESET);
2920
2921                 udelay(50);
2922
2923                 tmp &= ~srbm_soft_reset;
2924                 WREG32(mmSRBM_SOFT_RESET, tmp);
2925                 tmp = RREG32(mmSRBM_SOFT_RESET);
2926
2927                 /* Wait a little for things to settle down */
2928                 udelay(50);
2929         }
2930         return 0;
2931 }
2932
2933 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2934                                                      int crtc,
2935                                                      enum amdgpu_interrupt_state state)
2936 {
2937         u32 lb_interrupt_mask;
2938
2939         if (crtc >= adev->mode_info.num_crtc) {
2940                 DRM_DEBUG("invalid crtc %d\n", crtc);
2941                 return;
2942         }
2943
2944         switch (state) {
2945         case AMDGPU_IRQ_STATE_DISABLE:
2946                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2947                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2948                                                   VBLANK_INTERRUPT_MASK, 0);
2949                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2950                 break;
2951         case AMDGPU_IRQ_STATE_ENABLE:
2952                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2953                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2954                                                   VBLANK_INTERRUPT_MASK, 1);
2955                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2956                 break;
2957         default:
2958                 break;
2959         }
2960 }
2961
2962 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2963                                                     int crtc,
2964                                                     enum amdgpu_interrupt_state state)
2965 {
2966         u32 lb_interrupt_mask;
2967
2968         if (crtc >= adev->mode_info.num_crtc) {
2969                 DRM_DEBUG("invalid crtc %d\n", crtc);
2970                 return;
2971         }
2972
2973         switch (state) {
2974         case AMDGPU_IRQ_STATE_DISABLE:
2975                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2976                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2977                                                   VLINE_INTERRUPT_MASK, 0);
2978                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2979                 break;
2980         case AMDGPU_IRQ_STATE_ENABLE:
2981                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2982                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2983                                                   VLINE_INTERRUPT_MASK, 1);
2984                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2985                 break;
2986         default:
2987                 break;
2988         }
2989 }
2990
2991 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
2992                                        struct amdgpu_irq_src *source,
2993                                        unsigned hpd,
2994                                        enum amdgpu_interrupt_state state)
2995 {
2996         u32 tmp;
2997
2998         if (hpd >= adev->mode_info.num_hpd) {
2999                 DRM_DEBUG("invalid hdp %d\n", hpd);
3000                 return 0;
3001         }
3002
3003         switch (state) {
3004         case AMDGPU_IRQ_STATE_DISABLE:
3005                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3006                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3007                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3008                 break;
3009         case AMDGPU_IRQ_STATE_ENABLE:
3010                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3011                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3012                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3013                 break;
3014         default:
3015                 break;
3016         }
3017
3018         return 0;
3019 }
3020
3021 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3022                                         struct amdgpu_irq_src *source,
3023                                         unsigned type,
3024                                         enum amdgpu_interrupt_state state)
3025 {
3026         switch (type) {
3027         case AMDGPU_CRTC_IRQ_VBLANK1:
3028                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3029                 break;
3030         case AMDGPU_CRTC_IRQ_VBLANK2:
3031                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3032                 break;
3033         case AMDGPU_CRTC_IRQ_VBLANK3:
3034                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3035                 break;
3036         case AMDGPU_CRTC_IRQ_VBLANK4:
3037                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3038                 break;
3039         case AMDGPU_CRTC_IRQ_VBLANK5:
3040                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3041                 break;
3042         case AMDGPU_CRTC_IRQ_VBLANK6:
3043                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3044                 break;
3045         case AMDGPU_CRTC_IRQ_VLINE1:
3046                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3047                 break;
3048         case AMDGPU_CRTC_IRQ_VLINE2:
3049                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3050                 break;
3051         case AMDGPU_CRTC_IRQ_VLINE3:
3052                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3053                 break;
3054         case AMDGPU_CRTC_IRQ_VLINE4:
3055                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3056                 break;
3057         case AMDGPU_CRTC_IRQ_VLINE5:
3058                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3059                 break;
3060         case AMDGPU_CRTC_IRQ_VLINE6:
3061                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3062                 break;
3063         default:
3064                 break;
3065         }
3066         return 0;
3067 }
3068
3069 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3070                                             struct amdgpu_irq_src *src,
3071                                             unsigned type,
3072                                             enum amdgpu_interrupt_state state)
3073 {
3074         u32 reg;
3075
3076         if (type >= adev->mode_info.num_crtc) {
3077                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3078                 return -EINVAL;
3079         }
3080
3081         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3082         if (state == AMDGPU_IRQ_STATE_DISABLE)
3083                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3084                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3085         else
3086                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3087                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3088
3089         return 0;
3090 }
3091
3092 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3093                                   struct amdgpu_irq_src *source,
3094                                   struct amdgpu_iv_entry *entry)
3095 {
3096         unsigned long flags;
3097         unsigned crtc_id;
3098         struct amdgpu_crtc *amdgpu_crtc;
3099         struct amdgpu_flip_work *works;
3100
3101         crtc_id = (entry->src_id - 8) >> 1;
3102         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3103
3104         if (crtc_id >= adev->mode_info.num_crtc) {
3105                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3106                 return -EINVAL;
3107         }
3108
3109         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3110             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3111                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3112                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3113
3114         /* IRQ could occur when in initial stage */
3115         if (amdgpu_crtc == NULL)
3116                 return 0;
3117
3118         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3119         works = amdgpu_crtc->pflip_works;
3120         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3121                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3122                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3123                                                  amdgpu_crtc->pflip_status,
3124                                                  AMDGPU_FLIP_SUBMITTED);
3125                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3126                 return 0;
3127         }
3128
3129         /* page flip completed. clean up */
3130         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3131         amdgpu_crtc->pflip_works = NULL;
3132
3133         /* wakeup usersapce */
3134         if (works->event)
3135                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3136
3137         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3138
3139         drm_crtc_vblank_put(&amdgpu_crtc->base);
3140         schedule_work(&works->unpin_work);
3141
3142         return 0;
3143 }
3144
3145 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3146                                   int hpd)
3147 {
3148         u32 tmp;
3149
3150         if (hpd >= adev->mode_info.num_hpd) {
3151                 DRM_DEBUG("invalid hdp %d\n", hpd);
3152                 return;
3153         }
3154
3155         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3156         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3157         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3158 }
3159
3160 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3161                                           int crtc)
3162 {
3163         u32 tmp;
3164
3165         if (crtc >= adev->mode_info.num_crtc) {
3166                 DRM_DEBUG("invalid crtc %d\n", crtc);
3167                 return;
3168         }
3169
3170         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3171         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3172         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3173 }
3174
3175 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3176                                          int crtc)
3177 {
3178         u32 tmp;
3179
3180         if (crtc >= adev->mode_info.num_crtc) {
3181                 DRM_DEBUG("invalid crtc %d\n", crtc);
3182                 return;
3183         }
3184
3185         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3186         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3187         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3188 }
3189
3190 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3191                               struct amdgpu_irq_src *source,
3192                               struct amdgpu_iv_entry *entry)
3193 {
3194         unsigned crtc = entry->src_id - 1;
3195         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3196         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3197
3198         switch (entry->src_data[0]) {
3199         case 0: /* vblank */
3200                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3201                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3202                 else
3203                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3204
3205                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3206                         drm_handle_vblank(adev->ddev, crtc);
3207                 }
3208                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3209
3210                 break;
3211         case 1: /* vline */
3212                 if (disp_int & interrupt_status_offsets[crtc].vline)
3213                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3214                 else
3215                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3216
3217                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3218
3219                 break;
3220         default:
3221                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3222                 break;
3223         }
3224
3225         return 0;
3226 }
3227
3228 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3229                              struct amdgpu_irq_src *source,
3230                              struct amdgpu_iv_entry *entry)
3231 {
3232         uint32_t disp_int, mask;
3233         unsigned hpd;
3234
3235         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3236                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3237                 return 0;
3238         }
3239
3240         hpd = entry->src_data[0];
3241         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3242         mask = interrupt_status_offsets[hpd].hpd;
3243
3244         if (disp_int & mask) {
3245                 dce_v10_0_hpd_int_ack(adev, hpd);
3246                 schedule_work(&adev->hotplug_work);
3247                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3248         }
3249
3250         return 0;
3251 }
3252
3253 static int dce_v10_0_set_clockgating_state(void *handle,
3254                                           enum amd_clockgating_state state)
3255 {
3256         return 0;
3257 }
3258
3259 static int dce_v10_0_set_powergating_state(void *handle,
3260                                           enum amd_powergating_state state)
3261 {
3262         return 0;
3263 }
3264
3265 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3266         .name = "dce_v10_0",
3267         .early_init = dce_v10_0_early_init,
3268         .late_init = NULL,
3269         .sw_init = dce_v10_0_sw_init,
3270         .sw_fini = dce_v10_0_sw_fini,
3271         .hw_init = dce_v10_0_hw_init,
3272         .hw_fini = dce_v10_0_hw_fini,
3273         .suspend = dce_v10_0_suspend,
3274         .resume = dce_v10_0_resume,
3275         .is_idle = dce_v10_0_is_idle,
3276         .wait_for_idle = dce_v10_0_wait_for_idle,
3277         .check_soft_reset = dce_v10_0_check_soft_reset,
3278         .soft_reset = dce_v10_0_soft_reset,
3279         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3280         .set_powergating_state = dce_v10_0_set_powergating_state,
3281 };
3282
3283 static void
3284 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3285                           struct drm_display_mode *mode,
3286                           struct drm_display_mode *adjusted_mode)
3287 {
3288         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3289
3290         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3291
3292         /* need to call this here rather than in prepare() since we need some crtc info */
3293         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3294
3295         /* set scaler clears this on some chips */
3296         dce_v10_0_set_interleave(encoder->crtc, mode);
3297
3298         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3299                 dce_v10_0_afmt_enable(encoder, true);
3300                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3301         }
3302 }
3303
3304 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3305 {
3306         struct amdgpu_device *adev = encoder->dev->dev_private;
3307         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3308         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3309
3310         if ((amdgpu_encoder->active_device &
3311              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3312             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3313              ENCODER_OBJECT_ID_NONE)) {
3314                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3315                 if (dig) {
3316                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3317                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3318                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3319                 }
3320         }
3321
3322         amdgpu_atombios_scratch_regs_lock(adev, true);
3323
3324         if (connector) {
3325                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3326
3327                 /* select the clock/data port if it uses a router */
3328                 if (amdgpu_connector->router.cd_valid)
3329                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3330
3331                 /* turn eDP panel on for mode set */
3332                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3333                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3334                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3335         }
3336
3337         /* this is needed for the pll/ss setup to work correctly in some cases */
3338         amdgpu_atombios_encoder_set_crtc_source(encoder);
3339         /* set up the FMT blocks */
3340         dce_v10_0_program_fmt(encoder);
3341 }
3342
3343 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3344 {
3345         struct drm_device *dev = encoder->dev;
3346         struct amdgpu_device *adev = dev->dev_private;
3347
3348         /* need to call this here as we need the crtc set up */
3349         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3350         amdgpu_atombios_scratch_regs_lock(adev, false);
3351 }
3352
3353 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3354 {
3355         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3356         struct amdgpu_encoder_atom_dig *dig;
3357
3358         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3359
3360         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3361                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3362                         dce_v10_0_afmt_enable(encoder, false);
3363                 dig = amdgpu_encoder->enc_priv;
3364                 dig->dig_encoder = -1;
3365         }
3366         amdgpu_encoder->active_device = 0;
3367 }
3368
3369 /* these are handled by the primary encoders */
3370 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3371 {
3372
3373 }
3374
3375 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3376 {
3377
3378 }
3379
3380 static void
3381 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3382                       struct drm_display_mode *mode,
3383                       struct drm_display_mode *adjusted_mode)
3384 {
3385
3386 }
3387
3388 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3389 {
3390
3391 }
3392
3393 static void
3394 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3395 {
3396
3397 }
3398
3399 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3400         .dpms = dce_v10_0_ext_dpms,
3401         .prepare = dce_v10_0_ext_prepare,
3402         .mode_set = dce_v10_0_ext_mode_set,
3403         .commit = dce_v10_0_ext_commit,
3404         .disable = dce_v10_0_ext_disable,
3405         /* no detect for TMDS/LVDS yet */
3406 };
3407
3408 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3409         .dpms = amdgpu_atombios_encoder_dpms,
3410         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3411         .prepare = dce_v10_0_encoder_prepare,
3412         .mode_set = dce_v10_0_encoder_mode_set,
3413         .commit = dce_v10_0_encoder_commit,
3414         .disable = dce_v10_0_encoder_disable,
3415         .detect = amdgpu_atombios_encoder_dig_detect,
3416 };
3417
3418 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3419         .dpms = amdgpu_atombios_encoder_dpms,
3420         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3421         .prepare = dce_v10_0_encoder_prepare,
3422         .mode_set = dce_v10_0_encoder_mode_set,
3423         .commit = dce_v10_0_encoder_commit,
3424         .detect = amdgpu_atombios_encoder_dac_detect,
3425 };
3426
3427 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3428 {
3429         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3430         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3431                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3432         kfree(amdgpu_encoder->enc_priv);
3433         drm_encoder_cleanup(encoder);
3434         kfree(amdgpu_encoder);
3435 }
3436
3437 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3438         .destroy = dce_v10_0_encoder_destroy,
3439 };
3440
3441 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3442                                  uint32_t encoder_enum,
3443                                  uint32_t supported_device,
3444                                  u16 caps)
3445 {
3446         struct drm_device *dev = adev->ddev;
3447         struct drm_encoder *encoder;
3448         struct amdgpu_encoder *amdgpu_encoder;
3449
3450         /* see if we already added it */
3451         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3452                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3453                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3454                         amdgpu_encoder->devices |= supported_device;
3455                         return;
3456                 }
3457
3458         }
3459
3460         /* add a new one */
3461         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3462         if (!amdgpu_encoder)
3463                 return;
3464
3465         encoder = &amdgpu_encoder->base;
3466         switch (adev->mode_info.num_crtc) {
3467         case 1:
3468                 encoder->possible_crtcs = 0x1;
3469                 break;
3470         case 2:
3471         default:
3472                 encoder->possible_crtcs = 0x3;
3473                 break;
3474         case 4:
3475                 encoder->possible_crtcs = 0xf;
3476                 break;
3477         case 6:
3478                 encoder->possible_crtcs = 0x3f;
3479                 break;
3480         }
3481
3482         amdgpu_encoder->enc_priv = NULL;
3483
3484         amdgpu_encoder->encoder_enum = encoder_enum;
3485         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3486         amdgpu_encoder->devices = supported_device;
3487         amdgpu_encoder->rmx_type = RMX_OFF;
3488         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3489         amdgpu_encoder->is_ext_encoder = false;
3490         amdgpu_encoder->caps = caps;
3491
3492         switch (amdgpu_encoder->encoder_id) {
3493         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3494         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3495                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3496                                  DRM_MODE_ENCODER_DAC, NULL);
3497                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3498                 break;
3499         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3500         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3501         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3502         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3503         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3504                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3505                         amdgpu_encoder->rmx_type = RMX_FULL;
3506                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3507                                          DRM_MODE_ENCODER_LVDS, NULL);
3508                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3509                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3510                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3511                                          DRM_MODE_ENCODER_DAC, NULL);
3512                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3513                 } else {
3514                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3515                                          DRM_MODE_ENCODER_TMDS, NULL);
3516                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3517                 }
3518                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3519                 break;
3520         case ENCODER_OBJECT_ID_SI170B:
3521         case ENCODER_OBJECT_ID_CH7303:
3522         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3523         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3524         case ENCODER_OBJECT_ID_TITFP513:
3525         case ENCODER_OBJECT_ID_VT1623:
3526         case ENCODER_OBJECT_ID_HDMI_SI1930:
3527         case ENCODER_OBJECT_ID_TRAVIS:
3528         case ENCODER_OBJECT_ID_NUTMEG:
3529                 /* these are handled by the primary encoders */
3530                 amdgpu_encoder->is_ext_encoder = true;
3531                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3532                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3533                                          DRM_MODE_ENCODER_LVDS, NULL);
3534                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3535                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3536                                          DRM_MODE_ENCODER_DAC, NULL);
3537                 else
3538                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3539                                          DRM_MODE_ENCODER_TMDS, NULL);
3540                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3541                 break;
3542         }
3543 }
3544
3545 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3546         .bandwidth_update = &dce_v10_0_bandwidth_update,
3547         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3548         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3549         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3550         .hpd_sense = &dce_v10_0_hpd_sense,
3551         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3552         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3553         .page_flip = &dce_v10_0_page_flip,
3554         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3555         .add_encoder = &dce_v10_0_encoder_add,
3556         .add_connector = &amdgpu_connector_add,
3557 };
3558
3559 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3560 {
3561         if (adev->mode_info.funcs == NULL)
3562                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3563 }
3564
3565 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3566         .set = dce_v10_0_set_crtc_irq_state,
3567         .process = dce_v10_0_crtc_irq,
3568 };
3569
3570 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3571         .set = dce_v10_0_set_pageflip_irq_state,
3572         .process = dce_v10_0_pageflip_irq,
3573 };
3574
3575 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3576         .set = dce_v10_0_set_hpd_irq_state,
3577         .process = dce_v10_0_hpd_irq,
3578 };
3579
3580 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3581 {
3582         if (adev->mode_info.num_crtc > 0)
3583                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3584         else
3585                 adev->crtc_irq.num_types = 0;
3586         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3587
3588         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3589         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3590
3591         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3592         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3593 }
3594
3595 const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3596 {
3597         .type = AMD_IP_BLOCK_TYPE_DCE,
3598         .major = 10,
3599         .minor = 0,
3600         .rev = 0,
3601         .funcs = &dce_v10_0_ip_funcs,
3602 };
3603
3604 const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3605 {
3606         .type = AMD_IP_BLOCK_TYPE_DCE,
3607         .major = 10,
3608         .minor = 1,
3609         .rev = 0,
3610         .funcs = &dce_v10_0_ip_funcs,
3611 };