2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
47 SDMA0_REGISTER_OFFSET,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55 static int cik_sdma_soft_reset(void *handle);
59 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
62 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
65 for (i = 0; i < adev->sdma.num_instances; i++) {
66 release_firmware(adev->sdma.instance[i].fw);
67 adev->sdma.instance[i].fw = NULL;
73 * Starting with CIK, the GPU has new asynchronous
74 * DMA engines. These engines are used for compute
75 * and gfx. There are two DMA engines (SDMA0, SDMA1)
76 * and each one supports 1 ring buffer used for gfx
77 * and 2 queues used for compute.
79 * The programming model is very similar to the CP
80 * (ring buffer, IBs, etc.), but sDMA has it's own
81 * packet format that is different from the PM4 format
82 * used by the CP. sDMA supports copying data, writing
83 * embedded data, solid fills, and a number of other
84 * things. It also has support for tiling/detiling of
89 * cik_sdma_init_microcode - load ucode images from disk
91 * @adev: amdgpu_device pointer
93 * Use the firmware interface to load the ucode images into
94 * the driver (not loaded into hw).
95 * Returns 0 on success, error on failure.
97 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
99 const char *chip_name;
105 switch (adev->asic_type) {
107 chip_name = "bonaire";
110 chip_name = "hawaii";
113 chip_name = "kaveri";
116 chip_name = "kabini";
119 chip_name = "mullins";
124 for (i = 0; i < adev->sdma.num_instances; i++) {
126 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
128 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
129 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
132 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
136 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
137 for (i = 0; i < adev->sdma.num_instances; i++) {
138 release_firmware(adev->sdma.instance[i].fw);
139 adev->sdma.instance[i].fw = NULL;
146 * cik_sdma_ring_get_rptr - get the current read pointer
148 * @ring: amdgpu ring pointer
150 * Get the current rptr from the hardware (CIK+).
152 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
156 rptr = ring->adev->wb.wb[ring->rptr_offs];
158 return (rptr & 0x3fffc) >> 2;
162 * cik_sdma_ring_get_wptr - get the current write pointer
164 * @ring: amdgpu ring pointer
166 * Get the current wptr from the hardware (CIK+).
168 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
170 struct amdgpu_device *adev = ring->adev;
172 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
176 * cik_sdma_ring_set_wptr - commit the write pointer
178 * @ring: amdgpu ring pointer
180 * Write the wptr back to the hardware (CIK+).
182 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
184 struct amdgpu_device *adev = ring->adev;
186 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
187 (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
190 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
192 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
195 for (i = 0; i < count; i++)
196 if (sdma && sdma->burst_nop && (i == 0))
197 amdgpu_ring_write(ring, ring->funcs->nop |
198 SDMA_NOP_COUNT(count - 1));
200 amdgpu_ring_write(ring, ring->funcs->nop);
204 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
206 * @ring: amdgpu ring pointer
207 * @ib: IB object to schedule
209 * Schedule an IB in the DMA ring (CIK).
211 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
212 struct amdgpu_ib *ib,
213 unsigned vmid, bool ctx_switch)
215 u32 extra_bits = vmid & 0xf;
217 /* IB packet must end on a 8 DW boundary */
218 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
220 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
221 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
222 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
223 amdgpu_ring_write(ring, ib->length_dw);
228 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
230 * @ring: amdgpu ring pointer
232 * Emit an hdp flush packet on the requested DMA ring.
234 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
236 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
237 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
241 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
243 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
245 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
246 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
247 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
248 amdgpu_ring_write(ring, ref_and_mask); /* reference */
249 amdgpu_ring_write(ring, ref_and_mask); /* mask */
250 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
254 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
256 * @ring: amdgpu ring pointer
257 * @fence: amdgpu fence object
259 * Add a DMA fence packet to the ring to write
260 * the fence seq number and DMA trap packet to generate
261 * an interrupt if needed (CIK).
263 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
266 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
267 /* write the fence */
268 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
269 amdgpu_ring_write(ring, lower_32_bits(addr));
270 amdgpu_ring_write(ring, upper_32_bits(addr));
271 amdgpu_ring_write(ring, lower_32_bits(seq));
273 /* optionally write high bits as well */
276 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
277 amdgpu_ring_write(ring, lower_32_bits(addr));
278 amdgpu_ring_write(ring, upper_32_bits(addr));
279 amdgpu_ring_write(ring, upper_32_bits(seq));
282 /* generate an interrupt */
283 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
287 * cik_sdma_gfx_stop - stop the gfx async dma engines
289 * @adev: amdgpu_device pointer
291 * Stop the gfx async dma ring buffers (CIK).
293 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
295 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
296 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
300 if ((adev->mman.buffer_funcs_ring == sdma0) ||
301 (adev->mman.buffer_funcs_ring == sdma1))
302 amdgpu_ttm_set_buffer_funcs_status(adev, false);
304 for (i = 0; i < adev->sdma.num_instances; i++) {
305 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
306 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
307 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
308 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
310 sdma0->ready = false;
311 sdma1->ready = false;
315 * cik_sdma_rlc_stop - stop the compute async dma engines
317 * @adev: amdgpu_device pointer
319 * Stop the compute async dma queues (CIK).
321 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
327 * cik_ctx_switch_enable - stop the async dma engines context switch
329 * @adev: amdgpu_device pointer
330 * @enable: enable/disable the DMA MEs context switch.
332 * Halt or unhalt the async dma engines context switch (VI).
334 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
336 u32 f32_cntl, phase_quantum = 0;
339 if (amdgpu_sdma_phase_quantum) {
340 unsigned value = amdgpu_sdma_phase_quantum;
343 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
344 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
345 value = (value + 1) >> 1;
348 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
349 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
350 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
351 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
352 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
353 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
355 "clamping sdma_phase_quantum to %uK clock cycles\n",
359 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
360 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
363 for (i = 0; i < adev->sdma.num_instances; i++) {
364 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
366 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
367 AUTO_CTXSW_ENABLE, 1);
368 if (amdgpu_sdma_phase_quantum) {
369 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
371 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
375 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
376 AUTO_CTXSW_ENABLE, 0);
379 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
384 * cik_sdma_enable - stop the async dma engines
386 * @adev: amdgpu_device pointer
387 * @enable: enable/disable the DMA MEs.
389 * Halt or unhalt the async dma engines (CIK).
391 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
397 cik_sdma_gfx_stop(adev);
398 cik_sdma_rlc_stop(adev);
401 for (i = 0; i < adev->sdma.num_instances; i++) {
402 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
404 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
406 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
407 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
412 * cik_sdma_gfx_resume - setup and start the async dma engines
414 * @adev: amdgpu_device pointer
416 * Set up the gfx DMA ring buffers and enable them (CIK).
417 * Returns 0 for success, error for failure.
419 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
421 struct amdgpu_ring *ring;
422 u32 rb_cntl, ib_cntl;
427 for (i = 0; i < adev->sdma.num_instances; i++) {
428 ring = &adev->sdma.instance[i].ring;
429 wb_offset = (ring->rptr_offs * 4);
431 mutex_lock(&adev->srbm_mutex);
432 for (j = 0; j < 16; j++) {
433 cik_srbm_select(adev, 0, 0, 0, j);
435 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
436 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
437 /* XXX SDMA RLC - todo */
439 cik_srbm_select(adev, 0, 0, 0, 0);
440 mutex_unlock(&adev->srbm_mutex);
442 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
443 adev->gfx.config.gb_addr_config & 0x70);
445 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
446 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
448 /* Set ring buffer size in dwords */
449 rb_bufsz = order_base_2(ring->ring_size / 4);
450 rb_cntl = rb_bufsz << 1;
452 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
453 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
455 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
457 /* Initialize the ring buffer's read and write pointers */
458 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
459 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
460 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
461 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
463 /* set the wb address whether it's enabled or not */
464 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
465 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
466 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
467 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
469 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
471 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
472 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
475 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
478 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
479 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
481 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
483 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
486 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
491 cik_sdma_enable(adev, true);
493 for (i = 0; i < adev->sdma.num_instances; i++) {
494 ring = &adev->sdma.instance[i].ring;
495 r = amdgpu_ring_test_ring(ring);
501 if (adev->mman.buffer_funcs_ring == ring)
502 amdgpu_ttm_set_buffer_funcs_status(adev, true);
509 * cik_sdma_rlc_resume - setup and start the async dma engines
511 * @adev: amdgpu_device pointer
513 * Set up the compute DMA queues and enable them (CIK).
514 * Returns 0 for success, error for failure.
516 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
523 * cik_sdma_load_microcode - load the sDMA ME ucode
525 * @adev: amdgpu_device pointer
527 * Loads the sDMA0/1 ucode.
528 * Returns 0 for success, -EINVAL if the ucode is not available.
530 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
532 const struct sdma_firmware_header_v1_0 *hdr;
533 const __le32 *fw_data;
538 cik_sdma_enable(adev, false);
540 for (i = 0; i < adev->sdma.num_instances; i++) {
541 if (!adev->sdma.instance[i].fw)
543 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
544 amdgpu_ucode_print_sdma_hdr(&hdr->header);
545 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
546 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
547 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
548 if (adev->sdma.instance[i].feature_version >= 20)
549 adev->sdma.instance[i].burst_nop = true;
550 fw_data = (const __le32 *)
551 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
552 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
553 for (j = 0; j < fw_size; j++)
554 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
555 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
562 * cik_sdma_start - setup and start the async dma engines
564 * @adev: amdgpu_device pointer
566 * Set up the DMA engines and enable them (CIK).
567 * Returns 0 for success, error for failure.
569 static int cik_sdma_start(struct amdgpu_device *adev)
573 r = cik_sdma_load_microcode(adev);
577 /* halt the engine before programing */
578 cik_sdma_enable(adev, false);
579 /* enable sdma ring preemption */
580 cik_ctx_switch_enable(adev, true);
582 /* start the gfx rings and rlc compute queues */
583 r = cik_sdma_gfx_resume(adev);
586 r = cik_sdma_rlc_resume(adev);
594 * cik_sdma_ring_test_ring - simple async dma engine test
596 * @ring: amdgpu_ring structure holding ring information
598 * Test the DMA engine by writing using it to write an
599 * value to memory. (CIK).
600 * Returns 0 for success, error for failure.
602 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
604 struct amdgpu_device *adev = ring->adev;
611 r = amdgpu_device_wb_get(adev, &index);
613 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
617 gpu_addr = adev->wb.gpu_addr + (index * 4);
619 adev->wb.wb[index] = cpu_to_le32(tmp);
621 r = amdgpu_ring_alloc(ring, 5);
623 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
624 amdgpu_device_wb_free(adev, index);
627 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
628 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
629 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
630 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
631 amdgpu_ring_write(ring, 0xDEADBEEF);
632 amdgpu_ring_commit(ring);
634 for (i = 0; i < adev->usec_timeout; i++) {
635 tmp = le32_to_cpu(adev->wb.wb[index]);
636 if (tmp == 0xDEADBEEF)
641 if (i < adev->usec_timeout) {
642 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
644 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
648 amdgpu_device_wb_free(adev, index);
654 * cik_sdma_ring_test_ib - test an IB on the DMA engine
656 * @ring: amdgpu_ring structure holding ring information
658 * Test a simple IB in the DMA ring (CIK).
659 * Returns 0 on success, error on failure.
661 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
663 struct amdgpu_device *adev = ring->adev;
665 struct dma_fence *f = NULL;
671 r = amdgpu_device_wb_get(adev, &index);
673 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
677 gpu_addr = adev->wb.gpu_addr + (index * 4);
679 adev->wb.wb[index] = cpu_to_le32(tmp);
680 memset(&ib, 0, sizeof(ib));
681 r = amdgpu_ib_get(adev, NULL, 256, &ib);
683 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
687 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
688 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
689 ib.ptr[1] = lower_32_bits(gpu_addr);
690 ib.ptr[2] = upper_32_bits(gpu_addr);
692 ib.ptr[4] = 0xDEADBEEF;
694 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
698 r = dma_fence_wait_timeout(f, false, timeout);
700 DRM_ERROR("amdgpu: IB test timed out\n");
704 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
707 tmp = le32_to_cpu(adev->wb.wb[index]);
708 if (tmp == 0xDEADBEEF) {
709 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
712 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
717 amdgpu_ib_free(adev, &ib, NULL);
720 amdgpu_device_wb_free(adev, index);
725 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
727 * @ib: indirect buffer to fill with commands
728 * @pe: addr of the page entry
729 * @src: src addr to copy from
730 * @count: number of page entries to update
732 * Update PTEs by copying them from the GART using sDMA (CIK).
734 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
735 uint64_t pe, uint64_t src,
738 unsigned bytes = count * 8;
740 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
741 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
742 ib->ptr[ib->length_dw++] = bytes;
743 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
744 ib->ptr[ib->length_dw++] = lower_32_bits(src);
745 ib->ptr[ib->length_dw++] = upper_32_bits(src);
746 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
747 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
751 * cik_sdma_vm_write_pages - update PTEs by writing them manually
753 * @ib: indirect buffer to fill with commands
754 * @pe: addr of the page entry
755 * @value: dst addr to write into pe
756 * @count: number of page entries to update
757 * @incr: increase next addr by incr bytes
759 * Update PTEs by writing them manually using sDMA (CIK).
761 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
762 uint64_t value, unsigned count,
765 unsigned ndw = count * 2;
767 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
768 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
769 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
770 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
771 ib->ptr[ib->length_dw++] = ndw;
772 for (; ndw > 0; ndw -= 2) {
773 ib->ptr[ib->length_dw++] = lower_32_bits(value);
774 ib->ptr[ib->length_dw++] = upper_32_bits(value);
780 * cik_sdma_vm_set_pages - update the page tables using sDMA
782 * @ib: indirect buffer to fill with commands
783 * @pe: addr of the page entry
784 * @addr: dst addr to write into pe
785 * @count: number of page entries to update
786 * @incr: increase next addr by incr bytes
787 * @flags: access flags
789 * Update the page tables using sDMA (CIK).
791 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
792 uint64_t addr, unsigned count,
793 uint32_t incr, uint64_t flags)
795 /* for physically contiguous pages (vram) */
796 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
797 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
798 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
799 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
800 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
801 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
802 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
803 ib->ptr[ib->length_dw++] = incr; /* increment size */
804 ib->ptr[ib->length_dw++] = 0;
805 ib->ptr[ib->length_dw++] = count; /* number of entries */
809 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
811 * @ib: indirect buffer to fill with padding
814 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
816 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
820 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
821 for (i = 0; i < pad_count; i++)
822 if (sdma && sdma->burst_nop && (i == 0))
823 ib->ptr[ib->length_dw++] =
824 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
825 SDMA_NOP_COUNT(pad_count - 1);
827 ib->ptr[ib->length_dw++] =
828 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
832 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
834 * @ring: amdgpu_ring pointer
836 * Make sure all previous operations are completed (CIK).
838 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
840 uint32_t seq = ring->fence_drv.sync_seq;
841 uint64_t addr = ring->fence_drv.gpu_addr;
844 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
845 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
846 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
847 SDMA_POLL_REG_MEM_EXTRA_M));
848 amdgpu_ring_write(ring, addr & 0xfffffffc);
849 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
850 amdgpu_ring_write(ring, seq); /* reference */
851 amdgpu_ring_write(ring, 0xffffffff); /* mask */
852 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
856 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
858 * @ring: amdgpu_ring pointer
859 * @vm: amdgpu_vm pointer
861 * Update the page table base and flush the VM TLB
864 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
865 unsigned vmid, uint64_t pd_addr)
867 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
868 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
870 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
872 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
873 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
874 amdgpu_ring_write(ring, 0);
875 amdgpu_ring_write(ring, 0); /* reference */
876 amdgpu_ring_write(ring, 0); /* mask */
877 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
880 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
881 uint32_t reg, uint32_t val)
883 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
884 amdgpu_ring_write(ring, reg);
885 amdgpu_ring_write(ring, val);
888 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
893 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
894 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
895 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
897 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
900 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
902 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
905 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
909 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
914 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
915 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
918 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
920 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
923 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
925 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
928 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
930 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
933 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
937 static int cik_sdma_early_init(void *handle)
939 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
941 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
943 cik_sdma_set_ring_funcs(adev);
944 cik_sdma_set_irq_funcs(adev);
945 cik_sdma_set_buffer_funcs(adev);
946 cik_sdma_set_vm_pte_funcs(adev);
951 static int cik_sdma_sw_init(void *handle)
953 struct amdgpu_ring *ring;
954 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
957 r = cik_sdma_init_microcode(adev);
959 DRM_ERROR("Failed to load sdma firmware!\n");
963 /* SDMA trap event */
964 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
965 &adev->sdma.trap_irq);
969 /* SDMA Privileged inst */
970 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
971 &adev->sdma.illegal_inst_irq);
975 /* SDMA Privileged inst */
976 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
977 &adev->sdma.illegal_inst_irq);
981 for (i = 0; i < adev->sdma.num_instances; i++) {
982 ring = &adev->sdma.instance[i].ring;
983 ring->ring_obj = NULL;
984 sprintf(ring->name, "sdma%d", i);
985 r = amdgpu_ring_init(adev, ring, 1024,
986 &adev->sdma.trap_irq,
988 AMDGPU_SDMA_IRQ_TRAP0 :
989 AMDGPU_SDMA_IRQ_TRAP1);
997 static int cik_sdma_sw_fini(void *handle)
999 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002 for (i = 0; i < adev->sdma.num_instances; i++)
1003 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1005 cik_sdma_free_microcode(adev);
1009 static int cik_sdma_hw_init(void *handle)
1012 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1014 r = cik_sdma_start(adev);
1021 static int cik_sdma_hw_fini(void *handle)
1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025 cik_ctx_switch_enable(adev, false);
1026 cik_sdma_enable(adev, false);
1031 static int cik_sdma_suspend(void *handle)
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035 return cik_sdma_hw_fini(adev);
1038 static int cik_sdma_resume(void *handle)
1040 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1042 cik_sdma_soft_reset(handle);
1044 return cik_sdma_hw_init(adev);
1047 static bool cik_sdma_is_idle(void *handle)
1049 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050 u32 tmp = RREG32(mmSRBM_STATUS2);
1052 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1053 SRBM_STATUS2__SDMA1_BUSY_MASK))
1059 static int cik_sdma_wait_for_idle(void *handle)
1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1065 for (i = 0; i < adev->usec_timeout; i++) {
1066 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1067 SRBM_STATUS2__SDMA1_BUSY_MASK);
1076 static int cik_sdma_soft_reset(void *handle)
1078 u32 srbm_soft_reset = 0;
1079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1084 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1085 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1086 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1089 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1090 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1091 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1092 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1094 if (srbm_soft_reset) {
1095 tmp = RREG32(mmSRBM_SOFT_RESET);
1096 tmp |= srbm_soft_reset;
1097 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1098 WREG32(mmSRBM_SOFT_RESET, tmp);
1099 tmp = RREG32(mmSRBM_SOFT_RESET);
1103 tmp &= ~srbm_soft_reset;
1104 WREG32(mmSRBM_SOFT_RESET, tmp);
1105 tmp = RREG32(mmSRBM_SOFT_RESET);
1107 /* Wait a little for things to settle down */
1114 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1115 struct amdgpu_irq_src *src,
1117 enum amdgpu_interrupt_state state)
1122 case AMDGPU_SDMA_IRQ_TRAP0:
1124 case AMDGPU_IRQ_STATE_DISABLE:
1125 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1126 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1127 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1129 case AMDGPU_IRQ_STATE_ENABLE:
1130 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1131 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1132 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1138 case AMDGPU_SDMA_IRQ_TRAP1:
1140 case AMDGPU_IRQ_STATE_DISABLE:
1141 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1142 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1143 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1145 case AMDGPU_IRQ_STATE_ENABLE:
1146 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1147 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1148 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1160 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1161 struct amdgpu_irq_src *source,
1162 struct amdgpu_iv_entry *entry)
1164 u8 instance_id, queue_id;
1166 instance_id = (entry->ring_id & 0x3) >> 0;
1167 queue_id = (entry->ring_id & 0xc) >> 2;
1168 DRM_DEBUG("IH: SDMA trap\n");
1169 switch (instance_id) {
1173 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1186 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1201 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1202 struct amdgpu_irq_src *source,
1203 struct amdgpu_iv_entry *entry)
1205 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1206 schedule_work(&adev->reset_work);
1210 static int cik_sdma_set_clockgating_state(void *handle,
1211 enum amd_clockgating_state state)
1214 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1216 if (state == AMD_CG_STATE_GATE)
1219 cik_enable_sdma_mgcg(adev, gate);
1220 cik_enable_sdma_mgls(adev, gate);
1225 static int cik_sdma_set_powergating_state(void *handle,
1226 enum amd_powergating_state state)
1231 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1233 .early_init = cik_sdma_early_init,
1235 .sw_init = cik_sdma_sw_init,
1236 .sw_fini = cik_sdma_sw_fini,
1237 .hw_init = cik_sdma_hw_init,
1238 .hw_fini = cik_sdma_hw_fini,
1239 .suspend = cik_sdma_suspend,
1240 .resume = cik_sdma_resume,
1241 .is_idle = cik_sdma_is_idle,
1242 .wait_for_idle = cik_sdma_wait_for_idle,
1243 .soft_reset = cik_sdma_soft_reset,
1244 .set_clockgating_state = cik_sdma_set_clockgating_state,
1245 .set_powergating_state = cik_sdma_set_powergating_state,
1248 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1249 .type = AMDGPU_RING_TYPE_SDMA,
1251 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1252 .support_64bit_ptrs = false,
1253 .get_rptr = cik_sdma_ring_get_rptr,
1254 .get_wptr = cik_sdma_ring_get_wptr,
1255 .set_wptr = cik_sdma_ring_set_wptr,
1257 6 + /* cik_sdma_ring_emit_hdp_flush */
1258 3 + /* hdp invalidate */
1259 6 + /* cik_sdma_ring_emit_pipeline_sync */
1260 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1261 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1262 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1263 .emit_ib = cik_sdma_ring_emit_ib,
1264 .emit_fence = cik_sdma_ring_emit_fence,
1265 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1266 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1267 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1268 .test_ring = cik_sdma_ring_test_ring,
1269 .test_ib = cik_sdma_ring_test_ib,
1270 .insert_nop = cik_sdma_ring_insert_nop,
1271 .pad_ib = cik_sdma_ring_pad_ib,
1272 .emit_wreg = cik_sdma_ring_emit_wreg,
1275 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1279 for (i = 0; i < adev->sdma.num_instances; i++) {
1280 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1281 adev->sdma.instance[i].ring.me = i;
1285 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1286 .set = cik_sdma_set_trap_irq_state,
1287 .process = cik_sdma_process_trap_irq,
1290 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1291 .process = cik_sdma_process_illegal_inst_irq,
1294 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1296 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1297 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1298 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1302 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1304 * @ring: amdgpu_ring structure holding ring information
1305 * @src_offset: src GPU address
1306 * @dst_offset: dst GPU address
1307 * @byte_count: number of bytes to xfer
1309 * Copy GPU buffers using the DMA engine (CIK).
1310 * Used by the amdgpu ttm implementation to move pages if
1311 * registered as the asic copy callback.
1313 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1314 uint64_t src_offset,
1315 uint64_t dst_offset,
1316 uint32_t byte_count)
1318 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1319 ib->ptr[ib->length_dw++] = byte_count;
1320 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1321 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1322 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1323 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1324 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1328 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1330 * @ring: amdgpu_ring structure holding ring information
1331 * @src_data: value to write to buffer
1332 * @dst_offset: dst GPU address
1333 * @byte_count: number of bytes to xfer
1335 * Fill GPU buffers using the DMA engine (CIK).
1337 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1339 uint64_t dst_offset,
1340 uint32_t byte_count)
1342 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1343 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1344 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1345 ib->ptr[ib->length_dw++] = src_data;
1346 ib->ptr[ib->length_dw++] = byte_count;
1349 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1350 .copy_max_bytes = 0x1fffff,
1352 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1354 .fill_max_bytes = 0x1fffff,
1356 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1359 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1361 if (adev->mman.buffer_funcs == NULL) {
1362 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1363 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1367 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1368 .copy_pte_num_dw = 7,
1369 .copy_pte = cik_sdma_vm_copy_pte,
1371 .write_pte = cik_sdma_vm_write_pte,
1372 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1375 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1379 if (adev->vm_manager.vm_pte_funcs == NULL) {
1380 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1381 for (i = 0; i < adev->sdma.num_instances; i++)
1382 adev->vm_manager.vm_pte_rings[i] =
1383 &adev->sdma.instance[i].ring;
1385 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1389 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1391 .type = AMD_IP_BLOCK_TYPE_SDMA,
1395 .funcs = &cik_sdma_ip_funcs,