drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static int cik_sdma_soft_reset(void *handle);
  56
  57 /*(DEBLOBBED)*/
  58
  59 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  60
  61
  62 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  63 {
  64         int i;
  65         for (i = 0; i < adev->sdma.num_instances; i++) {
  66                         release_firmware(adev->sdma.instance[i].fw);
  67                         adev->sdma.instance[i].fw = NULL;
  68         }
  69 }
  70
  71 /*
  72  * sDMA - System DMA
  73  * Starting with CIK, the GPU has new asynchronous
  74  * DMA engines.  These engines are used for compute
  75  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  76  * and each one supports 1 ring buffer used for gfx
  77  * and 2 queues used for compute.
  78  *
  79  * The programming model is very similar to the CP
  80  * (ring buffer, IBs, etc.), but sDMA has it's own
  81  * packet format that is different from the PM4 format
  82  * used by the CP. sDMA supports copying data, writing
  83  * embedded data, solid fills, and a number of other
  84  * things.  It also has support for tiling/detiling of
  85  * buffers.
  86  */
  87
  88 /**
  89  * cik_sdma_init_microcode - load ucode images from disk
  90  *
  91  * @adev: amdgpu_device pointer
  92  *
  93  * Use the firmware interface to load the ucode images into
  94  * the driver (not loaded into hw).
  95  * Returns 0 on success, error on failure.
  96  */
  97 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  98 {
  99         const char *chip_name;
 100         char fw_name[30];
 101         int err = 0, i;
 102
 103         DRM_DEBUG("\n");
 104
 105         switch (adev->asic_type) {
 106         case CHIP_BONAIRE:
 107                 chip_name = "bonaire";
 108                 break;
 109         case CHIP_HAWAII:
 110                 chip_name = "hawaii";
 111                 break;
 112         case CHIP_KAVERI:
 113                 chip_name = "kaveri";
 114                 break;
 115         case CHIP_KABINI:
 116                 chip_name = "kabini";
 117                 break;
 118         case CHIP_MULLINS:
 119                 chip_name = "mullins";
 120                 break;
 121         default: BUG();
 122         }
 123
 124         for (i = 0; i < adev->sdma.num_instances; i++) {
 125                 if (i == 0)
 126                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 127                 else
 128                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 129                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 130                 if (err)
 131                         goto out;
 132                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 133         }
 134 out:
 135         if (err) {
 136                 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
 137                 for (i = 0; i < adev->sdma.num_instances; i++) {
 138                         release_firmware(adev->sdma.instance[i].fw);
 139                         adev->sdma.instance[i].fw = NULL;
 140                 }
 141         }
 142         return err;
 143 }
 144
 145 /**
 146  * cik_sdma_ring_get_rptr - get the current read pointer
 147  *
 148  * @ring: amdgpu ring pointer
 149  *
 150  * Get the current rptr from the hardware (CIK+).
 151  */
 152 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 153 {
 154         u32 rptr;
 155
 156         rptr = ring->adev->wb.wb[ring->rptr_offs];
 157
 158         return (rptr & 0x3fffc) >> 2;
 159 }
 160
 161 /**
 162  * cik_sdma_ring_get_wptr - get the current write pointer
 163  *
 164  * @ring: amdgpu ring pointer
 165  *
 166  * Get the current wptr from the hardware (CIK+).
 167  */
 168 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 169 {
 170         struct amdgpu_device *adev = ring->adev;
 171         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 172
 173         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 174 }
 175
 176 /**
 177  * cik_sdma_ring_set_wptr - commit the write pointer
 178  *
 179  * @ring: amdgpu ring pointer
 180  *
 181  * Write the wptr back to the hardware (CIK+).
 182  */
 183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 184 {
 185         struct amdgpu_device *adev = ring->adev;
 186         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 187
 188         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
 189                         (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
 190 }
 191
 192 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 193 {
 194         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 195         int i;
 196
 197         for (i = 0; i < count; i++)
 198                 if (sdma && sdma->burst_nop && (i == 0))
 199                         amdgpu_ring_write(ring, ring->funcs->nop |
 200                                           SDMA_NOP_COUNT(count - 1));
 201                 else
 202                         amdgpu_ring_write(ring, ring->funcs->nop);
 203 }
 204
 205 /**
 206  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 207  *
 208  * @ring: amdgpu ring pointer
 209  * @ib: IB object to schedule
 210  *
 211  * Schedule an IB in the DMA ring (CIK).
 212  */
 213 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 214                                   struct amdgpu_ib *ib,
 215                                   unsigned vm_id, bool ctx_switch)
 216 {
 217         u32 extra_bits = vm_id & 0xf;
 218
 219         /* IB packet must end on a 8 DW boundary */
 220         cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
 221
 222         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 223         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 224         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 225         amdgpu_ring_write(ring, ib->length_dw);
 226
 227 }
 228
 229 /**
 230  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 231  *
 232  * @ring: amdgpu ring pointer
 233  *
 234  * Emit an hdp flush packet on the requested DMA ring.
 235  */
 236 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 237 {
 238         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 239                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 240         u32 ref_and_mask;
 241
 242         if (ring == &ring->adev->sdma.instance[0].ring)
 243                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 244         else
 245                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 246
 247         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 248         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 249         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 250         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 251         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 252         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 253 }
 254
 255 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 256 {
 257         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 258         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 259         amdgpu_ring_write(ring, 1);
 260 }
 261
 262 /**
 263  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 264  *
 265  * @ring: amdgpu ring pointer
 266  * @fence: amdgpu fence object
 267  *
 268  * Add a DMA fence packet to the ring to write
 269  * the fence seq number and DMA trap packet to generate
 270  * an interrupt if needed (CIK).
 271  */
 272 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 273                                      unsigned flags)
 274 {
 275         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 276         /* write the fence */
 277         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 278         amdgpu_ring_write(ring, lower_32_bits(addr));
 279         amdgpu_ring_write(ring, upper_32_bits(addr));
 280         amdgpu_ring_write(ring, lower_32_bits(seq));
 281
 282         /* optionally write high bits as well */
 283         if (write64bit) {
 284                 addr += 4;
 285                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 286                 amdgpu_ring_write(ring, lower_32_bits(addr));
 287                 amdgpu_ring_write(ring, upper_32_bits(addr));
 288                 amdgpu_ring_write(ring, upper_32_bits(seq));
 289         }
 290
 291         /* generate an interrupt */
 292         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 293 }
 294
 295 /**
 296  * cik_sdma_gfx_stop - stop the gfx async dma engines
 297  *
 298  * @adev: amdgpu_device pointer
 299  *
 300  * Stop the gfx async dma ring buffers (CIK).
 301  */
 302 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 303 {
 304         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 305         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 306         u32 rb_cntl;
 307         int i;
 308
 309         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 310             (adev->mman.buffer_funcs_ring == sdma1))
 311                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 312
 313         for (i = 0; i < adev->sdma.num_instances; i++) {
 314                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 315                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 316                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 317                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 318         }
 319         sdma0->ready = false;
 320         sdma1->ready = false;
 321 }
 322
 323 /**
 324  * cik_sdma_rlc_stop - stop the compute async dma engines
 325  *
 326  * @adev: amdgpu_device pointer
 327  *
 328  * Stop the compute async dma queues (CIK).
 329  */
 330 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 331 {
 332         /* XXX todo */
 333 }
 334
 335 /**
 336  * cik_ctx_switch_enable - stop the async dma engines context switch
 337  *
 338  * @adev: amdgpu_device pointer
 339  * @enable: enable/disable the DMA MEs context switch.
 340  *
 341  * Halt or unhalt the async dma engines context switch (VI).
 342  */
 343 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 344 {
 345         u32 f32_cntl, phase_quantum = 0;
 346         int i;
 347
 348         if (amdgpu_sdma_phase_quantum) {
 349                 unsigned value = amdgpu_sdma_phase_quantum;
 350                 unsigned unit = 0;
 351
 352                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 353                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 354                         value = (value + 1) >> 1;
 355                         unit++;
 356                 }
 357                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 358                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 359                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 360                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 361                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 362                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 363                         WARN_ONCE(1,
 364                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 365                                   value << unit);
 366                 }
 367                 phase_quantum =
 368                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 369                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 370         }
 371
 372         for (i = 0; i < adev->sdma.num_instances; i++) {
 373                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 374                 if (enable) {
 375                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 376                                         AUTO_CTXSW_ENABLE, 1);
 377                         if (amdgpu_sdma_phase_quantum) {
 378                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 379                                        phase_quantum);
 380                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 381                                        phase_quantum);
 382                         }
 383                 } else {
 384                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 385                                         AUTO_CTXSW_ENABLE, 0);
 386                 }
 387
 388                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 389         }
 390 }
 391
 392 /**
 393  * cik_sdma_enable - stop the async dma engines
 394  *
 395  * @adev: amdgpu_device pointer
 396  * @enable: enable/disable the DMA MEs.
 397  *
 398  * Halt or unhalt the async dma engines (CIK).
 399  */
 400 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 401 {
 402         u32 me_cntl;
 403         int i;
 404
 405         if (!enable) {
 406                 cik_sdma_gfx_stop(adev);
 407                 cik_sdma_rlc_stop(adev);
 408         }
 409
 410         for (i = 0; i < adev->sdma.num_instances; i++) {
 411                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 412                 if (enable)
 413                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 414                 else
 415                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 416                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 417         }
 418 }
 419
 420 /**
 421  * cik_sdma_gfx_resume - setup and start the async dma engines
 422  *
 423  * @adev: amdgpu_device pointer
 424  *
 425  * Set up the gfx DMA ring buffers and enable them (CIK).
 426  * Returns 0 for success, error for failure.
 427  */
 428 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 429 {
 430         struct amdgpu_ring *ring;
 431         u32 rb_cntl, ib_cntl;
 432         u32 rb_bufsz;
 433         u32 wb_offset;
 434         int i, j, r;
 435
 436         for (i = 0; i < adev->sdma.num_instances; i++) {
 437                 ring = &adev->sdma.instance[i].ring;
 438                 wb_offset = (ring->rptr_offs * 4);
 439
 440                 mutex_lock(&adev->srbm_mutex);
 441                 for (j = 0; j < 16; j++) {
 442                         cik_srbm_select(adev, 0, 0, 0, j);
 443                         /* SDMA GFX */
 444                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 445                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 446                         /* XXX SDMA RLC - todo */
 447                 }
 448                 cik_srbm_select(adev, 0, 0, 0, 0);
 449                 mutex_unlock(&adev->srbm_mutex);
 450
 451                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 452                        adev->gfx.config.gb_addr_config & 0x70);
 453
 454                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 455                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 456
 457                 /* Set ring buffer size in dwords */
 458                 rb_bufsz = order_base_2(ring->ring_size / 4);
 459                 rb_cntl = rb_bufsz << 1;
 460 #ifdef __BIG_ENDIAN
 461                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 462                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 463 #endif
 464                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 465
 466                 /* Initialize the ring buffer's read and write pointers */
 467                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 468                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 469                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 470                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 471
 472                 /* set the wb address whether it's enabled or not */
 473                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 474                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 475                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 476                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 477
 478                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 479
 480                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 481                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 482
 483                 ring->wptr = 0;
 484                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 485
 486                 /* enable DMA RB */
 487                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 488                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 489
 490                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 491 #ifdef __BIG_ENDIAN
 492                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 493 #endif
 494                 /* enable DMA IBs */
 495                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 496
 497                 ring->ready = true;
 498         }
 499
 500         cik_sdma_enable(adev, true);
 501
 502         for (i = 0; i < adev->sdma.num_instances; i++) {
 503                 ring = &adev->sdma.instance[i].ring;
 504                 r = amdgpu_ring_test_ring(ring);
 505                 if (r) {
 506                         ring->ready = false;
 507                         return r;
 508                 }
 509
 510                 if (adev->mman.buffer_funcs_ring == ring)
 511                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 512         }
 513
 514         return 0;
 515 }
 516
 517 /**
 518  * cik_sdma_rlc_resume - setup and start the async dma engines
 519  *
 520  * @adev: amdgpu_device pointer
 521  *
 522  * Set up the compute DMA queues and enable them (CIK).
 523  * Returns 0 for success, error for failure.
 524  */
 525 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 526 {
 527         /* XXX todo */
 528         return 0;
 529 }
 530
 531 /**
 532  * cik_sdma_load_microcode - load the sDMA ME ucode
 533  *
 534  * @adev: amdgpu_device pointer
 535  *
 536  * Loads the sDMA0/1 ucode.
 537  * Returns 0 for success, -EINVAL if the ucode is not available.
 538  */
 539 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 540 {
 541         const struct sdma_firmware_header_v1_0 *hdr;
 542         const __le32 *fw_data;
 543         u32 fw_size;
 544         int i, j;
 545
 546         /* halt the MEs */
 547         cik_sdma_enable(adev, false);
 548
 549         for (i = 0; i < adev->sdma.num_instances; i++) {
 550                 if (!adev->sdma.instance[i].fw)
 551                         return -EINVAL;
 552                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 553                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 554                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 555                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 556                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 557                 if (adev->sdma.instance[i].feature_version >= 20)
 558                         adev->sdma.instance[i].burst_nop = true;
 559                 fw_data = (const __le32 *)
 560                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 561                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 562                 for (j = 0; j < fw_size; j++)
 563                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 564                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 565         }
 566
 567         return 0;
 568 }
 569
 570 /**
 571  * cik_sdma_start - setup and start the async dma engines
 572  *
 573  * @adev: amdgpu_device pointer
 574  *
 575  * Set up the DMA engines and enable them (CIK).
 576  * Returns 0 for success, error for failure.
 577  */
 578 static int cik_sdma_start(struct amdgpu_device *adev)
 579 {
 580         int r;
 581
 582         r = cik_sdma_load_microcode(adev);
 583         if (r)
 584                 return r;
 585
 586         /* halt the engine before programing */
 587         cik_sdma_enable(adev, false);
 588         /* enable sdma ring preemption */
 589         cik_ctx_switch_enable(adev, true);
 590
 591         /* start the gfx rings and rlc compute queues */
 592         r = cik_sdma_gfx_resume(adev);
 593         if (r)
 594                 return r;
 595         r = cik_sdma_rlc_resume(adev);
 596         if (r)
 597                 return r;
 598
 599         return 0;
 600 }
 601
 602 /**
 603  * cik_sdma_ring_test_ring - simple async dma engine test
 604  *
 605  * @ring: amdgpu_ring structure holding ring information
 606  *
 607  * Test the DMA engine by writing using it to write an
 608  * value to memory. (CIK).
 609  * Returns 0 for success, error for failure.
 610  */
 611 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 612 {
 613         struct amdgpu_device *adev = ring->adev;
 614         unsigned i;
 615         unsigned index;
 616         int r;
 617         u32 tmp;
 618         u64 gpu_addr;
 619
 620         r = amdgpu_wb_get(adev, &index);
 621         if (r) {
 622                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 623                 return r;
 624         }
 625
 626         gpu_addr = adev->wb.gpu_addr + (index * 4);
 627         tmp = 0xCAFEDEAD;
 628         adev->wb.wb[index] = cpu_to_le32(tmp);
 629
 630         r = amdgpu_ring_alloc(ring, 5);
 631         if (r) {
 632                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 633                 amdgpu_wb_free(adev, index);
 634                 return r;
 635         }
 636         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 637         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 638         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 639         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 640         amdgpu_ring_write(ring, 0xDEADBEEF);
 641         amdgpu_ring_commit(ring);
 642
 643         for (i = 0; i < adev->usec_timeout; i++) {
 644                 tmp = le32_to_cpu(adev->wb.wb[index]);
 645                 if (tmp == 0xDEADBEEF)
 646                         break;
 647                 DRM_UDELAY(1);
 648         }
 649
 650         if (i < adev->usec_timeout) {
 651                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 652         } else {
 653                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 654                           ring->idx, tmp);
 655                 r = -EINVAL;
 656         }
 657         amdgpu_wb_free(adev, index);
 658
 659         return r;
 660 }
 661
 662 /**
 663  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 664  *
 665  * @ring: amdgpu_ring structure holding ring information
 666  *
 667  * Test a simple IB in the DMA ring (CIK).
 668  * Returns 0 on success, error on failure.
 669  */
 670 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 671 {
 672         struct amdgpu_device *adev = ring->adev;
 673         struct amdgpu_ib ib;
 674         struct dma_fence *f = NULL;
 675         unsigned index;
 676         u32 tmp = 0;
 677         u64 gpu_addr;
 678         long r;
 679
 680         r = amdgpu_wb_get(adev, &index);
 681         if (r) {
 682                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 683                 return r;
 684         }
 685
 686         gpu_addr = adev->wb.gpu_addr + (index * 4);
 687         tmp = 0xCAFEDEAD;
 688         adev->wb.wb[index] = cpu_to_le32(tmp);
 689         memset(&ib, 0, sizeof(ib));
 690         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 691         if (r) {
 692                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 693                 goto err0;
 694         }
 695
 696         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 697                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 698         ib.ptr[1] = lower_32_bits(gpu_addr);
 699         ib.ptr[2] = upper_32_bits(gpu_addr);
 700         ib.ptr[3] = 1;
 701         ib.ptr[4] = 0xDEADBEEF;
 702         ib.length_dw = 5;
 703         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 704         if (r)
 705                 goto err1;
 706
 707         r = dma_fence_wait_timeout(f, false, timeout);
 708         if (r == 0) {
 709                 DRM_ERROR("amdgpu: IB test timed out\n");
 710                 r = -ETIMEDOUT;
 711                 goto err1;
 712         } else if (r < 0) {
 713                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 714                 goto err1;
 715         }
 716         tmp = le32_to_cpu(adev->wb.wb[index]);
 717         if (tmp == 0xDEADBEEF) {
 718                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 719                 r = 0;
 720         } else {
 721                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 722                 r = -EINVAL;
 723         }
 724
 725 err1:
 726         amdgpu_ib_free(adev, &ib, NULL);
 727         dma_fence_put(f);
 728 err0:
 729         amdgpu_wb_free(adev, index);
 730         return r;
 731 }
 732
 733 /**
 734  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 735  *
 736  * @ib: indirect buffer to fill with commands
 737  * @pe: addr of the page entry
 738  * @src: src addr to copy from
 739  * @count: number of page entries to update
 740  *
 741  * Update PTEs by copying them from the GART using sDMA (CIK).
 742  */
 743 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 744                                  uint64_t pe, uint64_t src,
 745                                  unsigned count)
 746 {
 747         unsigned bytes = count * 8;
 748
 749         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 750                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 751         ib->ptr[ib->length_dw++] = bytes;
 752         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 753         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 754         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 755         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 756         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 757 }
 758
 759 /**
 760  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 761  *
 762  * @ib: indirect buffer to fill with commands
 763  * @pe: addr of the page entry
 764  * @value: dst addr to write into pe
 765  * @count: number of page entries to update
 766  * @incr: increase next addr by incr bytes
 767  *
 768  * Update PTEs by writing them manually using sDMA (CIK).
 769  */
 770 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 771                                   uint64_t value, unsigned count,
 772                                   uint32_t incr)
 773 {
 774         unsigned ndw = count * 2;
 775
 776         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 777                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 778         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 779         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 780         ib->ptr[ib->length_dw++] = ndw;
 781         for (; ndw > 0; ndw -= 2) {
 782                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 783                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 784                 value += incr;
 785         }
 786 }
 787
 788 /**
 789  * cik_sdma_vm_set_pages - update the page tables using sDMA
 790  *
 791  * @ib: indirect buffer to fill with commands
 792  * @pe: addr of the page entry
 793  * @addr: dst addr to write into pe
 794  * @count: number of page entries to update
 795  * @incr: increase next addr by incr bytes
 796  * @flags: access flags
 797  *
 798  * Update the page tables using sDMA (CIK).
 799  */
 800 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 801                                     uint64_t addr, unsigned count,
 802                                     uint32_t incr, uint64_t flags)
 803 {
 804         /* for physically contiguous pages (vram) */
 805         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 806         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 807         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 808         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 809         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 810         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 811         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 812         ib->ptr[ib->length_dw++] = incr; /* increment size */
 813         ib->ptr[ib->length_dw++] = 0;
 814         ib->ptr[ib->length_dw++] = count; /* number of entries */
 815 }
 816
 817 /**
 818  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 819  *
 820  * @ib: indirect buffer to fill with padding
 821  *
 822  */
 823 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 824 {
 825         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 826         u32 pad_count;
 827         int i;
 828
 829         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 830         for (i = 0; i < pad_count; i++)
 831                 if (sdma && sdma->burst_nop && (i == 0))
 832                         ib->ptr[ib->length_dw++] =
 833                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 834                                         SDMA_NOP_COUNT(pad_count - 1);
 835                 else
 836                         ib->ptr[ib->length_dw++] =
 837                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 838 }
 839
 840 /**
 841  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 842  *
 843  * @ring: amdgpu_ring pointer
 844  *
 845  * Make sure all previous operations are completed (CIK).
 846  */
 847 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 848 {
 849         uint32_t seq = ring->fence_drv.sync_seq;
 850         uint64_t addr = ring->fence_drv.gpu_addr;
 851
 852         /* wait for idle */
 853         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 854                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 855                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 856                                             SDMA_POLL_REG_MEM_EXTRA_M));
 857         amdgpu_ring_write(ring, addr & 0xfffffffc);
 858         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 859         amdgpu_ring_write(ring, seq); /* reference */
 860         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 861         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 862 }
 863
 864 /**
 865  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 866  *
 867  * @ring: amdgpu_ring pointer
 868  * @vm: amdgpu_vm pointer
 869  *
 870  * Update the page table base and flush the VM TLB
 871  * using sDMA (CIK).
 872  */
 873 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 874                                         unsigned vm_id, uint64_t pd_addr)
 875 {
 876         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 877                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 878
 879         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 880         if (vm_id < 8) {
 881                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 882         } else {
 883                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 884         }
 885         amdgpu_ring_write(ring, pd_addr >> 12);
 886
 887         /* flush TLB */
 888         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 889         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 890         amdgpu_ring_write(ring, 1 << vm_id);
 891
 892         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 893         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 894         amdgpu_ring_write(ring, 0);
 895         amdgpu_ring_write(ring, 0); /* reference */
 896         amdgpu_ring_write(ring, 0); /* mask */
 897         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 898 }
 899
 900 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 901                                  bool enable)
 902 {
 903         u32 orig, data;
 904
 905         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 906                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 907                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 908         } else {
 909                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 910                 data |= 0xff000000;
 911                 if (data != orig)
 912                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 913
 914                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 915                 data |= 0xff000000;
 916                 if (data != orig)
 917                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 918         }
 919 }
 920
 921 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 922                                  bool enable)
 923 {
 924         u32 orig, data;
 925
 926         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 927                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 928                 data |= 0x100;
 929                 if (orig != data)
 930                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 931
 932                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 933                 data |= 0x100;
 934                 if (orig != data)
 935                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 936         } else {
 937                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 938                 data &= ~0x100;
 939                 if (orig != data)
 940                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 941
 942                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 943                 data &= ~0x100;
 944                 if (orig != data)
 945                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 946         }
 947 }
 948
 949 static int cik_sdma_early_init(void *handle)
 950 {
 951         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 952
 953         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 954
 955         cik_sdma_set_ring_funcs(adev);
 956         cik_sdma_set_irq_funcs(adev);
 957         cik_sdma_set_buffer_funcs(adev);
 958         cik_sdma_set_vm_pte_funcs(adev);
 959
 960         return 0;
 961 }
 962
 963 static int cik_sdma_sw_init(void *handle)
 964 {
 965         struct amdgpu_ring *ring;
 966         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 967         int r, i;
 968
 969         r = cik_sdma_init_microcode(adev);
 970         if (r) {
 971                 DRM_ERROR("Failed to load sdma firmware!\n");
 972                 return r;
 973         }
 974
 975         /* SDMA trap event */
 976         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
 977                               &adev->sdma.trap_irq);
 978         if (r)
 979                 return r;
 980
 981         /* SDMA Privileged inst */
 982         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
 983                               &adev->sdma.illegal_inst_irq);
 984         if (r)
 985                 return r;
 986
 987         /* SDMA Privileged inst */
 988         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
 989                               &adev->sdma.illegal_inst_irq);
 990         if (r)
 991                 return r;
 992
 993         for (i = 0; i < adev->sdma.num_instances; i++) {
 994                 ring = &adev->sdma.instance[i].ring;
 995                 ring->ring_obj = NULL;
 996                 sprintf(ring->name, "sdma%d", i);
 997                 r = amdgpu_ring_init(adev, ring, 1024,
 998                                      &adev->sdma.trap_irq,
 999                                      (i == 0) ?
1000                                      AMDGPU_SDMA_IRQ_TRAP0 :
1001                                      AMDGPU_SDMA_IRQ_TRAP1);
1002                 if (r)
1003                         return r;
1004         }
1005
1006         return r;
1007 }
1008
1009 static int cik_sdma_sw_fini(void *handle)
1010 {
1011         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1012         int i;
1013
1014         for (i = 0; i < adev->sdma.num_instances; i++)
1015                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1016
1017         cik_sdma_free_microcode(adev);
1018         return 0;
1019 }
1020
1021 static int cik_sdma_hw_init(void *handle)
1022 {
1023         int r;
1024         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025
1026         r = cik_sdma_start(adev);
1027         if (r)
1028                 return r;
1029
1030         return r;
1031 }
1032
1033 static int cik_sdma_hw_fini(void *handle)
1034 {
1035         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036
1037         cik_ctx_switch_enable(adev, false);
1038         cik_sdma_enable(adev, false);
1039
1040         return 0;
1041 }
1042
1043 static int cik_sdma_suspend(void *handle)
1044 {
1045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046
1047         return cik_sdma_hw_fini(adev);
1048 }
1049
1050 static int cik_sdma_resume(void *handle)
1051 {
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         cik_sdma_soft_reset(handle);
1055
1056         return cik_sdma_hw_init(adev);
1057 }
1058
1059 static bool cik_sdma_is_idle(void *handle)
1060 {
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062         u32 tmp = RREG32(mmSRBM_STATUS2);
1063
1064         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1065                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1066             return false;
1067
1068         return true;
1069 }
1070
1071 static int cik_sdma_wait_for_idle(void *handle)
1072 {
1073         unsigned i;
1074         u32 tmp;
1075         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1076
1077         for (i = 0; i < adev->usec_timeout; i++) {
1078                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1079                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1080
1081                 if (!tmp)
1082                         return 0;
1083                 udelay(1);
1084         }
1085         return -ETIMEDOUT;
1086 }
1087
1088 static int cik_sdma_soft_reset(void *handle)
1089 {
1090         u32 srbm_soft_reset = 0;
1091         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092         u32 tmp;
1093
1094         /* sdma0 */
1095         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1096         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1097         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1098         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1099
1100         /* sdma1 */
1101         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1102         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1103         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1104         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1105
1106         if (srbm_soft_reset) {
1107                 tmp = RREG32(mmSRBM_SOFT_RESET);
1108                 tmp |= srbm_soft_reset;
1109                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1110                 WREG32(mmSRBM_SOFT_RESET, tmp);
1111                 tmp = RREG32(mmSRBM_SOFT_RESET);
1112
1113                 udelay(50);
1114
1115                 tmp &= ~srbm_soft_reset;
1116                 WREG32(mmSRBM_SOFT_RESET, tmp);
1117                 tmp = RREG32(mmSRBM_SOFT_RESET);
1118
1119                 /* Wait a little for things to settle down */
1120                 udelay(50);
1121         }
1122
1123         return 0;
1124 }
1125
1126 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1127                                        struct amdgpu_irq_src *src,
1128                                        unsigned type,
1129                                        enum amdgpu_interrupt_state state)
1130 {
1131         u32 sdma_cntl;
1132
1133         switch (type) {
1134         case AMDGPU_SDMA_IRQ_TRAP0:
1135                 switch (state) {
1136                 case AMDGPU_IRQ_STATE_DISABLE:
1137                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1138                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1139                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1140                         break;
1141                 case AMDGPU_IRQ_STATE_ENABLE:
1142                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1143                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1144                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1145                         break;
1146                 default:
1147                         break;
1148                 }
1149                 break;
1150         case AMDGPU_SDMA_IRQ_TRAP1:
1151                 switch (state) {
1152                 case AMDGPU_IRQ_STATE_DISABLE:
1153                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1154                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1155                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1156                         break;
1157                 case AMDGPU_IRQ_STATE_ENABLE:
1158                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1159                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1160                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1161                         break;
1162                 default:
1163                         break;
1164                 }
1165                 break;
1166         default:
1167                 break;
1168         }
1169         return 0;
1170 }
1171
1172 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1173                                      struct amdgpu_irq_src *source,
1174                                      struct amdgpu_iv_entry *entry)
1175 {
1176         u8 instance_id, queue_id;
1177
1178         instance_id = (entry->ring_id & 0x3) >> 0;
1179         queue_id = (entry->ring_id & 0xc) >> 2;
1180         DRM_DEBUG("IH: SDMA trap\n");
1181         switch (instance_id) {
1182         case 0:
1183                 switch (queue_id) {
1184                 case 0:
1185                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1186                         break;
1187                 case 1:
1188                         /* XXX compute */
1189                         break;
1190                 case 2:
1191                         /* XXX compute */
1192                         break;
1193                 }
1194                 break;
1195         case 1:
1196                 switch (queue_id) {
1197                 case 0:
1198                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1199                         break;
1200                 case 1:
1201                         /* XXX compute */
1202                         break;
1203                 case 2:
1204                         /* XXX compute */
1205                         break;
1206                 }
1207                 break;
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1214                                              struct amdgpu_irq_src *source,
1215                                              struct amdgpu_iv_entry *entry)
1216 {
1217         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1218         schedule_work(&adev->reset_work);
1219         return 0;
1220 }
1221
1222 static int cik_sdma_set_clockgating_state(void *handle,
1223                                           enum amd_clockgating_state state)
1224 {
1225         bool gate = false;
1226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
1228         if (state == AMD_CG_STATE_GATE)
1229                 gate = true;
1230
1231         cik_enable_sdma_mgcg(adev, gate);
1232         cik_enable_sdma_mgls(adev, gate);
1233
1234         return 0;
1235 }
1236
1237 static int cik_sdma_set_powergating_state(void *handle,
1238                                           enum amd_powergating_state state)
1239 {
1240         return 0;
1241 }
1242
1243 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1244         .name = "cik_sdma",
1245         .early_init = cik_sdma_early_init,
1246         .late_init = NULL,
1247         .sw_init = cik_sdma_sw_init,
1248         .sw_fini = cik_sdma_sw_fini,
1249         .hw_init = cik_sdma_hw_init,
1250         .hw_fini = cik_sdma_hw_fini,
1251         .suspend = cik_sdma_suspend,
1252         .resume = cik_sdma_resume,
1253         .is_idle = cik_sdma_is_idle,
1254         .wait_for_idle = cik_sdma_wait_for_idle,
1255         .soft_reset = cik_sdma_soft_reset,
1256         .set_clockgating_state = cik_sdma_set_clockgating_state,
1257         .set_powergating_state = cik_sdma_set_powergating_state,
1258 };
1259
1260 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1261         .type = AMDGPU_RING_TYPE_SDMA,
1262         .align_mask = 0xf,
1263         .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1264         .support_64bit_ptrs = false,
1265         .get_rptr = cik_sdma_ring_get_rptr,
1266         .get_wptr = cik_sdma_ring_get_wptr,
1267         .set_wptr = cik_sdma_ring_set_wptr,
1268         .emit_frame_size =
1269                 6 + /* cik_sdma_ring_emit_hdp_flush */
1270                 3 + /* cik_sdma_ring_emit_hdp_invalidate */
1271                 6 + /* cik_sdma_ring_emit_pipeline_sync */
1272                 12 + /* cik_sdma_ring_emit_vm_flush */
1273                 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1274         .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1275         .emit_ib = cik_sdma_ring_emit_ib,
1276         .emit_fence = cik_sdma_ring_emit_fence,
1277         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1278         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1279         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1280         .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
1281         .test_ring = cik_sdma_ring_test_ring,
1282         .test_ib = cik_sdma_ring_test_ib,
1283         .insert_nop = cik_sdma_ring_insert_nop,
1284         .pad_ib = cik_sdma_ring_pad_ib,
1285 };
1286
1287 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1288 {
1289         int i;
1290
1291         for (i = 0; i < adev->sdma.num_instances; i++)
1292                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1293 }
1294
1295 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1296         .set = cik_sdma_set_trap_irq_state,
1297         .process = cik_sdma_process_trap_irq,
1298 };
1299
1300 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1301         .process = cik_sdma_process_illegal_inst_irq,
1302 };
1303
1304 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1305 {
1306         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1307         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1308         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1309 }
1310
1311 /**
1312  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1313  *
1314  * @ring: amdgpu_ring structure holding ring information
1315  * @src_offset: src GPU address
1316  * @dst_offset: dst GPU address
1317  * @byte_count: number of bytes to xfer
1318  *
1319  * Copy GPU buffers using the DMA engine (CIK).
1320  * Used by the amdgpu ttm implementation to move pages if
1321  * registered as the asic copy callback.
1322  */
1323 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1324                                       uint64_t src_offset,
1325                                       uint64_t dst_offset,
1326                                       uint32_t byte_count)
1327 {
1328         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1329         ib->ptr[ib->length_dw++] = byte_count;
1330         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1331         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1332         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1333         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1334         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1335 }
1336
1337 /**
1338  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1339  *
1340  * @ring: amdgpu_ring structure holding ring information
1341  * @src_data: value to write to buffer
1342  * @dst_offset: dst GPU address
1343  * @byte_count: number of bytes to xfer
1344  *
1345  * Fill GPU buffers using the DMA engine (CIK).
1346  */
1347 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1348                                       uint32_t src_data,
1349                                       uint64_t dst_offset,
1350                                       uint32_t byte_count)
1351 {
1352         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1353         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1354         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1355         ib->ptr[ib->length_dw++] = src_data;
1356         ib->ptr[ib->length_dw++] = byte_count;
1357 }
1358
1359 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1360         .copy_max_bytes = 0x1fffff,
1361         .copy_num_dw = 7,
1362         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1363
1364         .fill_max_bytes = 0x1fffff,
1365         .fill_num_dw = 5,
1366         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1367 };
1368
1369 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1370 {
1371         if (adev->mman.buffer_funcs == NULL) {
1372                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1373                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1374         }
1375 }
1376
1377 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1378         .copy_pte = cik_sdma_vm_copy_pte,
1379         .write_pte = cik_sdma_vm_write_pte,
1380         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1381 };
1382
1383 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1384 {
1385         unsigned i;
1386
1387         if (adev->vm_manager.vm_pte_funcs == NULL) {
1388                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1389                 for (i = 0; i < adev->sdma.num_instances; i++)
1390                         adev->vm_manager.vm_pte_rings[i] =
1391                                 &adev->sdma.instance[i].ring;
1392
1393                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1394         }
1395 }
1396
1397 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1398 {
1399         .type = AMD_IP_BLOCK_TYPE_SDMA,
1400         .major = 2,
1401         .minor = 0,
1402         .rev = 0,
1403         .funcs = &cik_sdma_ip_funcs,
1404 };