2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
47 SDMA0_REGISTER_OFFSET,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55 static int cik_sdma_soft_reset(void *handle);
59 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
62 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
65 for (i = 0; i < adev->sdma.num_instances; i++) {
66 release_firmware(adev->sdma.instance[i].fw);
67 adev->sdma.instance[i].fw = NULL;
73 * Starting with CIK, the GPU has new asynchronous
74 * DMA engines. These engines are used for compute
75 * and gfx. There are two DMA engines (SDMA0, SDMA1)
76 * and each one supports 1 ring buffer used for gfx
77 * and 2 queues used for compute.
79 * The programming model is very similar to the CP
80 * (ring buffer, IBs, etc.), but sDMA has it's own
81 * packet format that is different from the PM4 format
82 * used by the CP. sDMA supports copying data, writing
83 * embedded data, solid fills, and a number of other
84 * things. It also has support for tiling/detiling of
89 * cik_sdma_init_microcode - load ucode images from disk
91 * @adev: amdgpu_device pointer
93 * Use the firmware interface to load the ucode images into
94 * the driver (not loaded into hw).
95 * Returns 0 on success, error on failure.
97 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
99 const char *chip_name;
105 switch (adev->asic_type) {
107 chip_name = "bonaire";
110 chip_name = "hawaii";
113 chip_name = "kaveri";
116 chip_name = "kabini";
119 chip_name = "mullins";
124 for (i = 0; i < adev->sdma.num_instances; i++) {
126 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
128 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
129 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
132 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
137 "cik_sdma: Failed to load firmware \"%s\"\n",
139 for (i = 0; i < adev->sdma.num_instances; i++) {
140 release_firmware(adev->sdma.instance[i].fw);
141 adev->sdma.instance[i].fw = NULL;
148 * cik_sdma_ring_get_rptr - get the current read pointer
150 * @ring: amdgpu ring pointer
152 * Get the current rptr from the hardware (CIK+).
154 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
158 rptr = ring->adev->wb.wb[ring->rptr_offs];
160 return (rptr & 0x3fffc) >> 2;
164 * cik_sdma_ring_get_wptr - get the current write pointer
166 * @ring: amdgpu ring pointer
168 * Get the current wptr from the hardware (CIK+).
170 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
172 struct amdgpu_device *adev = ring->adev;
173 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
175 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
179 * cik_sdma_ring_set_wptr - commit the write pointer
181 * @ring: amdgpu ring pointer
183 * Write the wptr back to the hardware (CIK+).
185 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
187 struct amdgpu_device *adev = ring->adev;
188 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
190 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
193 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
195 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
198 for (i = 0; i < count; i++)
199 if (sdma && sdma->burst_nop && (i == 0))
200 amdgpu_ring_write(ring, ring->nop |
201 SDMA_NOP_COUNT(count - 1));
203 amdgpu_ring_write(ring, ring->nop);
207 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
209 * @ring: amdgpu ring pointer
210 * @ib: IB object to schedule
212 * Schedule an IB in the DMA ring (CIK).
214 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
215 struct amdgpu_ib *ib,
216 unsigned vm_id, bool ctx_switch)
218 u32 extra_bits = vm_id & 0xf;
220 /* IB packet must end on a 8 DW boundary */
221 cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
223 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
224 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
225 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
226 amdgpu_ring_write(ring, ib->length_dw);
231 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
233 * @ring: amdgpu ring pointer
235 * Emit an hdp flush packet on the requested DMA ring.
237 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
239 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
240 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
243 if (ring == &ring->adev->sdma.instance[0].ring)
244 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
246 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
248 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
249 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
250 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
251 amdgpu_ring_write(ring, ref_and_mask); /* reference */
252 amdgpu_ring_write(ring, ref_and_mask); /* mask */
253 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
256 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
258 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
259 amdgpu_ring_write(ring, mmHDP_DEBUG0);
260 amdgpu_ring_write(ring, 1);
264 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
266 * @ring: amdgpu ring pointer
267 * @fence: amdgpu fence object
269 * Add a DMA fence packet to the ring to write
270 * the fence seq number and DMA trap packet to generate
271 * an interrupt if needed (CIK).
273 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
276 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
277 /* write the fence */
278 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
279 amdgpu_ring_write(ring, lower_32_bits(addr));
280 amdgpu_ring_write(ring, upper_32_bits(addr));
281 amdgpu_ring_write(ring, lower_32_bits(seq));
283 /* optionally write high bits as well */
286 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
287 amdgpu_ring_write(ring, lower_32_bits(addr));
288 amdgpu_ring_write(ring, upper_32_bits(addr));
289 amdgpu_ring_write(ring, upper_32_bits(seq));
292 /* generate an interrupt */
293 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
297 * cik_sdma_gfx_stop - stop the gfx async dma engines
299 * @adev: amdgpu_device pointer
301 * Stop the gfx async dma ring buffers (CIK).
303 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
305 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
306 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
310 if ((adev->mman.buffer_funcs_ring == sdma0) ||
311 (adev->mman.buffer_funcs_ring == sdma1))
312 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
314 for (i = 0; i < adev->sdma.num_instances; i++) {
315 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
316 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
317 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
318 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
320 sdma0->ready = false;
321 sdma1->ready = false;
325 * cik_sdma_rlc_stop - stop the compute async dma engines
327 * @adev: amdgpu_device pointer
329 * Stop the compute async dma queues (CIK).
331 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
337 * cik_sdma_enable - stop the async dma engines
339 * @adev: amdgpu_device pointer
340 * @enable: enable/disable the DMA MEs.
342 * Halt or unhalt the async dma engines (CIK).
344 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
350 cik_sdma_gfx_stop(adev);
351 cik_sdma_rlc_stop(adev);
354 for (i = 0; i < adev->sdma.num_instances; i++) {
355 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
357 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
359 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
360 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
365 * cik_sdma_gfx_resume - setup and start the async dma engines
367 * @adev: amdgpu_device pointer
369 * Set up the gfx DMA ring buffers and enable them (CIK).
370 * Returns 0 for success, error for failure.
372 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
374 struct amdgpu_ring *ring;
375 u32 rb_cntl, ib_cntl;
380 for (i = 0; i < adev->sdma.num_instances; i++) {
381 ring = &adev->sdma.instance[i].ring;
382 wb_offset = (ring->rptr_offs * 4);
384 mutex_lock(&adev->srbm_mutex);
385 for (j = 0; j < 16; j++) {
386 cik_srbm_select(adev, 0, 0, 0, j);
388 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
389 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
390 /* XXX SDMA RLC - todo */
392 cik_srbm_select(adev, 0, 0, 0, 0);
393 mutex_unlock(&adev->srbm_mutex);
395 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
396 adev->gfx.config.gb_addr_config & 0x70);
398 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
399 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
401 /* Set ring buffer size in dwords */
402 rb_bufsz = order_base_2(ring->ring_size / 4);
403 rb_cntl = rb_bufsz << 1;
405 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
406 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
408 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
410 /* Initialize the ring buffer's read and write pointers */
411 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
412 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
413 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
414 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
416 /* set the wb address whether it's enabled or not */
417 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
418 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
419 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
420 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
422 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
424 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
425 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
428 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
431 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
432 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
434 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
436 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
439 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
444 cik_sdma_enable(adev, true);
446 for (i = 0; i < adev->sdma.num_instances; i++) {
447 ring = &adev->sdma.instance[i].ring;
448 r = amdgpu_ring_test_ring(ring);
454 if (adev->mman.buffer_funcs_ring == ring)
455 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
462 * cik_sdma_rlc_resume - setup and start the async dma engines
464 * @adev: amdgpu_device pointer
466 * Set up the compute DMA queues and enable them (CIK).
467 * Returns 0 for success, error for failure.
469 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
476 * cik_sdma_load_microcode - load the sDMA ME ucode
478 * @adev: amdgpu_device pointer
480 * Loads the sDMA0/1 ucode.
481 * Returns 0 for success, -EINVAL if the ucode is not available.
483 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
485 const struct sdma_firmware_header_v1_0 *hdr;
486 const __le32 *fw_data;
491 cik_sdma_enable(adev, false);
493 for (i = 0; i < adev->sdma.num_instances; i++) {
494 if (!adev->sdma.instance[i].fw)
496 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
497 amdgpu_ucode_print_sdma_hdr(&hdr->header);
498 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
499 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
500 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
501 if (adev->sdma.instance[i].feature_version >= 20)
502 adev->sdma.instance[i].burst_nop = true;
503 fw_data = (const __le32 *)
504 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
505 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
506 for (j = 0; j < fw_size; j++)
507 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
508 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
515 * cik_sdma_start - setup and start the async dma engines
517 * @adev: amdgpu_device pointer
519 * Set up the DMA engines and enable them (CIK).
520 * Returns 0 for success, error for failure.
522 static int cik_sdma_start(struct amdgpu_device *adev)
526 r = cik_sdma_load_microcode(adev);
530 /* halt the engine before programing */
531 cik_sdma_enable(adev, false);
533 /* start the gfx rings and rlc compute queues */
534 r = cik_sdma_gfx_resume(adev);
537 r = cik_sdma_rlc_resume(adev);
545 * cik_sdma_ring_test_ring - simple async dma engine test
547 * @ring: amdgpu_ring structure holding ring information
549 * Test the DMA engine by writing using it to write an
550 * value to memory. (CIK).
551 * Returns 0 for success, error for failure.
553 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
555 struct amdgpu_device *adev = ring->adev;
562 r = amdgpu_wb_get(adev, &index);
564 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
568 gpu_addr = adev->wb.gpu_addr + (index * 4);
570 adev->wb.wb[index] = cpu_to_le32(tmp);
572 r = amdgpu_ring_alloc(ring, 5);
574 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
575 amdgpu_wb_free(adev, index);
578 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
579 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
580 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
581 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
582 amdgpu_ring_write(ring, 0xDEADBEEF);
583 amdgpu_ring_commit(ring);
585 for (i = 0; i < adev->usec_timeout; i++) {
586 tmp = le32_to_cpu(adev->wb.wb[index]);
587 if (tmp == 0xDEADBEEF)
592 if (i < adev->usec_timeout) {
593 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
595 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
599 amdgpu_wb_free(adev, index);
605 * cik_sdma_ring_test_ib - test an IB on the DMA engine
607 * @ring: amdgpu_ring structure holding ring information
609 * Test a simple IB in the DMA ring (CIK).
610 * Returns 0 on success, error on failure.
612 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
614 struct amdgpu_device *adev = ring->adev;
616 struct fence *f = NULL;
622 r = amdgpu_wb_get(adev, &index);
624 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
628 gpu_addr = adev->wb.gpu_addr + (index * 4);
630 adev->wb.wb[index] = cpu_to_le32(tmp);
631 memset(&ib, 0, sizeof(ib));
632 r = amdgpu_ib_get(adev, NULL, 256, &ib);
634 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
638 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
639 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
640 ib.ptr[1] = lower_32_bits(gpu_addr);
641 ib.ptr[2] = upper_32_bits(gpu_addr);
643 ib.ptr[4] = 0xDEADBEEF;
645 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
649 r = fence_wait_timeout(f, false, timeout);
651 DRM_ERROR("amdgpu: IB test timed out\n");
655 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
658 tmp = le32_to_cpu(adev->wb.wb[index]);
659 if (tmp == 0xDEADBEEF) {
660 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
663 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
668 amdgpu_ib_free(adev, &ib, NULL);
671 amdgpu_wb_free(adev, index);
676 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
678 * @ib: indirect buffer to fill with commands
679 * @pe: addr of the page entry
680 * @src: src addr to copy from
681 * @count: number of page entries to update
683 * Update PTEs by copying them from the GART using sDMA (CIK).
685 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
686 uint64_t pe, uint64_t src,
689 unsigned bytes = count * 8;
691 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
692 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
693 ib->ptr[ib->length_dw++] = bytes;
694 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
695 ib->ptr[ib->length_dw++] = lower_32_bits(src);
696 ib->ptr[ib->length_dw++] = upper_32_bits(src);
697 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
698 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
702 * cik_sdma_vm_write_pages - update PTEs by writing them manually
704 * @ib: indirect buffer to fill with commands
705 * @pe: addr of the page entry
706 * @value: dst addr to write into pe
707 * @count: number of page entries to update
708 * @incr: increase next addr by incr bytes
710 * Update PTEs by writing them manually using sDMA (CIK).
712 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
713 uint64_t value, unsigned count,
716 unsigned ndw = count * 2;
718 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
719 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
720 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
721 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
722 ib->ptr[ib->length_dw++] = ndw;
723 for (; ndw > 0; ndw -= 2) {
724 ib->ptr[ib->length_dw++] = lower_32_bits(value);
725 ib->ptr[ib->length_dw++] = upper_32_bits(value);
731 * cik_sdma_vm_set_pages - update the page tables using sDMA
733 * @ib: indirect buffer to fill with commands
734 * @pe: addr of the page entry
735 * @addr: dst addr to write into pe
736 * @count: number of page entries to update
737 * @incr: increase next addr by incr bytes
738 * @flags: access flags
740 * Update the page tables using sDMA (CIK).
742 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
743 uint64_t addr, unsigned count,
744 uint32_t incr, uint32_t flags)
746 /* for physically contiguous pages (vram) */
747 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
748 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
749 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
750 ib->ptr[ib->length_dw++] = flags; /* mask */
751 ib->ptr[ib->length_dw++] = 0;
752 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
753 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
754 ib->ptr[ib->length_dw++] = incr; /* increment size */
755 ib->ptr[ib->length_dw++] = 0;
756 ib->ptr[ib->length_dw++] = count; /* number of entries */
760 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
762 * @ib: indirect buffer to fill with padding
765 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
767 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
771 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
772 for (i = 0; i < pad_count; i++)
773 if (sdma && sdma->burst_nop && (i == 0))
774 ib->ptr[ib->length_dw++] =
775 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
776 SDMA_NOP_COUNT(pad_count - 1);
778 ib->ptr[ib->length_dw++] =
779 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
783 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
785 * @ring: amdgpu_ring pointer
787 * Make sure all previous operations are completed (CIK).
789 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
791 uint32_t seq = ring->fence_drv.sync_seq;
792 uint64_t addr = ring->fence_drv.gpu_addr;
795 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
796 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
797 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
798 SDMA_POLL_REG_MEM_EXTRA_M));
799 amdgpu_ring_write(ring, addr & 0xfffffffc);
800 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
801 amdgpu_ring_write(ring, seq); /* reference */
802 amdgpu_ring_write(ring, 0xfffffff); /* mask */
803 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
807 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
809 * @ring: amdgpu_ring pointer
810 * @vm: amdgpu_vm pointer
812 * Update the page table base and flush the VM TLB
815 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
816 unsigned vm_id, uint64_t pd_addr)
818 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
819 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
821 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
823 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
825 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
827 amdgpu_ring_write(ring, pd_addr >> 12);
830 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
831 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
832 amdgpu_ring_write(ring, 1 << vm_id);
834 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
835 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
836 amdgpu_ring_write(ring, 0);
837 amdgpu_ring_write(ring, 0); /* reference */
838 amdgpu_ring_write(ring, 0); /* mask */
839 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
842 static unsigned cik_sdma_ring_get_emit_ib_size(struct amdgpu_ring *ring)
845 7 + 4; /* cik_sdma_ring_emit_ib */
848 static unsigned cik_sdma_ring_get_dma_frame_size(struct amdgpu_ring *ring)
851 6 + /* cik_sdma_ring_emit_hdp_flush */
852 3 + /* cik_sdma_ring_emit_hdp_invalidate */
853 6 + /* cik_sdma_ring_emit_pipeline_sync */
854 12 + /* cik_sdma_ring_emit_vm_flush */
855 9 + 9 + 9; /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
858 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
863 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
864 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
865 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
867 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
870 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
872 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
875 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
879 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
884 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
885 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
888 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
890 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
893 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
895 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
898 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
900 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
903 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
907 static int cik_sdma_early_init(void *handle)
909 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
911 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
913 cik_sdma_set_ring_funcs(adev);
914 cik_sdma_set_irq_funcs(adev);
915 cik_sdma_set_buffer_funcs(adev);
916 cik_sdma_set_vm_pte_funcs(adev);
921 static int cik_sdma_sw_init(void *handle)
923 struct amdgpu_ring *ring;
924 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
927 r = cik_sdma_init_microcode(adev);
929 DRM_ERROR("Failed to load sdma firmware!\n");
933 /* SDMA trap event */
934 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
938 /* SDMA Privileged inst */
939 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
943 /* SDMA Privileged inst */
944 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
948 for (i = 0; i < adev->sdma.num_instances; i++) {
949 ring = &adev->sdma.instance[i].ring;
950 ring->ring_obj = NULL;
951 sprintf(ring->name, "sdma%d", i);
952 r = amdgpu_ring_init(adev, ring, 1024,
953 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
954 &adev->sdma.trap_irq,
956 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
957 AMDGPU_RING_TYPE_SDMA);
965 static int cik_sdma_sw_fini(void *handle)
967 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
970 for (i = 0; i < adev->sdma.num_instances; i++)
971 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
973 cik_sdma_free_microcode(adev);
977 static int cik_sdma_hw_init(void *handle)
980 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
982 r = cik_sdma_start(adev);
989 static int cik_sdma_hw_fini(void *handle)
991 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
993 cik_sdma_enable(adev, false);
998 static int cik_sdma_suspend(void *handle)
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002 return cik_sdma_hw_fini(adev);
1005 static int cik_sdma_resume(void *handle)
1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1009 cik_sdma_soft_reset(handle);
1011 return cik_sdma_hw_init(adev);
1014 static bool cik_sdma_is_idle(void *handle)
1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017 u32 tmp = RREG32(mmSRBM_STATUS2);
1019 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1020 SRBM_STATUS2__SDMA1_BUSY_MASK))
1026 static int cik_sdma_wait_for_idle(void *handle)
1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032 for (i = 0; i < adev->usec_timeout; i++) {
1033 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1034 SRBM_STATUS2__SDMA1_BUSY_MASK);
1043 static int cik_sdma_soft_reset(void *handle)
1045 u32 srbm_soft_reset = 0;
1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1051 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1052 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1053 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1056 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1057 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1058 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1059 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1061 if (srbm_soft_reset) {
1062 tmp = RREG32(mmSRBM_SOFT_RESET);
1063 tmp |= srbm_soft_reset;
1064 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1065 WREG32(mmSRBM_SOFT_RESET, tmp);
1066 tmp = RREG32(mmSRBM_SOFT_RESET);
1070 tmp &= ~srbm_soft_reset;
1071 WREG32(mmSRBM_SOFT_RESET, tmp);
1072 tmp = RREG32(mmSRBM_SOFT_RESET);
1074 /* Wait a little for things to settle down */
1081 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1082 struct amdgpu_irq_src *src,
1084 enum amdgpu_interrupt_state state)
1089 case AMDGPU_SDMA_IRQ_TRAP0:
1091 case AMDGPU_IRQ_STATE_DISABLE:
1092 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1093 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1094 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1096 case AMDGPU_IRQ_STATE_ENABLE:
1097 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1098 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1099 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1105 case AMDGPU_SDMA_IRQ_TRAP1:
1107 case AMDGPU_IRQ_STATE_DISABLE:
1108 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1109 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1110 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1112 case AMDGPU_IRQ_STATE_ENABLE:
1113 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1114 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1115 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1127 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1128 struct amdgpu_irq_src *source,
1129 struct amdgpu_iv_entry *entry)
1131 u8 instance_id, queue_id;
1133 instance_id = (entry->ring_id & 0x3) >> 0;
1134 queue_id = (entry->ring_id & 0xc) >> 2;
1135 DRM_DEBUG("IH: SDMA trap\n");
1136 switch (instance_id) {
1140 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1153 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1168 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1169 struct amdgpu_irq_src *source,
1170 struct amdgpu_iv_entry *entry)
1172 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1173 schedule_work(&adev->reset_work);
1177 static int cik_sdma_set_clockgating_state(void *handle,
1178 enum amd_clockgating_state state)
1181 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183 if (state == AMD_CG_STATE_GATE)
1186 cik_enable_sdma_mgcg(adev, gate);
1187 cik_enable_sdma_mgls(adev, gate);
1192 static int cik_sdma_set_powergating_state(void *handle,
1193 enum amd_powergating_state state)
1198 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1200 .early_init = cik_sdma_early_init,
1202 .sw_init = cik_sdma_sw_init,
1203 .sw_fini = cik_sdma_sw_fini,
1204 .hw_init = cik_sdma_hw_init,
1205 .hw_fini = cik_sdma_hw_fini,
1206 .suspend = cik_sdma_suspend,
1207 .resume = cik_sdma_resume,
1208 .is_idle = cik_sdma_is_idle,
1209 .wait_for_idle = cik_sdma_wait_for_idle,
1210 .soft_reset = cik_sdma_soft_reset,
1211 .set_clockgating_state = cik_sdma_set_clockgating_state,
1212 .set_powergating_state = cik_sdma_set_powergating_state,
1215 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1216 .get_rptr = cik_sdma_ring_get_rptr,
1217 .get_wptr = cik_sdma_ring_get_wptr,
1218 .set_wptr = cik_sdma_ring_set_wptr,
1220 .emit_ib = cik_sdma_ring_emit_ib,
1221 .emit_fence = cik_sdma_ring_emit_fence,
1222 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1223 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1224 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1225 .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
1226 .test_ring = cik_sdma_ring_test_ring,
1227 .test_ib = cik_sdma_ring_test_ib,
1228 .insert_nop = cik_sdma_ring_insert_nop,
1229 .pad_ib = cik_sdma_ring_pad_ib,
1230 .get_emit_ib_size = cik_sdma_ring_get_emit_ib_size,
1231 .get_dma_frame_size = cik_sdma_ring_get_dma_frame_size,
1234 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1238 for (i = 0; i < adev->sdma.num_instances; i++)
1239 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1242 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1243 .set = cik_sdma_set_trap_irq_state,
1244 .process = cik_sdma_process_trap_irq,
1247 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1248 .process = cik_sdma_process_illegal_inst_irq,
1251 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1253 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1254 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1255 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1259 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1261 * @ring: amdgpu_ring structure holding ring information
1262 * @src_offset: src GPU address
1263 * @dst_offset: dst GPU address
1264 * @byte_count: number of bytes to xfer
1266 * Copy GPU buffers using the DMA engine (CIK).
1267 * Used by the amdgpu ttm implementation to move pages if
1268 * registered as the asic copy callback.
1270 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1271 uint64_t src_offset,
1272 uint64_t dst_offset,
1273 uint32_t byte_count)
1275 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1276 ib->ptr[ib->length_dw++] = byte_count;
1277 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1278 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1279 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1280 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1281 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1285 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1287 * @ring: amdgpu_ring structure holding ring information
1288 * @src_data: value to write to buffer
1289 * @dst_offset: dst GPU address
1290 * @byte_count: number of bytes to xfer
1292 * Fill GPU buffers using the DMA engine (CIK).
1294 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1296 uint64_t dst_offset,
1297 uint32_t byte_count)
1299 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1300 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1301 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1302 ib->ptr[ib->length_dw++] = src_data;
1303 ib->ptr[ib->length_dw++] = byte_count;
1306 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1307 .copy_max_bytes = 0x1fffff,
1309 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1311 .fill_max_bytes = 0x1fffff,
1313 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1316 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1318 if (adev->mman.buffer_funcs == NULL) {
1319 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1320 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1324 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1325 .copy_pte = cik_sdma_vm_copy_pte,
1326 .write_pte = cik_sdma_vm_write_pte,
1327 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1330 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1334 if (adev->vm_manager.vm_pte_funcs == NULL) {
1335 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1336 for (i = 0; i < adev->sdma.num_instances; i++)
1337 adev->vm_manager.vm_pte_rings[i] =
1338 &adev->sdma.instance[i].ring;
1340 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;