drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static int cik_sdma_soft_reset(void *handle);
  56
  57 /*(DEBLOBBED)*/
  58
  59 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  60
  61
  62 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  63 {
  64         int i;
  65         for (i = 0; i < adev->sdma.num_instances; i++) {
  66                         release_firmware(adev->sdma.instance[i].fw);
  67                         adev->sdma.instance[i].fw = NULL;
  68         }
  69 }
  70
  71 /*
  72  * sDMA - System DMA
  73  * Starting with CIK, the GPU has new asynchronous
  74  * DMA engines.  These engines are used for compute
  75  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  76  * and each one supports 1 ring buffer used for gfx
  77  * and 2 queues used for compute.
  78  *
  79  * The programming model is very similar to the CP
  80  * (ring buffer, IBs, etc.), but sDMA has it's own
  81  * packet format that is different from the PM4 format
  82  * used by the CP. sDMA supports copying data, writing
  83  * embedded data, solid fills, and a number of other
  84  * things.  It also has support for tiling/detiling of
  85  * buffers.
  86  */
  87
  88 /**
  89  * cik_sdma_init_microcode - load ucode images from disk
  90  *
  91  * @adev: amdgpu_device pointer
  92  *
  93  * Use the firmware interface to load the ucode images into
  94  * the driver (not loaded into hw).
  95  * Returns 0 on success, error on failure.
  96  */
  97 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  98 {
  99         const char *chip_name;
 100         char fw_name[30];
 101         int err = 0, i;
 102
 103         DRM_DEBUG("\n");
 104
 105         switch (adev->asic_type) {
 106         case CHIP_BONAIRE:
 107                 chip_name = "bonaire";
 108                 break;
 109         case CHIP_HAWAII:
 110                 chip_name = "hawaii";
 111                 break;
 112         case CHIP_KAVERI:
 113                 chip_name = "kaveri";
 114                 break;
 115         case CHIP_KABINI:
 116                 chip_name = "kabini";
 117                 break;
 118         case CHIP_MULLINS:
 119                 chip_name = "mullins";
 120                 break;
 121         default: BUG();
 122         }
 123
 124         for (i = 0; i < adev->sdma.num_instances; i++) {
 125                 if (i == 0)
 126                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 127                 else
 128                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 129                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 130                 if (err)
 131                         goto out;
 132                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 133         }
 134 out:
 135         if (err) {
 136                 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
 137                 for (i = 0; i < adev->sdma.num_instances; i++) {
 138                         release_firmware(adev->sdma.instance[i].fw);
 139                         adev->sdma.instance[i].fw = NULL;
 140                 }
 141         }
 142         return err;
 143 }
 144
 145 /**
 146  * cik_sdma_ring_get_rptr - get the current read pointer
 147  *
 148  * @ring: amdgpu ring pointer
 149  *
 150  * Get the current rptr from the hardware (CIK+).
 151  */
 152 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 153 {
 154         u32 rptr;
 155
 156         rptr = ring->adev->wb.wb[ring->rptr_offs];
 157
 158         return (rptr & 0x3fffc) >> 2;
 159 }
 160
 161 /**
 162  * cik_sdma_ring_get_wptr - get the current write pointer
 163  *
 164  * @ring: amdgpu ring pointer
 165  *
 166  * Get the current wptr from the hardware (CIK+).
 167  */
 168 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 169 {
 170         struct amdgpu_device *adev = ring->adev;
 171
 172         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
 173 }
 174
 175 /**
 176  * cik_sdma_ring_set_wptr - commit the write pointer
 177  *
 178  * @ring: amdgpu ring pointer
 179  *
 180  * Write the wptr back to the hardware (CIK+).
 181  */
 182 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 183 {
 184         struct amdgpu_device *adev = ring->adev;
 185
 186         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
 187                         (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
 188 }
 189
 190 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 191 {
 192         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 193         int i;
 194
 195         for (i = 0; i < count; i++)
 196                 if (sdma && sdma->burst_nop && (i == 0))
 197                         amdgpu_ring_write(ring, ring->funcs->nop |
 198                                           SDMA_NOP_COUNT(count - 1));
 199                 else
 200                         amdgpu_ring_write(ring, ring->funcs->nop);
 201 }
 202
 203 /**
 204  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 205  *
 206  * @ring: amdgpu ring pointer
 207  * @ib: IB object to schedule
 208  *
 209  * Schedule an IB in the DMA ring (CIK).
 210  */
 211 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 212                                   struct amdgpu_ib *ib,
 213                                   unsigned vmid, bool ctx_switch)
 214 {
 215         u32 extra_bits = vmid & 0xf;
 216
 217         /* IB packet must end on a 8 DW boundary */
 218         cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
 219
 220         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 221         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 222         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 223         amdgpu_ring_write(ring, ib->length_dw);
 224
 225 }
 226
 227 /**
 228  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 229  *
 230  * @ring: amdgpu ring pointer
 231  *
 232  * Emit an hdp flush packet on the requested DMA ring.
 233  */
 234 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 235 {
 236         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 237                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 238         u32 ref_and_mask;
 239
 240         if (ring->me == 0)
 241                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 242         else
 243                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 244
 245         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 246         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 247         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 248         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 249         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 250         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 251 }
 252
 253 /**
 254  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 255  *
 256  * @ring: amdgpu ring pointer
 257  * @fence: amdgpu fence object
 258  *
 259  * Add a DMA fence packet to the ring to write
 260  * the fence seq number and DMA trap packet to generate
 261  * an interrupt if needed (CIK).
 262  */
 263 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 264                                      unsigned flags)
 265 {
 266         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 267         /* write the fence */
 268         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 269         amdgpu_ring_write(ring, lower_32_bits(addr));
 270         amdgpu_ring_write(ring, upper_32_bits(addr));
 271         amdgpu_ring_write(ring, lower_32_bits(seq));
 272
 273         /* optionally write high bits as well */
 274         if (write64bit) {
 275                 addr += 4;
 276                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 277                 amdgpu_ring_write(ring, lower_32_bits(addr));
 278                 amdgpu_ring_write(ring, upper_32_bits(addr));
 279                 amdgpu_ring_write(ring, upper_32_bits(seq));
 280         }
 281
 282         /* generate an interrupt */
 283         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 284 }
 285
 286 /**
 287  * cik_sdma_gfx_stop - stop the gfx async dma engines
 288  *
 289  * @adev: amdgpu_device pointer
 290  *
 291  * Stop the gfx async dma ring buffers (CIK).
 292  */
 293 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 294 {
 295         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 296         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 297         u32 rb_cntl;
 298         int i;
 299
 300         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 301             (adev->mman.buffer_funcs_ring == sdma1))
 302                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 303
 304         for (i = 0; i < adev->sdma.num_instances; i++) {
 305                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 306                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 307                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 308                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 309         }
 310         sdma0->ready = false;
 311         sdma1->ready = false;
 312 }
 313
 314 /**
 315  * cik_sdma_rlc_stop - stop the compute async dma engines
 316  *
 317  * @adev: amdgpu_device pointer
 318  *
 319  * Stop the compute async dma queues (CIK).
 320  */
 321 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 322 {
 323         /* XXX todo */
 324 }
 325
 326 /**
 327  * cik_ctx_switch_enable - stop the async dma engines context switch
 328  *
 329  * @adev: amdgpu_device pointer
 330  * @enable: enable/disable the DMA MEs context switch.
 331  *
 332  * Halt or unhalt the async dma engines context switch (VI).
 333  */
 334 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 335 {
 336         u32 f32_cntl, phase_quantum = 0;
 337         int i;
 338
 339         if (amdgpu_sdma_phase_quantum) {
 340                 unsigned value = amdgpu_sdma_phase_quantum;
 341                 unsigned unit = 0;
 342
 343                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 344                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 345                         value = (value + 1) >> 1;
 346                         unit++;
 347                 }
 348                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 349                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 350                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 351                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 352                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 353                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 354                         WARN_ONCE(1,
 355                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 356                                   value << unit);
 357                 }
 358                 phase_quantum =
 359                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 360                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 361         }
 362
 363         for (i = 0; i < adev->sdma.num_instances; i++) {
 364                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 365                 if (enable) {
 366                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 367                                         AUTO_CTXSW_ENABLE, 1);
 368                         if (amdgpu_sdma_phase_quantum) {
 369                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 370                                        phase_quantum);
 371                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 372                                        phase_quantum);
 373                         }
 374                 } else {
 375                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 376                                         AUTO_CTXSW_ENABLE, 0);
 377                 }
 378
 379                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 380         }
 381 }
 382
 383 /**
 384  * cik_sdma_enable - stop the async dma engines
 385  *
 386  * @adev: amdgpu_device pointer
 387  * @enable: enable/disable the DMA MEs.
 388  *
 389  * Halt or unhalt the async dma engines (CIK).
 390  */
 391 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 392 {
 393         u32 me_cntl;
 394         int i;
 395
 396         if (!enable) {
 397                 cik_sdma_gfx_stop(adev);
 398                 cik_sdma_rlc_stop(adev);
 399         }
 400
 401         for (i = 0; i < adev->sdma.num_instances; i++) {
 402                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 403                 if (enable)
 404                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 405                 else
 406                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 407                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 408         }
 409 }
 410
 411 /**
 412  * cik_sdma_gfx_resume - setup and start the async dma engines
 413  *
 414  * @adev: amdgpu_device pointer
 415  *
 416  * Set up the gfx DMA ring buffers and enable them (CIK).
 417  * Returns 0 for success, error for failure.
 418  */
 419 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 420 {
 421         struct amdgpu_ring *ring;
 422         u32 rb_cntl, ib_cntl;
 423         u32 rb_bufsz;
 424         u32 wb_offset;
 425         int i, j, r;
 426
 427         for (i = 0; i < adev->sdma.num_instances; i++) {
 428                 ring = &adev->sdma.instance[i].ring;
 429                 wb_offset = (ring->rptr_offs * 4);
 430
 431                 mutex_lock(&adev->srbm_mutex);
 432                 for (j = 0; j < 16; j++) {
 433                         cik_srbm_select(adev, 0, 0, 0, j);
 434                         /* SDMA GFX */
 435                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 436                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 437                         /* XXX SDMA RLC - todo */
 438                 }
 439                 cik_srbm_select(adev, 0, 0, 0, 0);
 440                 mutex_unlock(&adev->srbm_mutex);
 441
 442                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 443                        adev->gfx.config.gb_addr_config & 0x70);
 444
 445                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 446                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 447
 448                 /* Set ring buffer size in dwords */
 449                 rb_bufsz = order_base_2(ring->ring_size / 4);
 450                 rb_cntl = rb_bufsz << 1;
 451 #ifdef __BIG_ENDIAN
 452                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 453                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 454 #endif
 455                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 456
 457                 /* Initialize the ring buffer's read and write pointers */
 458                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 459                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 460                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 461                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 462
 463                 /* set the wb address whether it's enabled or not */
 464                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 465                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 466                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 467                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 468
 469                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 470
 471                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 472                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 473
 474                 ring->wptr = 0;
 475                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 476
 477                 /* enable DMA RB */
 478                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 479                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 480
 481                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 482 #ifdef __BIG_ENDIAN
 483                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 484 #endif
 485                 /* enable DMA IBs */
 486                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 487
 488                 ring->ready = true;
 489         }
 490
 491         cik_sdma_enable(adev, true);
 492
 493         for (i = 0; i < adev->sdma.num_instances; i++) {
 494                 ring = &adev->sdma.instance[i].ring;
 495                 r = amdgpu_ring_test_ring(ring);
 496                 if (r) {
 497                         ring->ready = false;
 498                         return r;
 499                 }
 500
 501                 if (adev->mman.buffer_funcs_ring == ring)
 502                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 503         }
 504
 505         return 0;
 506 }
 507
 508 /**
 509  * cik_sdma_rlc_resume - setup and start the async dma engines
 510  *
 511  * @adev: amdgpu_device pointer
 512  *
 513  * Set up the compute DMA queues and enable them (CIK).
 514  * Returns 0 for success, error for failure.
 515  */
 516 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 517 {
 518         /* XXX todo */
 519         return 0;
 520 }
 521
 522 /**
 523  * cik_sdma_load_microcode - load the sDMA ME ucode
 524  *
 525  * @adev: amdgpu_device pointer
 526  *
 527  * Loads the sDMA0/1 ucode.
 528  * Returns 0 for success, -EINVAL if the ucode is not available.
 529  */
 530 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 531 {
 532         const struct sdma_firmware_header_v1_0 *hdr;
 533         const __le32 *fw_data;
 534         u32 fw_size;
 535         int i, j;
 536
 537         /* halt the MEs */
 538         cik_sdma_enable(adev, false);
 539
 540         for (i = 0; i < adev->sdma.num_instances; i++) {
 541                 if (!adev->sdma.instance[i].fw)
 542                         return -EINVAL;
 543                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 544                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 545                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 546                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 547                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 548                 if (adev->sdma.instance[i].feature_version >= 20)
 549                         adev->sdma.instance[i].burst_nop = true;
 550                 fw_data = (const __le32 *)
 551                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 552                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 553                 for (j = 0; j < fw_size; j++)
 554                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 555                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 556         }
 557
 558         return 0;
 559 }
 560
 561 /**
 562  * cik_sdma_start - setup and start the async dma engines
 563  *
 564  * @adev: amdgpu_device pointer
 565  *
 566  * Set up the DMA engines and enable them (CIK).
 567  * Returns 0 for success, error for failure.
 568  */
 569 static int cik_sdma_start(struct amdgpu_device *adev)
 570 {
 571         int r;
 572
 573         r = cik_sdma_load_microcode(adev);
 574         if (r)
 575                 return r;
 576
 577         /* halt the engine before programing */
 578         cik_sdma_enable(adev, false);
 579         /* enable sdma ring preemption */
 580         cik_ctx_switch_enable(adev, true);
 581
 582         /* start the gfx rings and rlc compute queues */
 583         r = cik_sdma_gfx_resume(adev);
 584         if (r)
 585                 return r;
 586         r = cik_sdma_rlc_resume(adev);
 587         if (r)
 588                 return r;
 589
 590         return 0;
 591 }
 592
 593 /**
 594  * cik_sdma_ring_test_ring - simple async dma engine test
 595  *
 596  * @ring: amdgpu_ring structure holding ring information
 597  *
 598  * Test the DMA engine by writing using it to write an
 599  * value to memory. (CIK).
 600  * Returns 0 for success, error for failure.
 601  */
 602 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 603 {
 604         struct amdgpu_device *adev = ring->adev;
 605         unsigned i;
 606         unsigned index;
 607         int r;
 608         u32 tmp;
 609         u64 gpu_addr;
 610
 611         r = amdgpu_device_wb_get(adev, &index);
 612         if (r) {
 613                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 614                 return r;
 615         }
 616
 617         gpu_addr = adev->wb.gpu_addr + (index * 4);
 618         tmp = 0xCAFEDEAD;
 619         adev->wb.wb[index] = cpu_to_le32(tmp);
 620
 621         r = amdgpu_ring_alloc(ring, 5);
 622         if (r) {
 623                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 624                 amdgpu_device_wb_free(adev, index);
 625                 return r;
 626         }
 627         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 628         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 629         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 630         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 631         amdgpu_ring_write(ring, 0xDEADBEEF);
 632         amdgpu_ring_commit(ring);
 633
 634         for (i = 0; i < adev->usec_timeout; i++) {
 635                 tmp = le32_to_cpu(adev->wb.wb[index]);
 636                 if (tmp == 0xDEADBEEF)
 637                         break;
 638                 DRM_UDELAY(1);
 639         }
 640
 641         if (i < adev->usec_timeout) {
 642                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 643         } else {
 644                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 645                           ring->idx, tmp);
 646                 r = -EINVAL;
 647         }
 648         amdgpu_device_wb_free(adev, index);
 649
 650         return r;
 651 }
 652
 653 /**
 654  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 655  *
 656  * @ring: amdgpu_ring structure holding ring information
 657  *
 658  * Test a simple IB in the DMA ring (CIK).
 659  * Returns 0 on success, error on failure.
 660  */
 661 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 662 {
 663         struct amdgpu_device *adev = ring->adev;
 664         struct amdgpu_ib ib;
 665         struct dma_fence *f = NULL;
 666         unsigned index;
 667         u32 tmp = 0;
 668         u64 gpu_addr;
 669         long r;
 670
 671         r = amdgpu_device_wb_get(adev, &index);
 672         if (r) {
 673                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 674                 return r;
 675         }
 676
 677         gpu_addr = adev->wb.gpu_addr + (index * 4);
 678         tmp = 0xCAFEDEAD;
 679         adev->wb.wb[index] = cpu_to_le32(tmp);
 680         memset(&ib, 0, sizeof(ib));
 681         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 682         if (r) {
 683                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 684                 goto err0;
 685         }
 686
 687         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 688                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 689         ib.ptr[1] = lower_32_bits(gpu_addr);
 690         ib.ptr[2] = upper_32_bits(gpu_addr);
 691         ib.ptr[3] = 1;
 692         ib.ptr[4] = 0xDEADBEEF;
 693         ib.length_dw = 5;
 694         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 695         if (r)
 696                 goto err1;
 697
 698         r = dma_fence_wait_timeout(f, false, timeout);
 699         if (r == 0) {
 700                 DRM_ERROR("amdgpu: IB test timed out\n");
 701                 r = -ETIMEDOUT;
 702                 goto err1;
 703         } else if (r < 0) {
 704                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 705                 goto err1;
 706         }
 707         tmp = le32_to_cpu(adev->wb.wb[index]);
 708         if (tmp == 0xDEADBEEF) {
 709                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 710                 r = 0;
 711         } else {
 712                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 713                 r = -EINVAL;
 714         }
 715
 716 err1:
 717         amdgpu_ib_free(adev, &ib, NULL);
 718         dma_fence_put(f);
 719 err0:
 720         amdgpu_device_wb_free(adev, index);
 721         return r;
 722 }
 723
 724 /**
 725  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 726  *
 727  * @ib: indirect buffer to fill with commands
 728  * @pe: addr of the page entry
 729  * @src: src addr to copy from
 730  * @count: number of page entries to update
 731  *
 732  * Update PTEs by copying them from the GART using sDMA (CIK).
 733  */
 734 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 735                                  uint64_t pe, uint64_t src,
 736                                  unsigned count)
 737 {
 738         unsigned bytes = count * 8;
 739
 740         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 741                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 742         ib->ptr[ib->length_dw++] = bytes;
 743         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 744         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 745         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 746         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 747         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 748 }
 749
 750 /**
 751  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 752  *
 753  * @ib: indirect buffer to fill with commands
 754  * @pe: addr of the page entry
 755  * @value: dst addr to write into pe
 756  * @count: number of page entries to update
 757  * @incr: increase next addr by incr bytes
 758  *
 759  * Update PTEs by writing them manually using sDMA (CIK).
 760  */
 761 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 762                                   uint64_t value, unsigned count,
 763                                   uint32_t incr)
 764 {
 765         unsigned ndw = count * 2;
 766
 767         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 768                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 769         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 770         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 771         ib->ptr[ib->length_dw++] = ndw;
 772         for (; ndw > 0; ndw -= 2) {
 773                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 774                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 775                 value += incr;
 776         }
 777 }
 778
 779 /**
 780  * cik_sdma_vm_set_pages - update the page tables using sDMA
 781  *
 782  * @ib: indirect buffer to fill with commands
 783  * @pe: addr of the page entry
 784  * @addr: dst addr to write into pe
 785  * @count: number of page entries to update
 786  * @incr: increase next addr by incr bytes
 787  * @flags: access flags
 788  *
 789  * Update the page tables using sDMA (CIK).
 790  */
 791 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 792                                     uint64_t addr, unsigned count,
 793                                     uint32_t incr, uint64_t flags)
 794 {
 795         /* for physically contiguous pages (vram) */
 796         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 797         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 798         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 799         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 800         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 801         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 802         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 803         ib->ptr[ib->length_dw++] = incr; /* increment size */
 804         ib->ptr[ib->length_dw++] = 0;
 805         ib->ptr[ib->length_dw++] = count; /* number of entries */
 806 }
 807
 808 /**
 809  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 810  *
 811  * @ib: indirect buffer to fill with padding
 812  *
 813  */
 814 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 815 {
 816         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 817         u32 pad_count;
 818         int i;
 819
 820         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 821         for (i = 0; i < pad_count; i++)
 822                 if (sdma && sdma->burst_nop && (i == 0))
 823                         ib->ptr[ib->length_dw++] =
 824                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 825                                         SDMA_NOP_COUNT(pad_count - 1);
 826                 else
 827                         ib->ptr[ib->length_dw++] =
 828                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 829 }
 830
 831 /**
 832  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 833  *
 834  * @ring: amdgpu_ring pointer
 835  *
 836  * Make sure all previous operations are completed (CIK).
 837  */
 838 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 839 {
 840         uint32_t seq = ring->fence_drv.sync_seq;
 841         uint64_t addr = ring->fence_drv.gpu_addr;
 842
 843         /* wait for idle */
 844         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 845                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 846                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 847                                             SDMA_POLL_REG_MEM_EXTRA_M));
 848         amdgpu_ring_write(ring, addr & 0xfffffffc);
 849         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 850         amdgpu_ring_write(ring, seq); /* reference */
 851         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 852         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 853 }
 854
 855 /**
 856  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 857  *
 858  * @ring: amdgpu_ring pointer
 859  * @vm: amdgpu_vm pointer
 860  *
 861  * Update the page table base and flush the VM TLB
 862  * using sDMA (CIK).
 863  */
 864 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 865                                         unsigned vmid, uint64_t pd_addr)
 866 {
 867         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 868                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 869
 870         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 871
 872         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 873         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 874         amdgpu_ring_write(ring, 0);
 875         amdgpu_ring_write(ring, 0); /* reference */
 876         amdgpu_ring_write(ring, 0); /* mask */
 877         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 878 }
 879
 880 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
 881                                     uint32_t reg, uint32_t val)
 882 {
 883         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 884         amdgpu_ring_write(ring, reg);
 885         amdgpu_ring_write(ring, val);
 886 }
 887
 888 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 889                                  bool enable)
 890 {
 891         u32 orig, data;
 892
 893         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 894                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 895                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 896         } else {
 897                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 898                 data |= 0xff000000;
 899                 if (data != orig)
 900                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 901
 902                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 903                 data |= 0xff000000;
 904                 if (data != orig)
 905                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 906         }
 907 }
 908
 909 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 910                                  bool enable)
 911 {
 912         u32 orig, data;
 913
 914         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 915                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 916                 data |= 0x100;
 917                 if (orig != data)
 918                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 919
 920                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 921                 data |= 0x100;
 922                 if (orig != data)
 923                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 924         } else {
 925                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 926                 data &= ~0x100;
 927                 if (orig != data)
 928                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 929
 930                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 931                 data &= ~0x100;
 932                 if (orig != data)
 933                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 934         }
 935 }
 936
 937 static int cik_sdma_early_init(void *handle)
 938 {
 939         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 940
 941         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 942
 943         cik_sdma_set_ring_funcs(adev);
 944         cik_sdma_set_irq_funcs(adev);
 945         cik_sdma_set_buffer_funcs(adev);
 946         cik_sdma_set_vm_pte_funcs(adev);
 947
 948         return 0;
 949 }
 950
 951 static int cik_sdma_sw_init(void *handle)
 952 {
 953         struct amdgpu_ring *ring;
 954         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 955         int r, i;
 956
 957         r = cik_sdma_init_microcode(adev);
 958         if (r) {
 959                 DRM_ERROR("Failed to load sdma firmware!\n");
 960                 return r;
 961         }
 962
 963         /* SDMA trap event */
 964         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
 965                               &adev->sdma.trap_irq);
 966         if (r)
 967                 return r;
 968
 969         /* SDMA Privileged inst */
 970         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
 971                               &adev->sdma.illegal_inst_irq);
 972         if (r)
 973                 return r;
 974
 975         /* SDMA Privileged inst */
 976         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
 977                               &adev->sdma.illegal_inst_irq);
 978         if (r)
 979                 return r;
 980
 981         for (i = 0; i < adev->sdma.num_instances; i++) {
 982                 ring = &adev->sdma.instance[i].ring;
 983                 ring->ring_obj = NULL;
 984                 sprintf(ring->name, "sdma%d", i);
 985                 r = amdgpu_ring_init(adev, ring, 1024,
 986                                      &adev->sdma.trap_irq,
 987                                      (i == 0) ?
 988                                      AMDGPU_SDMA_IRQ_TRAP0 :
 989                                      AMDGPU_SDMA_IRQ_TRAP1);
 990                 if (r)
 991                         return r;
 992         }
 993
 994         return r;
 995 }
 996
 997 static int cik_sdma_sw_fini(void *handle)
 998 {
 999         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1000         int i;
1001
1002         for (i = 0; i < adev->sdma.num_instances; i++)
1003                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1004
1005         cik_sdma_free_microcode(adev);
1006         return 0;
1007 }
1008
1009 static int cik_sdma_hw_init(void *handle)
1010 {
1011         int r;
1012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013
1014         r = cik_sdma_start(adev);
1015         if (r)
1016                 return r;
1017
1018         return r;
1019 }
1020
1021 static int cik_sdma_hw_fini(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         cik_ctx_switch_enable(adev, false);
1026         cik_sdma_enable(adev, false);
1027
1028         return 0;
1029 }
1030
1031 static int cik_sdma_suspend(void *handle)
1032 {
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         return cik_sdma_hw_fini(adev);
1036 }
1037
1038 static int cik_sdma_resume(void *handle)
1039 {
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041
1042         cik_sdma_soft_reset(handle);
1043
1044         return cik_sdma_hw_init(adev);
1045 }
1046
1047 static bool cik_sdma_is_idle(void *handle)
1048 {
1049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050         u32 tmp = RREG32(mmSRBM_STATUS2);
1051
1052         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1053                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1054             return false;
1055
1056         return true;
1057 }
1058
1059 static int cik_sdma_wait_for_idle(void *handle)
1060 {
1061         unsigned i;
1062         u32 tmp;
1063         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1064
1065         for (i = 0; i < adev->usec_timeout; i++) {
1066                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1067                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1068
1069                 if (!tmp)
1070                         return 0;
1071                 udelay(1);
1072         }
1073         return -ETIMEDOUT;
1074 }
1075
1076 static int cik_sdma_soft_reset(void *handle)
1077 {
1078         u32 srbm_soft_reset = 0;
1079         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1080         u32 tmp;
1081
1082         /* sdma0 */
1083         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1084         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1085         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1086         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1087
1088         /* sdma1 */
1089         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1090         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1091         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1092         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1093
1094         if (srbm_soft_reset) {
1095                 tmp = RREG32(mmSRBM_SOFT_RESET);
1096                 tmp |= srbm_soft_reset;
1097                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1098                 WREG32(mmSRBM_SOFT_RESET, tmp);
1099                 tmp = RREG32(mmSRBM_SOFT_RESET);
1100
1101                 udelay(50);
1102
1103                 tmp &= ~srbm_soft_reset;
1104                 WREG32(mmSRBM_SOFT_RESET, tmp);
1105                 tmp = RREG32(mmSRBM_SOFT_RESET);
1106
1107                 /* Wait a little for things to settle down */
1108                 udelay(50);
1109         }
1110
1111         return 0;
1112 }
1113
1114 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1115                                        struct amdgpu_irq_src *src,
1116                                        unsigned type,
1117                                        enum amdgpu_interrupt_state state)
1118 {
1119         u32 sdma_cntl;
1120
1121         switch (type) {
1122         case AMDGPU_SDMA_IRQ_TRAP0:
1123                 switch (state) {
1124                 case AMDGPU_IRQ_STATE_DISABLE:
1125                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1126                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1127                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1128                         break;
1129                 case AMDGPU_IRQ_STATE_ENABLE:
1130                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1131                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1132                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1133                         break;
1134                 default:
1135                         break;
1136                 }
1137                 break;
1138         case AMDGPU_SDMA_IRQ_TRAP1:
1139                 switch (state) {
1140                 case AMDGPU_IRQ_STATE_DISABLE:
1141                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1142                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1143                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1144                         break;
1145                 case AMDGPU_IRQ_STATE_ENABLE:
1146                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1147                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1148                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1149                         break;
1150                 default:
1151                         break;
1152                 }
1153                 break;
1154         default:
1155                 break;
1156         }
1157         return 0;
1158 }
1159
1160 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1161                                      struct amdgpu_irq_src *source,
1162                                      struct amdgpu_iv_entry *entry)
1163 {
1164         u8 instance_id, queue_id;
1165
1166         instance_id = (entry->ring_id & 0x3) >> 0;
1167         queue_id = (entry->ring_id & 0xc) >> 2;
1168         DRM_DEBUG("IH: SDMA trap\n");
1169         switch (instance_id) {
1170         case 0:
1171                 switch (queue_id) {
1172                 case 0:
1173                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1174                         break;
1175                 case 1:
1176                         /* XXX compute */
1177                         break;
1178                 case 2:
1179                         /* XXX compute */
1180                         break;
1181                 }
1182                 break;
1183         case 1:
1184                 switch (queue_id) {
1185                 case 0:
1186                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1187                         break;
1188                 case 1:
1189                         /* XXX compute */
1190                         break;
1191                 case 2:
1192                         /* XXX compute */
1193                         break;
1194                 }
1195                 break;
1196         }
1197
1198         return 0;
1199 }
1200
1201 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1202                                              struct amdgpu_irq_src *source,
1203                                              struct amdgpu_iv_entry *entry)
1204 {
1205         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1206         schedule_work(&adev->reset_work);
1207         return 0;
1208 }
1209
1210 static int cik_sdma_set_clockgating_state(void *handle,
1211                                           enum amd_clockgating_state state)
1212 {
1213         bool gate = false;
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215
1216         if (state == AMD_CG_STATE_GATE)
1217                 gate = true;
1218
1219         cik_enable_sdma_mgcg(adev, gate);
1220         cik_enable_sdma_mgls(adev, gate);
1221
1222         return 0;
1223 }
1224
1225 static int cik_sdma_set_powergating_state(void *handle,
1226                                           enum amd_powergating_state state)
1227 {
1228         return 0;
1229 }
1230
1231 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1232         .name = "cik_sdma",
1233         .early_init = cik_sdma_early_init,
1234         .late_init = NULL,
1235         .sw_init = cik_sdma_sw_init,
1236         .sw_fini = cik_sdma_sw_fini,
1237         .hw_init = cik_sdma_hw_init,
1238         .hw_fini = cik_sdma_hw_fini,
1239         .suspend = cik_sdma_suspend,
1240         .resume = cik_sdma_resume,
1241         .is_idle = cik_sdma_is_idle,
1242         .wait_for_idle = cik_sdma_wait_for_idle,
1243         .soft_reset = cik_sdma_soft_reset,
1244         .set_clockgating_state = cik_sdma_set_clockgating_state,
1245         .set_powergating_state = cik_sdma_set_powergating_state,
1246 };
1247
1248 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1249         .type = AMDGPU_RING_TYPE_SDMA,
1250         .align_mask = 0xf,
1251         .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1252         .support_64bit_ptrs = false,
1253         .get_rptr = cik_sdma_ring_get_rptr,
1254         .get_wptr = cik_sdma_ring_get_wptr,
1255         .set_wptr = cik_sdma_ring_set_wptr,
1256         .emit_frame_size =
1257                 6 + /* cik_sdma_ring_emit_hdp_flush */
1258                 3 + /* hdp invalidate */
1259                 6 + /* cik_sdma_ring_emit_pipeline_sync */
1260                 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1261                 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1262         .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1263         .emit_ib = cik_sdma_ring_emit_ib,
1264         .emit_fence = cik_sdma_ring_emit_fence,
1265         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1266         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1267         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1268         .test_ring = cik_sdma_ring_test_ring,
1269         .test_ib = cik_sdma_ring_test_ib,
1270         .insert_nop = cik_sdma_ring_insert_nop,
1271         .pad_ib = cik_sdma_ring_pad_ib,
1272         .emit_wreg = cik_sdma_ring_emit_wreg,
1273 };
1274
1275 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1276 {
1277         int i;
1278
1279         for (i = 0; i < adev->sdma.num_instances; i++) {
1280                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1281                 adev->sdma.instance[i].ring.me = i;
1282         }
1283 }
1284
1285 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1286         .set = cik_sdma_set_trap_irq_state,
1287         .process = cik_sdma_process_trap_irq,
1288 };
1289
1290 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1291         .process = cik_sdma_process_illegal_inst_irq,
1292 };
1293
1294 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1295 {
1296         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1297         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1298         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1299 }
1300
1301 /**
1302  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1303  *
1304  * @ring: amdgpu_ring structure holding ring information
1305  * @src_offset: src GPU address
1306  * @dst_offset: dst GPU address
1307  * @byte_count: number of bytes to xfer
1308  *
1309  * Copy GPU buffers using the DMA engine (CIK).
1310  * Used by the amdgpu ttm implementation to move pages if
1311  * registered as the asic copy callback.
1312  */
1313 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1314                                       uint64_t src_offset,
1315                                       uint64_t dst_offset,
1316                                       uint32_t byte_count)
1317 {
1318         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1319         ib->ptr[ib->length_dw++] = byte_count;
1320         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1321         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1322         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1323         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1324         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1325 }
1326
1327 /**
1328  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1329  *
1330  * @ring: amdgpu_ring structure holding ring information
1331  * @src_data: value to write to buffer
1332  * @dst_offset: dst GPU address
1333  * @byte_count: number of bytes to xfer
1334  *
1335  * Fill GPU buffers using the DMA engine (CIK).
1336  */
1337 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1338                                       uint32_t src_data,
1339                                       uint64_t dst_offset,
1340                                       uint32_t byte_count)
1341 {
1342         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1343         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1344         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1345         ib->ptr[ib->length_dw++] = src_data;
1346         ib->ptr[ib->length_dw++] = byte_count;
1347 }
1348
1349 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1350         .copy_max_bytes = 0x1fffff,
1351         .copy_num_dw = 7,
1352         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1353
1354         .fill_max_bytes = 0x1fffff,
1355         .fill_num_dw = 5,
1356         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1357 };
1358
1359 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1360 {
1361         if (adev->mman.buffer_funcs == NULL) {
1362                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1363                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1364         }
1365 }
1366
1367 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1368         .copy_pte_num_dw = 7,
1369         .copy_pte = cik_sdma_vm_copy_pte,
1370
1371         .write_pte = cik_sdma_vm_write_pte,
1372         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1373 };
1374
1375 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1376 {
1377         unsigned i;
1378
1379         if (adev->vm_manager.vm_pte_funcs == NULL) {
1380                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1381                 for (i = 0; i < adev->sdma.num_instances; i++)
1382                         adev->vm_manager.vm_pte_rings[i] =
1383                                 &adev->sdma.instance[i].ring;
1384
1385                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1386         }
1387 }
1388
1389 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1390 {
1391         .type = AMD_IP_BLOCK_TYPE_SDMA,
1392         .major = 2,
1393         .minor = 0,
1394         .rev = 0,
1395         .funcs = &cik_sdma_ip_funcs,
1396 };