drivers/gpu/drm/amd/amdgpu/cik.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "cikd.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "cik.h"
  38 #include "gmc_v7_0.h"
  39 #include "cik_ih.h"
  40 #include "dce_v8_0.h"
  41 #include "gfx_v7_0.h"
  42 #include "cik_sdma.h"
  43 #include "uvd_v4_2.h"
  44 #include "vce_v2_0.h"
  45 #include "cik_dpm.h"
  46
  47 #include "uvd/uvd_4_2_d.h"
  48
  49 #include "smu/smu_7_0_1_d.h"
  50 #include "smu/smu_7_0_1_sh_mask.h"
  51
  52 #include "dce/dce_8_0_d.h"
  53 #include "dce/dce_8_0_sh_mask.h"
  54
  55 #include "bif/bif_4_1_d.h"
  56 #include "bif/bif_4_1_sh_mask.h"
  57
  58 #include "gca/gfx_7_2_d.h"
  59 #include "gca/gfx_7_2_enum.h"
  60 #include "gca/gfx_7_2_sh_mask.h"
  61
  62 #include "gmc/gmc_7_1_d.h"
  63 #include "gmc/gmc_7_1_sh_mask.h"
  64
  65 #include "oss/oss_2_0_d.h"
  66 #include "oss/oss_2_0_sh_mask.h"
  67
  68 #include "amdgpu_dm.h"
  69 #include "amdgpu_amdkfd.h"
  70 #include "dce_virtual.h"
  71
  72 /*
  73  * Indirect registers accessor
  74  */
  75 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  76 {
  77         unsigned long flags;
  78         u32 r;
  79
  80         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  81         WREG32(mmPCIE_INDEX, reg);
  82         (void)RREG32(mmPCIE_INDEX);
  83         r = RREG32(mmPCIE_DATA);
  84         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  85         return r;
  86 }
  87
  88 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  89 {
  90         unsigned long flags;
  91
  92         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  93         WREG32(mmPCIE_INDEX, reg);
  94         (void)RREG32(mmPCIE_INDEX);
  95         WREG32(mmPCIE_DATA, v);
  96         (void)RREG32(mmPCIE_DATA);
  97         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  98 }
  99
 100 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)
 101 {
 102         unsigned long flags;
 103         u32 r;
 104
 105         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 106         WREG32(mmSMC_IND_INDEX_0, (reg));
 107         r = RREG32(mmSMC_IND_DATA_0);
 108         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 109         return r;
 110 }
 111
 112 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 113 {
 114         unsigned long flags;
 115
 116         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 117         WREG32(mmSMC_IND_INDEX_0, (reg));
 118         WREG32(mmSMC_IND_DATA_0, (v));
 119         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 120 }
 121
 122 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 123 {
 124         unsigned long flags;
 125         u32 r;
 126
 127         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 128         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 129         r = RREG32(mmUVD_CTX_DATA);
 130         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 131         return r;
 132 }
 133
 134 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 135 {
 136         unsigned long flags;
 137
 138         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 139         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 140         WREG32(mmUVD_CTX_DATA, (v));
 141         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 142 }
 143
 144 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)
 145 {
 146         unsigned long flags;
 147         u32 r;
 148
 149         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 150         WREG32(mmDIDT_IND_INDEX, (reg));
 151         r = RREG32(mmDIDT_IND_DATA);
 152         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 153         return r;
 154 }
 155
 156 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 157 {
 158         unsigned long flags;
 159
 160         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 161         WREG32(mmDIDT_IND_INDEX, (reg));
 162         WREG32(mmDIDT_IND_DATA, (v));
 163         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 164 }
 165
 166 static const u32 bonaire_golden_spm_registers[] =
 167 {
 168         0xc200, 0xe0ffffff, 0xe0000000
 169 };
 170
 171 static const u32 bonaire_golden_common_registers[] =
 172 {
 173         0x31dc, 0xffffffff, 0x00000800,
 174         0x31dd, 0xffffffff, 0x00000800,
 175         0x31e6, 0xffffffff, 0x00007fbf,
 176         0x31e7, 0xffffffff, 0x00007faf
 177 };
 178
 179 static const u32 bonaire_golden_registers[] =
 180 {
 181         0xcd5, 0x00000333, 0x00000333,
 182         0xcd4, 0x000c0fc0, 0x00040200,
 183         0x2684, 0x00010000, 0x00058208,
 184         0xf000, 0xffff1fff, 0x00140000,
 185         0xf080, 0xfdfc0fff, 0x00000100,
 186         0xf08d, 0x40000000, 0x40000200,
 187         0x260c, 0xffffffff, 0x00000000,
 188         0x260d, 0xf00fffff, 0x00000400,
 189         0x260e, 0x0002021c, 0x00020200,
 190         0x31e, 0x00000080, 0x00000000,
 191         0x16ec, 0x000000f0, 0x00000070,
 192         0x16f0, 0xf0311fff, 0x80300000,
 193         0x263e, 0x73773777, 0x12010001,
 194         0xd43, 0x00810000, 0x408af000,
 195         0x1c0c, 0x31000111, 0x00000011,
 196         0xbd2, 0x73773777, 0x12010001,
 197         0x883, 0x00007fb6, 0x0021a1b1,
 198         0x884, 0x00007fb6, 0x002021b1,
 199         0x860, 0x00007fb6, 0x00002191,
 200         0x886, 0x00007fb6, 0x002121b1,
 201         0x887, 0x00007fb6, 0x002021b1,
 202         0x877, 0x00007fb6, 0x00002191,
 203         0x878, 0x00007fb6, 0x00002191,
 204         0xd8a, 0x0000003f, 0x0000000a,
 205         0xd8b, 0x0000003f, 0x0000000a,
 206         0xab9, 0x00073ffe, 0x000022a2,
 207         0x903, 0x000007ff, 0x00000000,
 208         0x2285, 0xf000003f, 0x00000007,
 209         0x22fc, 0x00002001, 0x00000001,
 210         0x22c9, 0xffffffff, 0x00ffffff,
 211         0xc281, 0x0000ff0f, 0x00000000,
 212         0xa293, 0x07ffffff, 0x06000000,
 213         0x136, 0x00000fff, 0x00000100,
 214         0xf9e, 0x00000001, 0x00000002,
 215         0x2440, 0x03000000, 0x0362c688,
 216         0x2300, 0x000000ff, 0x00000001,
 217         0x390, 0x00001fff, 0x00001fff,
 218         0x2418, 0x0000007f, 0x00000020,
 219         0x2542, 0x00010000, 0x00010000,
 220         0x2b05, 0x000003ff, 0x000000f3,
 221         0x2b03, 0xffffffff, 0x00001032
 222 };
 223
 224 static const u32 bonaire_mgcg_cgcg_init[] =
 225 {
 226         0x3108, 0xffffffff, 0xfffffffc,
 227         0xc200, 0xffffffff, 0xe0000000,
 228         0xf0a8, 0xffffffff, 0x00000100,
 229         0xf082, 0xffffffff, 0x00000100,
 230         0xf0b0, 0xffffffff, 0xc0000100,
 231         0xf0b2, 0xffffffff, 0xc0000100,
 232         0xf0b1, 0xffffffff, 0xc0000100,
 233         0x1579, 0xffffffff, 0x00600100,
 234         0xf0a0, 0xffffffff, 0x00000100,
 235         0xf085, 0xffffffff, 0x06000100,
 236         0xf088, 0xffffffff, 0x00000100,
 237         0xf086, 0xffffffff, 0x06000100,
 238         0xf081, 0xffffffff, 0x00000100,
 239         0xf0b8, 0xffffffff, 0x00000100,
 240         0xf089, 0xffffffff, 0x00000100,
 241         0xf080, 0xffffffff, 0x00000100,
 242         0xf08c, 0xffffffff, 0x00000100,
 243         0xf08d, 0xffffffff, 0x00000100,
 244         0xf094, 0xffffffff, 0x00000100,
 245         0xf095, 0xffffffff, 0x00000100,
 246         0xf096, 0xffffffff, 0x00000100,
 247         0xf097, 0xffffffff, 0x00000100,
 248         0xf098, 0xffffffff, 0x00000100,
 249         0xf09f, 0xffffffff, 0x00000100,
 250         0xf09e, 0xffffffff, 0x00000100,
 251         0xf084, 0xffffffff, 0x06000100,
 252         0xf0a4, 0xffffffff, 0x00000100,
 253         0xf09d, 0xffffffff, 0x00000100,
 254         0xf0ad, 0xffffffff, 0x00000100,
 255         0xf0ac, 0xffffffff, 0x00000100,
 256         0xf09c, 0xffffffff, 0x00000100,
 257         0xc200, 0xffffffff, 0xe0000000,
 258         0xf008, 0xffffffff, 0x00010000,
 259         0xf009, 0xffffffff, 0x00030002,
 260         0xf00a, 0xffffffff, 0x00040007,
 261         0xf00b, 0xffffffff, 0x00060005,
 262         0xf00c, 0xffffffff, 0x00090008,
 263         0xf00d, 0xffffffff, 0x00010000,
 264         0xf00e, 0xffffffff, 0x00030002,
 265         0xf00f, 0xffffffff, 0x00040007,
 266         0xf010, 0xffffffff, 0x00060005,
 267         0xf011, 0xffffffff, 0x00090008,
 268         0xf012, 0xffffffff, 0x00010000,
 269         0xf013, 0xffffffff, 0x00030002,
 270         0xf014, 0xffffffff, 0x00040007,
 271         0xf015, 0xffffffff, 0x00060005,
 272         0xf016, 0xffffffff, 0x00090008,
 273         0xf017, 0xffffffff, 0x00010000,
 274         0xf018, 0xffffffff, 0x00030002,
 275         0xf019, 0xffffffff, 0x00040007,
 276         0xf01a, 0xffffffff, 0x00060005,
 277         0xf01b, 0xffffffff, 0x00090008,
 278         0xf01c, 0xffffffff, 0x00010000,
 279         0xf01d, 0xffffffff, 0x00030002,
 280         0xf01e, 0xffffffff, 0x00040007,
 281         0xf01f, 0xffffffff, 0x00060005,
 282         0xf020, 0xffffffff, 0x00090008,
 283         0xf021, 0xffffffff, 0x00010000,
 284         0xf022, 0xffffffff, 0x00030002,
 285         0xf023, 0xffffffff, 0x00040007,
 286         0xf024, 0xffffffff, 0x00060005,
 287         0xf025, 0xffffffff, 0x00090008,
 288         0xf026, 0xffffffff, 0x00010000,
 289         0xf027, 0xffffffff, 0x00030002,
 290         0xf028, 0xffffffff, 0x00040007,
 291         0xf029, 0xffffffff, 0x00060005,
 292         0xf02a, 0xffffffff, 0x00090008,
 293         0xf000, 0xffffffff, 0x96e00200,
 294         0x21c2, 0xffffffff, 0x00900100,
 295         0x3109, 0xffffffff, 0x0020003f,
 296         0xe, 0xffffffff, 0x0140001c,
 297         0xf, 0x000f0000, 0x000f0000,
 298         0x88, 0xffffffff, 0xc060000c,
 299         0x89, 0xc0000fff, 0x00000100,
 300         0x3e4, 0xffffffff, 0x00000100,
 301         0x3e6, 0x00000101, 0x00000000,
 302         0x82a, 0xffffffff, 0x00000104,
 303         0x1579, 0xff000fff, 0x00000100,
 304         0xc33, 0xc0000fff, 0x00000104,
 305         0x3079, 0x00000001, 0x00000001,
 306         0x3403, 0xff000ff0, 0x00000100,
 307         0x3603, 0xff000ff0, 0x00000100
 308 };
 309
 310 static const u32 spectre_golden_spm_registers[] =
 311 {
 312         0xc200, 0xe0ffffff, 0xe0000000
 313 };
 314
 315 static const u32 spectre_golden_common_registers[] =
 316 {
 317         0x31dc, 0xffffffff, 0x00000800,
 318         0x31dd, 0xffffffff, 0x00000800,
 319         0x31e6, 0xffffffff, 0x00007fbf,
 320         0x31e7, 0xffffffff, 0x00007faf
 321 };
 322
 323 static const u32 spectre_golden_registers[] =
 324 {
 325         0xf000, 0xffff1fff, 0x96940200,
 326         0xf003, 0xffff0001, 0xff000000,
 327         0xf080, 0xfffc0fff, 0x00000100,
 328         0x1bb6, 0x00010101, 0x00010000,
 329         0x260d, 0xf00fffff, 0x00000400,
 330         0x260e, 0xfffffffc, 0x00020200,
 331         0x16ec, 0x000000f0, 0x00000070,
 332         0x16f0, 0xf0311fff, 0x80300000,
 333         0x263e, 0x73773777, 0x12010001,
 334         0x26df, 0x00ff0000, 0x00fc0000,
 335         0xbd2, 0x73773777, 0x12010001,
 336         0x2285, 0xf000003f, 0x00000007,
 337         0x22c9, 0xffffffff, 0x00ffffff,
 338         0xa0d4, 0x3f3f3fff, 0x00000082,
 339         0xa0d5, 0x0000003f, 0x00000000,
 340         0xf9e, 0x00000001, 0x00000002,
 341         0x244f, 0xffff03df, 0x00000004,
 342         0x31da, 0x00000008, 0x00000008,
 343         0x2300, 0x000008ff, 0x00000800,
 344         0x2542, 0x00010000, 0x00010000,
 345         0x2b03, 0xffffffff, 0x54763210,
 346         0x853e, 0x01ff01ff, 0x00000002,
 347         0x8526, 0x007ff800, 0x00200000,
 348         0x8057, 0xffffffff, 0x00000f40,
 349         0xc24d, 0xffffffff, 0x00000001
 350 };
 351
 352 static const u32 spectre_mgcg_cgcg_init[] =
 353 {
 354         0x3108, 0xffffffff, 0xfffffffc,
 355         0xc200, 0xffffffff, 0xe0000000,
 356         0xf0a8, 0xffffffff, 0x00000100,
 357         0xf082, 0xffffffff, 0x00000100,
 358         0xf0b0, 0xffffffff, 0x00000100,
 359         0xf0b2, 0xffffffff, 0x00000100,
 360         0xf0b1, 0xffffffff, 0x00000100,
 361         0x1579, 0xffffffff, 0x00600100,
 362         0xf0a0, 0xffffffff, 0x00000100,
 363         0xf085, 0xffffffff, 0x06000100,
 364         0xf088, 0xffffffff, 0x00000100,
 365         0xf086, 0xffffffff, 0x06000100,
 366         0xf081, 0xffffffff, 0x00000100,
 367         0xf0b8, 0xffffffff, 0x00000100,
 368         0xf089, 0xffffffff, 0x00000100,
 369         0xf080, 0xffffffff, 0x00000100,
 370         0xf08c, 0xffffffff, 0x00000100,
 371         0xf08d, 0xffffffff, 0x00000100,
 372         0xf094, 0xffffffff, 0x00000100,
 373         0xf095, 0xffffffff, 0x00000100,
 374         0xf096, 0xffffffff, 0x00000100,
 375         0xf097, 0xffffffff, 0x00000100,
 376         0xf098, 0xffffffff, 0x00000100,
 377         0xf09f, 0xffffffff, 0x00000100,
 378         0xf09e, 0xffffffff, 0x00000100,
 379         0xf084, 0xffffffff, 0x06000100,
 380         0xf0a4, 0xffffffff, 0x00000100,
 381         0xf09d, 0xffffffff, 0x00000100,
 382         0xf0ad, 0xffffffff, 0x00000100,
 383         0xf0ac, 0xffffffff, 0x00000100,
 384         0xf09c, 0xffffffff, 0x00000100,
 385         0xc200, 0xffffffff, 0xe0000000,
 386         0xf008, 0xffffffff, 0x00010000,
 387         0xf009, 0xffffffff, 0x00030002,
 388         0xf00a, 0xffffffff, 0x00040007,
 389         0xf00b, 0xffffffff, 0x00060005,
 390         0xf00c, 0xffffffff, 0x00090008,
 391         0xf00d, 0xffffffff, 0x00010000,
 392         0xf00e, 0xffffffff, 0x00030002,
 393         0xf00f, 0xffffffff, 0x00040007,
 394         0xf010, 0xffffffff, 0x00060005,
 395         0xf011, 0xffffffff, 0x00090008,
 396         0xf012, 0xffffffff, 0x00010000,
 397         0xf013, 0xffffffff, 0x00030002,
 398         0xf014, 0xffffffff, 0x00040007,
 399         0xf015, 0xffffffff, 0x00060005,
 400         0xf016, 0xffffffff, 0x00090008,
 401         0xf017, 0xffffffff, 0x00010000,
 402         0xf018, 0xffffffff, 0x00030002,
 403         0xf019, 0xffffffff, 0x00040007,
 404         0xf01a, 0xffffffff, 0x00060005,
 405         0xf01b, 0xffffffff, 0x00090008,
 406         0xf01c, 0xffffffff, 0x00010000,
 407         0xf01d, 0xffffffff, 0x00030002,
 408         0xf01e, 0xffffffff, 0x00040007,
 409         0xf01f, 0xffffffff, 0x00060005,
 410         0xf020, 0xffffffff, 0x00090008,
 411         0xf021, 0xffffffff, 0x00010000,
 412         0xf022, 0xffffffff, 0x00030002,
 413         0xf023, 0xffffffff, 0x00040007,
 414         0xf024, 0xffffffff, 0x00060005,
 415         0xf025, 0xffffffff, 0x00090008,
 416         0xf026, 0xffffffff, 0x00010000,
 417         0xf027, 0xffffffff, 0x00030002,
 418         0xf028, 0xffffffff, 0x00040007,
 419         0xf029, 0xffffffff, 0x00060005,
 420         0xf02a, 0xffffffff, 0x00090008,
 421         0xf02b, 0xffffffff, 0x00010000,
 422         0xf02c, 0xffffffff, 0x00030002,
 423         0xf02d, 0xffffffff, 0x00040007,
 424         0xf02e, 0xffffffff, 0x00060005,
 425         0xf02f, 0xffffffff, 0x00090008,
 426         0xf000, 0xffffffff, 0x96e00200,
 427         0x21c2, 0xffffffff, 0x00900100,
 428         0x3109, 0xffffffff, 0x0020003f,
 429         0xe, 0xffffffff, 0x0140001c,
 430         0xf, 0x000f0000, 0x000f0000,
 431         0x88, 0xffffffff, 0xc060000c,
 432         0x89, 0xc0000fff, 0x00000100,
 433         0x3e4, 0xffffffff, 0x00000100,
 434         0x3e6, 0x00000101, 0x00000000,
 435         0x82a, 0xffffffff, 0x00000104,
 436         0x1579, 0xff000fff, 0x00000100,
 437         0xc33, 0xc0000fff, 0x00000104,
 438         0x3079, 0x00000001, 0x00000001,
 439         0x3403, 0xff000ff0, 0x00000100,
 440         0x3603, 0xff000ff0, 0x00000100
 441 };
 442
 443 static const u32 kalindi_golden_spm_registers[] =
 444 {
 445         0xc200, 0xe0ffffff, 0xe0000000
 446 };
 447
 448 static const u32 kalindi_golden_common_registers[] =
 449 {
 450         0x31dc, 0xffffffff, 0x00000800,
 451         0x31dd, 0xffffffff, 0x00000800,
 452         0x31e6, 0xffffffff, 0x00007fbf,
 453         0x31e7, 0xffffffff, 0x00007faf
 454 };
 455
 456 static const u32 kalindi_golden_registers[] =
 457 {
 458         0xf000, 0xffffdfff, 0x6e944040,
 459         0x1579, 0xff607fff, 0xfc000100,
 460         0xf088, 0xff000fff, 0x00000100,
 461         0xf089, 0xff000fff, 0x00000100,
 462         0xf080, 0xfffc0fff, 0x00000100,
 463         0x1bb6, 0x00010101, 0x00010000,
 464         0x260c, 0xffffffff, 0x00000000,
 465         0x260d, 0xf00fffff, 0x00000400,
 466         0x16ec, 0x000000f0, 0x00000070,
 467         0x16f0, 0xf0311fff, 0x80300000,
 468         0x263e, 0x73773777, 0x12010001,
 469         0x263f, 0xffffffff, 0x00000010,
 470         0x26df, 0x00ff0000, 0x00fc0000,
 471         0x200c, 0x00001f0f, 0x0000100a,
 472         0xbd2, 0x73773777, 0x12010001,
 473         0x902, 0x000fffff, 0x000c007f,
 474         0x2285, 0xf000003f, 0x00000007,
 475         0x22c9, 0x3fff3fff, 0x00ffcfff,
 476         0xc281, 0x0000ff0f, 0x00000000,
 477         0xa293, 0x07ffffff, 0x06000000,
 478         0x136, 0x00000fff, 0x00000100,
 479         0xf9e, 0x00000001, 0x00000002,
 480         0x31da, 0x00000008, 0x00000008,
 481         0x2300, 0x000000ff, 0x00000003,
 482         0x853e, 0x01ff01ff, 0x00000002,
 483         0x8526, 0x007ff800, 0x00200000,
 484         0x8057, 0xffffffff, 0x00000f40,
 485         0x2231, 0x001f3ae3, 0x00000082,
 486         0x2235, 0x0000001f, 0x00000010,
 487         0xc24d, 0xffffffff, 0x00000000
 488 };
 489
 490 static const u32 kalindi_mgcg_cgcg_init[] =
 491 {
 492         0x3108, 0xffffffff, 0xfffffffc,
 493         0xc200, 0xffffffff, 0xe0000000,
 494         0xf0a8, 0xffffffff, 0x00000100,
 495         0xf082, 0xffffffff, 0x00000100,
 496         0xf0b0, 0xffffffff, 0x00000100,
 497         0xf0b2, 0xffffffff, 0x00000100,
 498         0xf0b1, 0xffffffff, 0x00000100,
 499         0x1579, 0xffffffff, 0x00600100,
 500         0xf0a0, 0xffffffff, 0x00000100,
 501         0xf085, 0xffffffff, 0x06000100,
 502         0xf088, 0xffffffff, 0x00000100,
 503         0xf086, 0xffffffff, 0x06000100,
 504         0xf081, 0xffffffff, 0x00000100,
 505         0xf0b8, 0xffffffff, 0x00000100,
 506         0xf089, 0xffffffff, 0x00000100,
 507         0xf080, 0xffffffff, 0x00000100,
 508         0xf08c, 0xffffffff, 0x00000100,
 509         0xf08d, 0xffffffff, 0x00000100,
 510         0xf094, 0xffffffff, 0x00000100,
 511         0xf095, 0xffffffff, 0x00000100,
 512         0xf096, 0xffffffff, 0x00000100,
 513         0xf097, 0xffffffff, 0x00000100,
 514         0xf098, 0xffffffff, 0x00000100,
 515         0xf09f, 0xffffffff, 0x00000100,
 516         0xf09e, 0xffffffff, 0x00000100,
 517         0xf084, 0xffffffff, 0x06000100,
 518         0xf0a4, 0xffffffff, 0x00000100,
 519         0xf09d, 0xffffffff, 0x00000100,
 520         0xf0ad, 0xffffffff, 0x00000100,
 521         0xf0ac, 0xffffffff, 0x00000100,
 522         0xf09c, 0xffffffff, 0x00000100,
 523         0xc200, 0xffffffff, 0xe0000000,
 524         0xf008, 0xffffffff, 0x00010000,
 525         0xf009, 0xffffffff, 0x00030002,
 526         0xf00a, 0xffffffff, 0x00040007,
 527         0xf00b, 0xffffffff, 0x00060005,
 528         0xf00c, 0xffffffff, 0x00090008,
 529         0xf00d, 0xffffffff, 0x00010000,
 530         0xf00e, 0xffffffff, 0x00030002,
 531         0xf00f, 0xffffffff, 0x00040007,
 532         0xf010, 0xffffffff, 0x00060005,
 533         0xf011, 0xffffffff, 0x00090008,
 534         0xf000, 0xffffffff, 0x96e00200,
 535         0x21c2, 0xffffffff, 0x00900100,
 536         0x3109, 0xffffffff, 0x0020003f,
 537         0xe, 0xffffffff, 0x0140001c,
 538         0xf, 0x000f0000, 0x000f0000,
 539         0x88, 0xffffffff, 0xc060000c,
 540         0x89, 0xc0000fff, 0x00000100,
 541         0x82a, 0xffffffff, 0x00000104,
 542         0x1579, 0xff000fff, 0x00000100,
 543         0xc33, 0xc0000fff, 0x00000104,
 544         0x3079, 0x00000001, 0x00000001,
 545         0x3403, 0xff000ff0, 0x00000100,
 546         0x3603, 0xff000ff0, 0x00000100
 547 };
 548
 549 static const u32 hawaii_golden_spm_registers[] =
 550 {
 551         0xc200, 0xe0ffffff, 0xe0000000
 552 };
 553
 554 static const u32 hawaii_golden_common_registers[] =
 555 {
 556         0xc200, 0xffffffff, 0xe0000000,
 557         0xa0d4, 0xffffffff, 0x3a00161a,
 558         0xa0d5, 0xffffffff, 0x0000002e,
 559         0x2684, 0xffffffff, 0x00018208,
 560         0x263e, 0xffffffff, 0x12011003
 561 };
 562
 563 static const u32 hawaii_golden_registers[] =
 564 {
 565         0xcd5, 0x00000333, 0x00000333,
 566         0x2684, 0x00010000, 0x00058208,
 567         0x260c, 0xffffffff, 0x00000000,
 568         0x260d, 0xf00fffff, 0x00000400,
 569         0x260e, 0x0002021c, 0x00020200,
 570         0x31e, 0x00000080, 0x00000000,
 571         0x16ec, 0x000000f0, 0x00000070,
 572         0x16f0, 0xf0311fff, 0x80300000,
 573         0xd43, 0x00810000, 0x408af000,
 574         0x1c0c, 0x31000111, 0x00000011,
 575         0xbd2, 0x73773777, 0x12010001,
 576         0x848, 0x0000007f, 0x0000001b,
 577         0x877, 0x00007fb6, 0x00002191,
 578         0xd8a, 0x0000003f, 0x0000000a,
 579         0xd8b, 0x0000003f, 0x0000000a,
 580         0xab9, 0x00073ffe, 0x000022a2,
 581         0x903, 0x000007ff, 0x00000000,
 582         0x22fc, 0x00002001, 0x00000001,
 583         0x22c9, 0xffffffff, 0x00ffffff,
 584         0xc281, 0x0000ff0f, 0x00000000,
 585         0xa293, 0x07ffffff, 0x06000000,
 586         0xf9e, 0x00000001, 0x00000002,
 587         0x31da, 0x00000008, 0x00000008,
 588         0x31dc, 0x00000f00, 0x00000800,
 589         0x31dd, 0x00000f00, 0x00000800,
 590         0x31e6, 0x00ffffff, 0x00ff7fbf,
 591         0x31e7, 0x00ffffff, 0x00ff7faf,
 592         0x2300, 0x000000ff, 0x00000800,
 593         0x390, 0x00001fff, 0x00001fff,
 594         0x2418, 0x0000007f, 0x00000020,
 595         0x2542, 0x00010000, 0x00010000,
 596         0x2b80, 0x00100000, 0x000ff07c,
 597         0x2b05, 0x000003ff, 0x0000000f,
 598         0x2b04, 0xffffffff, 0x7564fdec,
 599         0x2b03, 0xffffffff, 0x3120b9a8,
 600         0x2b02, 0x20000000, 0x0f9c0000
 601 };
 602
 603 static const u32 hawaii_mgcg_cgcg_init[] =
 604 {
 605         0x3108, 0xffffffff, 0xfffffffd,
 606         0xc200, 0xffffffff, 0xe0000000,
 607         0xf0a8, 0xffffffff, 0x00000100,
 608         0xf082, 0xffffffff, 0x00000100,
 609         0xf0b0, 0xffffffff, 0x00000100,
 610         0xf0b2, 0xffffffff, 0x00000100,
 611         0xf0b1, 0xffffffff, 0x00000100,
 612         0x1579, 0xffffffff, 0x00200100,
 613         0xf0a0, 0xffffffff, 0x00000100,
 614         0xf085, 0xffffffff, 0x06000100,
 615         0xf088, 0xffffffff, 0x00000100,
 616         0xf086, 0xffffffff, 0x06000100,
 617         0xf081, 0xffffffff, 0x00000100,
 618         0xf0b8, 0xffffffff, 0x00000100,
 619         0xf089, 0xffffffff, 0x00000100,
 620         0xf080, 0xffffffff, 0x00000100,
 621         0xf08c, 0xffffffff, 0x00000100,
 622         0xf08d, 0xffffffff, 0x00000100,
 623         0xf094, 0xffffffff, 0x00000100,
 624         0xf095, 0xffffffff, 0x00000100,
 625         0xf096, 0xffffffff, 0x00000100,
 626         0xf097, 0xffffffff, 0x00000100,
 627         0xf098, 0xffffffff, 0x00000100,
 628         0xf09f, 0xffffffff, 0x00000100,
 629         0xf09e, 0xffffffff, 0x00000100,
 630         0xf084, 0xffffffff, 0x06000100,
 631         0xf0a4, 0xffffffff, 0x00000100,
 632         0xf09d, 0xffffffff, 0x00000100,
 633         0xf0ad, 0xffffffff, 0x00000100,
 634         0xf0ac, 0xffffffff, 0x00000100,
 635         0xf09c, 0xffffffff, 0x00000100,
 636         0xc200, 0xffffffff, 0xe0000000,
 637         0xf008, 0xffffffff, 0x00010000,
 638         0xf009, 0xffffffff, 0x00030002,
 639         0xf00a, 0xffffffff, 0x00040007,
 640         0xf00b, 0xffffffff, 0x00060005,
 641         0xf00c, 0xffffffff, 0x00090008,
 642         0xf00d, 0xffffffff, 0x00010000,
 643         0xf00e, 0xffffffff, 0x00030002,
 644         0xf00f, 0xffffffff, 0x00040007,
 645         0xf010, 0xffffffff, 0x00060005,
 646         0xf011, 0xffffffff, 0x00090008,
 647         0xf012, 0xffffffff, 0x00010000,
 648         0xf013, 0xffffffff, 0x00030002,
 649         0xf014, 0xffffffff, 0x00040007,
 650         0xf015, 0xffffffff, 0x00060005,
 651         0xf016, 0xffffffff, 0x00090008,
 652         0xf017, 0xffffffff, 0x00010000,
 653         0xf018, 0xffffffff, 0x00030002,
 654         0xf019, 0xffffffff, 0x00040007,
 655         0xf01a, 0xffffffff, 0x00060005,
 656         0xf01b, 0xffffffff, 0x00090008,
 657         0xf01c, 0xffffffff, 0x00010000,
 658         0xf01d, 0xffffffff, 0x00030002,
 659         0xf01e, 0xffffffff, 0x00040007,
 660         0xf01f, 0xffffffff, 0x00060005,
 661         0xf020, 0xffffffff, 0x00090008,
 662         0xf021, 0xffffffff, 0x00010000,
 663         0xf022, 0xffffffff, 0x00030002,
 664         0xf023, 0xffffffff, 0x00040007,
 665         0xf024, 0xffffffff, 0x00060005,
 666         0xf025, 0xffffffff, 0x00090008,
 667         0xf026, 0xffffffff, 0x00010000,
 668         0xf027, 0xffffffff, 0x00030002,
 669         0xf028, 0xffffffff, 0x00040007,
 670         0xf029, 0xffffffff, 0x00060005,
 671         0xf02a, 0xffffffff, 0x00090008,
 672         0xf02b, 0xffffffff, 0x00010000,
 673         0xf02c, 0xffffffff, 0x00030002,
 674         0xf02d, 0xffffffff, 0x00040007,
 675         0xf02e, 0xffffffff, 0x00060005,
 676         0xf02f, 0xffffffff, 0x00090008,
 677         0xf030, 0xffffffff, 0x00010000,
 678         0xf031, 0xffffffff, 0x00030002,
 679         0xf032, 0xffffffff, 0x00040007,
 680         0xf033, 0xffffffff, 0x00060005,
 681         0xf034, 0xffffffff, 0x00090008,
 682         0xf035, 0xffffffff, 0x00010000,
 683         0xf036, 0xffffffff, 0x00030002,
 684         0xf037, 0xffffffff, 0x00040007,
 685         0xf038, 0xffffffff, 0x00060005,
 686         0xf039, 0xffffffff, 0x00090008,
 687         0xf03a, 0xffffffff, 0x00010000,
 688         0xf03b, 0xffffffff, 0x00030002,
 689         0xf03c, 0xffffffff, 0x00040007,
 690         0xf03d, 0xffffffff, 0x00060005,
 691         0xf03e, 0xffffffff, 0x00090008,
 692         0x30c6, 0xffffffff, 0x00020200,
 693         0xcd4, 0xffffffff, 0x00000200,
 694         0x570, 0xffffffff, 0x00000400,
 695         0x157a, 0xffffffff, 0x00000000,
 696         0xbd4, 0xffffffff, 0x00000902,
 697         0xf000, 0xffffffff, 0x96940200,
 698         0x21c2, 0xffffffff, 0x00900100,
 699         0x3109, 0xffffffff, 0x0020003f,
 700         0xe, 0xffffffff, 0x0140001c,
 701         0xf, 0x000f0000, 0x000f0000,
 702         0x88, 0xffffffff, 0xc060000c,
 703         0x89, 0xc0000fff, 0x00000100,
 704         0x3e4, 0xffffffff, 0x00000100,
 705         0x3e6, 0x00000101, 0x00000000,
 706         0x82a, 0xffffffff, 0x00000104,
 707         0x1579, 0xff000fff, 0x00000100,
 708         0xc33, 0xc0000fff, 0x00000104,
 709         0x3079, 0x00000001, 0x00000001,
 710         0x3403, 0xff000ff0, 0x00000100,
 711         0x3603, 0xff000ff0, 0x00000100
 712 };
 713
 714 static const u32 godavari_golden_registers[] =
 715 {
 716         0x1579, 0xff607fff, 0xfc000100,
 717         0x1bb6, 0x00010101, 0x00010000,
 718         0x260c, 0xffffffff, 0x00000000,
 719         0x260c0, 0xf00fffff, 0x00000400,
 720         0x184c, 0xffffffff, 0x00010000,
 721         0x16ec, 0x000000f0, 0x00000070,
 722         0x16f0, 0xf0311fff, 0x80300000,
 723         0x263e, 0x73773777, 0x12010001,
 724         0x263f, 0xffffffff, 0x00000010,
 725         0x200c, 0x00001f0f, 0x0000100a,
 726         0xbd2, 0x73773777, 0x12010001,
 727         0x902, 0x000fffff, 0x000c007f,
 728         0x2285, 0xf000003f, 0x00000007,
 729         0x22c9, 0xffffffff, 0x00ff0fff,
 730         0xc281, 0x0000ff0f, 0x00000000,
 731         0xa293, 0x07ffffff, 0x06000000,
 732         0x136, 0x00000fff, 0x00000100,
 733         0x3405, 0x00010000, 0x00810001,
 734         0x3605, 0x00010000, 0x00810001,
 735         0xf9e, 0x00000001, 0x00000002,
 736         0x31da, 0x00000008, 0x00000008,
 737         0x31dc, 0x00000f00, 0x00000800,
 738         0x31dd, 0x00000f00, 0x00000800,
 739         0x31e6, 0x00ffffff, 0x00ff7fbf,
 740         0x31e7, 0x00ffffff, 0x00ff7faf,
 741         0x2300, 0x000000ff, 0x00000001,
 742         0x853e, 0x01ff01ff, 0x00000002,
 743         0x8526, 0x007ff800, 0x00200000,
 744         0x8057, 0xffffffff, 0x00000f40,
 745         0x2231, 0x001f3ae3, 0x00000082,
 746         0x2235, 0x0000001f, 0x00000010,
 747         0xc24d, 0xffffffff, 0x00000000
 748 };
 749
 750 static void cik_init_golden_registers(struct amdgpu_device *adev)
 751 {
 752         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 753         mutex_lock(&adev->grbm_idx_mutex);
 754
 755         switch (adev->asic_type) {
 756         case CHIP_BONAIRE:
 757                 amdgpu_device_program_register_sequence(adev,
 758                                                         bonaire_mgcg_cgcg_init,
 759                                                         ARRAY_SIZE(bonaire_mgcg_cgcg_init));
 760                 amdgpu_device_program_register_sequence(adev,
 761                                                         bonaire_golden_registers,
 762                                                         ARRAY_SIZE(bonaire_golden_registers));
 763                 amdgpu_device_program_register_sequence(adev,
 764                                                         bonaire_golden_common_registers,
 765                                                         ARRAY_SIZE(bonaire_golden_common_registers));
 766                 amdgpu_device_program_register_sequence(adev,
 767                                                         bonaire_golden_spm_registers,
 768                                                         ARRAY_SIZE(bonaire_golden_spm_registers));
 769                 break;
 770         case CHIP_KABINI:
 771                 amdgpu_device_program_register_sequence(adev,
 772                                                         kalindi_mgcg_cgcg_init,
 773                                                         ARRAY_SIZE(kalindi_mgcg_cgcg_init));
 774                 amdgpu_device_program_register_sequence(adev,
 775                                                         kalindi_golden_registers,
 776                                                         ARRAY_SIZE(kalindi_golden_registers));
 777                 amdgpu_device_program_register_sequence(adev,
 778                                                         kalindi_golden_common_registers,
 779                                                         ARRAY_SIZE(kalindi_golden_common_registers));
 780                 amdgpu_device_program_register_sequence(adev,
 781                                                         kalindi_golden_spm_registers,
 782                                                         ARRAY_SIZE(kalindi_golden_spm_registers));
 783                 break;
 784         case CHIP_MULLINS:
 785                 amdgpu_device_program_register_sequence(adev,
 786                                                         kalindi_mgcg_cgcg_init,
 787                                                         ARRAY_SIZE(kalindi_mgcg_cgcg_init));
 788                 amdgpu_device_program_register_sequence(adev,
 789                                                         godavari_golden_registers,
 790                                                         ARRAY_SIZE(godavari_golden_registers));
 791                 amdgpu_device_program_register_sequence(adev,
 792                                                         kalindi_golden_common_registers,
 793                                                         ARRAY_SIZE(kalindi_golden_common_registers));
 794                 amdgpu_device_program_register_sequence(adev,
 795                                                         kalindi_golden_spm_registers,
 796                                                         ARRAY_SIZE(kalindi_golden_spm_registers));
 797                 break;
 798         case CHIP_KAVERI:
 799                 amdgpu_device_program_register_sequence(adev,
 800                                                         spectre_mgcg_cgcg_init,
 801                                                         ARRAY_SIZE(spectre_mgcg_cgcg_init));
 802                 amdgpu_device_program_register_sequence(adev,
 803                                                         spectre_golden_registers,
 804                                                         ARRAY_SIZE(spectre_golden_registers));
 805                 amdgpu_device_program_register_sequence(adev,
 806                                                         spectre_golden_common_registers,
 807                                                         ARRAY_SIZE(spectre_golden_common_registers));
 808                 amdgpu_device_program_register_sequence(adev,
 809                                                         spectre_golden_spm_registers,
 810                                                         ARRAY_SIZE(spectre_golden_spm_registers));
 811                 break;
 812         case CHIP_HAWAII:
 813                 amdgpu_device_program_register_sequence(adev,
 814                                                         hawaii_mgcg_cgcg_init,
 815                                                         ARRAY_SIZE(hawaii_mgcg_cgcg_init));
 816                 amdgpu_device_program_register_sequence(adev,
 817                                                         hawaii_golden_registers,
 818                                                         ARRAY_SIZE(hawaii_golden_registers));
 819                 amdgpu_device_program_register_sequence(adev,
 820                                                         hawaii_golden_common_registers,
 821                                                         ARRAY_SIZE(hawaii_golden_common_registers));
 822                 amdgpu_device_program_register_sequence(adev,
 823                                                         hawaii_golden_spm_registers,
 824                                                         ARRAY_SIZE(hawaii_golden_spm_registers));
 825                 break;
 826         default:
 827                 break;
 828         }
 829         mutex_unlock(&adev->grbm_idx_mutex);
 830 }
 831
 832 /**
 833  * cik_get_xclk - get the xclk
 834  *
 835  * @adev: amdgpu_device pointer
 836  *
 837  * Returns the reference clock used by the gfx engine
 838  * (CIK).
 839  */
 840 static u32 cik_get_xclk(struct amdgpu_device *adev)
 841 {
 842         u32 reference_clock = adev->clock.spll.reference_freq;
 843
 844         if (adev->flags & AMD_IS_APU) {
 845                 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
 846                         return reference_clock / 2;
 847         } else {
 848                 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
 849                         return reference_clock / 4;
 850         }
 851         return reference_clock;
 852 }
 853
 854 /**
 855  * cik_srbm_select - select specific register instances
 856  *
 857  * @adev: amdgpu_device pointer
 858  * @me: selected ME (micro engine)
 859  * @pipe: pipe
 860  * @queue: queue
 861  * @vmid: VMID
 862  *
 863  * Switches the currently active registers instances.  Some
 864  * registers are instanced per VMID, others are instanced per
 865  * me/pipe/queue combination.
 866  */
 867 void cik_srbm_select(struct amdgpu_device *adev,
 868                      u32 me, u32 pipe, u32 queue, u32 vmid)
 869 {
 870         u32 srbm_gfx_cntl =
 871                 (((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)|
 872                 ((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)|
 873                 ((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)|
 874                 ((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK));
 875         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 876 }
 877
 878 static void cik_vga_set_state(struct amdgpu_device *adev, bool state)
 879 {
 880         uint32_t tmp;
 881
 882         tmp = RREG32(mmCONFIG_CNTL);
 883         if (!state)
 884                 tmp |= CONFIG_CNTL__VGA_DIS_MASK;
 885         else
 886                 tmp &= ~CONFIG_CNTL__VGA_DIS_MASK;
 887         WREG32(mmCONFIG_CNTL, tmp);
 888 }
 889
 890 static bool cik_read_disabled_bios(struct amdgpu_device *adev)
 891 {
 892         u32 bus_cntl;
 893         u32 d1vga_control = 0;
 894         u32 d2vga_control = 0;
 895         u32 vga_render_control = 0;
 896         u32 rom_cntl;
 897         bool r;
 898
 899         bus_cntl = RREG32(mmBUS_CNTL);
 900         if (adev->mode_info.num_crtc) {
 901                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 902                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 903                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 904         }
 905         rom_cntl = RREG32_SMC(ixROM_CNTL);
 906
 907         /* enable the rom */
 908         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 909         if (adev->mode_info.num_crtc) {
 910                 /* Disable VGA mode */
 911                 WREG32(mmD1VGA_CONTROL,
 912                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 913                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 914                 WREG32(mmD2VGA_CONTROL,
 915                        (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 916                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 917                 WREG32(mmVGA_RENDER_CONTROL,
 918                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 919         }
 920         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 921
 922         r = amdgpu_read_bios(adev);
 923
 924         /* restore regs */
 925         WREG32(mmBUS_CNTL, bus_cntl);
 926         if (adev->mode_info.num_crtc) {
 927                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 928                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 929                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 930         }
 931         WREG32_SMC(ixROM_CNTL, rom_cntl);
 932         return r;
 933 }
 934
 935 static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
 936                                    u8 *bios, u32 length_bytes)
 937 {
 938         u32 *dw_ptr;
 939         unsigned long flags;
 940         u32 i, length_dw;
 941
 942         if (bios == NULL)
 943                 return false;
 944         if (length_bytes == 0)
 945                 return false;
 946         /* APU vbios image is part of sbios image */
 947         if (adev->flags & AMD_IS_APU)
 948                 return false;
 949
 950         dw_ptr = (u32 *)bios;
 951         length_dw = ALIGN(length_bytes, 4) / 4;
 952         /* take the smc lock since we are using the smc index */
 953         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 954         /* set rom index to 0 */
 955         WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
 956         WREG32(mmSMC_IND_DATA_0, 0);
 957         /* set index to data for continous read */
 958         WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
 959         for (i = 0; i < length_dw; i++)
 960                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
 961         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 962
 963         return true;
 964 }
 965
 966 static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
 967         {mmGRBM_STATUS},
 968         {mmGB_ADDR_CONFIG},
 969         {mmMC_ARB_RAMCFG},
 970         {mmGB_TILE_MODE0},
 971         {mmGB_TILE_MODE1},
 972         {mmGB_TILE_MODE2},
 973         {mmGB_TILE_MODE3},
 974         {mmGB_TILE_MODE4},
 975         {mmGB_TILE_MODE5},
 976         {mmGB_TILE_MODE6},
 977         {mmGB_TILE_MODE7},
 978         {mmGB_TILE_MODE8},
 979         {mmGB_TILE_MODE9},
 980         {mmGB_TILE_MODE10},
 981         {mmGB_TILE_MODE11},
 982         {mmGB_TILE_MODE12},
 983         {mmGB_TILE_MODE13},
 984         {mmGB_TILE_MODE14},
 985         {mmGB_TILE_MODE15},
 986         {mmGB_TILE_MODE16},
 987         {mmGB_TILE_MODE17},
 988         {mmGB_TILE_MODE18},
 989         {mmGB_TILE_MODE19},
 990         {mmGB_TILE_MODE20},
 991         {mmGB_TILE_MODE21},
 992         {mmGB_TILE_MODE22},
 993         {mmGB_TILE_MODE23},
 994         {mmGB_TILE_MODE24},
 995         {mmGB_TILE_MODE25},
 996         {mmGB_TILE_MODE26},
 997         {mmGB_TILE_MODE27},
 998         {mmGB_TILE_MODE28},
 999         {mmGB_TILE_MODE29},
1000         {mmGB_TILE_MODE30},
1001         {mmGB_TILE_MODE31},
1002         {mmGB_MACROTILE_MODE0},
1003         {mmGB_MACROTILE_MODE1},
1004         {mmGB_MACROTILE_MODE2},
1005         {mmGB_MACROTILE_MODE3},
1006         {mmGB_MACROTILE_MODE4},
1007         {mmGB_MACROTILE_MODE5},
1008         {mmGB_MACROTILE_MODE6},
1009         {mmGB_MACROTILE_MODE7},
1010         {mmGB_MACROTILE_MODE8},
1011         {mmGB_MACROTILE_MODE9},
1012         {mmGB_MACROTILE_MODE10},
1013         {mmGB_MACROTILE_MODE11},
1014         {mmGB_MACROTILE_MODE12},
1015         {mmGB_MACROTILE_MODE13},
1016         {mmGB_MACROTILE_MODE14},
1017         {mmGB_MACROTILE_MODE15},
1018         {mmCC_RB_BACKEND_DISABLE, true},
1019         {mmGC_USER_RB_BACKEND_DISABLE, true},
1020         {mmGB_BACKEND_MAP, false},
1021         {mmPA_SC_RASTER_CONFIG, true},
1022         {mmPA_SC_RASTER_CONFIG_1, true},
1023 };
1024
1025
1026 static uint32_t cik_get_register_value(struct amdgpu_device *adev,
1027                                        bool indexed, u32 se_num,
1028                                        u32 sh_num, u32 reg_offset)
1029 {
1030         if (indexed) {
1031                 uint32_t val;
1032                 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
1033                 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
1034
1035                 switch (reg_offset) {
1036                 case mmCC_RB_BACKEND_DISABLE:
1037                         return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
1038                 case mmGC_USER_RB_BACKEND_DISABLE:
1039                         return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
1040                 case mmPA_SC_RASTER_CONFIG:
1041                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
1042                 case mmPA_SC_RASTER_CONFIG_1:
1043                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
1044                 }
1045
1046                 mutex_lock(&adev->grbm_idx_mutex);
1047                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1048                         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1049
1050                 val = RREG32(reg_offset);
1051
1052                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1053                         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1054                 mutex_unlock(&adev->grbm_idx_mutex);
1055                 return val;
1056         } else {
1057                 unsigned idx;
1058
1059                 switch (reg_offset) {
1060                 case mmGB_ADDR_CONFIG:
1061                         return adev->gfx.config.gb_addr_config;
1062                 case mmMC_ARB_RAMCFG:
1063                         return adev->gfx.config.mc_arb_ramcfg;
1064                 case mmGB_TILE_MODE0:
1065                 case mmGB_TILE_MODE1:
1066                 case mmGB_TILE_MODE2:
1067                 case mmGB_TILE_MODE3:
1068                 case mmGB_TILE_MODE4:
1069                 case mmGB_TILE_MODE5:
1070                 case mmGB_TILE_MODE6:
1071                 case mmGB_TILE_MODE7:
1072                 case mmGB_TILE_MODE8:
1073                 case mmGB_TILE_MODE9:
1074                 case mmGB_TILE_MODE10:
1075                 case mmGB_TILE_MODE11:
1076                 case mmGB_TILE_MODE12:
1077                 case mmGB_TILE_MODE13:
1078                 case mmGB_TILE_MODE14:
1079                 case mmGB_TILE_MODE15:
1080                 case mmGB_TILE_MODE16:
1081                 case mmGB_TILE_MODE17:
1082                 case mmGB_TILE_MODE18:
1083                 case mmGB_TILE_MODE19:
1084                 case mmGB_TILE_MODE20:
1085                 case mmGB_TILE_MODE21:
1086                 case mmGB_TILE_MODE22:
1087                 case mmGB_TILE_MODE23:
1088                 case mmGB_TILE_MODE24:
1089                 case mmGB_TILE_MODE25:
1090                 case mmGB_TILE_MODE26:
1091                 case mmGB_TILE_MODE27:
1092                 case mmGB_TILE_MODE28:
1093                 case mmGB_TILE_MODE29:
1094                 case mmGB_TILE_MODE30:
1095                 case mmGB_TILE_MODE31:
1096                         idx = (reg_offset - mmGB_TILE_MODE0);
1097                         return adev->gfx.config.tile_mode_array[idx];
1098                 case mmGB_MACROTILE_MODE0:
1099                 case mmGB_MACROTILE_MODE1:
1100                 case mmGB_MACROTILE_MODE2:
1101                 case mmGB_MACROTILE_MODE3:
1102                 case mmGB_MACROTILE_MODE4:
1103                 case mmGB_MACROTILE_MODE5:
1104                 case mmGB_MACROTILE_MODE6:
1105                 case mmGB_MACROTILE_MODE7:
1106                 case mmGB_MACROTILE_MODE8:
1107                 case mmGB_MACROTILE_MODE9:
1108                 case mmGB_MACROTILE_MODE10:
1109                 case mmGB_MACROTILE_MODE11:
1110                 case mmGB_MACROTILE_MODE12:
1111                 case mmGB_MACROTILE_MODE13:
1112                 case mmGB_MACROTILE_MODE14:
1113                 case mmGB_MACROTILE_MODE15:
1114                         idx = (reg_offset - mmGB_MACROTILE_MODE0);
1115                         return adev->gfx.config.macrotile_mode_array[idx];
1116                 default:
1117                         return RREG32(reg_offset);
1118                 }
1119         }
1120 }
1121
1122 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
1123                              u32 sh_num, u32 reg_offset, u32 *value)
1124 {
1125         uint32_t i;
1126
1127         *value = 0;
1128         for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {
1129                 bool indexed = cik_allowed_read_registers[i].grbm_indexed;
1130
1131                 if (reg_offset != cik_allowed_read_registers[i].reg_offset)
1132                         continue;
1133
1134                 *value = cik_get_register_value(adev, indexed, se_num, sh_num,
1135                                                 reg_offset);
1136                 return 0;
1137         }
1138         return -EINVAL;
1139 }
1140
1141 struct kv_reset_save_regs {
1142         u32 gmcon_reng_execute;
1143         u32 gmcon_misc;
1144         u32 gmcon_misc3;
1145 };
1146
1147 static void kv_save_regs_for_reset(struct amdgpu_device *adev,
1148                                    struct kv_reset_save_regs *save)
1149 {
1150         save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);
1151         save->gmcon_misc = RREG32(mmGMCON_MISC);
1152         save->gmcon_misc3 = RREG32(mmGMCON_MISC3);
1153
1154         WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute &
1155                 ~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK);
1156         WREG32(mmGMCON_MISC, save->gmcon_misc &
1157                 ~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK |
1158                         GMCON_MISC__STCTRL_STUTTER_EN_MASK));
1159 }
1160
1161 static void kv_restore_regs_for_reset(struct amdgpu_device *adev,
1162                                       struct kv_reset_save_regs *save)
1163 {
1164         int i;
1165
1166         WREG32(mmGMCON_PGFSM_WRITE, 0);
1167         WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff);
1168
1169         for (i = 0; i < 5; i++)
1170                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1171
1172         WREG32(mmGMCON_PGFSM_WRITE, 0);
1173         WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff);
1174
1175         for (i = 0; i < 5; i++)
1176                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1177
1178         WREG32(mmGMCON_PGFSM_WRITE, 0x210000);
1179         WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff);
1180
1181         for (i = 0; i < 5; i++)
1182                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1183
1184         WREG32(mmGMCON_PGFSM_WRITE, 0x21003);
1185         WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff);
1186
1187         for (i = 0; i < 5; i++)
1188                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1189
1190         WREG32(mmGMCON_PGFSM_WRITE, 0x2b00);
1191         WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff);
1192
1193         for (i = 0; i < 5; i++)
1194                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1195
1196         WREG32(mmGMCON_PGFSM_WRITE, 0);
1197         WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff);
1198
1199         for (i = 0; i < 5; i++)
1200                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1201
1202         WREG32(mmGMCON_PGFSM_WRITE, 0x420000);
1203         WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff);
1204
1205         for (i = 0; i < 5; i++)
1206                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1207
1208         WREG32(mmGMCON_PGFSM_WRITE, 0x120202);
1209         WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff);
1210
1211         for (i = 0; i < 5; i++)
1212                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1213
1214         WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36);
1215         WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff);
1216
1217         for (i = 0; i < 5; i++)
1218                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1219
1220         WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e);
1221         WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff);
1222
1223         for (i = 0; i < 5; i++)
1224                 WREG32(mmGMCON_PGFSM_WRITE, 0);
1225
1226         WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332);
1227         WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff);
1228
1229         WREG32(mmGMCON_MISC3, save->gmcon_misc3);
1230         WREG32(mmGMCON_MISC, save->gmcon_misc);
1231         WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);
1232 }
1233
1234 static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
1235 {
1236         struct kv_reset_save_regs kv_save = { 0 };
1237         u32 i;
1238         int r = -EINVAL;
1239
1240         dev_info(adev->dev, "GPU pci config reset\n");
1241
1242         if (adev->flags & AMD_IS_APU)
1243                 kv_save_regs_for_reset(adev, &kv_save);
1244
1245         /* disable BM */
1246         pci_clear_master(adev->pdev);
1247         /* reset */
1248         amdgpu_device_pci_config_reset(adev);
1249
1250         udelay(100);
1251
1252         /* wait for asic to come out of reset */
1253         for (i = 0; i < adev->usec_timeout; i++) {
1254                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
1255                         /* enable BM */
1256                         pci_set_master(adev->pdev);
1257                         adev->has_hw_reset = true;
1258                         r = 0;
1259                         break;
1260                 }
1261                 udelay(1);
1262         }
1263
1264         /* does asic init need to be run first??? */
1265         if (adev->flags & AMD_IS_APU)
1266                 kv_restore_regs_for_reset(adev, &kv_save);
1267
1268         return r;
1269 }
1270
1271 /**
1272  * cik_asic_reset - soft reset GPU
1273  *
1274  * @adev: amdgpu_device pointer
1275  *
1276  * Look up which blocks are hung and attempt
1277  * to reset them.
1278  * Returns 0 for success.
1279  */
1280 static int cik_asic_reset(struct amdgpu_device *adev)
1281 {
1282         int r;
1283
1284         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
1285
1286         r = cik_gpu_pci_config_reset(adev);
1287
1288         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
1289
1290         return r;
1291 }
1292
1293 static u32 cik_get_config_memsize(struct amdgpu_device *adev)
1294 {
1295         return RREG32(mmCONFIG_MEMSIZE);
1296 }
1297
1298 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1299                               u32 cntl_reg, u32 status_reg)
1300 {
1301         int r, i;
1302         struct atom_clock_dividers dividers;
1303         uint32_t tmp;
1304
1305         r = amdgpu_atombios_get_clock_dividers(adev,
1306                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1307                                                clock, false, &dividers);
1308         if (r)
1309                 return r;
1310
1311         tmp = RREG32_SMC(cntl_reg);
1312         tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
1313                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
1314         tmp |= dividers.post_divider;
1315         WREG32_SMC(cntl_reg, tmp);
1316
1317         for (i = 0; i < 100; i++) {
1318                 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1319                         break;
1320                 mdelay(10);
1321         }
1322         if (i == 100)
1323                 return -ETIMEDOUT;
1324
1325         return 0;
1326 }
1327
1328 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1329 {
1330         int r = 0;
1331
1332         r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1333         if (r)
1334                 return r;
1335
1336         r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1337         return r;
1338 }
1339
1340 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1341 {
1342         int r, i;
1343         struct atom_clock_dividers dividers;
1344         u32 tmp;
1345
1346         r = amdgpu_atombios_get_clock_dividers(adev,
1347                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1348                                                ecclk, false, &dividers);
1349         if (r)
1350                 return r;
1351
1352         for (i = 0; i < 100; i++) {
1353                 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1354                         break;
1355                 mdelay(10);
1356         }
1357         if (i == 100)
1358                 return -ETIMEDOUT;
1359
1360         tmp = RREG32_SMC(ixCG_ECLK_CNTL);
1361         tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
1362                 CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
1363         tmp |= dividers.post_divider;
1364         WREG32_SMC(ixCG_ECLK_CNTL, tmp);
1365
1366         for (i = 0; i < 100; i++) {
1367                 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1368                         break;
1369                 mdelay(10);
1370         }
1371         if (i == 100)
1372                 return -ETIMEDOUT;
1373
1374         return 0;
1375 }
1376
1377 static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
1378 {
1379         struct pci_dev *root = adev->pdev->bus->self;
1380         int bridge_pos, gpu_pos;
1381         u32 speed_cntl, current_data_rate;
1382         int i;
1383         u16 tmp16;
1384
1385         if (pci_is_root_bus(adev->pdev->bus))
1386                 return;
1387
1388         if (amdgpu_pcie_gen2 == 0)
1389                 return;
1390
1391         if (adev->flags & AMD_IS_APU)
1392                 return;
1393
1394         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1395                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1396                 return;
1397
1398         speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1399         current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >>
1400                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1401         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1402                 if (current_data_rate == 2) {
1403                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1404                         return;
1405                 }
1406                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1407         } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1408                 if (current_data_rate == 1) {
1409                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1410                         return;
1411                 }
1412                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1413         }
1414
1415         bridge_pos = pci_pcie_cap(root);
1416         if (!bridge_pos)
1417                 return;
1418
1419         gpu_pos = pci_pcie_cap(adev->pdev);
1420         if (!gpu_pos)
1421                 return;
1422
1423         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1424                 /* re-try equalization if gen3 is not already enabled */
1425                 if (current_data_rate != 2) {
1426                         u16 bridge_cfg, gpu_cfg;
1427                         u16 bridge_cfg2, gpu_cfg2;
1428                         u32 max_lw, current_lw, tmp;
1429
1430                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1431                         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1432
1433                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1434                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1435
1436                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1437                         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1438
1439                         tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
1440                         max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
1441                                 PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT;
1442                         current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK)
1443                                 >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT;
1444
1445                         if (current_lw < max_lw) {
1446                                 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1447                                 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
1448                                         tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK |
1449                                                 PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK);
1450                                         tmp |= (max_lw <<
1451                                                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT);
1452                                         tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK |
1453                                         PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK |
1454                                         PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK;
1455                                         WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
1456                                 }
1457                         }
1458
1459                         for (i = 0; i < 10; i++) {
1460                                 /* check status */
1461                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1462                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1463                                         break;
1464
1465                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1466                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1467
1468                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1469                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1470
1471                                 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1472                                 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
1473                                 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1474
1475                                 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1476                                 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
1477                                 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1478
1479                                 msleep(100);
1480
1481                                 /* linkctl */
1482                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1483                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1484                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1485                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1486
1487                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1488                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1489                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1490                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1491
1492                                 /* linkctl2 */
1493                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1494                                 tmp16 &= ~((1 << 4) | (7 << 9));
1495                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1496                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1497
1498                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1499                                 tmp16 &= ~((1 << 4) | (7 << 9));
1500                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1501                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1502
1503                                 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1504                                 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
1505                                 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1506                         }
1507                 }
1508         }
1509
1510         /* set the link speed */
1511         speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK |
1512                 PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK;
1513         speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
1514         WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
1515
1516         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1517         tmp16 &= ~0xf;
1518         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1519                 tmp16 |= 3; /* gen3 */
1520         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1521                 tmp16 |= 2; /* gen2 */
1522         else
1523                 tmp16 |= 1; /* gen1 */
1524         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1525
1526         speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1527         speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
1528         WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
1529
1530         for (i = 0; i < adev->usec_timeout; i++) {
1531                 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1532                 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0)
1533                         break;
1534                 udelay(1);
1535         }
1536 }
1537
1538 static void cik_program_aspm(struct amdgpu_device *adev)
1539 {
1540         u32 data, orig;
1541         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1542         bool disable_clkreq = false;
1543
1544         if (amdgpu_aspm == 0)
1545                 return;
1546
1547         if (pci_is_root_bus(adev->pdev->bus))
1548                 return;
1549
1550         /* XXX double check APUs */
1551         if (adev->flags & AMD_IS_APU)
1552                 return;
1553
1554         orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1555         data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
1556         data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) |
1557                 PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
1558         if (orig != data)
1559                 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
1560
1561         orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
1562         data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
1563         if (orig != data)
1564                 WREG32_PCIE(ixPCIE_LC_CNTL3, data);
1565
1566         orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
1567         data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
1568         if (orig != data)
1569                 WREG32_PCIE(ixPCIE_P_CNTL, data);
1570
1571         orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1572         data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK |
1573                 PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
1574         data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1575         if (!disable_l0s)
1576                 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT);
1577
1578         if (!disable_l1) {
1579                 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT);
1580                 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1581                 if (orig != data)
1582                         WREG32_PCIE(ixPCIE_LC_CNTL, data);
1583
1584                 if (!disable_plloff_in_l1) {
1585                         bool clk_req_support;
1586
1587                         orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0);
1588                         data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1589                                 PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
1590                         data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1591                                 (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
1592                         if (orig != data)
1593                                 WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data);
1594
1595                         orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1);
1596                         data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1597                                 PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
1598                         data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1599                                 (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
1600                         if (orig != data)
1601                                 WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data);
1602
1603                         orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0);
1604                         data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1605                                 PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
1606                         data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1607                                 (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
1608                         if (orig != data)
1609                                 WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data);
1610
1611                         orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1);
1612                         data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1613                                 PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
1614                         data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1615                                 (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
1616                         if (orig != data)
1617                                 WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data);
1618
1619                         orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1620                         data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
1621                         data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);
1622                         if (orig != data)
1623                                 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
1624
1625                         if (!disable_clkreq) {
1626                                 struct pci_dev *root = adev->pdev->bus->self;
1627                                 u32 lnkcap;
1628
1629                                 clk_req_support = false;
1630                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1631                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1632                                         clk_req_support = true;
1633                         } else {
1634                                 clk_req_support = false;
1635                         }
1636
1637                         if (clk_req_support) {
1638                                 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
1639                                 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
1640                                         PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
1641                                 if (orig != data)
1642                                         WREG32_PCIE(ixPCIE_LC_CNTL2, data);
1643
1644                                 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1645                                 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK |
1646                                         THM_CLK_CNTL__TMON_CLK_SEL_MASK);
1647                                 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
1648                                         (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);
1649                                 if (orig != data)
1650                                         WREG32_SMC(ixTHM_CLK_CNTL, data);
1651
1652                                 orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
1653                                 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
1654                                         MISC_CLK_CTRL__ZCLK_SEL_MASK);
1655                                 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
1656                                         (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT);
1657                                 if (orig != data)
1658                                         WREG32_SMC(ixMISC_CLK_CTRL, data);
1659
1660                                 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
1661                                 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;
1662                                 if (orig != data)
1663                                         WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1664
1665                                 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1666                                 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK;
1667                                 if (orig != data)
1668                                         WREG32_SMC(ixCG_CLKPIN_CNTL_2, data);
1669
1670                                 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
1671                                 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
1672                                 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
1673                                 if (orig != data)
1674                                         WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
1675                         }
1676                 }
1677         } else {
1678                 if (orig != data)
1679                         WREG32_PCIE(ixPCIE_LC_CNTL, data);
1680         }
1681
1682         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
1683         data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1684                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1685                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1686         if (orig != data)
1687                 WREG32_PCIE(ixPCIE_CNTL2, data);
1688
1689         if (!disable_l0s) {
1690                 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1691                 if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) ==
1692                                 PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) {
1693                         data = RREG32_PCIE(ixPCIE_LC_STATUS1);
1694                         if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) &&
1695                         (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) {
1696                                 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1697                                 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1698                                 if (orig != data)
1699                                         WREG32_PCIE(ixPCIE_LC_CNTL, data);
1700                         }
1701                 }
1702         }
1703 }
1704
1705 static uint32_t cik_get_rev_id(struct amdgpu_device *adev)
1706 {
1707         return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1708                 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1709 }
1710
1711 static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
1712 {
1713         if (is_virtual_machine()) /* passthrough mode */
1714                 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
1715 }
1716
1717 static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1718 {
1719         if (!ring || !ring->funcs->emit_wreg) {
1720                 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1721                 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1722         } else {
1723                 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1724         }
1725 }
1726
1727 static void cik_invalidate_hdp(struct amdgpu_device *adev,
1728                                struct amdgpu_ring *ring)
1729 {
1730         if (!ring || !ring->funcs->emit_wreg) {
1731                 WREG32(mmHDP_DEBUG0, 1);
1732                 RREG32(mmHDP_DEBUG0);
1733         } else {
1734                 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
1735         }
1736 }
1737
1738 static bool cik_need_full_reset(struct amdgpu_device *adev)
1739 {
1740         /* change this when we support soft reset */
1741         return true;
1742 }
1743
1744 static const struct amdgpu_asic_funcs cik_asic_funcs =
1745 {
1746         .read_disabled_bios = &cik_read_disabled_bios,
1747         .read_bios_from_rom = &cik_read_bios_from_rom,
1748         .read_register = &cik_read_register,
1749         .reset = &cik_asic_reset,
1750         .set_vga_state = &cik_vga_set_state,
1751         .get_xclk = &cik_get_xclk,
1752         .set_uvd_clocks = &cik_set_uvd_clocks,
1753         .set_vce_clocks = &cik_set_vce_clocks,
1754         .get_config_memsize = &cik_get_config_memsize,
1755         .flush_hdp = &cik_flush_hdp,
1756         .invalidate_hdp = &cik_invalidate_hdp,
1757         .need_full_reset = &cik_need_full_reset,
1758 };
1759
1760 static int cik_common_early_init(void *handle)
1761 {
1762         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1763
1764         adev->smc_rreg = &cik_smc_rreg;
1765         adev->smc_wreg = &cik_smc_wreg;
1766         adev->pcie_rreg = &cik_pcie_rreg;
1767         adev->pcie_wreg = &cik_pcie_wreg;
1768         adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;
1769         adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg;
1770         adev->didt_rreg = &cik_didt_rreg;
1771         adev->didt_wreg = &cik_didt_wreg;
1772
1773         adev->asic_funcs = &cik_asic_funcs;
1774
1775         adev->rev_id = cik_get_rev_id(adev);
1776         adev->external_rev_id = 0xFF;
1777         switch (adev->asic_type) {
1778         case CHIP_BONAIRE:
1779                 adev->cg_flags =
1780                         AMD_CG_SUPPORT_GFX_MGCG |
1781                         AMD_CG_SUPPORT_GFX_MGLS |
1782                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1783                         AMD_CG_SUPPORT_GFX_CGLS |
1784                         AMD_CG_SUPPORT_GFX_CGTS |
1785                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1786                         AMD_CG_SUPPORT_GFX_CP_LS |
1787                         AMD_CG_SUPPORT_MC_LS |
1788                         AMD_CG_SUPPORT_MC_MGCG |
1789                         AMD_CG_SUPPORT_SDMA_MGCG |
1790                         AMD_CG_SUPPORT_SDMA_LS |
1791                         AMD_CG_SUPPORT_BIF_LS |
1792                         AMD_CG_SUPPORT_VCE_MGCG |
1793                         AMD_CG_SUPPORT_UVD_MGCG |
1794                         AMD_CG_SUPPORT_HDP_LS |
1795                         AMD_CG_SUPPORT_HDP_MGCG;
1796                 adev->pg_flags = 0;
1797                 adev->external_rev_id = adev->rev_id + 0x14;
1798                 break;
1799         case CHIP_HAWAII:
1800                 adev->cg_flags =
1801                         AMD_CG_SUPPORT_GFX_MGCG |
1802                         AMD_CG_SUPPORT_GFX_MGLS |
1803                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1804                         AMD_CG_SUPPORT_GFX_CGLS |
1805                         AMD_CG_SUPPORT_GFX_CGTS |
1806                         AMD_CG_SUPPORT_GFX_CP_LS |
1807                         AMD_CG_SUPPORT_MC_LS |
1808                         AMD_CG_SUPPORT_MC_MGCG |
1809                         AMD_CG_SUPPORT_SDMA_MGCG |
1810                         AMD_CG_SUPPORT_SDMA_LS |
1811                         AMD_CG_SUPPORT_BIF_LS |
1812                         AMD_CG_SUPPORT_VCE_MGCG |
1813                         AMD_CG_SUPPORT_UVD_MGCG |
1814                         AMD_CG_SUPPORT_HDP_LS |
1815                         AMD_CG_SUPPORT_HDP_MGCG;
1816                 adev->pg_flags = 0;
1817                 adev->external_rev_id = 0x28;
1818                 break;
1819         case CHIP_KAVERI:
1820                 adev->cg_flags =
1821                         AMD_CG_SUPPORT_GFX_MGCG |
1822                         AMD_CG_SUPPORT_GFX_MGLS |
1823                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1824                         AMD_CG_SUPPORT_GFX_CGLS |
1825                         AMD_CG_SUPPORT_GFX_CGTS |
1826                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1827                         AMD_CG_SUPPORT_GFX_CP_LS |
1828                         AMD_CG_SUPPORT_SDMA_MGCG |
1829                         AMD_CG_SUPPORT_SDMA_LS |
1830                         AMD_CG_SUPPORT_BIF_LS |
1831                         AMD_CG_SUPPORT_VCE_MGCG |
1832                         AMD_CG_SUPPORT_UVD_MGCG |
1833                         AMD_CG_SUPPORT_HDP_LS |
1834                         AMD_CG_SUPPORT_HDP_MGCG;
1835                 adev->pg_flags =
1836                         /*AMD_PG_SUPPORT_GFX_PG |
1837                           AMD_PG_SUPPORT_GFX_SMG |
1838                           AMD_PG_SUPPORT_GFX_DMG |*/
1839                         AMD_PG_SUPPORT_UVD |
1840                         AMD_PG_SUPPORT_VCE |
1841                         /*  AMD_PG_SUPPORT_CP |
1842                           AMD_PG_SUPPORT_GDS |
1843                           AMD_PG_SUPPORT_RLC_SMU_HS |
1844                           AMD_PG_SUPPORT_ACP |
1845                           AMD_PG_SUPPORT_SAMU |*/
1846                         0;
1847                 if (adev->pdev->device == 0x1312 ||
1848                         adev->pdev->device == 0x1316 ||
1849                         adev->pdev->device == 0x1317)
1850                         adev->external_rev_id = 0x41;
1851                 else
1852                         adev->external_rev_id = 0x1;
1853                 break;
1854         case CHIP_KABINI:
1855         case CHIP_MULLINS:
1856                 adev->cg_flags =
1857                         AMD_CG_SUPPORT_GFX_MGCG |
1858                         AMD_CG_SUPPORT_GFX_MGLS |
1859                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1860                         AMD_CG_SUPPORT_GFX_CGLS |
1861                         AMD_CG_SUPPORT_GFX_CGTS |
1862                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1863                         AMD_CG_SUPPORT_GFX_CP_LS |
1864                         AMD_CG_SUPPORT_SDMA_MGCG |
1865                         AMD_CG_SUPPORT_SDMA_LS |
1866                         AMD_CG_SUPPORT_BIF_LS |
1867                         AMD_CG_SUPPORT_VCE_MGCG |
1868                         AMD_CG_SUPPORT_UVD_MGCG |
1869                         AMD_CG_SUPPORT_HDP_LS |
1870                         AMD_CG_SUPPORT_HDP_MGCG;
1871                 adev->pg_flags =
1872                         /*AMD_PG_SUPPORT_GFX_PG |
1873                           AMD_PG_SUPPORT_GFX_SMG | */
1874                         AMD_PG_SUPPORT_UVD |
1875                         /*AMD_PG_SUPPORT_VCE |
1876                           AMD_PG_SUPPORT_CP |
1877                           AMD_PG_SUPPORT_GDS |
1878                           AMD_PG_SUPPORT_RLC_SMU_HS |
1879                           AMD_PG_SUPPORT_SAMU |*/
1880                         0;
1881                 if (adev->asic_type == CHIP_KABINI) {
1882                         if (adev->rev_id == 0)
1883                                 adev->external_rev_id = 0x81;
1884                         else if (adev->rev_id == 1)
1885                                 adev->external_rev_id = 0x82;
1886                         else if (adev->rev_id == 2)
1887                                 adev->external_rev_id = 0x85;
1888                 } else
1889                         adev->external_rev_id = adev->rev_id + 0xa1;
1890                 break;
1891         default:
1892                 /* FIXME: not supported yet */
1893                 return -EINVAL;
1894         }
1895
1896         return 0;
1897 }
1898
1899 static int cik_common_sw_init(void *handle)
1900 {
1901         return 0;
1902 }
1903
1904 static int cik_common_sw_fini(void *handle)
1905 {
1906         return 0;
1907 }
1908
1909 static int cik_common_hw_init(void *handle)
1910 {
1911         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1912
1913         /* move the golden regs per IP block */
1914         cik_init_golden_registers(adev);
1915         /* enable pcie gen2/3 link */
1916         cik_pcie_gen3_enable(adev);
1917         /* enable aspm */
1918         cik_program_aspm(adev);
1919
1920         return 0;
1921 }
1922
1923 static int cik_common_hw_fini(void *handle)
1924 {
1925         return 0;
1926 }
1927
1928 static int cik_common_suspend(void *handle)
1929 {
1930         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1931
1932         return cik_common_hw_fini(adev);
1933 }
1934
1935 static int cik_common_resume(void *handle)
1936 {
1937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1938
1939         return cik_common_hw_init(adev);
1940 }
1941
1942 static bool cik_common_is_idle(void *handle)
1943 {
1944         return true;
1945 }
1946
1947 static int cik_common_wait_for_idle(void *handle)
1948 {
1949         return 0;
1950 }
1951
1952 static int cik_common_soft_reset(void *handle)
1953 {
1954         /* XXX hard reset?? */
1955         return 0;
1956 }
1957
1958 static int cik_common_set_clockgating_state(void *handle,
1959                                             enum amd_clockgating_state state)
1960 {
1961         return 0;
1962 }
1963
1964 static int cik_common_set_powergating_state(void *handle,
1965                                             enum amd_powergating_state state)
1966 {
1967         return 0;
1968 }
1969
1970 static const struct amd_ip_funcs cik_common_ip_funcs = {
1971         .name = "cik_common",
1972         .early_init = cik_common_early_init,
1973         .late_init = NULL,
1974         .sw_init = cik_common_sw_init,
1975         .sw_fini = cik_common_sw_fini,
1976         .hw_init = cik_common_hw_init,
1977         .hw_fini = cik_common_hw_fini,
1978         .suspend = cik_common_suspend,
1979         .resume = cik_common_resume,
1980         .is_idle = cik_common_is_idle,
1981         .wait_for_idle = cik_common_wait_for_idle,
1982         .soft_reset = cik_common_soft_reset,
1983         .set_clockgating_state = cik_common_set_clockgating_state,
1984         .set_powergating_state = cik_common_set_powergating_state,
1985 };
1986
1987 static const struct amdgpu_ip_block_version cik_common_ip_block =
1988 {
1989         .type = AMD_IP_BLOCK_TYPE_COMMON,
1990         .major = 1,
1991         .minor = 0,
1992         .rev = 0,
1993         .funcs = &cik_common_ip_funcs,
1994 };
1995
1996 int cik_set_ip_blocks(struct amdgpu_device *adev)
1997 {
1998         cik_detect_hw_virtualization(adev);
1999
2000         switch (adev->asic_type) {
2001         case CHIP_BONAIRE:
2002                 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2003                 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2004                 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2005                 if (amdgpu_dpm == -1)
2006                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2007                 else
2008                         amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
2009                 if (adev->enable_virtual_display)
2010                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2011 #if defined(CONFIG_DRM_AMD_DC)
2012                 else if (amdgpu_device_has_dc_support(adev))
2013                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2014 #endif
2015                 else
2016                         amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);
2017                 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
2018                 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2019                 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2020                 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2021                 break;
2022         case CHIP_HAWAII:
2023                 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2024                 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2025                 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2026                 if (amdgpu_dpm == -1)
2027                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2028                 else
2029                         amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
2030                 if (adev->enable_virtual_display)
2031                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2032 #if defined(CONFIG_DRM_AMD_DC)
2033                 else if (amdgpu_device_has_dc_support(adev))
2034                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2035 #endif
2036                 else
2037                         amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);
2038                 amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
2039                 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2040                 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2041                 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2042                 break;
2043         case CHIP_KAVERI:
2044                 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2045                 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2046                 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2047                 amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
2048                 if (adev->enable_virtual_display)
2049                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2050 #if defined(CONFIG_DRM_AMD_DC)
2051                 else if (amdgpu_device_has_dc_support(adev))
2052                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2053 #endif
2054                 else
2055                         amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
2056                 amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
2057                 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2058                 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2059                 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2060                 break;
2061         case CHIP_KABINI:
2062         case CHIP_MULLINS:
2063                 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2064                 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2065                 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2066                 amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
2067                 if (adev->enable_virtual_display)
2068                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2069 #if defined(CONFIG_DRM_AMD_DC)
2070                 else if (amdgpu_device_has_dc_support(adev))
2071                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2072 #endif
2073                 else
2074                         amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);
2075                 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
2076                 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2077                 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2078                 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2079                 break;
2080         default:
2081                 /* FIXME: not supported yet */
2082                 return -EINVAL;
2083         }
2084         return 0;
2085 }