2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_pm.h"
28 #include "amdgpu_ucode.h"
30 #include "amdgpu_dpm.h"
35 #include <linux/seq_file.h>
37 #include "smu/smu_7_0_1_d.h"
38 #include "smu/smu_7_0_1_sh_mask.h"
40 #include "dce/dce_8_0_d.h"
41 #include "dce/dce_8_0_sh_mask.h"
43 #include "bif/bif_4_1_d.h"
44 #include "bif/bif_4_1_sh_mask.h"
46 #include "gca/gfx_7_2_d.h"
47 #include "gca/gfx_7_2_sh_mask.h"
49 #include "gmc/gmc_7_1_d.h"
50 #include "gmc/gmc_7_1_sh_mask.h"
54 #define MC_CG_ARB_FREQ_F0 0x0a
55 #define MC_CG_ARB_FREQ_F1 0x0b
56 #define MC_CG_ARB_FREQ_F2 0x0c
57 #define MC_CG_ARB_FREQ_F3 0x0d
59 #define SMC_RAM_END 0x40000
61 #define VOLTAGE_SCALE 4
62 #define VOLTAGE_VID_OFFSET_SCALE1 625
63 #define VOLTAGE_VID_OFFSET_SCALE2 100
65 static const struct amd_pm_funcs ci_dpm_funcs;
67 static const struct ci_pt_defaults defaults_hawaii_xt =
69 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
70 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
71 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
74 static const struct ci_pt_defaults defaults_hawaii_pro =
76 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
77 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
78 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
81 static const struct ci_pt_defaults defaults_bonaire_xt =
83 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
84 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
85 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
89 static const struct ci_pt_defaults defaults_bonaire_pro =
91 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
92 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
93 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
97 static const struct ci_pt_defaults defaults_saturn_xt =
99 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
100 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
101 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
105 static const struct ci_pt_defaults defaults_saturn_pro =
107 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
108 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
109 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
113 static const struct ci_pt_config_reg didt_config_ci[] =
115 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
163 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
164 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
165 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
166 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
167 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
168 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
169 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
170 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
171 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
172 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
173 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
174 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
175 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
176 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
177 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
178 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
179 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
180 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
181 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
182 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
183 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
184 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
185 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
186 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
190 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
192 return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
195 #define MC_CG_ARB_FREQ_F0 0x0a
196 #define MC_CG_ARB_FREQ_F1 0x0b
197 #define MC_CG_ARB_FREQ_F2 0x0c
198 #define MC_CG_ARB_FREQ_F3 0x0d
200 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
201 u32 arb_freq_src, u32 arb_freq_dest)
203 u32 mc_arb_dram_timing;
204 u32 mc_arb_dram_timing2;
208 switch (arb_freq_src) {
209 case MC_CG_ARB_FREQ_F0:
210 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
211 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
212 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
213 MC_ARB_BURST_TIME__STATE0__SHIFT;
215 case MC_CG_ARB_FREQ_F1:
216 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1);
217 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
218 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
219 MC_ARB_BURST_TIME__STATE1__SHIFT;
225 switch (arb_freq_dest) {
226 case MC_CG_ARB_FREQ_F0:
227 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
228 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
229 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
230 ~MC_ARB_BURST_TIME__STATE0_MASK);
232 case MC_CG_ARB_FREQ_F1:
233 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
234 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
235 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
236 ~MC_ARB_BURST_TIME__STATE1_MASK);
242 mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
243 WREG32(mmMC_CG_CONFIG, mc_cg_config);
244 WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
245 ~MC_ARB_CG__CG_ARB_REQ_MASK);
250 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
254 if (memory_clock < 10000)
256 else if (memory_clock >= 80000)
257 mc_para_index = 0x0f;
259 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
260 return mc_para_index;
263 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
268 if (memory_clock < 12500)
269 mc_para_index = 0x00;
270 else if (memory_clock > 47500)
271 mc_para_index = 0x0f;
273 mc_para_index = (u8)((memory_clock - 10000) / 2500);
275 if (memory_clock < 65000)
276 mc_para_index = 0x00;
277 else if (memory_clock > 135000)
278 mc_para_index = 0x0f;
280 mc_para_index = (u8)((memory_clock - 60000) / 5000);
282 return mc_para_index;
285 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
286 u32 max_voltage_steps,
287 struct atom_voltage_table *voltage_table)
289 unsigned int i, diff;
291 if (voltage_table->count <= max_voltage_steps)
294 diff = voltage_table->count - max_voltage_steps;
296 for (i = 0; i < max_voltage_steps; i++)
297 voltage_table->entries[i] = voltage_table->entries[i + diff];
299 voltage_table->count = max_voltage_steps;
302 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
303 struct atom_voltage_table_entry *voltage_table,
304 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
305 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
306 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
308 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
309 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
311 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
312 PPSMC_Msg msg, u32 parameter);
313 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
314 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
316 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
318 struct ci_power_info *pi = adev->pm.dpm.priv;
323 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
325 struct ci_ps *ps = rps->ps_priv;
330 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
332 struct ci_power_info *pi = ci_get_pi(adev);
334 switch (adev->pdev->device) {
342 pi->powertune_defaults = &defaults_bonaire_xt;
348 pi->powertune_defaults = &defaults_saturn_xt;
352 pi->powertune_defaults = &defaults_hawaii_xt;
356 pi->powertune_defaults = &defaults_hawaii_pro;
366 pi->powertune_defaults = &defaults_bonaire_xt;
370 pi->dte_tj_offset = 0;
372 pi->caps_power_containment = true;
373 pi->caps_cac = false;
374 pi->caps_sq_ramping = false;
375 pi->caps_db_ramping = false;
376 pi->caps_td_ramping = false;
377 pi->caps_tcp_ramping = false;
379 if (pi->caps_power_containment) {
381 if (adev->asic_type == CHIP_HAWAII)
382 pi->enable_bapm_feature = false;
384 pi->enable_bapm_feature = true;
385 pi->enable_tdc_limit_feature = true;
386 pi->enable_pkg_pwr_tracking_feature = true;
390 static u8 ci_convert_to_vid(u16 vddc)
392 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
395 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
397 struct ci_power_info *pi = ci_get_pi(adev);
398 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
399 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
400 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
403 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
405 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
407 if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
408 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
411 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
412 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
413 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
414 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
415 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
417 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
418 hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
424 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
426 struct ci_power_info *pi = ci_get_pi(adev);
427 u8 *vid = pi->smc_powertune_table.VddCVid;
430 if (pi->vddc_voltage_table.count > 8)
433 for (i = 0; i < pi->vddc_voltage_table.count; i++)
434 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
439 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
441 struct ci_power_info *pi = ci_get_pi(adev);
442 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
444 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
445 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
446 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
447 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
452 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
454 struct ci_power_info *pi = ci_get_pi(adev);
455 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
458 tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
459 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
460 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
461 pt_defaults->tdc_vddc_throttle_release_limit_perc;
462 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
467 static int ci_populate_dw8(struct amdgpu_device *adev)
469 struct ci_power_info *pi = ci_get_pi(adev);
470 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
473 ret = amdgpu_ci_read_smc_sram_dword(adev,
474 SMU7_FIRMWARE_HEADER_LOCATION +
475 offsetof(SMU7_Firmware_Header, PmFuseTable) +
476 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
477 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
482 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
487 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
489 struct ci_power_info *pi = ci_get_pi(adev);
491 if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
492 (adev->pm.dpm.fan.fan_output_sensitivity == 0))
493 adev->pm.dpm.fan.fan_output_sensitivity =
494 adev->pm.dpm.fan.default_fan_output_sensitivity;
496 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
497 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
502 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
504 struct ci_power_info *pi = ci_get_pi(adev);
505 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
506 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
509 min = max = hi_vid[0];
510 for (i = 0; i < 8; i++) {
511 if (0 != hi_vid[i]) {
518 if (0 != lo_vid[i]) {
526 if ((min == 0) || (max == 0))
528 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
529 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
534 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
536 struct ci_power_info *pi = ci_get_pi(adev);
537 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
538 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
539 struct amdgpu_cac_tdp_table *cac_tdp_table =
540 adev->pm.dpm.dyn_state.cac_tdp_table;
542 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
543 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
545 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
546 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
551 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
553 struct ci_power_info *pi = ci_get_pi(adev);
554 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
555 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
556 struct amdgpu_cac_tdp_table *cac_tdp_table =
557 adev->pm.dpm.dyn_state.cac_tdp_table;
558 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
563 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
564 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
566 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
567 dpm_table->GpuTjMax =
568 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
569 dpm_table->GpuTjHyst = 8;
571 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
574 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
575 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
577 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
578 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
581 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
582 def1 = pt_defaults->bapmti_r;
583 def2 = pt_defaults->bapmti_rc;
585 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
586 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
587 for (k = 0; k < SMU7_DTE_SINKS; k++) {
588 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
589 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
599 static int ci_populate_pm_base(struct amdgpu_device *adev)
601 struct ci_power_info *pi = ci_get_pi(adev);
602 u32 pm_fuse_table_offset;
605 if (pi->caps_power_containment) {
606 ret = amdgpu_ci_read_smc_sram_dword(adev,
607 SMU7_FIRMWARE_HEADER_LOCATION +
608 offsetof(SMU7_Firmware_Header, PmFuseTable),
609 &pm_fuse_table_offset, pi->sram_end);
612 ret = ci_populate_bapm_vddc_vid_sidd(adev);
615 ret = ci_populate_vddc_vid(adev);
618 ret = ci_populate_svi_load_line(adev);
621 ret = ci_populate_tdc_limit(adev);
624 ret = ci_populate_dw8(adev);
627 ret = ci_populate_fuzzy_fan(adev);
630 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
633 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
636 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
637 (u8 *)&pi->smc_powertune_table,
638 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
646 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
648 struct ci_power_info *pi = ci_get_pi(adev);
651 if (pi->caps_sq_ramping) {
652 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
654 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
656 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
657 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
660 if (pi->caps_db_ramping) {
661 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
663 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
665 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
666 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
669 if (pi->caps_td_ramping) {
670 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
672 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
674 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
675 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
678 if (pi->caps_tcp_ramping) {
679 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
681 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
683 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
684 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
688 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
689 const struct ci_pt_config_reg *cac_config_regs)
691 const struct ci_pt_config_reg *config_regs = cac_config_regs;
695 if (config_regs == NULL)
698 while (config_regs->offset != 0xFFFFFFFF) {
699 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
700 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
702 switch (config_regs->type) {
703 case CISLANDS_CONFIGREG_SMC_IND:
704 data = RREG32_SMC(config_regs->offset);
706 case CISLANDS_CONFIGREG_DIDT_IND:
707 data = RREG32_DIDT(config_regs->offset);
710 data = RREG32(config_regs->offset);
714 data &= ~config_regs->mask;
715 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
718 switch (config_regs->type) {
719 case CISLANDS_CONFIGREG_SMC_IND:
720 WREG32_SMC(config_regs->offset, data);
722 case CISLANDS_CONFIGREG_DIDT_IND:
723 WREG32_DIDT(config_regs->offset, data);
726 WREG32(config_regs->offset, data);
736 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
738 struct ci_power_info *pi = ci_get_pi(adev);
741 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
742 pi->caps_td_ramping || pi->caps_tcp_ramping) {
743 adev->gfx.rlc.funcs->enter_safe_mode(adev);
746 ret = ci_program_pt_config_registers(adev, didt_config_ci);
748 adev->gfx.rlc.funcs->exit_safe_mode(adev);
753 ci_do_enable_didt(adev, enable);
755 adev->gfx.rlc.funcs->exit_safe_mode(adev);
761 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
763 struct ci_power_info *pi = ci_get_pi(adev);
764 PPSMC_Result smc_result;
768 pi->power_containment_features = 0;
769 if (pi->caps_power_containment) {
770 if (pi->enable_bapm_feature) {
771 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
772 if (smc_result != PPSMC_Result_OK)
775 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
778 if (pi->enable_tdc_limit_feature) {
779 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
780 if (smc_result != PPSMC_Result_OK)
783 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
786 if (pi->enable_pkg_pwr_tracking_feature) {
787 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
788 if (smc_result != PPSMC_Result_OK) {
791 struct amdgpu_cac_tdp_table *cac_tdp_table =
792 adev->pm.dpm.dyn_state.cac_tdp_table;
793 u32 default_pwr_limit =
794 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
796 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
798 ci_set_power_limit(adev, default_pwr_limit);
803 if (pi->caps_power_containment && pi->power_containment_features) {
804 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
805 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
807 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
808 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
810 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
811 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
812 pi->power_containment_features = 0;
819 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
821 struct ci_power_info *pi = ci_get_pi(adev);
822 PPSMC_Result smc_result;
827 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
828 if (smc_result != PPSMC_Result_OK) {
830 pi->cac_enabled = false;
832 pi->cac_enabled = true;
834 } else if (pi->cac_enabled) {
835 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
836 pi->cac_enabled = false;
843 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
846 struct ci_power_info *pi = ci_get_pi(adev);
847 PPSMC_Result smc_result = PPSMC_Result_OK;
849 if (pi->thermal_sclk_dpm_enabled) {
851 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
853 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
856 if (smc_result == PPSMC_Result_OK)
862 static int ci_power_control_set_level(struct amdgpu_device *adev)
864 struct ci_power_info *pi = ci_get_pi(adev);
865 struct amdgpu_cac_tdp_table *cac_tdp_table =
866 adev->pm.dpm.dyn_state.cac_tdp_table;
870 bool adjust_polarity = false; /* ??? */
872 if (pi->caps_power_containment) {
873 adjust_percent = adjust_polarity ?
874 adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
875 target_tdp = ((100 + adjust_percent) *
876 (s32)cac_tdp_table->configurable_tdp) / 100;
878 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
884 static void ci_dpm_powergate_uvd(void *handle, bool gate)
886 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
887 struct ci_power_info *pi = ci_get_pi(adev);
889 pi->uvd_power_gated = gate;
892 /* stop the UVD block */
893 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
895 ci_update_uvd_dpm(adev, gate);
897 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
898 AMD_PG_STATE_UNGATE);
899 ci_update_uvd_dpm(adev, gate);
903 static bool ci_dpm_vblank_too_short(void *handle)
905 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
906 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
907 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
909 /* disable mclk switching if the refresh is >120Hz, even if the
910 * blanking period would allow it
912 if (amdgpu_dpm_get_vrefresh(adev) > 120)
915 if (vblank_time < switch_limit)
922 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
923 struct amdgpu_ps *rps)
925 struct ci_ps *ps = ci_get_ps(rps);
926 struct ci_power_info *pi = ci_get_pi(adev);
927 struct amdgpu_clock_and_voltage_limits *max_limits;
928 bool disable_mclk_switching;
932 if (rps->vce_active) {
933 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
934 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
940 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
941 ci_dpm_vblank_too_short(adev))
942 disable_mclk_switching = true;
944 disable_mclk_switching = false;
946 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
947 pi->battery_state = true;
949 pi->battery_state = false;
951 if (adev->pm.ac_power)
952 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
954 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
956 if (adev->pm.ac_power == false) {
957 for (i = 0; i < ps->performance_level_count; i++) {
958 if (ps->performance_levels[i].mclk > max_limits->mclk)
959 ps->performance_levels[i].mclk = max_limits->mclk;
960 if (ps->performance_levels[i].sclk > max_limits->sclk)
961 ps->performance_levels[i].sclk = max_limits->sclk;
965 /* XXX validate the min clocks required for display */
967 if (disable_mclk_switching) {
968 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
969 sclk = ps->performance_levels[0].sclk;
971 mclk = ps->performance_levels[0].mclk;
972 sclk = ps->performance_levels[0].sclk;
975 if (adev->pm.pm_display_cfg.min_core_set_clock > sclk)
976 sclk = adev->pm.pm_display_cfg.min_core_set_clock;
978 if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk)
979 mclk = adev->pm.pm_display_cfg.min_mem_set_clock;
981 if (rps->vce_active) {
982 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
983 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
984 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
985 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
988 ps->performance_levels[0].sclk = sclk;
989 ps->performance_levels[0].mclk = mclk;
991 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
992 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
994 if (disable_mclk_switching) {
995 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
996 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
998 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
999 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
1003 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
1004 int min_temp, int max_temp)
1006 int low_temp = 0 * 1000;
1007 int high_temp = 255 * 1000;
1010 if (low_temp < min_temp)
1011 low_temp = min_temp;
1012 if (high_temp > max_temp)
1013 high_temp = max_temp;
1014 if (high_temp < low_temp) {
1015 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1019 tmp = RREG32_SMC(ixCG_THERMAL_INT);
1020 tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
1021 tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1022 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1023 WREG32_SMC(ixCG_THERMAL_INT, tmp);
1026 /* XXX: need to figure out how to handle this properly */
1027 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1028 tmp &= DIG_THERM_DPM_MASK;
1029 tmp |= DIG_THERM_DPM(high_temp / 1000);
1030 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1033 adev->pm.dpm.thermal.min_temp = low_temp;
1034 adev->pm.dpm.thermal.max_temp = high_temp;
1038 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1041 u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1042 PPSMC_Result result;
1045 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1046 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1047 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1048 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1049 if (result != PPSMC_Result_OK) {
1050 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1054 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1055 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1056 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1057 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1058 if (result != PPSMC_Result_OK) {
1059 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1067 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1069 struct ci_power_info *pi = ci_get_pi(adev);
1072 if (pi->fan_ctrl_is_in_default_mode) {
1073 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1074 >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1075 pi->fan_ctrl_default_mode = tmp;
1076 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1077 >> CG_FDO_CTRL2__TMIN__SHIFT;
1079 pi->fan_ctrl_is_in_default_mode = false;
1082 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1083 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1084 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1086 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1087 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1088 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1091 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1093 struct ci_power_info *pi = ci_get_pi(adev);
1094 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1096 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1097 u16 fdo_min, slope1, slope2;
1098 u32 reference_clock, tmp;
1102 if (!pi->fan_table_start) {
1103 adev->pm.dpm.fan.ucode_fan_control = false;
1107 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1108 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1111 adev->pm.dpm.fan.ucode_fan_control = false;
1115 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1116 do_div(tmp64, 10000);
1117 fdo_min = (u16)tmp64;
1119 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1120 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1122 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1123 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1125 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1126 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1128 fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1129 fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1130 fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1132 fan_table.Slope1 = cpu_to_be16(slope1);
1133 fan_table.Slope2 = cpu_to_be16(slope2);
1135 fan_table.FdoMin = cpu_to_be16(fdo_min);
1137 fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1139 fan_table.HystUp = cpu_to_be16(1);
1141 fan_table.HystSlope = cpu_to_be16(1);
1143 fan_table.TempRespLim = cpu_to_be16(5);
1145 reference_clock = amdgpu_asic_get_xclk(adev);
1147 fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1148 reference_clock) / 1600);
1150 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1152 tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1153 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1154 fan_table.TempSrc = (uint8_t)tmp;
1156 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1157 pi->fan_table_start,
1163 DRM_ERROR("Failed to load fan table to the SMC.");
1164 adev->pm.dpm.fan.ucode_fan_control = false;
1170 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1172 struct ci_power_info *pi = ci_get_pi(adev);
1175 if (pi->caps_od_fuzzy_fan_control_support) {
1176 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1177 PPSMC_StartFanControl,
1179 if (ret != PPSMC_Result_OK)
1181 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1182 PPSMC_MSG_SetFanPwmMax,
1183 adev->pm.dpm.fan.default_max_fan_pwm);
1184 if (ret != PPSMC_Result_OK)
1187 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1188 PPSMC_StartFanControl,
1190 if (ret != PPSMC_Result_OK)
1194 pi->fan_is_controlled_by_smc = true;
1199 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1202 struct ci_power_info *pi = ci_get_pi(adev);
1204 ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1205 if (ret == PPSMC_Result_OK) {
1206 pi->fan_is_controlled_by_smc = false;
1213 static int ci_dpm_get_fan_speed_percent(void *handle,
1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220 if (adev->pm.no_fan)
1223 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1224 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1225 duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1226 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1231 tmp64 = (u64)duty * 100;
1232 do_div(tmp64, duty100);
1233 *speed = (u32)tmp64;
1241 static int ci_dpm_set_fan_speed_percent(void *handle,
1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1248 struct ci_power_info *pi = ci_get_pi(adev);
1250 if (adev->pm.no_fan)
1253 if (pi->fan_is_controlled_by_smc)
1259 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1260 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1265 tmp64 = (u64)speed * duty100;
1269 tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1270 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1271 WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1276 static void ci_dpm_set_fan_control_mode(void *handle, u32 mode)
1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281 case AMD_FAN_CTRL_NONE:
1282 if (adev->pm.dpm.fan.ucode_fan_control)
1283 ci_fan_ctrl_stop_smc_fan_control(adev);
1284 ci_dpm_set_fan_speed_percent(adev, 100);
1286 case AMD_FAN_CTRL_MANUAL:
1287 if (adev->pm.dpm.fan.ucode_fan_control)
1288 ci_fan_ctrl_stop_smc_fan_control(adev);
1290 case AMD_FAN_CTRL_AUTO:
1291 if (adev->pm.dpm.fan.ucode_fan_control)
1292 ci_thermal_start_smc_fan_control(adev);
1299 static u32 ci_dpm_get_fan_control_mode(void *handle)
1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1302 struct ci_power_info *pi = ci_get_pi(adev);
1304 if (pi->fan_is_controlled_by_smc)
1305 return AMD_FAN_CTRL_AUTO;
1307 return AMD_FAN_CTRL_MANUAL;
1311 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1315 u32 xclk = amdgpu_asic_get_xclk(adev);
1317 if (adev->pm.no_fan)
1320 if (adev->pm.fan_pulses_per_revolution == 0)
1323 tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1324 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1325 if (tach_period == 0)
1328 *speed = 60 * xclk * 10000 / tach_period;
1333 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1336 u32 tach_period, tmp;
1337 u32 xclk = amdgpu_asic_get_xclk(adev);
1339 if (adev->pm.no_fan)
1342 if (adev->pm.fan_pulses_per_revolution == 0)
1345 if ((speed < adev->pm.fan_min_rpm) ||
1346 (speed > adev->pm.fan_max_rpm))
1349 if (adev->pm.dpm.fan.ucode_fan_control)
1350 ci_fan_ctrl_stop_smc_fan_control(adev);
1352 tach_period = 60 * xclk * 10000 / (8 * speed);
1353 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1354 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1355 WREG32_SMC(CG_TACH_CTRL, tmp);
1357 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1363 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1365 struct ci_power_info *pi = ci_get_pi(adev);
1368 if (!pi->fan_ctrl_is_in_default_mode) {
1369 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1370 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1371 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1373 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1374 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1375 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1376 pi->fan_ctrl_is_in_default_mode = true;
1380 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1382 if (adev->pm.dpm.fan.ucode_fan_control) {
1383 ci_fan_ctrl_start_smc_fan_control(adev);
1384 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1388 static void ci_thermal_initialize(struct amdgpu_device *adev)
1392 if (adev->pm.fan_pulses_per_revolution) {
1393 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1394 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1395 << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1396 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1399 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1400 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1401 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1404 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1408 ci_thermal_initialize(adev);
1409 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1412 ret = ci_thermal_enable_alert(adev, true);
1415 if (adev->pm.dpm.fan.ucode_fan_control) {
1416 ret = ci_thermal_setup_fan_table(adev);
1419 ci_thermal_start_smc_fan_control(adev);
1425 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1427 if (!adev->pm.no_fan)
1428 ci_fan_ctrl_set_default_mode(adev);
1431 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1432 u16 reg_offset, u32 *value)
1434 struct ci_power_info *pi = ci_get_pi(adev);
1436 return amdgpu_ci_read_smc_sram_dword(adev,
1437 pi->soft_regs_start + reg_offset,
1438 value, pi->sram_end);
1441 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1442 u16 reg_offset, u32 value)
1444 struct ci_power_info *pi = ci_get_pi(adev);
1446 return amdgpu_ci_write_smc_sram_dword(adev,
1447 pi->soft_regs_start + reg_offset,
1448 value, pi->sram_end);
1451 static void ci_init_fps_limits(struct amdgpu_device *adev)
1453 struct ci_power_info *pi = ci_get_pi(adev);
1454 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1460 table->FpsHighT = cpu_to_be16(tmp);
1463 table->FpsLowT = cpu_to_be16(tmp);
1467 static int ci_update_sclk_t(struct amdgpu_device *adev)
1469 struct ci_power_info *pi = ci_get_pi(adev);
1471 u32 low_sclk_interrupt_t = 0;
1473 if (pi->caps_sclk_throttle_low_notification) {
1474 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1476 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1477 pi->dpm_table_start +
1478 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1479 (u8 *)&low_sclk_interrupt_t,
1480 sizeof(u32), pi->sram_end);
1487 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1489 struct ci_power_info *pi = ci_get_pi(adev);
1490 u16 leakage_id, virtual_voltage_id;
1494 pi->vddc_leakage.count = 0;
1495 pi->vddci_leakage.count = 0;
1497 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1498 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1499 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1500 if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1502 if (vddc != 0 && vddc != virtual_voltage_id) {
1503 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1504 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1505 pi->vddc_leakage.count++;
1508 } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1509 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1510 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1511 if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1514 if (vddc != 0 && vddc != virtual_voltage_id) {
1515 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1516 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1517 pi->vddc_leakage.count++;
1519 if (vddci != 0 && vddci != virtual_voltage_id) {
1520 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1521 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1522 pi->vddci_leakage.count++;
1529 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1531 struct ci_power_info *pi = ci_get_pi(adev);
1532 bool want_thermal_protection;
1533 enum amdgpu_dpm_event_src dpm_event_src;
1539 want_thermal_protection = false;
1541 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1542 want_thermal_protection = true;
1543 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1545 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1546 want_thermal_protection = true;
1547 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1549 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1550 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1551 want_thermal_protection = true;
1552 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1556 if (want_thermal_protection) {
1558 /* XXX: need to figure out how to handle this properly */
1559 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1560 tmp &= DPM_EVENT_SRC_MASK;
1561 tmp |= DPM_EVENT_SRC(dpm_event_src);
1562 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1565 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1566 if (pi->thermal_protection)
1567 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1569 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1570 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1572 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1573 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1574 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1578 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1579 enum amdgpu_dpm_auto_throttle_src source,
1582 struct ci_power_info *pi = ci_get_pi(adev);
1585 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1586 pi->active_auto_throttle_sources |= 1 << source;
1587 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1590 if (pi->active_auto_throttle_sources & (1 << source)) {
1591 pi->active_auto_throttle_sources &= ~(1 << source);
1592 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1597 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1599 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1600 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1603 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1605 struct ci_power_info *pi = ci_get_pi(adev);
1606 PPSMC_Result smc_result;
1608 if (!pi->need_update_smu7_dpm_table)
1611 if ((!pi->sclk_dpm_key_disabled) &&
1612 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1613 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1614 if (smc_result != PPSMC_Result_OK)
1618 if ((!pi->mclk_dpm_key_disabled) &&
1619 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1620 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1621 if (smc_result != PPSMC_Result_OK)
1625 pi->need_update_smu7_dpm_table = 0;
1629 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1631 struct ci_power_info *pi = ci_get_pi(adev);
1632 PPSMC_Result smc_result;
1635 if (!pi->sclk_dpm_key_disabled) {
1636 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1637 if (smc_result != PPSMC_Result_OK)
1641 if (!pi->mclk_dpm_key_disabled) {
1642 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1643 if (smc_result != PPSMC_Result_OK)
1646 WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1647 ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1649 WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1650 WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1651 WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1655 WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1656 WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1657 WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1660 if (!pi->sclk_dpm_key_disabled) {
1661 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1662 if (smc_result != PPSMC_Result_OK)
1666 if (!pi->mclk_dpm_key_disabled) {
1667 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1668 if (smc_result != PPSMC_Result_OK)
1676 static int ci_start_dpm(struct amdgpu_device *adev)
1678 struct ci_power_info *pi = ci_get_pi(adev);
1679 PPSMC_Result smc_result;
1683 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1684 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1685 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1687 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1688 tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1689 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1691 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1693 WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1695 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1696 if (smc_result != PPSMC_Result_OK)
1699 ret = ci_enable_sclk_mclk_dpm(adev, true);
1703 if (!pi->pcie_dpm_key_disabled) {
1704 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1705 if (smc_result != PPSMC_Result_OK)
1712 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1714 struct ci_power_info *pi = ci_get_pi(adev);
1715 PPSMC_Result smc_result;
1717 if (!pi->need_update_smu7_dpm_table)
1720 if ((!pi->sclk_dpm_key_disabled) &&
1721 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1722 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1723 if (smc_result != PPSMC_Result_OK)
1727 if ((!pi->mclk_dpm_key_disabled) &&
1728 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1729 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1730 if (smc_result != PPSMC_Result_OK)
1737 static int ci_stop_dpm(struct amdgpu_device *adev)
1739 struct ci_power_info *pi = ci_get_pi(adev);
1740 PPSMC_Result smc_result;
1744 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1745 tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1746 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1748 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1749 tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1750 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1752 if (!pi->pcie_dpm_key_disabled) {
1753 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1754 if (smc_result != PPSMC_Result_OK)
1758 ret = ci_enable_sclk_mclk_dpm(adev, false);
1762 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1763 if (smc_result != PPSMC_Result_OK)
1769 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1771 u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1774 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1776 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1777 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1781 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1784 struct ci_power_info *pi = ci_get_pi(adev);
1785 struct amdgpu_cac_tdp_table *cac_tdp_table =
1786 adev->pm.dpm.dyn_state.cac_tdp_table;
1790 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1792 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1794 ci_set_power_limit(adev, power_limit);
1796 if (pi->caps_automatic_dc_transition) {
1798 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1800 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1807 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1808 PPSMC_Msg msg, u32 parameter)
1810 WREG32(mmSMC_MSG_ARG_0, parameter);
1811 return amdgpu_ci_send_msg_to_smc(adev, msg);
1814 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1815 PPSMC_Msg msg, u32 *parameter)
1817 PPSMC_Result smc_result;
1819 smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1821 if ((smc_result == PPSMC_Result_OK) && parameter)
1822 *parameter = RREG32(mmSMC_MSG_ARG_0);
1827 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1829 struct ci_power_info *pi = ci_get_pi(adev);
1831 if (!pi->sclk_dpm_key_disabled) {
1832 PPSMC_Result smc_result =
1833 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1834 if (smc_result != PPSMC_Result_OK)
1841 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1843 struct ci_power_info *pi = ci_get_pi(adev);
1845 if (!pi->mclk_dpm_key_disabled) {
1846 PPSMC_Result smc_result =
1847 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1848 if (smc_result != PPSMC_Result_OK)
1855 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1857 struct ci_power_info *pi = ci_get_pi(adev);
1859 if (!pi->pcie_dpm_key_disabled) {
1860 PPSMC_Result smc_result =
1861 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1862 if (smc_result != PPSMC_Result_OK)
1869 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1871 struct ci_power_info *pi = ci_get_pi(adev);
1873 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1874 PPSMC_Result smc_result =
1875 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1876 if (smc_result != PPSMC_Result_OK)
1883 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1886 PPSMC_Result smc_result =
1887 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1888 if (smc_result != PPSMC_Result_OK)
1894 static int ci_set_boot_state(struct amdgpu_device *adev)
1896 return ci_enable_sclk_mclk_dpm(adev, false);
1900 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1903 PPSMC_Result smc_result =
1904 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1905 PPSMC_MSG_API_GetSclkFrequency,
1907 if (smc_result != PPSMC_Result_OK)
1913 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1916 PPSMC_Result smc_result =
1917 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1918 PPSMC_MSG_API_GetMclkFrequency,
1920 if (smc_result != PPSMC_Result_OK)
1926 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1930 amdgpu_ci_program_jump_on_start(adev);
1931 amdgpu_ci_start_smc_clock(adev);
1932 amdgpu_ci_start_smc(adev);
1933 for (i = 0; i < adev->usec_timeout; i++) {
1934 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1939 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1941 amdgpu_ci_reset_smc(adev);
1942 amdgpu_ci_stop_smc_clock(adev);
1945 static int ci_process_firmware_header(struct amdgpu_device *adev)
1947 struct ci_power_info *pi = ci_get_pi(adev);
1951 ret = amdgpu_ci_read_smc_sram_dword(adev,
1952 SMU7_FIRMWARE_HEADER_LOCATION +
1953 offsetof(SMU7_Firmware_Header, DpmTable),
1954 &tmp, pi->sram_end);
1958 pi->dpm_table_start = tmp;
1960 ret = amdgpu_ci_read_smc_sram_dword(adev,
1961 SMU7_FIRMWARE_HEADER_LOCATION +
1962 offsetof(SMU7_Firmware_Header, SoftRegisters),
1963 &tmp, pi->sram_end);
1967 pi->soft_regs_start = tmp;
1969 ret = amdgpu_ci_read_smc_sram_dword(adev,
1970 SMU7_FIRMWARE_HEADER_LOCATION +
1971 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1972 &tmp, pi->sram_end);
1976 pi->mc_reg_table_start = tmp;
1978 ret = amdgpu_ci_read_smc_sram_dword(adev,
1979 SMU7_FIRMWARE_HEADER_LOCATION +
1980 offsetof(SMU7_Firmware_Header, FanTable),
1981 &tmp, pi->sram_end);
1985 pi->fan_table_start = tmp;
1987 ret = amdgpu_ci_read_smc_sram_dword(adev,
1988 SMU7_FIRMWARE_HEADER_LOCATION +
1989 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1990 &tmp, pi->sram_end);
1994 pi->arb_table_start = tmp;
1999 static void ci_read_clock_registers(struct amdgpu_device *adev)
2001 struct ci_power_info *pi = ci_get_pi(adev);
2003 pi->clock_registers.cg_spll_func_cntl =
2004 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
2005 pi->clock_registers.cg_spll_func_cntl_2 =
2006 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
2007 pi->clock_registers.cg_spll_func_cntl_3 =
2008 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
2009 pi->clock_registers.cg_spll_func_cntl_4 =
2010 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
2011 pi->clock_registers.cg_spll_spread_spectrum =
2012 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2013 pi->clock_registers.cg_spll_spread_spectrum_2 =
2014 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
2015 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
2016 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
2017 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
2018 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
2019 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
2020 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
2021 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
2022 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
2023 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
2026 static void ci_init_sclk_t(struct amdgpu_device *adev)
2028 struct ci_power_info *pi = ci_get_pi(adev);
2030 pi->low_sclk_interrupt_t = 0;
2033 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2036 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2039 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2041 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2042 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2045 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2047 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2049 tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2051 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2055 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2058 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2065 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2069 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2073 for (i = 0; i < adev->usec_timeout; i++) {
2074 if (RREG32(mmSMC_RESP_0) == 1)
2083 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2086 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2088 return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
2091 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2094 struct ci_power_info *pi = ci_get_pi(adev);
2097 if (pi->caps_sclk_ds) {
2098 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2101 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2105 if (pi->caps_sclk_ds) {
2106 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2114 static void ci_program_display_gap(struct amdgpu_device *adev)
2116 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2117 u32 pre_vbi_time_in_us;
2118 u32 frame_time_in_us;
2119 u32 ref_clock = adev->clock.spll.reference_freq;
2120 u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2121 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2123 tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2124 if (adev->pm.dpm.new_active_crtc_count > 0)
2125 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2127 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2128 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2130 if (refresh_rate == 0)
2132 if (vblank_time == 0xffffffff)
2134 frame_time_in_us = 1000000 / refresh_rate;
2135 pre_vbi_time_in_us =
2136 frame_time_in_us - 200 - vblank_time;
2137 tmp = pre_vbi_time_in_us * (ref_clock / 100);
2139 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2140 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2141 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2144 ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2148 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2150 struct ci_power_info *pi = ci_get_pi(adev);
2154 if (pi->caps_sclk_ss_support) {
2155 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2156 tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2157 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2160 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2161 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2162 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2164 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2165 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2166 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2170 static void ci_program_sstp(struct amdgpu_device *adev)
2172 WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2173 ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2174 (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2177 static void ci_enable_display_gap(struct amdgpu_device *adev)
2179 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2181 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2182 CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2183 tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2184 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2186 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2189 static void ci_program_vc(struct amdgpu_device *adev)
2193 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2194 tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2195 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2197 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2198 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2199 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2200 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2201 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2202 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2203 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2204 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2207 static void ci_clear_vc(struct amdgpu_device *adev)
2211 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2212 tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2213 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2215 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2216 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2217 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2218 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2219 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2220 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2221 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2222 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2225 static int ci_upload_firmware(struct amdgpu_device *adev)
2229 if (amdgpu_ci_is_smc_running(adev)) {
2230 DRM_INFO("smc is running, no need to load smc firmware\n");
2234 for (i = 0; i < adev->usec_timeout; i++) {
2235 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2238 WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2240 amdgpu_ci_stop_smc_clock(adev);
2241 amdgpu_ci_reset_smc(adev);
2243 ret = amdgpu_ci_load_smc_ucode(adev, SMC_RAM_END);
2249 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2250 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2251 struct atom_voltage_table *voltage_table)
2255 if (voltage_dependency_table == NULL)
2258 voltage_table->mask_low = 0;
2259 voltage_table->phase_delay = 0;
2261 voltage_table->count = voltage_dependency_table->count;
2262 for (i = 0; i < voltage_table->count; i++) {
2263 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2264 voltage_table->entries[i].smio_low = 0;
2270 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2272 struct ci_power_info *pi = ci_get_pi(adev);
2275 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2276 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2277 VOLTAGE_OBJ_GPIO_LUT,
2278 &pi->vddc_voltage_table);
2281 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2282 ret = ci_get_svi2_voltage_table(adev,
2283 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2284 &pi->vddc_voltage_table);
2289 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2290 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2291 &pi->vddc_voltage_table);
2293 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2294 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2295 VOLTAGE_OBJ_GPIO_LUT,
2296 &pi->vddci_voltage_table);
2299 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2300 ret = ci_get_svi2_voltage_table(adev,
2301 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2302 &pi->vddci_voltage_table);
2307 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2308 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2309 &pi->vddci_voltage_table);
2311 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2312 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2313 VOLTAGE_OBJ_GPIO_LUT,
2314 &pi->mvdd_voltage_table);
2317 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2318 ret = ci_get_svi2_voltage_table(adev,
2319 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2320 &pi->mvdd_voltage_table);
2325 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2326 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2327 &pi->mvdd_voltage_table);
2332 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2333 struct atom_voltage_table_entry *voltage_table,
2334 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2338 ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2339 &smc_voltage_table->StdVoltageHiSidd,
2340 &smc_voltage_table->StdVoltageLoSidd);
2343 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2344 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2347 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2348 smc_voltage_table->StdVoltageHiSidd =
2349 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2350 smc_voltage_table->StdVoltageLoSidd =
2351 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2354 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2355 SMU7_Discrete_DpmTable *table)
2357 struct ci_power_info *pi = ci_get_pi(adev);
2360 table->VddcLevelCount = pi->vddc_voltage_table.count;
2361 for (count = 0; count < table->VddcLevelCount; count++) {
2362 ci_populate_smc_voltage_table(adev,
2363 &pi->vddc_voltage_table.entries[count],
2364 &table->VddcLevel[count]);
2366 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2367 table->VddcLevel[count].Smio |=
2368 pi->vddc_voltage_table.entries[count].smio_low;
2370 table->VddcLevel[count].Smio = 0;
2372 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2377 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2378 SMU7_Discrete_DpmTable *table)
2381 struct ci_power_info *pi = ci_get_pi(adev);
2383 table->VddciLevelCount = pi->vddci_voltage_table.count;
2384 for (count = 0; count < table->VddciLevelCount; count++) {
2385 ci_populate_smc_voltage_table(adev,
2386 &pi->vddci_voltage_table.entries[count],
2387 &table->VddciLevel[count]);
2389 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2390 table->VddciLevel[count].Smio |=
2391 pi->vddci_voltage_table.entries[count].smio_low;
2393 table->VddciLevel[count].Smio = 0;
2395 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2400 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2401 SMU7_Discrete_DpmTable *table)
2403 struct ci_power_info *pi = ci_get_pi(adev);
2406 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2407 for (count = 0; count < table->MvddLevelCount; count++) {
2408 ci_populate_smc_voltage_table(adev,
2409 &pi->mvdd_voltage_table.entries[count],
2410 &table->MvddLevel[count]);
2412 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2413 table->MvddLevel[count].Smio |=
2414 pi->mvdd_voltage_table.entries[count].smio_low;
2416 table->MvddLevel[count].Smio = 0;
2418 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2423 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2424 SMU7_Discrete_DpmTable *table)
2428 ret = ci_populate_smc_vddc_table(adev, table);
2432 ret = ci_populate_smc_vddci_table(adev, table);
2436 ret = ci_populate_smc_mvdd_table(adev, table);
2443 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2444 SMU7_Discrete_VoltageLevel *voltage)
2446 struct ci_power_info *pi = ci_get_pi(adev);
2449 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2450 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2451 if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2452 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2457 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2464 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2465 struct atom_voltage_table_entry *voltage_table,
2466 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2469 bool voltage_found = false;
2470 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2471 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2473 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2476 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2477 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2478 if (voltage_table->value ==
2479 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2480 voltage_found = true;
2481 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2484 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2485 *std_voltage_lo_sidd =
2486 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2487 *std_voltage_hi_sidd =
2488 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2493 if (!voltage_found) {
2494 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2495 if (voltage_table->value <=
2496 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2497 voltage_found = true;
2498 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2501 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2502 *std_voltage_lo_sidd =
2503 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2504 *std_voltage_hi_sidd =
2505 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2515 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2516 const struct amdgpu_phase_shedding_limits_table *limits,
2518 u32 *phase_shedding)
2522 *phase_shedding = 1;
2524 for (i = 0; i < limits->count; i++) {
2525 if (sclk < limits->entries[i].sclk) {
2526 *phase_shedding = i;
2532 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2533 const struct amdgpu_phase_shedding_limits_table *limits,
2535 u32 *phase_shedding)
2539 *phase_shedding = 1;
2541 for (i = 0; i < limits->count; i++) {
2542 if (mclk < limits->entries[i].mclk) {
2543 *phase_shedding = i;
2549 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2551 struct ci_power_info *pi = ci_get_pi(adev);
2555 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2556 &tmp, pi->sram_end);
2561 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2563 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2567 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2568 struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2569 u32 clock, u32 *voltage)
2573 if (allowed_clock_voltage_table->count == 0)
2576 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2577 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2578 *voltage = allowed_clock_voltage_table->entries[i].v;
2583 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2588 static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2592 u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2597 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2599 if (tmp >= min || i == 0)
2606 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2608 return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2611 static int ci_reset_to_default(struct amdgpu_device *adev)
2613 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2617 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2621 tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2623 if (tmp == MC_CG_ARB_FREQ_F0)
2626 return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2629 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2630 const u32 engine_clock,
2631 const u32 memory_clock,
2637 tmp = RREG32(mmMC_SEQ_MISC0);
2638 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2641 ((adev->pdev->device == 0x67B0) ||
2642 (adev->pdev->device == 0x67B1))) {
2643 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2644 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2645 *dram_timimg2 &= ~0x00ff0000;
2646 *dram_timimg2 |= tmp2 << 16;
2647 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2648 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2649 *dram_timimg2 &= ~0x00ff0000;
2650 *dram_timimg2 |= tmp2 << 16;
2655 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2658 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2664 amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2666 dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
2667 dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2668 burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2670 ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2672 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2673 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2674 arb_regs->McArbBurstTime = (u8)burst_time;
2679 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2681 struct ci_power_info *pi = ci_get_pi(adev);
2682 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2686 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2688 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2689 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2690 ret = ci_populate_memory_timing_parameters(adev,
2691 pi->dpm_table.sclk_table.dpm_levels[i].value,
2692 pi->dpm_table.mclk_table.dpm_levels[j].value,
2693 &arb_regs.entries[i][j]);
2700 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2701 pi->arb_table_start,
2703 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2709 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2711 struct ci_power_info *pi = ci_get_pi(adev);
2713 if (pi->need_update_smu7_dpm_table == 0)
2716 return ci_do_program_memory_timing_parameters(adev);
2719 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2720 struct amdgpu_ps *amdgpu_boot_state)
2722 struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2723 struct ci_power_info *pi = ci_get_pi(adev);
2726 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2727 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2728 boot_state->performance_levels[0].sclk) {
2729 pi->smc_state_table.GraphicsBootLevel = level;
2734 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2735 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2736 boot_state->performance_levels[0].mclk) {
2737 pi->smc_state_table.MemoryBootLevel = level;
2743 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2748 for (i = dpm_table->count; i > 0; i--) {
2749 mask_value = mask_value << 1;
2750 if (dpm_table->dpm_levels[i-1].enabled)
2753 mask_value &= 0xFFFFFFFE;
2759 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2760 SMU7_Discrete_DpmTable *table)
2762 struct ci_power_info *pi = ci_get_pi(adev);
2763 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2766 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2767 table->LinkLevel[i].PcieGenSpeed =
2768 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2769 table->LinkLevel[i].PcieLaneCount =
2770 amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2771 table->LinkLevel[i].EnabledForActivity = 1;
2772 table->LinkLevel[i].DownT = cpu_to_be32(5);
2773 table->LinkLevel[i].UpT = cpu_to_be32(30);
2776 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2777 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2778 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2781 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2782 SMU7_Discrete_DpmTable *table)
2785 struct atom_clock_dividers dividers;
2788 table->UvdLevelCount =
2789 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2791 for (count = 0; count < table->UvdLevelCount; count++) {
2792 table->UvdLevel[count].VclkFrequency =
2793 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2794 table->UvdLevel[count].DclkFrequency =
2795 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2796 table->UvdLevel[count].MinVddc =
2797 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2798 table->UvdLevel[count].MinVddcPhases = 1;
2800 ret = amdgpu_atombios_get_clock_dividers(adev,
2801 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2802 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2806 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2808 ret = amdgpu_atombios_get_clock_dividers(adev,
2809 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2810 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2814 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2816 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2817 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2818 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2824 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2825 SMU7_Discrete_DpmTable *table)
2828 struct atom_clock_dividers dividers;
2831 table->VceLevelCount =
2832 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2834 for (count = 0; count < table->VceLevelCount; count++) {
2835 table->VceLevel[count].Frequency =
2836 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2837 table->VceLevel[count].MinVoltage =
2838 (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2839 table->VceLevel[count].MinPhases = 1;
2841 ret = amdgpu_atombios_get_clock_dividers(adev,
2842 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2843 table->VceLevel[count].Frequency, false, ÷rs);
2847 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2849 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2850 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2857 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2858 SMU7_Discrete_DpmTable *table)
2861 struct atom_clock_dividers dividers;
2864 table->AcpLevelCount = (u8)
2865 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2867 for (count = 0; count < table->AcpLevelCount; count++) {
2868 table->AcpLevel[count].Frequency =
2869 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2870 table->AcpLevel[count].MinVoltage =
2871 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2872 table->AcpLevel[count].MinPhases = 1;
2874 ret = amdgpu_atombios_get_clock_dividers(adev,
2875 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2876 table->AcpLevel[count].Frequency, false, ÷rs);
2880 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2882 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2883 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2889 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2890 SMU7_Discrete_DpmTable *table)
2893 struct atom_clock_dividers dividers;
2896 table->SamuLevelCount =
2897 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2899 for (count = 0; count < table->SamuLevelCount; count++) {
2900 table->SamuLevel[count].Frequency =
2901 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2902 table->SamuLevel[count].MinVoltage =
2903 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2904 table->SamuLevel[count].MinPhases = 1;
2906 ret = amdgpu_atombios_get_clock_dividers(adev,
2907 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2908 table->SamuLevel[count].Frequency, false, ÷rs);
2912 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2914 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2915 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2921 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2923 SMU7_Discrete_MemoryLevel *mclk,
2927 struct ci_power_info *pi = ci_get_pi(adev);
2928 u32 dll_cntl = pi->clock_registers.dll_cntl;
2929 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2930 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2931 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2932 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2933 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2934 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2935 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2936 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2937 struct atom_mpll_param mpll_param;
2940 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2944 mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2945 mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2947 mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2948 MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2949 mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2950 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2951 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2953 mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2954 mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2956 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2957 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2958 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2959 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2960 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2963 if (pi->caps_mclk_ss_support) {
2964 struct amdgpu_atom_ss ss;
2967 u32 reference_clock = adev->clock.mpll.reference_freq;
2969 if (mpll_param.qdr == 1)
2970 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2972 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2974 tmp = (freq_nom / reference_clock);
2976 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2977 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2978 u32 clks = reference_clock * 5 / ss.rate;
2979 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2981 mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2982 mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2984 mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2985 mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2989 mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2990 mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2993 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2994 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2996 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2997 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2999 mclk->MclkFrequency = memory_clock;
3000 mclk->MpllFuncCntl = mpll_func_cntl;
3001 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
3002 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
3003 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
3004 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
3005 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
3006 mclk->DllCntl = dll_cntl;
3007 mclk->MpllSs1 = mpll_ss1;
3008 mclk->MpllSs2 = mpll_ss2;
3013 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
3015 SMU7_Discrete_MemoryLevel *memory_level)
3017 struct ci_power_info *pi = ci_get_pi(adev);
3021 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
3022 ret = ci_get_dependency_volt_by_clk(adev,
3023 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3024 memory_clock, &memory_level->MinVddc);
3029 if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
3030 ret = ci_get_dependency_volt_by_clk(adev,
3031 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3032 memory_clock, &memory_level->MinVddci);
3037 if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3038 ret = ci_get_dependency_volt_by_clk(adev,
3039 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3040 memory_clock, &memory_level->MinMvdd);
3045 memory_level->MinVddcPhases = 1;
3047 if (pi->vddc_phase_shed_control)
3048 ci_populate_phase_value_based_on_mclk(adev,
3049 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3051 &memory_level->MinVddcPhases);
3053 memory_level->EnabledForActivity = 1;
3054 memory_level->EnabledForThrottle = 1;
3055 memory_level->UpH = 0;
3056 memory_level->DownH = 100;
3057 memory_level->VoltageDownH = 0;
3058 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3060 memory_level->StutterEnable = false;
3061 memory_level->StrobeEnable = false;
3062 memory_level->EdcReadEnable = false;
3063 memory_level->EdcWriteEnable = false;
3064 memory_level->RttEnable = false;
3066 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3068 if (pi->mclk_stutter_mode_threshold &&
3069 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3070 (!pi->uvd_enabled) &&
3071 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3072 (adev->pm.dpm.new_active_crtc_count <= 2))
3073 memory_level->StutterEnable = true;
3075 if (pi->mclk_strobe_mode_threshold &&
3076 (memory_clock <= pi->mclk_strobe_mode_threshold))
3077 memory_level->StrobeEnable = 1;
3079 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3080 memory_level->StrobeRatio =
3081 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3082 if (pi->mclk_edc_enable_threshold &&
3083 (memory_clock > pi->mclk_edc_enable_threshold))
3084 memory_level->EdcReadEnable = true;
3086 if (pi->mclk_edc_wr_enable_threshold &&
3087 (memory_clock > pi->mclk_edc_wr_enable_threshold))
3088 memory_level->EdcWriteEnable = true;
3090 if (memory_level->StrobeEnable) {
3091 if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3092 ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3093 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3095 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3097 dll_state_on = pi->dll_default_on;
3100 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3101 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3104 ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3108 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3109 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3110 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3111 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3113 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3114 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3115 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3116 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3117 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3118 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3119 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3120 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3121 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3122 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3123 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3128 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3129 SMU7_Discrete_DpmTable *table)
3131 struct ci_power_info *pi = ci_get_pi(adev);
3132 struct atom_clock_dividers dividers;
3133 SMU7_Discrete_VoltageLevel voltage_level;
3134 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3135 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3136 u32 dll_cntl = pi->clock_registers.dll_cntl;
3137 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3140 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3143 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3145 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3147 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3149 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3151 ret = amdgpu_atombios_get_clock_dividers(adev,
3152 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3153 table->ACPILevel.SclkFrequency, false, ÷rs);
3157 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3158 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3159 table->ACPILevel.DeepSleepDivId = 0;
3161 spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3162 spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3164 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3165 spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3167 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3168 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3169 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3170 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3171 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3172 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3173 table->ACPILevel.CcPwrDynRm = 0;
3174 table->ACPILevel.CcPwrDynRm1 = 0;
3176 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3177 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3178 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3179 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3180 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3181 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3182 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3183 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3184 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3185 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3186 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3188 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3189 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3191 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3193 table->MemoryACPILevel.MinVddci =
3194 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3196 table->MemoryACPILevel.MinVddci =
3197 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3200 if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3201 table->MemoryACPILevel.MinMvdd = 0;
3203 table->MemoryACPILevel.MinMvdd =
3204 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3206 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3207 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3208 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3209 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3211 dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3213 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3214 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3215 table->MemoryACPILevel.MpllAdFuncCntl =
3216 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3217 table->MemoryACPILevel.MpllDqFuncCntl =
3218 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3219 table->MemoryACPILevel.MpllFuncCntl =
3220 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3221 table->MemoryACPILevel.MpllFuncCntl_1 =
3222 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3223 table->MemoryACPILevel.MpllFuncCntl_2 =
3224 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3225 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3226 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3228 table->MemoryACPILevel.EnabledForThrottle = 0;
3229 table->MemoryACPILevel.EnabledForActivity = 0;
3230 table->MemoryACPILevel.UpH = 0;
3231 table->MemoryACPILevel.DownH = 100;
3232 table->MemoryACPILevel.VoltageDownH = 0;
3233 table->MemoryACPILevel.ActivityLevel =
3234 cpu_to_be16((u16)pi->mclk_activity_target);
3236 table->MemoryACPILevel.StutterEnable = false;
3237 table->MemoryACPILevel.StrobeEnable = false;
3238 table->MemoryACPILevel.EdcReadEnable = false;
3239 table->MemoryACPILevel.EdcWriteEnable = false;
3240 table->MemoryACPILevel.RttEnable = false;
3246 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3248 struct ci_power_info *pi = ci_get_pi(adev);
3249 struct ci_ulv_parm *ulv = &pi->ulv;
3251 if (ulv->supported) {
3253 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3256 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3263 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3264 SMU7_Discrete_Ulv *state)
3266 struct ci_power_info *pi = ci_get_pi(adev);
3267 u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3269 state->CcPwrDynRm = 0;
3270 state->CcPwrDynRm1 = 0;
3272 if (ulv_voltage == 0) {
3273 pi->ulv.supported = false;
3277 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3278 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3279 state->VddcOffset = 0;
3282 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3284 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3285 state->VddcOffsetVid = 0;
3287 state->VddcOffsetVid = (u8)
3288 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3289 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3291 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3293 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3294 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3295 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3300 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3302 SMU7_Discrete_GraphicsLevel *sclk)
3304 struct ci_power_info *pi = ci_get_pi(adev);
3305 struct atom_clock_dividers dividers;
3306 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3307 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3308 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3309 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3310 u32 reference_clock = adev->clock.spll.reference_freq;
3311 u32 reference_divider;
3315 ret = amdgpu_atombios_get_clock_dividers(adev,
3316 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3317 engine_clock, false, ÷rs);
3321 reference_divider = 1 + dividers.ref_div;
3322 fbdiv = dividers.fb_div & 0x3FFFFFF;
3324 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3325 spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3326 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3328 if (pi->caps_sclk_ss_support) {
3329 struct amdgpu_atom_ss ss;
3330 u32 vco_freq = engine_clock * dividers.post_div;
3332 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3333 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3334 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3335 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3337 cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3338 cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3339 cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3341 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3342 cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3346 sclk->SclkFrequency = engine_clock;
3347 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3348 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3349 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3350 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3351 sclk->SclkDid = (u8)dividers.post_divider;
3356 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3358 u16 sclk_activity_level_t,
3359 SMU7_Discrete_GraphicsLevel *graphic_level)
3361 struct ci_power_info *pi = ci_get_pi(adev);
3364 ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3368 ret = ci_get_dependency_volt_by_clk(adev,
3369 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3370 engine_clock, &graphic_level->MinVddc);
3374 graphic_level->SclkFrequency = engine_clock;
3376 graphic_level->Flags = 0;
3377 graphic_level->MinVddcPhases = 1;
3379 if (pi->vddc_phase_shed_control)
3380 ci_populate_phase_value_based_on_sclk(adev,
3381 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3383 &graphic_level->MinVddcPhases);
3385 graphic_level->ActivityLevel = sclk_activity_level_t;
3387 graphic_level->CcPwrDynRm = 0;
3388 graphic_level->CcPwrDynRm1 = 0;
3389 graphic_level->EnabledForThrottle = 1;
3390 graphic_level->UpH = 0;
3391 graphic_level->DownH = 0;
3392 graphic_level->VoltageDownH = 0;
3393 graphic_level->PowerThrottle = 0;
3395 if (pi->caps_sclk_ds)
3396 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
3397 CISLAND_MINIMUM_ENGINE_CLOCK);
3399 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3401 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3402 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3403 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3404 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3405 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3406 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3407 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3408 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3409 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3410 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3411 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3416 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3418 struct ci_power_info *pi = ci_get_pi(adev);
3419 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3420 u32 level_array_address = pi->dpm_table_start +
3421 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3422 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3423 SMU7_MAX_LEVELS_GRAPHICS;
3424 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3427 memset(levels, 0, level_array_size);
3429 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3430 ret = ci_populate_single_graphic_level(adev,
3431 dpm_table->sclk_table.dpm_levels[i].value,
3432 (u16)pi->activity_target[i],
3433 &pi->smc_state_table.GraphicsLevel[i]);
3437 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3438 if (i == (dpm_table->sclk_table.count - 1))
3439 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3440 PPSMC_DISPLAY_WATERMARK_HIGH;
3442 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3444 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3445 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3446 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3448 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3449 (u8 *)levels, level_array_size,
3457 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3458 SMU7_Discrete_Ulv *ulv_level)
3460 return ci_populate_ulv_level(adev, ulv_level);
3463 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3465 struct ci_power_info *pi = ci_get_pi(adev);
3466 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3467 u32 level_array_address = pi->dpm_table_start +
3468 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3469 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3470 SMU7_MAX_LEVELS_MEMORY;
3471 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3474 memset(levels, 0, level_array_size);
3476 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3477 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3479 ret = ci_populate_single_memory_level(adev,
3480 dpm_table->mclk_table.dpm_levels[i].value,
3481 &pi->smc_state_table.MemoryLevel[i]);
3486 if ((dpm_table->mclk_table.count >= 2) &&
3487 ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3488 pi->smc_state_table.MemoryLevel[1].MinVddc =
3489 pi->smc_state_table.MemoryLevel[0].MinVddc;
3490 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3491 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3494 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3496 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3497 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3498 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3500 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3501 PPSMC_DISPLAY_WATERMARK_HIGH;
3503 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3504 (u8 *)levels, level_array_size,
3512 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3513 struct ci_single_dpm_table* dpm_table,
3518 dpm_table->count = count;
3519 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3520 dpm_table->dpm_levels[i].enabled = false;
3523 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3524 u32 index, u32 pcie_gen, u32 pcie_lanes)
3526 dpm_table->dpm_levels[index].value = pcie_gen;
3527 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3528 dpm_table->dpm_levels[index].enabled = true;
3531 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3533 struct ci_power_info *pi = ci_get_pi(adev);
3535 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3538 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3539 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3540 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3541 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3542 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3543 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3546 ci_reset_single_dpm_table(adev,
3547 &pi->dpm_table.pcie_speed_table,
3548 SMU7_MAX_LEVELS_LINK);
3550 if (adev->asic_type == CHIP_BONAIRE)
3551 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3552 pi->pcie_gen_powersaving.min,
3553 pi->pcie_lane_powersaving.max);
3555 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3556 pi->pcie_gen_powersaving.min,
3557 pi->pcie_lane_powersaving.min);
3558 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3559 pi->pcie_gen_performance.min,
3560 pi->pcie_lane_performance.min);
3561 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3562 pi->pcie_gen_powersaving.min,
3563 pi->pcie_lane_powersaving.max);
3564 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3565 pi->pcie_gen_performance.min,
3566 pi->pcie_lane_performance.max);
3567 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3568 pi->pcie_gen_powersaving.max,
3569 pi->pcie_lane_powersaving.max);
3570 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3571 pi->pcie_gen_performance.max,
3572 pi->pcie_lane_performance.max);
3574 pi->dpm_table.pcie_speed_table.count = 6;
3579 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3581 struct ci_power_info *pi = ci_get_pi(adev);
3582 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3583 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3584 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3585 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3586 struct amdgpu_cac_leakage_table *std_voltage_table =
3587 &adev->pm.dpm.dyn_state.cac_leakage_table;
3590 if (allowed_sclk_vddc_table == NULL)
3592 if (allowed_sclk_vddc_table->count < 1)
3594 if (allowed_mclk_table == NULL)
3596 if (allowed_mclk_table->count < 1)
3599 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3601 ci_reset_single_dpm_table(adev,
3602 &pi->dpm_table.sclk_table,
3603 SMU7_MAX_LEVELS_GRAPHICS);
3604 ci_reset_single_dpm_table(adev,
3605 &pi->dpm_table.mclk_table,
3606 SMU7_MAX_LEVELS_MEMORY);
3607 ci_reset_single_dpm_table(adev,
3608 &pi->dpm_table.vddc_table,
3609 SMU7_MAX_LEVELS_VDDC);
3610 ci_reset_single_dpm_table(adev,
3611 &pi->dpm_table.vddci_table,
3612 SMU7_MAX_LEVELS_VDDCI);
3613 ci_reset_single_dpm_table(adev,
3614 &pi->dpm_table.mvdd_table,
3615 SMU7_MAX_LEVELS_MVDD);
3617 pi->dpm_table.sclk_table.count = 0;
3618 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3620 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3621 allowed_sclk_vddc_table->entries[i].clk)) {
3622 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3623 allowed_sclk_vddc_table->entries[i].clk;
3624 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3625 (i == 0) ? true : false;
3626 pi->dpm_table.sclk_table.count++;
3630 pi->dpm_table.mclk_table.count = 0;
3631 for (i = 0; i < allowed_mclk_table->count; i++) {
3633 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3634 allowed_mclk_table->entries[i].clk)) {
3635 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3636 allowed_mclk_table->entries[i].clk;
3637 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3638 (i == 0) ? true : false;
3639 pi->dpm_table.mclk_table.count++;
3643 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3644 pi->dpm_table.vddc_table.dpm_levels[i].value =
3645 allowed_sclk_vddc_table->entries[i].v;
3646 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3647 std_voltage_table->entries[i].leakage;
3648 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3650 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3652 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3653 if (allowed_mclk_table) {
3654 for (i = 0; i < allowed_mclk_table->count; i++) {
3655 pi->dpm_table.vddci_table.dpm_levels[i].value =
3656 allowed_mclk_table->entries[i].v;
3657 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3659 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3662 allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3663 if (allowed_mclk_table) {
3664 for (i = 0; i < allowed_mclk_table->count; i++) {
3665 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3666 allowed_mclk_table->entries[i].v;
3667 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3669 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3672 ci_setup_default_pcie_tables(adev);
3674 /* save a copy of the default DPM table */
3675 memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),
3676 sizeof(struct ci_dpm_table));
3681 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3682 u32 value, u32 *boot_level)
3687 for(i = 0; i < table->count; i++) {
3688 if (value == table->dpm_levels[i].value) {
3697 static int ci_init_smc_table(struct amdgpu_device *adev)
3699 struct ci_power_info *pi = ci_get_pi(adev);
3700 struct ci_ulv_parm *ulv = &pi->ulv;
3701 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3702 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3705 ret = ci_setup_default_dpm_tables(adev);
3709 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3710 ci_populate_smc_voltage_tables(adev, table);
3712 ci_init_fps_limits(adev);
3714 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3715 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3717 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3718 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3720 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3721 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3723 if (ulv->supported) {
3724 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3727 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3730 ret = ci_populate_all_graphic_levels(adev);
3734 ret = ci_populate_all_memory_levels(adev);
3738 ci_populate_smc_link_level(adev, table);
3740 ret = ci_populate_smc_acpi_level(adev, table);
3744 ret = ci_populate_smc_vce_level(adev, table);
3748 ret = ci_populate_smc_acp_level(adev, table);
3752 ret = ci_populate_smc_samu_level(adev, table);
3756 ret = ci_do_program_memory_timing_parameters(adev);
3760 ret = ci_populate_smc_uvd_level(adev, table);
3764 table->UvdBootLevel = 0;
3765 table->VceBootLevel = 0;
3766 table->AcpBootLevel = 0;
3767 table->SamuBootLevel = 0;
3768 table->GraphicsBootLevel = 0;
3769 table->MemoryBootLevel = 0;
3771 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3772 pi->vbios_boot_state.sclk_bootup_value,
3773 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3775 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3776 pi->vbios_boot_state.mclk_bootup_value,
3777 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3779 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3780 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3781 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3783 ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3785 ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3789 table->UVDInterval = 1;
3790 table->VCEInterval = 1;
3791 table->ACPInterval = 1;
3792 table->SAMUInterval = 1;
3793 table->GraphicsVoltageChangeEnable = 1;
3794 table->GraphicsThermThrottleEnable = 1;
3795 table->GraphicsInterval = 1;
3796 table->VoltageInterval = 1;
3797 table->ThermalInterval = 1;
3798 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3799 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3800 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3801 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3802 table->MemoryVoltageChangeEnable = 1;
3803 table->MemoryInterval = 1;
3804 table->VoltageResponseTime = 0;
3805 table->VddcVddciDelta = 4000;
3806 table->PhaseResponseTime = 0;
3807 table->MemoryThermThrottleEnable = 1;
3808 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3809 table->PCIeGenInterval = 1;
3810 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3811 table->SVI2Enable = 1;
3813 table->SVI2Enable = 0;
3815 table->ThermGpio = 17;
3816 table->SclkStepSize = 0x4000;
3818 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3819 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3820 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3821 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3822 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3823 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3824 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3825 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3826 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3827 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3828 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3829 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3830 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3831 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3833 ret = amdgpu_ci_copy_bytes_to_smc(adev,
3834 pi->dpm_table_start +
3835 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3836 (u8 *)&table->SystemFlags,
3837 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3845 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3846 struct ci_single_dpm_table *dpm_table,
3847 u32 low_limit, u32 high_limit)
3851 for (i = 0; i < dpm_table->count; i++) {
3852 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3853 (dpm_table->dpm_levels[i].value > high_limit))
3854 dpm_table->dpm_levels[i].enabled = false;
3856 dpm_table->dpm_levels[i].enabled = true;
3860 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3861 u32 speed_low, u32 lanes_low,
3862 u32 speed_high, u32 lanes_high)
3864 struct ci_power_info *pi = ci_get_pi(adev);
3865 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3868 for (i = 0; i < pcie_table->count; i++) {
3869 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3870 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3871 (pcie_table->dpm_levels[i].value > speed_high) ||
3872 (pcie_table->dpm_levels[i].param1 > lanes_high))
3873 pcie_table->dpm_levels[i].enabled = false;
3875 pcie_table->dpm_levels[i].enabled = true;
3878 for (i = 0; i < pcie_table->count; i++) {
3879 if (pcie_table->dpm_levels[i].enabled) {
3880 for (j = i + 1; j < pcie_table->count; j++) {
3881 if (pcie_table->dpm_levels[j].enabled) {
3882 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3883 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3884 pcie_table->dpm_levels[j].enabled = false;
3891 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3892 struct amdgpu_ps *amdgpu_state)
3894 struct ci_ps *state = ci_get_ps(amdgpu_state);
3895 struct ci_power_info *pi = ci_get_pi(adev);
3896 u32 high_limit_count;
3898 if (state->performance_level_count < 1)
3901 if (state->performance_level_count == 1)
3902 high_limit_count = 0;
3904 high_limit_count = 1;
3906 ci_trim_single_dpm_states(adev,
3907 &pi->dpm_table.sclk_table,
3908 state->performance_levels[0].sclk,
3909 state->performance_levels[high_limit_count].sclk);
3911 ci_trim_single_dpm_states(adev,
3912 &pi->dpm_table.mclk_table,
3913 state->performance_levels[0].mclk,
3914 state->performance_levels[high_limit_count].mclk);
3916 ci_trim_pcie_dpm_states(adev,
3917 state->performance_levels[0].pcie_gen,
3918 state->performance_levels[0].pcie_lane,
3919 state->performance_levels[high_limit_count].pcie_gen,
3920 state->performance_levels[high_limit_count].pcie_lane);
3925 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3927 struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3928 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3929 struct amdgpu_clock_voltage_dependency_table *vddc_table =
3930 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3931 u32 requested_voltage = 0;
3934 if (disp_voltage_table == NULL)
3936 if (!disp_voltage_table->count)
3939 for (i = 0; i < disp_voltage_table->count; i++) {
3940 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3941 requested_voltage = disp_voltage_table->entries[i].v;
3944 for (i = 0; i < vddc_table->count; i++) {
3945 if (requested_voltage <= vddc_table->entries[i].v) {
3946 requested_voltage = vddc_table->entries[i].v;
3947 return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3948 PPSMC_MSG_VddC_Request,
3949 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3957 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3959 struct ci_power_info *pi = ci_get_pi(adev);
3960 PPSMC_Result result;
3962 ci_apply_disp_minimum_voltage_request(adev);
3964 if (!pi->sclk_dpm_key_disabled) {
3965 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3966 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3967 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3968 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3969 if (result != PPSMC_Result_OK)
3974 if (!pi->mclk_dpm_key_disabled) {
3975 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3976 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3977 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3978 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3979 if (result != PPSMC_Result_OK)
3985 if (!pi->pcie_dpm_key_disabled) {
3986 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3987 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3988 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3989 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3990 if (result != PPSMC_Result_OK)
3999 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
4000 struct amdgpu_ps *amdgpu_state)
4002 struct ci_power_info *pi = ci_get_pi(adev);
4003 struct ci_ps *state = ci_get_ps(amdgpu_state);
4004 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
4005 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4006 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
4007 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4010 pi->need_update_smu7_dpm_table = 0;
4012 for (i = 0; i < sclk_table->count; i++) {
4013 if (sclk == sclk_table->dpm_levels[i].value)
4017 if (i >= sclk_table->count) {
4018 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4020 /* XXX check display min clock requirements */
4021 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
4022 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4025 for (i = 0; i < mclk_table->count; i++) {
4026 if (mclk == mclk_table->dpm_levels[i].value)
4030 if (i >= mclk_table->count)
4031 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4033 if (adev->pm.dpm.current_active_crtc_count !=
4034 adev->pm.dpm.new_active_crtc_count)
4035 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4038 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4039 struct amdgpu_ps *amdgpu_state)
4041 struct ci_power_info *pi = ci_get_pi(adev);
4042 struct ci_ps *state = ci_get_ps(amdgpu_state);
4043 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4044 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4045 struct ci_dpm_table *dpm_table = &pi->dpm_table;
4048 if (!pi->need_update_smu7_dpm_table)
4051 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4052 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4054 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4055 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4057 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4058 ret = ci_populate_all_graphic_levels(adev);
4063 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4064 ret = ci_populate_all_memory_levels(adev);
4072 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4074 struct ci_power_info *pi = ci_get_pi(adev);
4075 const struct amdgpu_clock_and_voltage_limits *max_limits;
4078 if (adev->pm.ac_power)
4079 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4081 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4084 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4086 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4087 if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4088 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4090 if (!pi->caps_uvd_dpm)
4095 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4096 PPSMC_MSG_UVDDPM_SetEnabledMask,
4097 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4099 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4100 pi->uvd_enabled = true;
4101 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4102 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4103 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4104 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4107 if (pi->uvd_enabled) {
4108 pi->uvd_enabled = false;
4109 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4110 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4111 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4112 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4116 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4117 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4121 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4123 struct ci_power_info *pi = ci_get_pi(adev);
4124 const struct amdgpu_clock_and_voltage_limits *max_limits;
4127 if (adev->pm.ac_power)
4128 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4130 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4133 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4134 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4135 if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4136 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4138 if (!pi->caps_vce_dpm)
4143 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4144 PPSMC_MSG_VCEDPM_SetEnabledMask,
4145 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4148 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4149 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4154 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4156 struct ci_power_info *pi = ci_get_pi(adev);
4157 const struct amdgpu_clock_and_voltage_limits *max_limits;
4160 if (adev->pm.ac_power)
4161 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4163 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4166 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4167 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4168 if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4169 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4171 if (!pi->caps_samu_dpm)
4176 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4177 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4178 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4180 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4181 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4185 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4187 struct ci_power_info *pi = ci_get_pi(adev);
4188 const struct amdgpu_clock_and_voltage_limits *max_limits;
4191 if (adev->pm.ac_power)
4192 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4194 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4197 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4198 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4199 if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4200 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4202 if (!pi->caps_acp_dpm)
4207 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4208 PPSMC_MSG_ACPDPM_SetEnabledMask,
4209 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4212 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4213 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4218 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4220 struct ci_power_info *pi = ci_get_pi(adev);
4225 /* turn the clocks on when decoding */
4226 if (pi->caps_uvd_dpm ||
4227 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4228 pi->smc_state_table.UvdBootLevel = 0;
4230 pi->smc_state_table.UvdBootLevel =
4231 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4233 tmp = RREG32_SMC(ixDPM_TABLE_475);
4234 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4235 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4236 WREG32_SMC(ixDPM_TABLE_475, tmp);
4237 ret = ci_enable_uvd_dpm(adev, true);
4239 ret = ci_enable_uvd_dpm(adev, false);
4247 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4250 u32 min_evclk = 30000; /* ??? */
4251 struct amdgpu_vce_clock_voltage_dependency_table *table =
4252 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4254 for (i = 0; i < table->count; i++) {
4255 if (table->entries[i].evclk >= min_evclk)
4259 return table->count - 1;
4262 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4263 struct amdgpu_ps *amdgpu_new_state,
4264 struct amdgpu_ps *amdgpu_current_state)
4266 struct ci_power_info *pi = ci_get_pi(adev);
4270 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4271 if (amdgpu_new_state->evclk) {
4272 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4273 tmp = RREG32_SMC(ixDPM_TABLE_475);
4274 tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4275 tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4276 WREG32_SMC(ixDPM_TABLE_475, tmp);
4278 ret = ci_enable_vce_dpm(adev, true);
4280 ret = ci_enable_vce_dpm(adev, false);
4289 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4291 return ci_enable_samu_dpm(adev, gate);
4294 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4296 struct ci_power_info *pi = ci_get_pi(adev);
4300 pi->smc_state_table.AcpBootLevel = 0;
4302 tmp = RREG32_SMC(ixDPM_TABLE_475);
4303 tmp &= ~AcpBootLevel_MASK;
4304 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4305 WREG32_SMC(ixDPM_TABLE_475, tmp);
4308 return ci_enable_acp_dpm(adev, !gate);
4312 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4313 struct amdgpu_ps *amdgpu_state)
4315 struct ci_power_info *pi = ci_get_pi(adev);
4318 ret = ci_trim_dpm_states(adev, amdgpu_state);
4322 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4323 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4324 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4325 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4326 pi->last_mclk_dpm_enable_mask =
4327 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4328 if (pi->uvd_enabled) {
4329 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4330 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4332 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4333 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4338 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4343 while ((level_mask & (1 << level)) == 0)
4350 static int ci_dpm_force_performance_level(void *handle,
4351 enum amd_dpm_forced_level level)
4353 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4354 struct ci_power_info *pi = ci_get_pi(adev);
4358 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
4359 if ((!pi->pcie_dpm_key_disabled) &&
4360 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4362 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4366 ret = ci_dpm_force_state_pcie(adev, level);
4369 for (i = 0; i < adev->usec_timeout; i++) {
4370 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4371 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4372 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4379 if ((!pi->sclk_dpm_key_disabled) &&
4380 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4382 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4386 ret = ci_dpm_force_state_sclk(adev, levels);
4389 for (i = 0; i < adev->usec_timeout; i++) {
4390 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4391 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4392 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4399 if ((!pi->mclk_dpm_key_disabled) &&
4400 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4402 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4406 ret = ci_dpm_force_state_mclk(adev, levels);
4409 for (i = 0; i < adev->usec_timeout; i++) {
4410 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4411 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4412 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4419 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
4420 if ((!pi->sclk_dpm_key_disabled) &&
4421 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4422 levels = ci_get_lowest_enabled_level(adev,
4423 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4424 ret = ci_dpm_force_state_sclk(adev, levels);
4427 for (i = 0; i < adev->usec_timeout; i++) {
4428 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4429 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4430 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4436 if ((!pi->mclk_dpm_key_disabled) &&
4437 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4438 levels = ci_get_lowest_enabled_level(adev,
4439 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4440 ret = ci_dpm_force_state_mclk(adev, levels);
4443 for (i = 0; i < adev->usec_timeout; i++) {
4444 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4445 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4446 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4452 if ((!pi->pcie_dpm_key_disabled) &&
4453 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4454 levels = ci_get_lowest_enabled_level(adev,
4455 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4456 ret = ci_dpm_force_state_pcie(adev, levels);
4459 for (i = 0; i < adev->usec_timeout; i++) {
4460 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4461 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4462 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4468 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
4469 if (!pi->pcie_dpm_key_disabled) {
4470 PPSMC_Result smc_result;
4472 smc_result = amdgpu_ci_send_msg_to_smc(adev,
4473 PPSMC_MSG_PCIeDPM_UnForceLevel);
4474 if (smc_result != PPSMC_Result_OK)
4477 ret = ci_upload_dpm_level_enable_mask(adev);
4482 adev->pm.dpm.forced_level = level;
4487 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4488 struct ci_mc_reg_table *table)
4493 for (i = 0, j = table->last; i < table->last; i++) {
4494 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4496 switch(table->mc_reg_address[i].s1) {
4497 case mmMC_SEQ_MISC1:
4498 temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4499 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4500 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4501 for (k = 0; k < table->num_entries; k++) {
4502 table->mc_reg_table_entry[k].mc_data[j] =
4503 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4507 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4509 temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4510 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4511 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4512 for (k = 0; k < table->num_entries; k++) {
4513 table->mc_reg_table_entry[k].mc_data[j] =
4514 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4515 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4516 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4520 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4521 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4523 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4524 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4525 for (k = 0; k < table->num_entries; k++) {
4526 table->mc_reg_table_entry[k].mc_data[j] =
4527 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4532 case mmMC_SEQ_RESERVE_M:
4533 temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4534 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4535 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4536 for (k = 0; k < table->num_entries; k++) {
4537 table->mc_reg_table_entry[k].mc_data[j] =
4538 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4553 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4558 case mmMC_SEQ_RAS_TIMING:
4559 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4561 case mmMC_SEQ_DLL_STBY:
4562 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4564 case mmMC_SEQ_G5PDX_CMD0:
4565 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4567 case mmMC_SEQ_G5PDX_CMD1:
4568 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4570 case mmMC_SEQ_G5PDX_CTRL:
4571 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4573 case mmMC_SEQ_CAS_TIMING:
4574 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4576 case mmMC_SEQ_MISC_TIMING:
4577 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4579 case mmMC_SEQ_MISC_TIMING2:
4580 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4582 case mmMC_SEQ_PMG_DVS_CMD:
4583 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4585 case mmMC_SEQ_PMG_DVS_CTL:
4586 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4588 case mmMC_SEQ_RD_CTL_D0:
4589 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4591 case mmMC_SEQ_RD_CTL_D1:
4592 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4594 case mmMC_SEQ_WR_CTL_D0:
4595 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4597 case mmMC_SEQ_WR_CTL_D1:
4598 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4600 case mmMC_PMG_CMD_EMRS:
4601 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4603 case mmMC_PMG_CMD_MRS:
4604 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4606 case mmMC_PMG_CMD_MRS1:
4607 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4609 case mmMC_SEQ_PMG_TIMING:
4610 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4612 case mmMC_PMG_CMD_MRS2:
4613 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4615 case mmMC_SEQ_WR_CTL_2:
4616 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4626 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4630 for (i = 0; i < table->last; i++) {
4631 for (j = 1; j < table->num_entries; j++) {
4632 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4633 table->mc_reg_table_entry[j].mc_data[i]) {
4634 table->valid_flag |= 1 << i;
4641 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4646 for (i = 0; i < table->last; i++) {
4647 table->mc_reg_address[i].s0 =
4648 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4649 address : table->mc_reg_address[i].s1;
4653 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4654 struct ci_mc_reg_table *ci_table)
4658 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4660 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4663 for (i = 0; i < table->last; i++)
4664 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4666 ci_table->last = table->last;
4668 for (i = 0; i < table->num_entries; i++) {
4669 ci_table->mc_reg_table_entry[i].mclk_max =
4670 table->mc_reg_table_entry[i].mclk_max;
4671 for (j = 0; j < table->last; j++)
4672 ci_table->mc_reg_table_entry[i].mc_data[j] =
4673 table->mc_reg_table_entry[i].mc_data[j];
4675 ci_table->num_entries = table->num_entries;
4680 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4681 struct ci_mc_reg_table *table)
4687 tmp = RREG32(mmMC_SEQ_MISC0);
4688 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4691 ((adev->pdev->device == 0x67B0) ||
4692 (adev->pdev->device == 0x67B1))) {
4693 for (i = 0; i < table->last; i++) {
4694 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4696 switch (table->mc_reg_address[i].s1) {
4697 case mmMC_SEQ_MISC1:
4698 for (k = 0; k < table->num_entries; k++) {
4699 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4700 (table->mc_reg_table_entry[k].mclk_max == 137500))
4701 table->mc_reg_table_entry[k].mc_data[i] =
4702 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4706 case mmMC_SEQ_WR_CTL_D0:
4707 for (k = 0; k < table->num_entries; k++) {
4708 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4709 (table->mc_reg_table_entry[k].mclk_max == 137500))
4710 table->mc_reg_table_entry[k].mc_data[i] =
4711 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4715 case mmMC_SEQ_WR_CTL_D1:
4716 for (k = 0; k < table->num_entries; k++) {
4717 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4718 (table->mc_reg_table_entry[k].mclk_max == 137500))
4719 table->mc_reg_table_entry[k].mc_data[i] =
4720 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4724 case mmMC_SEQ_WR_CTL_2:
4725 for (k = 0; k < table->num_entries; k++) {
4726 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4727 (table->mc_reg_table_entry[k].mclk_max == 137500))
4728 table->mc_reg_table_entry[k].mc_data[i] = 0;
4731 case mmMC_SEQ_CAS_TIMING:
4732 for (k = 0; k < table->num_entries; k++) {
4733 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4734 table->mc_reg_table_entry[k].mc_data[i] =
4735 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4737 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4738 table->mc_reg_table_entry[k].mc_data[i] =
4739 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4743 case mmMC_SEQ_MISC_TIMING:
4744 for (k = 0; k < table->num_entries; k++) {
4745 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4746 table->mc_reg_table_entry[k].mc_data[i] =
4747 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4749 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4750 table->mc_reg_table_entry[k].mc_data[i] =
4751 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4760 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4761 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4762 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4763 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4764 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4770 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4772 struct ci_power_info *pi = ci_get_pi(adev);
4773 struct atom_mc_reg_table *table;
4774 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4775 u8 module_index = ci_get_memory_module_index(adev);
4778 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4782 WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4783 WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4784 WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4785 WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4786 WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4787 WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4788 WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4789 WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4790 WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4791 WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4792 WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4793 WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4794 WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4795 WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4796 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4797 WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4798 WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4799 WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4800 WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4801 WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4803 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4807 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4811 ci_set_s0_mc_reg_index(ci_table);
4813 ret = ci_register_patching_mc_seq(adev, ci_table);
4817 ret = ci_set_mc_special_registers(adev, ci_table);
4821 ci_set_valid_flag(ci_table);
4829 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4830 SMU7_Discrete_MCRegisters *mc_reg_table)
4832 struct ci_power_info *pi = ci_get_pi(adev);
4835 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4836 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4837 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4839 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4840 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4845 mc_reg_table->last = (u8)i;
4850 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4851 SMU7_Discrete_MCRegisterSet *data,
4852 u32 num_entries, u32 valid_flag)
4856 for (i = 0, j = 0; j < num_entries; j++) {
4857 if (valid_flag & (1 << j)) {
4858 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4864 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4865 const u32 memory_clock,
4866 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4868 struct ci_power_info *pi = ci_get_pi(adev);
4871 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4872 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4876 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4879 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4880 mc_reg_table_data, pi->mc_reg_table.last,
4881 pi->mc_reg_table.valid_flag);
4884 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4885 SMU7_Discrete_MCRegisters *mc_reg_table)
4887 struct ci_power_info *pi = ci_get_pi(adev);
4890 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4891 ci_convert_mc_reg_table_entry_to_smc(adev,
4892 pi->dpm_table.mclk_table.dpm_levels[i].value,
4893 &mc_reg_table->data[i]);
4896 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4898 struct ci_power_info *pi = ci_get_pi(adev);
4901 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4903 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4906 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4908 return amdgpu_ci_copy_bytes_to_smc(adev,
4909 pi->mc_reg_table_start,
4910 (u8 *)&pi->smc_mc_reg_table,
4911 sizeof(SMU7_Discrete_MCRegisters),
4915 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4917 struct ci_power_info *pi = ci_get_pi(adev);
4919 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4922 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4924 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4926 return amdgpu_ci_copy_bytes_to_smc(adev,
4927 pi->mc_reg_table_start +
4928 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4929 (u8 *)&pi->smc_mc_reg_table.data[0],
4930 sizeof(SMU7_Discrete_MCRegisterSet) *
4931 pi->dpm_table.mclk_table.count,
4935 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4937 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4939 tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4940 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4943 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4944 struct amdgpu_ps *amdgpu_state)
4946 struct ci_ps *state = ci_get_ps(amdgpu_state);
4948 u16 pcie_speed, max_speed = 0;
4950 for (i = 0; i < state->performance_level_count; i++) {
4951 pcie_speed = state->performance_levels[i].pcie_gen;
4952 if (max_speed < pcie_speed)
4953 max_speed = pcie_speed;
4959 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4963 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4964 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4965 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4967 return (u16)speed_cntl;
4970 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
4974 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
4975 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
4976 link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4978 switch (link_width) {
4994 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
4995 struct amdgpu_ps *amdgpu_new_state,
4996 struct amdgpu_ps *amdgpu_current_state)
4998 struct ci_power_info *pi = ci_get_pi(adev);
4999 enum amdgpu_pcie_gen target_link_speed =
5000 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5001 enum amdgpu_pcie_gen current_link_speed;
5003 if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
5004 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
5006 current_link_speed = pi->force_pcie_gen;
5008 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5009 pi->pspp_notify_required = false;
5010 if (target_link_speed > current_link_speed) {
5011 switch (target_link_speed) {
5013 case AMDGPU_PCIE_GEN3:
5014 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5016 pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
5017 if (current_link_speed == AMDGPU_PCIE_GEN2)
5019 case AMDGPU_PCIE_GEN2:
5020 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5024 pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
5028 if (target_link_speed < current_link_speed)
5029 pi->pspp_notify_required = true;
5033 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5034 struct amdgpu_ps *amdgpu_new_state,
5035 struct amdgpu_ps *amdgpu_current_state)
5037 struct ci_power_info *pi = ci_get_pi(adev);
5038 enum amdgpu_pcie_gen target_link_speed =
5039 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5042 if (pi->pspp_notify_required) {
5043 if (target_link_speed == AMDGPU_PCIE_GEN3)
5044 request = PCIE_PERF_REQ_PECI_GEN3;
5045 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5046 request = PCIE_PERF_REQ_PECI_GEN2;
5048 request = PCIE_PERF_REQ_PECI_GEN1;
5050 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5051 (ci_get_current_pcie_speed(adev) > 0))
5055 amdgpu_acpi_pcie_performance_request(adev, request, false);
5060 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5062 struct ci_power_info *pi = ci_get_pi(adev);
5063 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5064 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5065 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5066 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5067 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5068 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5070 if (allowed_sclk_vddc_table == NULL)
5072 if (allowed_sclk_vddc_table->count < 1)
5074 if (allowed_mclk_vddc_table == NULL)
5076 if (allowed_mclk_vddc_table->count < 1)
5078 if (allowed_mclk_vddci_table == NULL)
5080 if (allowed_mclk_vddci_table->count < 1)
5083 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5084 pi->max_vddc_in_pp_table =
5085 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5087 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5088 pi->max_vddci_in_pp_table =
5089 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5091 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5092 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5093 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5094 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5095 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5096 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5097 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5098 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5103 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5105 struct ci_power_info *pi = ci_get_pi(adev);
5106 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5109 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5110 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5111 *vddc = leakage_table->actual_voltage[leakage_index];
5117 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5119 struct ci_power_info *pi = ci_get_pi(adev);
5120 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5123 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5124 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5125 *vddci = leakage_table->actual_voltage[leakage_index];
5131 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5132 struct amdgpu_clock_voltage_dependency_table *table)
5137 for (i = 0; i < table->count; i++)
5138 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5142 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5143 struct amdgpu_clock_voltage_dependency_table *table)
5148 for (i = 0; i < table->count; i++)
5149 ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5153 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5154 struct amdgpu_vce_clock_voltage_dependency_table *table)
5159 for (i = 0; i < table->count; i++)
5160 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5164 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5165 struct amdgpu_uvd_clock_voltage_dependency_table *table)
5170 for (i = 0; i < table->count; i++)
5171 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5175 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5176 struct amdgpu_phase_shedding_limits_table *table)
5181 for (i = 0; i < table->count; i++)
5182 ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5186 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5187 struct amdgpu_clock_and_voltage_limits *table)
5190 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5191 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5195 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5196 struct amdgpu_cac_leakage_table *table)
5201 for (i = 0; i < table->count; i++)
5202 ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5206 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5209 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5210 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5211 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5212 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5213 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5214 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5215 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5216 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5217 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5218 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5219 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5220 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5221 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5222 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5223 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5224 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5225 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5226 &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5227 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5228 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5229 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5230 &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5231 ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5232 &adev->pm.dpm.dyn_state.cac_leakage_table);
5236 static void ci_update_current_ps(struct amdgpu_device *adev,
5237 struct amdgpu_ps *rps)
5239 struct ci_ps *new_ps = ci_get_ps(rps);
5240 struct ci_power_info *pi = ci_get_pi(adev);
5242 pi->current_rps = *rps;
5243 pi->current_ps = *new_ps;
5244 pi->current_rps.ps_priv = &pi->current_ps;
5245 adev->pm.dpm.current_ps = &pi->current_rps;
5248 static void ci_update_requested_ps(struct amdgpu_device *adev,
5249 struct amdgpu_ps *rps)
5251 struct ci_ps *new_ps = ci_get_ps(rps);
5252 struct ci_power_info *pi = ci_get_pi(adev);
5254 pi->requested_rps = *rps;
5255 pi->requested_ps = *new_ps;
5256 pi->requested_rps.ps_priv = &pi->requested_ps;
5257 adev->pm.dpm.requested_ps = &pi->requested_rps;
5260 static int ci_dpm_pre_set_power_state(void *handle)
5262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5263 struct ci_power_info *pi = ci_get_pi(adev);
5264 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5265 struct amdgpu_ps *new_ps = &requested_ps;
5267 ci_update_requested_ps(adev, new_ps);
5269 ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5274 static void ci_dpm_post_set_power_state(void *handle)
5276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5277 struct ci_power_info *pi = ci_get_pi(adev);
5278 struct amdgpu_ps *new_ps = &pi->requested_rps;
5280 ci_update_current_ps(adev, new_ps);
5284 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5286 ci_read_clock_registers(adev);
5287 ci_enable_acpi_power_management(adev);
5288 ci_init_sclk_t(adev);
5291 static int ci_dpm_enable(struct amdgpu_device *adev)
5293 struct ci_power_info *pi = ci_get_pi(adev);
5294 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5297 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5298 ci_enable_voltage_control(adev);
5299 ret = ci_construct_voltage_tables(adev);
5301 DRM_ERROR("ci_construct_voltage_tables failed\n");
5305 if (pi->caps_dynamic_ac_timing) {
5306 ret = ci_initialize_mc_reg_table(adev);
5308 pi->caps_dynamic_ac_timing = false;
5311 ci_enable_spread_spectrum(adev, true);
5312 if (pi->thermal_protection)
5313 ci_enable_thermal_protection(adev, true);
5314 ci_program_sstp(adev);
5315 ci_enable_display_gap(adev);
5316 ci_program_vc(adev);
5317 ret = ci_upload_firmware(adev);
5319 DRM_ERROR("ci_upload_firmware failed\n");
5322 ret = ci_process_firmware_header(adev);
5324 DRM_ERROR("ci_process_firmware_header failed\n");
5327 ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5329 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5332 ret = ci_init_smc_table(adev);
5334 DRM_ERROR("ci_init_smc_table failed\n");
5337 ret = ci_init_arb_table_index(adev);
5339 DRM_ERROR("ci_init_arb_table_index failed\n");
5342 if (pi->caps_dynamic_ac_timing) {
5343 ret = ci_populate_initial_mc_reg_table(adev);
5345 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5349 ret = ci_populate_pm_base(adev);
5351 DRM_ERROR("ci_populate_pm_base failed\n");
5354 ci_dpm_start_smc(adev);
5355 ci_enable_vr_hot_gpio_interrupt(adev);
5356 ret = ci_notify_smc_display_change(adev, false);
5358 DRM_ERROR("ci_notify_smc_display_change failed\n");
5361 ci_enable_sclk_control(adev, true);
5362 ret = ci_enable_ulv(adev, true);
5364 DRM_ERROR("ci_enable_ulv failed\n");
5367 ret = ci_enable_ds_master_switch(adev, true);
5369 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5372 ret = ci_start_dpm(adev);
5374 DRM_ERROR("ci_start_dpm failed\n");
5377 ret = ci_enable_didt(adev, true);
5379 DRM_ERROR("ci_enable_didt failed\n");
5382 ret = ci_enable_smc_cac(adev, true);
5384 DRM_ERROR("ci_enable_smc_cac failed\n");
5387 ret = ci_enable_power_containment(adev, true);
5389 DRM_ERROR("ci_enable_power_containment failed\n");
5393 ret = ci_power_control_set_level(adev);
5395 DRM_ERROR("ci_power_control_set_level failed\n");
5399 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5401 ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5403 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5407 ci_thermal_start_thermal_controller(adev);
5409 ci_update_current_ps(adev, boot_ps);
5414 static void ci_dpm_disable(struct amdgpu_device *adev)
5416 struct ci_power_info *pi = ci_get_pi(adev);
5417 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5419 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5420 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5421 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5422 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5424 ci_dpm_powergate_uvd(adev, true);
5426 if (!amdgpu_ci_is_smc_running(adev))
5429 ci_thermal_stop_thermal_controller(adev);
5431 if (pi->thermal_protection)
5432 ci_enable_thermal_protection(adev, false);
5433 ci_enable_power_containment(adev, false);
5434 ci_enable_smc_cac(adev, false);
5435 ci_enable_didt(adev, false);
5436 ci_enable_spread_spectrum(adev, false);
5437 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5439 ci_enable_ds_master_switch(adev, false);
5440 ci_enable_ulv(adev, false);
5442 ci_reset_to_default(adev);
5443 ci_dpm_stop_smc(adev);
5444 ci_force_switch_to_arb_f0(adev);
5445 ci_enable_thermal_based_sclk_dpm(adev, false);
5447 ci_update_current_ps(adev, boot_ps);
5450 static int ci_dpm_set_power_state(void *handle)
5452 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5453 struct ci_power_info *pi = ci_get_pi(adev);
5454 struct amdgpu_ps *new_ps = &pi->requested_rps;
5455 struct amdgpu_ps *old_ps = &pi->current_rps;
5458 ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5459 if (pi->pcie_performance_request)
5460 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5461 ret = ci_freeze_sclk_mclk_dpm(adev);
5463 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5466 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5468 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5471 ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5473 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5477 ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5479 DRM_ERROR("ci_update_vce_dpm failed\n");
5483 ret = ci_update_sclk_t(adev);
5485 DRM_ERROR("ci_update_sclk_t failed\n");
5488 if (pi->caps_dynamic_ac_timing) {
5489 ret = ci_update_and_upload_mc_reg_table(adev);
5491 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5495 ret = ci_program_memory_timing_parameters(adev);
5497 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5500 ret = ci_unfreeze_sclk_mclk_dpm(adev);
5502 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5505 ret = ci_upload_dpm_level_enable_mask(adev);
5507 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5510 if (pi->pcie_performance_request)
5511 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5517 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5519 ci_set_boot_state(adev);
5523 static void ci_dpm_display_configuration_changed(void *handle)
5525 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5527 ci_program_display_gap(adev);
5531 struct _ATOM_POWERPLAY_INFO info;
5532 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5533 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5534 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5535 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5536 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5539 union pplib_clock_info {
5540 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5541 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5542 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5543 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5544 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5545 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5548 union pplib_power_state {
5549 struct _ATOM_PPLIB_STATE v1;
5550 struct _ATOM_PPLIB_STATE_V2 v2;
5553 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5554 struct amdgpu_ps *rps,
5555 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5558 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5559 rps->class = le16_to_cpu(non_clock_info->usClassification);
5560 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5562 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5563 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5564 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5570 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5571 adev->pm.dpm.boot_ps = rps;
5572 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5573 adev->pm.dpm.uvd_ps = rps;
5576 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5577 struct amdgpu_ps *rps, int index,
5578 union pplib_clock_info *clock_info)
5580 struct ci_power_info *pi = ci_get_pi(adev);
5581 struct ci_ps *ps = ci_get_ps(rps);
5582 struct ci_pl *pl = &ps->performance_levels[index];
5584 ps->performance_level_count = index + 1;
5586 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5587 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5588 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5589 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5591 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5593 pi->vbios_boot_state.pcie_gen_bootup_value,
5594 clock_info->ci.ucPCIEGen);
5595 pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5596 pi->vbios_boot_state.pcie_lane_bootup_value,
5597 le16_to_cpu(clock_info->ci.usPCIELane));
5599 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5600 pi->acpi_pcie_gen = pl->pcie_gen;
5603 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5604 pi->ulv.supported = true;
5606 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5609 /* patch up boot state */
5610 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5611 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5612 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5613 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5614 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5617 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5618 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5619 pi->use_pcie_powersaving_levels = true;
5620 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5621 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5622 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5623 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5624 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5625 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5626 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5627 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5629 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5630 pi->use_pcie_performance_levels = true;
5631 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5632 pi->pcie_gen_performance.max = pl->pcie_gen;
5633 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5634 pi->pcie_gen_performance.min = pl->pcie_gen;
5635 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5636 pi->pcie_lane_performance.max = pl->pcie_lane;
5637 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5638 pi->pcie_lane_performance.min = pl->pcie_lane;
5645 static int ci_parse_power_table(struct amdgpu_device *adev)
5647 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5648 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5649 union pplib_power_state *power_state;
5650 int i, j, k, non_clock_array_index, clock_array_index;
5651 union pplib_clock_info *clock_info;
5652 struct _StateArray *state_array;
5653 struct _ClockInfoArray *clock_info_array;
5654 struct _NonClockInfoArray *non_clock_info_array;
5655 union power_info *power_info;
5656 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5659 u8 *power_state_offset;
5662 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5663 &frev, &crev, &data_offset))
5665 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5667 amdgpu_add_thermal_controller(adev);
5669 state_array = (struct _StateArray *)
5670 (mode_info->atom_context->bios + data_offset +
5671 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5672 clock_info_array = (struct _ClockInfoArray *)
5673 (mode_info->atom_context->bios + data_offset +
5674 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5675 non_clock_info_array = (struct _NonClockInfoArray *)
5676 (mode_info->atom_context->bios + data_offset +
5677 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5679 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
5680 sizeof(struct amdgpu_ps),
5682 if (!adev->pm.dpm.ps)
5684 power_state_offset = (u8 *)state_array->states;
5685 for (i = 0; i < state_array->ucNumEntries; i++) {
5687 power_state = (union pplib_power_state *)power_state_offset;
5688 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5689 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5690 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5691 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5693 kfree(adev->pm.dpm.ps);
5696 adev->pm.dpm.ps[i].ps_priv = ps;
5697 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5699 non_clock_info_array->ucEntrySize);
5701 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5702 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5703 clock_array_index = idx[j];
5704 if (clock_array_index >= clock_info_array->ucNumEntries)
5706 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5708 clock_info = (union pplib_clock_info *)
5709 ((u8 *)&clock_info_array->clockInfo[0] +
5710 (clock_array_index * clock_info_array->ucEntrySize));
5711 ci_parse_pplib_clock_info(adev,
5712 &adev->pm.dpm.ps[i], k,
5716 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5718 adev->pm.dpm.num_ps = state_array->ucNumEntries;
5720 /* fill in the vce power states */
5721 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
5723 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5724 clock_info = (union pplib_clock_info *)
5725 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5726 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5727 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5728 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5729 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5730 adev->pm.dpm.vce_states[i].sclk = sclk;
5731 adev->pm.dpm.vce_states[i].mclk = mclk;
5737 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5738 struct ci_vbios_boot_state *boot_state)
5740 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5741 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5742 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5746 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5747 &frev, &crev, &data_offset)) {
5749 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5751 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5752 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5753 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5754 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5755 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5756 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5757 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5764 static void ci_dpm_fini(struct amdgpu_device *adev)
5768 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5769 kfree(adev->pm.dpm.ps[i].ps_priv);
5771 kfree(adev->pm.dpm.ps);
5772 kfree(adev->pm.dpm.priv);
5773 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5774 amdgpu_free_extended_power_table(adev);
5778 * ci_dpm_init_microcode - load ucode images from disk
5780 * @adev: amdgpu_device pointer
5782 * Use the firmware interface to load the ucode images into
5783 * the driver (not loaded into hw).
5784 * Returns 0 on success, error on failure.
5786 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5788 const char *chip_name;
5794 switch (adev->asic_type) {
5796 if ((adev->pdev->revision == 0x80) ||
5797 (adev->pdev->revision == 0x81) ||
5798 (adev->pdev->device == 0x665f))
5799 chip_name = "bonaire_k";
5801 chip_name = "bonaire";
5804 if (adev->pdev->revision == 0x80)
5805 chip_name = "hawaii_k";
5807 chip_name = "hawaii";
5815 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
5816 err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
5819 err = amdgpu_ucode_validate(adev->pm.fw);
5823 pr_err("cik_smc: Failed to load firmware \"%s\"\n", fw_name);
5824 release_firmware(adev->pm.fw);
5830 static int ci_dpm_init(struct amdgpu_device *adev)
5832 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5833 SMU7_Discrete_DpmTable *dpm_table;
5834 struct amdgpu_gpio_rec gpio;
5835 u16 data_offset, size;
5837 struct ci_power_info *pi;
5840 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5843 adev->pm.dpm.priv = pi;
5846 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
5848 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5850 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5851 pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5852 pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5853 pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5855 pi->pcie_lane_performance.max = 0;
5856 pi->pcie_lane_performance.min = 16;
5857 pi->pcie_lane_powersaving.max = 0;
5858 pi->pcie_lane_powersaving.min = 16;
5860 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5866 ret = amdgpu_get_platform_caps(adev);
5872 ret = amdgpu_parse_extended_power_table(adev);
5878 ret = ci_parse_power_table(adev);
5884 pi->dll_default_on = false;
5885 pi->sram_end = SMC_RAM_END;
5887 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5888 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5889 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5890 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5891 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5892 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5893 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5894 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5896 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5898 pi->sclk_dpm_key_disabled = 0;
5899 pi->mclk_dpm_key_disabled = 0;
5900 pi->pcie_dpm_key_disabled = 0;
5901 pi->thermal_sclk_dpm_enabled = 0;
5903 if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
5904 pi->caps_sclk_ds = true;
5906 pi->caps_sclk_ds = false;
5908 pi->mclk_strobe_mode_threshold = 40000;
5909 pi->mclk_stutter_mode_threshold = 40000;
5910 pi->mclk_edc_enable_threshold = 40000;
5911 pi->mclk_edc_wr_enable_threshold = 40000;
5913 ci_initialize_powertune_defaults(adev);
5915 pi->caps_fps = false;
5917 pi->caps_sclk_throttle_low_notification = false;
5919 pi->caps_uvd_dpm = true;
5920 pi->caps_vce_dpm = true;
5922 ci_get_leakage_voltages(adev);
5923 ci_patch_dependency_tables_with_leakage(adev);
5924 ci_set_private_data_variables_based_on_pptable(adev);
5926 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5928 sizeof(struct amdgpu_clock_voltage_dependency_entry),
5930 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5934 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5935 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5936 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5937 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5938 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5939 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5940 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5941 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5942 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5944 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5945 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5946 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5948 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5949 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5950 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5951 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5953 if (adev->asic_type == CHIP_HAWAII) {
5954 pi->thermal_temp_setting.temperature_low = 94500;
5955 pi->thermal_temp_setting.temperature_high = 95000;
5956 pi->thermal_temp_setting.temperature_shutdown = 104000;
5958 pi->thermal_temp_setting.temperature_low = 99500;
5959 pi->thermal_temp_setting.temperature_high = 100000;
5960 pi->thermal_temp_setting.temperature_shutdown = 104000;
5963 pi->uvd_enabled = false;
5965 dpm_table = &pi->smc_state_table;
5967 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5969 dpm_table->VRHotGpio = gpio.shift;
5970 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5972 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5973 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5976 gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
5978 dpm_table->AcDcGpio = gpio.shift;
5979 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5981 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5982 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5985 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
5987 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
5989 switch (gpio.shift) {
5991 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5992 tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5995 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5996 tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5999 tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
6002 tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
6005 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
6008 DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift);
6011 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
6014 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6015 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6016 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6017 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
6018 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6019 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
6020 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6022 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
6023 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
6024 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6025 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
6026 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6028 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
6031 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
6032 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
6033 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6034 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
6035 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6037 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
6040 pi->vddc_phase_shed_control = true;
6042 #if defined(CONFIG_ACPI)
6043 pi->pcie_performance_request =
6044 amdgpu_acpi_is_pcie_performance_request_supported(adev);
6046 pi->pcie_performance_request = false;
6049 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6050 &frev, &crev, &data_offset)) {
6051 pi->caps_sclk_ss_support = true;
6052 pi->caps_mclk_ss_support = true;
6053 pi->dynamic_ss = true;
6055 pi->caps_sclk_ss_support = false;
6056 pi->caps_mclk_ss_support = false;
6057 pi->dynamic_ss = true;
6060 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6061 pi->thermal_protection = true;
6063 pi->thermal_protection = false;
6065 pi->caps_dynamic_ac_timing = true;
6067 pi->uvd_power_gated = true;
6069 /* make sure dc limits are valid */
6070 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6071 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6072 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6073 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6075 pi->fan_ctrl_is_in_default_mode = true;
6081 ci_dpm_debugfs_print_current_performance_level(void *handle,
6084 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6085 struct ci_power_info *pi = ci_get_pi(adev);
6086 struct amdgpu_ps *rps = &pi->current_rps;
6087 u32 sclk = ci_get_average_sclk_freq(adev);
6088 u32 mclk = ci_get_average_mclk_freq(adev);
6089 u32 activity_percent = 50;
6092 ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6096 activity_percent += 0x80;
6097 activity_percent >>= 8;
6098 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6101 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
6102 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6103 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
6105 seq_printf(m, "GPU load: %u %%\n", activity_percent);
6108 static void ci_dpm_print_power_state(void *handle, void *current_ps)
6110 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
6111 struct ci_ps *ps = ci_get_ps(rps);
6114 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6116 amdgpu_dpm_print_class_info(rps->class, rps->class2);
6117 amdgpu_dpm_print_cap_info(rps->caps);
6118 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6119 for (i = 0; i < ps->performance_level_count; i++) {
6120 pl = &ps->performance_levels[i];
6121 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6122 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6124 amdgpu_dpm_print_ps_status(adev, rps);
6127 static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1,
6128 const struct ci_pl *ci_cpl2)
6130 return ((ci_cpl1->mclk == ci_cpl2->mclk) &&
6131 (ci_cpl1->sclk == ci_cpl2->sclk) &&
6132 (ci_cpl1->pcie_gen == ci_cpl2->pcie_gen) &&
6133 (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));
6136 static int ci_check_state_equal(void *handle,
6141 struct ci_ps *ci_cps;
6142 struct ci_ps *ci_rps;
6144 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
6145 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
6146 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6148 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
6151 ci_cps = ci_get_ps((struct amdgpu_ps *)cps);
6152 ci_rps = ci_get_ps((struct amdgpu_ps *)rps);
6154 if (ci_cps == NULL) {
6159 if (ci_cps->performance_level_count != ci_rps->performance_level_count) {
6165 for (i = 0; i < ci_cps->performance_level_count; i++) {
6166 if (!ci_are_power_levels_equal(&(ci_cps->performance_levels[i]),
6167 &(ci_rps->performance_levels[i]))) {
6173 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6174 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
6175 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
6180 static u32 ci_dpm_get_sclk(void *handle, bool low)
6182 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6183 struct ci_power_info *pi = ci_get_pi(adev);
6184 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6187 return requested_state->performance_levels[0].sclk;
6189 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6192 static u32 ci_dpm_get_mclk(void *handle, bool low)
6194 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6195 struct ci_power_info *pi = ci_get_pi(adev);
6196 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6199 return requested_state->performance_levels[0].mclk;
6201 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6204 /* get temperature in millidegrees */
6205 static int ci_dpm_get_temp(void *handle)
6208 int actual_temp = 0;
6209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6211 temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6212 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6217 actual_temp = temp & 0x1ff;
6219 actual_temp = actual_temp * 1000;
6224 static int ci_set_temperature_range(struct amdgpu_device *adev)
6228 ret = ci_thermal_enable_alert(adev, false);
6231 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6232 CISLANDS_TEMP_RANGE_MAX);
6235 ret = ci_thermal_enable_alert(adev, true);
6241 static int ci_dpm_early_init(void *handle)
6243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6245 adev->powerplay.pp_funcs = &ci_dpm_funcs;
6246 adev->powerplay.pp_handle = adev;
6247 ci_dpm_set_irq_funcs(adev);
6252 static int ci_dpm_late_init(void *handle)
6255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6257 if (!adev->pm.dpm_enabled)
6260 /* init the sysfs and debugfs files late */
6261 ret = amdgpu_pm_sysfs_init(adev);
6265 ret = ci_set_temperature_range(adev);
6272 static int ci_dpm_sw_init(void *handle)
6275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6277 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
6278 &adev->pm.dpm.thermal.irq);
6282 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
6283 &adev->pm.dpm.thermal.irq);
6287 /* default to balanced state */
6288 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6289 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6290 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
6291 adev->pm.default_sclk = adev->clock.default_sclk;
6292 adev->pm.default_mclk = adev->clock.default_mclk;
6293 adev->pm.current_sclk = adev->clock.default_sclk;
6294 adev->pm.current_mclk = adev->clock.default_mclk;
6295 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6297 ret = ci_dpm_init_microcode(adev);
6301 if (amdgpu_dpm == 0)
6304 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6305 mutex_lock(&adev->pm.mutex);
6306 ret = ci_dpm_init(adev);
6309 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6310 if (amdgpu_dpm == 1)
6311 amdgpu_pm_print_power_states(adev);
6312 mutex_unlock(&adev->pm.mutex);
6313 DRM_INFO("amdgpu: dpm initialized\n");
6319 mutex_unlock(&adev->pm.mutex);
6320 DRM_ERROR("amdgpu: dpm initialization failed\n");
6324 static int ci_dpm_sw_fini(void *handle)
6326 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6328 flush_work(&adev->pm.dpm.thermal.work);
6330 mutex_lock(&adev->pm.mutex);
6332 mutex_unlock(&adev->pm.mutex);
6334 release_firmware(adev->pm.fw);
6340 static int ci_dpm_hw_init(void *handle)
6344 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6347 ret = ci_upload_firmware(adev);
6349 DRM_ERROR("ci_upload_firmware failed\n");
6352 ci_dpm_start_smc(adev);
6356 mutex_lock(&adev->pm.mutex);
6357 ci_dpm_setup_asic(adev);
6358 ret = ci_dpm_enable(adev);
6360 adev->pm.dpm_enabled = false;
6362 adev->pm.dpm_enabled = true;
6363 mutex_unlock(&adev->pm.mutex);
6368 static int ci_dpm_hw_fini(void *handle)
6370 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6372 if (adev->pm.dpm_enabled) {
6373 mutex_lock(&adev->pm.mutex);
6374 ci_dpm_disable(adev);
6375 mutex_unlock(&adev->pm.mutex);
6377 ci_dpm_stop_smc(adev);
6383 static int ci_dpm_suspend(void *handle)
6385 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6387 if (adev->pm.dpm_enabled) {
6388 mutex_lock(&adev->pm.mutex);
6389 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
6390 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
6391 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
6392 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
6393 adev->pm.dpm.last_user_state = adev->pm.dpm.user_state;
6394 adev->pm.dpm.last_state = adev->pm.dpm.state;
6395 adev->pm.dpm.user_state = POWER_STATE_TYPE_INTERNAL_BOOT;
6396 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_BOOT;
6397 mutex_unlock(&adev->pm.mutex);
6398 amdgpu_pm_compute_clocks(adev);
6405 static int ci_dpm_resume(void *handle)
6408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6410 if (adev->pm.dpm_enabled) {
6411 /* asic init will reset to the boot state */
6412 mutex_lock(&adev->pm.mutex);
6413 ci_dpm_setup_asic(adev);
6414 ret = ci_dpm_enable(adev);
6416 adev->pm.dpm_enabled = false;
6418 adev->pm.dpm_enabled = true;
6419 adev->pm.dpm.user_state = adev->pm.dpm.last_user_state;
6420 adev->pm.dpm.state = adev->pm.dpm.last_state;
6421 mutex_unlock(&adev->pm.mutex);
6422 if (adev->pm.dpm_enabled)
6423 amdgpu_pm_compute_clocks(adev);
6428 static bool ci_dpm_is_idle(void *handle)
6434 static int ci_dpm_wait_for_idle(void *handle)
6440 static int ci_dpm_soft_reset(void *handle)
6445 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6446 struct amdgpu_irq_src *source,
6448 enum amdgpu_interrupt_state state)
6453 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6455 case AMDGPU_IRQ_STATE_DISABLE:
6456 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6457 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6458 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6460 case AMDGPU_IRQ_STATE_ENABLE:
6461 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6462 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6463 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6470 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6472 case AMDGPU_IRQ_STATE_DISABLE:
6473 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6474 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6475 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6477 case AMDGPU_IRQ_STATE_ENABLE:
6478 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6479 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6480 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6493 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6494 struct amdgpu_irq_src *source,
6495 struct amdgpu_iv_entry *entry)
6497 bool queue_thermal = false;
6502 switch (entry->src_id) {
6503 case 230: /* thermal low to high */
6504 DRM_DEBUG("IH: thermal low to high\n");
6505 adev->pm.dpm.thermal.high_to_low = false;
6506 queue_thermal = true;
6508 case 231: /* thermal high to low */
6509 DRM_DEBUG("IH: thermal high to low\n");
6510 adev->pm.dpm.thermal.high_to_low = true;
6511 queue_thermal = true;
6518 schedule_work(&adev->pm.dpm.thermal.work);
6523 static int ci_dpm_set_clockgating_state(void *handle,
6524 enum amd_clockgating_state state)
6529 static int ci_dpm_set_powergating_state(void *handle,
6530 enum amd_powergating_state state)
6535 static int ci_dpm_print_clock_levels(void *handle,
6536 enum pp_clock_type type, char *buf)
6538 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6539 struct ci_power_info *pi = ci_get_pi(adev);
6540 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
6541 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
6542 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
6544 int i, now, size = 0;
6545 uint32_t clock, pcie_speed;
6549 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
6550 clock = RREG32(mmSMC_MSG_ARG_0);
6552 for (i = 0; i < sclk_table->count; i++) {
6553 if (clock > sclk_table->dpm_levels[i].value)
6559 for (i = 0; i < sclk_table->count; i++)
6560 size += sprintf(buf + size, "%d: %uMhz %s\n",
6561 i, sclk_table->dpm_levels[i].value / 100,
6562 (i == now) ? "*" : "");
6565 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
6566 clock = RREG32(mmSMC_MSG_ARG_0);
6568 for (i = 0; i < mclk_table->count; i++) {
6569 if (clock > mclk_table->dpm_levels[i].value)
6575 for (i = 0; i < mclk_table->count; i++)
6576 size += sprintf(buf + size, "%d: %uMhz %s\n",
6577 i, mclk_table->dpm_levels[i].value / 100,
6578 (i == now) ? "*" : "");
6581 pcie_speed = ci_get_current_pcie_speed(adev);
6582 for (i = 0; i < pcie_table->count; i++) {
6583 if (pcie_speed != pcie_table->dpm_levels[i].value)
6589 for (i = 0; i < pcie_table->count; i++)
6590 size += sprintf(buf + size, "%d: %s %s\n", i,
6591 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x1" :
6592 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
6593 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
6594 (i == now) ? "*" : "");
6603 static int ci_dpm_force_clock_level(void *handle,
6604 enum pp_clock_type type, uint32_t mask)
6606 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6607 struct ci_power_info *pi = ci_get_pi(adev);
6609 if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL)
6617 if (!pi->sclk_dpm_key_disabled)
6618 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6619 PPSMC_MSG_SCLKDPM_SetEnabledMask,
6620 pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
6624 if (!pi->mclk_dpm_key_disabled)
6625 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6626 PPSMC_MSG_MCLKDPM_SetEnabledMask,
6627 pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
6632 uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
6634 if (!pi->pcie_dpm_key_disabled) {
6635 if (fls(tmp) != ffs(tmp))
6636 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_UnForceLevel);
6638 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6639 PPSMC_MSG_PCIeDPM_ForceLevel,
6651 static int ci_dpm_get_sclk_od(void *handle)
6653 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6654 struct ci_power_info *pi = ci_get_pi(adev);
6655 struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
6656 struct ci_single_dpm_table *golden_sclk_table =
6657 &(pi->golden_dpm_table.sclk_table);
6660 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
6661 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
6663 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6668 static int ci_dpm_set_sclk_od(void *handle, uint32_t value)
6670 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6671 struct ci_power_info *pi = ci_get_pi(adev);
6672 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6673 struct ci_single_dpm_table *golden_sclk_table =
6674 &(pi->golden_dpm_table.sclk_table);
6679 ps->performance_levels[ps->performance_level_count - 1].sclk =
6680 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
6682 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6687 static int ci_dpm_get_mclk_od(void *handle)
6689 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6690 struct ci_power_info *pi = ci_get_pi(adev);
6691 struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
6692 struct ci_single_dpm_table *golden_mclk_table =
6693 &(pi->golden_dpm_table.mclk_table);
6696 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
6697 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
6699 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6704 static int ci_dpm_set_mclk_od(void *handle, uint32_t value)
6706 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6707 struct ci_power_info *pi = ci_get_pi(adev);
6708 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6709 struct ci_single_dpm_table *golden_mclk_table =
6710 &(pi->golden_dpm_table.mclk_table);
6715 ps->performance_levels[ps->performance_level_count - 1].mclk =
6716 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
6718 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6723 static int ci_dpm_read_sensor(void *handle, int idx,
6724 void *value, int *size)
6726 u32 activity_percent = 50;
6728 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6730 /* size must be at least 4 bytes for all sensors */
6735 case AMDGPU_PP_SENSOR_GFX_SCLK:
6736 *((uint32_t *)value) = ci_get_average_sclk_freq(adev);
6739 case AMDGPU_PP_SENSOR_GFX_MCLK:
6740 *((uint32_t *)value) = ci_get_average_mclk_freq(adev);
6743 case AMDGPU_PP_SENSOR_GPU_TEMP:
6744 *((uint32_t *)value) = ci_dpm_get_temp(adev);
6747 case AMDGPU_PP_SENSOR_GPU_LOAD:
6748 ret = ci_read_smc_soft_register(adev,
6749 offsetof(SMU7_SoftRegisters,
6753 activity_percent += 0x80;
6754 activity_percent >>= 8;
6756 activity_percent > 100 ? 100 : activity_percent;
6758 *((uint32_t *)value) = activity_percent;
6766 static int ci_set_powergating_by_smu(void *handle,
6767 uint32_t block_type, bool gate)
6769 switch (block_type) {
6770 case AMD_IP_BLOCK_TYPE_UVD:
6771 ci_dpm_powergate_uvd(handle, gate);
6779 static const struct amd_ip_funcs ci_dpm_ip_funcs = {
6781 .early_init = ci_dpm_early_init,
6782 .late_init = ci_dpm_late_init,
6783 .sw_init = ci_dpm_sw_init,
6784 .sw_fini = ci_dpm_sw_fini,
6785 .hw_init = ci_dpm_hw_init,
6786 .hw_fini = ci_dpm_hw_fini,
6787 .suspend = ci_dpm_suspend,
6788 .resume = ci_dpm_resume,
6789 .is_idle = ci_dpm_is_idle,
6790 .wait_for_idle = ci_dpm_wait_for_idle,
6791 .soft_reset = ci_dpm_soft_reset,
6792 .set_clockgating_state = ci_dpm_set_clockgating_state,
6793 .set_powergating_state = ci_dpm_set_powergating_state,
6796 const struct amdgpu_ip_block_version ci_smu_ip_block =
6798 .type = AMD_IP_BLOCK_TYPE_SMC,
6802 .funcs = &ci_dpm_ip_funcs,
6805 static const struct amd_pm_funcs ci_dpm_funcs = {
6806 .pre_set_power_state = &ci_dpm_pre_set_power_state,
6807 .set_power_state = &ci_dpm_set_power_state,
6808 .post_set_power_state = &ci_dpm_post_set_power_state,
6809 .display_configuration_changed = &ci_dpm_display_configuration_changed,
6810 .get_sclk = &ci_dpm_get_sclk,
6811 .get_mclk = &ci_dpm_get_mclk,
6812 .print_power_state = &ci_dpm_print_power_state,
6813 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
6814 .force_performance_level = &ci_dpm_force_performance_level,
6815 .vblank_too_short = &ci_dpm_vblank_too_short,
6816 .set_powergating_by_smu = &ci_set_powergating_by_smu,
6817 .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
6818 .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
6819 .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
6820 .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
6821 .print_clock_levels = ci_dpm_print_clock_levels,
6822 .force_clock_level = ci_dpm_force_clock_level,
6823 .get_sclk_od = ci_dpm_get_sclk_od,
6824 .set_sclk_od = ci_dpm_set_sclk_od,
6825 .get_mclk_od = ci_dpm_get_mclk_od,
6826 .set_mclk_od = ci_dpm_set_mclk_od,
6827 .check_state_equal = ci_check_state_equal,
6828 .get_vce_clock_state = amdgpu_get_vce_clock_state,
6829 .read_sensor = ci_dpm_read_sensor,
6832 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
6833 .set = ci_dpm_set_interrupt_state,
6834 .process = ci_dpm_process_interrupt,
6837 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6839 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6840 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;