2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_pm.h"
28 #include "amdgpu_ucode.h"
30 #include "amdgpu_dpm.h"
35 #include <linux/seq_file.h>
37 #include "smu/smu_7_0_1_d.h"
38 #include "smu/smu_7_0_1_sh_mask.h"
40 #include "dce/dce_8_0_d.h"
41 #include "dce/dce_8_0_sh_mask.h"
43 #include "bif/bif_4_1_d.h"
44 #include "bif/bif_4_1_sh_mask.h"
46 #include "gca/gfx_7_2_d.h"
47 #include "gca/gfx_7_2_sh_mask.h"
49 #include "gmc/gmc_7_1_d.h"
50 #include "gmc/gmc_7_1_sh_mask.h"
54 #define MC_CG_ARB_FREQ_F0 0x0a
55 #define MC_CG_ARB_FREQ_F1 0x0b
56 #define MC_CG_ARB_FREQ_F2 0x0c
57 #define MC_CG_ARB_FREQ_F3 0x0d
59 #define SMC_RAM_END 0x40000
61 #define VOLTAGE_SCALE 4
62 #define VOLTAGE_VID_OFFSET_SCALE1 625
63 #define VOLTAGE_VID_OFFSET_SCALE2 100
65 static const struct ci_pt_defaults defaults_hawaii_xt =
67 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
68 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
69 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
72 static const struct ci_pt_defaults defaults_hawaii_pro =
74 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
75 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
76 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
79 static const struct ci_pt_defaults defaults_bonaire_xt =
81 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
82 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
83 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
87 static const struct ci_pt_defaults defaults_bonaire_pro =
89 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
90 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
91 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
95 static const struct ci_pt_defaults defaults_saturn_xt =
97 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
98 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
99 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
103 static const struct ci_pt_defaults defaults_saturn_pro =
105 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
106 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
107 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
111 static const struct ci_pt_config_reg didt_config_ci[] =
113 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
163 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
164 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
165 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
166 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
167 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
168 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
169 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
170 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
171 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
172 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
173 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
174 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
175 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
176 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
177 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
178 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
179 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
180 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
181 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
182 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
183 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
184 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
188 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
190 return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
193 #define MC_CG_ARB_FREQ_F0 0x0a
194 #define MC_CG_ARB_FREQ_F1 0x0b
195 #define MC_CG_ARB_FREQ_F2 0x0c
196 #define MC_CG_ARB_FREQ_F3 0x0d
198 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
199 u32 arb_freq_src, u32 arb_freq_dest)
201 u32 mc_arb_dram_timing;
202 u32 mc_arb_dram_timing2;
206 switch (arb_freq_src) {
207 case MC_CG_ARB_FREQ_F0:
208 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
209 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
210 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
211 MC_ARB_BURST_TIME__STATE0__SHIFT;
213 case MC_CG_ARB_FREQ_F1:
214 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1);
215 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
216 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
217 MC_ARB_BURST_TIME__STATE1__SHIFT;
223 switch (arb_freq_dest) {
224 case MC_CG_ARB_FREQ_F0:
225 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
226 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
227 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
228 ~MC_ARB_BURST_TIME__STATE0_MASK);
230 case MC_CG_ARB_FREQ_F1:
231 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
232 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
233 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
234 ~MC_ARB_BURST_TIME__STATE1_MASK);
240 mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
241 WREG32(mmMC_CG_CONFIG, mc_cg_config);
242 WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
243 ~MC_ARB_CG__CG_ARB_REQ_MASK);
248 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
252 if (memory_clock < 10000)
254 else if (memory_clock >= 80000)
255 mc_para_index = 0x0f;
257 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
258 return mc_para_index;
261 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
266 if (memory_clock < 12500)
267 mc_para_index = 0x00;
268 else if (memory_clock > 47500)
269 mc_para_index = 0x0f;
271 mc_para_index = (u8)((memory_clock - 10000) / 2500);
273 if (memory_clock < 65000)
274 mc_para_index = 0x00;
275 else if (memory_clock > 135000)
276 mc_para_index = 0x0f;
278 mc_para_index = (u8)((memory_clock - 60000) / 5000);
280 return mc_para_index;
283 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
284 u32 max_voltage_steps,
285 struct atom_voltage_table *voltage_table)
287 unsigned int i, diff;
289 if (voltage_table->count <= max_voltage_steps)
292 diff = voltage_table->count - max_voltage_steps;
294 for (i = 0; i < max_voltage_steps; i++)
295 voltage_table->entries[i] = voltage_table->entries[i + diff];
297 voltage_table->count = max_voltage_steps;
300 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
301 struct atom_voltage_table_entry *voltage_table,
302 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
303 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
304 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
306 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
307 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
308 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
310 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
311 PPSMC_Msg msg, u32 parameter);
312 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
313 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
315 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
317 struct ci_power_info *pi = adev->pm.dpm.priv;
322 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
324 struct ci_ps *ps = rps->ps_priv;
329 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
331 struct ci_power_info *pi = ci_get_pi(adev);
333 switch (adev->pdev->device) {
341 pi->powertune_defaults = &defaults_bonaire_xt;
347 pi->powertune_defaults = &defaults_saturn_xt;
351 pi->powertune_defaults = &defaults_hawaii_xt;
355 pi->powertune_defaults = &defaults_hawaii_pro;
365 pi->powertune_defaults = &defaults_bonaire_xt;
369 pi->dte_tj_offset = 0;
371 pi->caps_power_containment = true;
372 pi->caps_cac = false;
373 pi->caps_sq_ramping = false;
374 pi->caps_db_ramping = false;
375 pi->caps_td_ramping = false;
376 pi->caps_tcp_ramping = false;
378 if (pi->caps_power_containment) {
380 if (adev->asic_type == CHIP_HAWAII)
381 pi->enable_bapm_feature = false;
383 pi->enable_bapm_feature = true;
384 pi->enable_tdc_limit_feature = true;
385 pi->enable_pkg_pwr_tracking_feature = true;
389 static u8 ci_convert_to_vid(u16 vddc)
391 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
394 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
396 struct ci_power_info *pi = ci_get_pi(adev);
397 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
398 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
399 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
402 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
404 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
406 if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
407 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
410 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
411 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
412 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
413 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
414 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
416 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
417 hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
423 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
425 struct ci_power_info *pi = ci_get_pi(adev);
426 u8 *vid = pi->smc_powertune_table.VddCVid;
429 if (pi->vddc_voltage_table.count > 8)
432 for (i = 0; i < pi->vddc_voltage_table.count; i++)
433 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
438 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
440 struct ci_power_info *pi = ci_get_pi(adev);
441 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
443 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
444 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
445 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
446 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
451 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
453 struct ci_power_info *pi = ci_get_pi(adev);
454 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
457 tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
458 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
459 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
460 pt_defaults->tdc_vddc_throttle_release_limit_perc;
461 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
466 static int ci_populate_dw8(struct amdgpu_device *adev)
468 struct ci_power_info *pi = ci_get_pi(adev);
469 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
472 ret = amdgpu_ci_read_smc_sram_dword(adev,
473 SMU7_FIRMWARE_HEADER_LOCATION +
474 offsetof(SMU7_Firmware_Header, PmFuseTable) +
475 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
476 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
481 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
486 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
488 struct ci_power_info *pi = ci_get_pi(adev);
490 if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
491 (adev->pm.dpm.fan.fan_output_sensitivity == 0))
492 adev->pm.dpm.fan.fan_output_sensitivity =
493 adev->pm.dpm.fan.default_fan_output_sensitivity;
495 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
496 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
501 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
503 struct ci_power_info *pi = ci_get_pi(adev);
504 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
505 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
508 min = max = hi_vid[0];
509 for (i = 0; i < 8; i++) {
510 if (0 != hi_vid[i]) {
517 if (0 != lo_vid[i]) {
525 if ((min == 0) || (max == 0))
527 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
528 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
533 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
535 struct ci_power_info *pi = ci_get_pi(adev);
536 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
537 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
538 struct amdgpu_cac_tdp_table *cac_tdp_table =
539 adev->pm.dpm.dyn_state.cac_tdp_table;
541 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
542 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
544 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
545 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
550 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
552 struct ci_power_info *pi = ci_get_pi(adev);
553 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
554 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
555 struct amdgpu_cac_tdp_table *cac_tdp_table =
556 adev->pm.dpm.dyn_state.cac_tdp_table;
557 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
562 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
563 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
565 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
566 dpm_table->GpuTjMax =
567 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
568 dpm_table->GpuTjHyst = 8;
570 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
573 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
574 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
576 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
577 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
580 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
581 def1 = pt_defaults->bapmti_r;
582 def2 = pt_defaults->bapmti_rc;
584 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
585 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
586 for (k = 0; k < SMU7_DTE_SINKS; k++) {
587 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
588 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
598 static int ci_populate_pm_base(struct amdgpu_device *adev)
600 struct ci_power_info *pi = ci_get_pi(adev);
601 u32 pm_fuse_table_offset;
604 if (pi->caps_power_containment) {
605 ret = amdgpu_ci_read_smc_sram_dword(adev,
606 SMU7_FIRMWARE_HEADER_LOCATION +
607 offsetof(SMU7_Firmware_Header, PmFuseTable),
608 &pm_fuse_table_offset, pi->sram_end);
611 ret = ci_populate_bapm_vddc_vid_sidd(adev);
614 ret = ci_populate_vddc_vid(adev);
617 ret = ci_populate_svi_load_line(adev);
620 ret = ci_populate_tdc_limit(adev);
623 ret = ci_populate_dw8(adev);
626 ret = ci_populate_fuzzy_fan(adev);
629 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
632 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
635 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
636 (u8 *)&pi->smc_powertune_table,
637 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
645 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
647 struct ci_power_info *pi = ci_get_pi(adev);
650 if (pi->caps_sq_ramping) {
651 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
653 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
655 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
656 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
659 if (pi->caps_db_ramping) {
660 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
662 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
664 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
665 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
668 if (pi->caps_td_ramping) {
669 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
671 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
673 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
674 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
677 if (pi->caps_tcp_ramping) {
678 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
680 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
682 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
683 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
687 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
688 const struct ci_pt_config_reg *cac_config_regs)
690 const struct ci_pt_config_reg *config_regs = cac_config_regs;
694 if (config_regs == NULL)
697 while (config_regs->offset != 0xFFFFFFFF) {
698 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
699 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
701 switch (config_regs->type) {
702 case CISLANDS_CONFIGREG_SMC_IND:
703 data = RREG32_SMC(config_regs->offset);
705 case CISLANDS_CONFIGREG_DIDT_IND:
706 data = RREG32_DIDT(config_regs->offset);
709 data = RREG32(config_regs->offset);
713 data &= ~config_regs->mask;
714 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
717 switch (config_regs->type) {
718 case CISLANDS_CONFIGREG_SMC_IND:
719 WREG32_SMC(config_regs->offset, data);
721 case CISLANDS_CONFIGREG_DIDT_IND:
722 WREG32_DIDT(config_regs->offset, data);
725 WREG32(config_regs->offset, data);
735 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
737 struct ci_power_info *pi = ci_get_pi(adev);
740 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
741 pi->caps_td_ramping || pi->caps_tcp_ramping) {
742 adev->gfx.rlc.funcs->enter_safe_mode(adev);
745 ret = ci_program_pt_config_registers(adev, didt_config_ci);
747 adev->gfx.rlc.funcs->exit_safe_mode(adev);
752 ci_do_enable_didt(adev, enable);
754 adev->gfx.rlc.funcs->exit_safe_mode(adev);
760 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
762 struct ci_power_info *pi = ci_get_pi(adev);
763 PPSMC_Result smc_result;
767 pi->power_containment_features = 0;
768 if (pi->caps_power_containment) {
769 if (pi->enable_bapm_feature) {
770 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
771 if (smc_result != PPSMC_Result_OK)
774 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
777 if (pi->enable_tdc_limit_feature) {
778 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
779 if (smc_result != PPSMC_Result_OK)
782 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
785 if (pi->enable_pkg_pwr_tracking_feature) {
786 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
787 if (smc_result != PPSMC_Result_OK) {
790 struct amdgpu_cac_tdp_table *cac_tdp_table =
791 adev->pm.dpm.dyn_state.cac_tdp_table;
792 u32 default_pwr_limit =
793 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
795 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
797 ci_set_power_limit(adev, default_pwr_limit);
802 if (pi->caps_power_containment && pi->power_containment_features) {
803 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
804 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
806 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
807 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
809 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
810 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
811 pi->power_containment_features = 0;
818 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
820 struct ci_power_info *pi = ci_get_pi(adev);
821 PPSMC_Result smc_result;
826 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
827 if (smc_result != PPSMC_Result_OK) {
829 pi->cac_enabled = false;
831 pi->cac_enabled = true;
833 } else if (pi->cac_enabled) {
834 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
835 pi->cac_enabled = false;
842 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
845 struct ci_power_info *pi = ci_get_pi(adev);
846 PPSMC_Result smc_result = PPSMC_Result_OK;
848 if (pi->thermal_sclk_dpm_enabled) {
850 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
852 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
855 if (smc_result == PPSMC_Result_OK)
861 static int ci_power_control_set_level(struct amdgpu_device *adev)
863 struct ci_power_info *pi = ci_get_pi(adev);
864 struct amdgpu_cac_tdp_table *cac_tdp_table =
865 adev->pm.dpm.dyn_state.cac_tdp_table;
869 bool adjust_polarity = false; /* ??? */
871 if (pi->caps_power_containment) {
872 adjust_percent = adjust_polarity ?
873 adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
874 target_tdp = ((100 + adjust_percent) *
875 (s32)cac_tdp_table->configurable_tdp) / 100;
877 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
883 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
885 struct ci_power_info *pi = ci_get_pi(adev);
887 if (pi->uvd_power_gated == gate)
890 pi->uvd_power_gated = gate;
892 ci_update_uvd_dpm(adev, gate);
895 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
897 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
898 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
900 /* disable mclk switching if the refresh is >120Hz, even if the
901 * blanking period would allow it
903 if (amdgpu_dpm_get_vrefresh(adev) > 120)
906 if (vblank_time < switch_limit)
913 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
914 struct amdgpu_ps *rps)
916 struct ci_ps *ps = ci_get_ps(rps);
917 struct ci_power_info *pi = ci_get_pi(adev);
918 struct amdgpu_clock_and_voltage_limits *max_limits;
919 bool disable_mclk_switching;
923 if (rps->vce_active) {
924 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
925 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
931 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
932 ci_dpm_vblank_too_short(adev))
933 disable_mclk_switching = true;
935 disable_mclk_switching = false;
937 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
938 pi->battery_state = true;
940 pi->battery_state = false;
942 if (adev->pm.dpm.ac_power)
943 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
945 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
947 if (adev->pm.dpm.ac_power == false) {
948 for (i = 0; i < ps->performance_level_count; i++) {
949 if (ps->performance_levels[i].mclk > max_limits->mclk)
950 ps->performance_levels[i].mclk = max_limits->mclk;
951 if (ps->performance_levels[i].sclk > max_limits->sclk)
952 ps->performance_levels[i].sclk = max_limits->sclk;
956 /* XXX validate the min clocks required for display */
958 if (disable_mclk_switching) {
959 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
960 sclk = ps->performance_levels[0].sclk;
962 mclk = ps->performance_levels[0].mclk;
963 sclk = ps->performance_levels[0].sclk;
966 if (rps->vce_active) {
967 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
968 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
969 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
970 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
973 ps->performance_levels[0].sclk = sclk;
974 ps->performance_levels[0].mclk = mclk;
976 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
977 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
979 if (disable_mclk_switching) {
980 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
981 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
983 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
984 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
988 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
989 int min_temp, int max_temp)
991 int low_temp = 0 * 1000;
992 int high_temp = 255 * 1000;
995 if (low_temp < min_temp)
997 if (high_temp > max_temp)
998 high_temp = max_temp;
999 if (high_temp < low_temp) {
1000 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1004 tmp = RREG32_SMC(ixCG_THERMAL_INT);
1005 tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
1006 tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1007 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1008 WREG32_SMC(ixCG_THERMAL_INT, tmp);
1011 /* XXX: need to figure out how to handle this properly */
1012 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1013 tmp &= DIG_THERM_DPM_MASK;
1014 tmp |= DIG_THERM_DPM(high_temp / 1000);
1015 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1018 adev->pm.dpm.thermal.min_temp = low_temp;
1019 adev->pm.dpm.thermal.max_temp = high_temp;
1023 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1026 u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1027 PPSMC_Result result;
1030 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1031 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1032 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1033 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1034 if (result != PPSMC_Result_OK) {
1035 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1039 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1040 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1041 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1042 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1043 if (result != PPSMC_Result_OK) {
1044 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1052 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1054 struct ci_power_info *pi = ci_get_pi(adev);
1057 if (pi->fan_ctrl_is_in_default_mode) {
1058 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1059 >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1060 pi->fan_ctrl_default_mode = tmp;
1061 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1062 >> CG_FDO_CTRL2__TMIN__SHIFT;
1064 pi->fan_ctrl_is_in_default_mode = false;
1067 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1068 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1069 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1071 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1072 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1073 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1076 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1078 struct ci_power_info *pi = ci_get_pi(adev);
1079 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1081 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1082 u16 fdo_min, slope1, slope2;
1083 u32 reference_clock, tmp;
1087 if (!pi->fan_table_start) {
1088 adev->pm.dpm.fan.ucode_fan_control = false;
1092 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1093 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1096 adev->pm.dpm.fan.ucode_fan_control = false;
1100 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1101 do_div(tmp64, 10000);
1102 fdo_min = (u16)tmp64;
1104 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1105 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1107 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1108 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1110 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1111 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1113 fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1114 fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1115 fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1117 fan_table.Slope1 = cpu_to_be16(slope1);
1118 fan_table.Slope2 = cpu_to_be16(slope2);
1120 fan_table.FdoMin = cpu_to_be16(fdo_min);
1122 fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1124 fan_table.HystUp = cpu_to_be16(1);
1126 fan_table.HystSlope = cpu_to_be16(1);
1128 fan_table.TempRespLim = cpu_to_be16(5);
1130 reference_clock = amdgpu_asic_get_xclk(adev);
1132 fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1133 reference_clock) / 1600);
1135 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1137 tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1138 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1139 fan_table.TempSrc = (uint8_t)tmp;
1141 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1142 pi->fan_table_start,
1148 DRM_ERROR("Failed to load fan table to the SMC.");
1149 adev->pm.dpm.fan.ucode_fan_control = false;
1155 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1157 struct ci_power_info *pi = ci_get_pi(adev);
1160 if (pi->caps_od_fuzzy_fan_control_support) {
1161 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1162 PPSMC_StartFanControl,
1164 if (ret != PPSMC_Result_OK)
1166 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1167 PPSMC_MSG_SetFanPwmMax,
1168 adev->pm.dpm.fan.default_max_fan_pwm);
1169 if (ret != PPSMC_Result_OK)
1172 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1173 PPSMC_StartFanControl,
1175 if (ret != PPSMC_Result_OK)
1179 pi->fan_is_controlled_by_smc = true;
1184 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1187 struct ci_power_info *pi = ci_get_pi(adev);
1189 ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1190 if (ret == PPSMC_Result_OK) {
1191 pi->fan_is_controlled_by_smc = false;
1198 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1204 if (adev->pm.no_fan)
1207 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1208 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1209 duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1210 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1215 tmp64 = (u64)duty * 100;
1216 do_div(tmp64, duty100);
1217 *speed = (u32)tmp64;
1225 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1231 struct ci_power_info *pi = ci_get_pi(adev);
1233 if (adev->pm.no_fan)
1236 if (pi->fan_is_controlled_by_smc)
1242 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1243 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1248 tmp64 = (u64)speed * duty100;
1252 tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1253 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1254 WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1259 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1262 /* stop auto-manage */
1263 if (adev->pm.dpm.fan.ucode_fan_control)
1264 ci_fan_ctrl_stop_smc_fan_control(adev);
1265 ci_fan_ctrl_set_static_mode(adev, mode);
1267 /* restart auto-manage */
1268 if (adev->pm.dpm.fan.ucode_fan_control)
1269 ci_thermal_start_smc_fan_control(adev);
1271 ci_fan_ctrl_set_default_mode(adev);
1275 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1277 struct ci_power_info *pi = ci_get_pi(adev);
1280 if (pi->fan_is_controlled_by_smc)
1283 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1284 return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
1288 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1292 u32 xclk = amdgpu_asic_get_xclk(adev);
1294 if (adev->pm.no_fan)
1297 if (adev->pm.fan_pulses_per_revolution == 0)
1300 tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1301 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1302 if (tach_period == 0)
1305 *speed = 60 * xclk * 10000 / tach_period;
1310 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1313 u32 tach_period, tmp;
1314 u32 xclk = amdgpu_asic_get_xclk(adev);
1316 if (adev->pm.no_fan)
1319 if (adev->pm.fan_pulses_per_revolution == 0)
1322 if ((speed < adev->pm.fan_min_rpm) ||
1323 (speed > adev->pm.fan_max_rpm))
1326 if (adev->pm.dpm.fan.ucode_fan_control)
1327 ci_fan_ctrl_stop_smc_fan_control(adev);
1329 tach_period = 60 * xclk * 10000 / (8 * speed);
1330 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1331 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1332 WREG32_SMC(CG_TACH_CTRL, tmp);
1334 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1340 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1342 struct ci_power_info *pi = ci_get_pi(adev);
1345 if (!pi->fan_ctrl_is_in_default_mode) {
1346 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1347 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1348 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1350 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1351 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1352 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1353 pi->fan_ctrl_is_in_default_mode = true;
1357 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1359 if (adev->pm.dpm.fan.ucode_fan_control) {
1360 ci_fan_ctrl_start_smc_fan_control(adev);
1361 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1365 static void ci_thermal_initialize(struct amdgpu_device *adev)
1369 if (adev->pm.fan_pulses_per_revolution) {
1370 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1371 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1372 << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1373 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1376 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1377 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1378 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1381 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1385 ci_thermal_initialize(adev);
1386 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1389 ret = ci_thermal_enable_alert(adev, true);
1392 if (adev->pm.dpm.fan.ucode_fan_control) {
1393 ret = ci_thermal_setup_fan_table(adev);
1396 ci_thermal_start_smc_fan_control(adev);
1402 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1404 if (!adev->pm.no_fan)
1405 ci_fan_ctrl_set_default_mode(adev);
1408 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1409 u16 reg_offset, u32 *value)
1411 struct ci_power_info *pi = ci_get_pi(adev);
1413 return amdgpu_ci_read_smc_sram_dword(adev,
1414 pi->soft_regs_start + reg_offset,
1415 value, pi->sram_end);
1418 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1419 u16 reg_offset, u32 value)
1421 struct ci_power_info *pi = ci_get_pi(adev);
1423 return amdgpu_ci_write_smc_sram_dword(adev,
1424 pi->soft_regs_start + reg_offset,
1425 value, pi->sram_end);
1428 static void ci_init_fps_limits(struct amdgpu_device *adev)
1430 struct ci_power_info *pi = ci_get_pi(adev);
1431 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1437 table->FpsHighT = cpu_to_be16(tmp);
1440 table->FpsLowT = cpu_to_be16(tmp);
1444 static int ci_update_sclk_t(struct amdgpu_device *adev)
1446 struct ci_power_info *pi = ci_get_pi(adev);
1448 u32 low_sclk_interrupt_t = 0;
1450 if (pi->caps_sclk_throttle_low_notification) {
1451 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1453 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1454 pi->dpm_table_start +
1455 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1456 (u8 *)&low_sclk_interrupt_t,
1457 sizeof(u32), pi->sram_end);
1464 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1466 struct ci_power_info *pi = ci_get_pi(adev);
1467 u16 leakage_id, virtual_voltage_id;
1471 pi->vddc_leakage.count = 0;
1472 pi->vddci_leakage.count = 0;
1474 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1475 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1476 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1477 if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1479 if (vddc != 0 && vddc != virtual_voltage_id) {
1480 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1481 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1482 pi->vddc_leakage.count++;
1485 } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1486 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1487 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1488 if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1491 if (vddc != 0 && vddc != virtual_voltage_id) {
1492 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1493 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1494 pi->vddc_leakage.count++;
1496 if (vddci != 0 && vddci != virtual_voltage_id) {
1497 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1498 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1499 pi->vddci_leakage.count++;
1506 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1508 struct ci_power_info *pi = ci_get_pi(adev);
1509 bool want_thermal_protection;
1510 enum amdgpu_dpm_event_src dpm_event_src;
1516 want_thermal_protection = false;
1518 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1519 want_thermal_protection = true;
1520 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1522 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1523 want_thermal_protection = true;
1524 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1526 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1527 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1528 want_thermal_protection = true;
1529 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1533 if (want_thermal_protection) {
1535 /* XXX: need to figure out how to handle this properly */
1536 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1537 tmp &= DPM_EVENT_SRC_MASK;
1538 tmp |= DPM_EVENT_SRC(dpm_event_src);
1539 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1542 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1543 if (pi->thermal_protection)
1544 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1546 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1547 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1549 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1550 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1551 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1555 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1556 enum amdgpu_dpm_auto_throttle_src source,
1559 struct ci_power_info *pi = ci_get_pi(adev);
1562 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1563 pi->active_auto_throttle_sources |= 1 << source;
1564 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1567 if (pi->active_auto_throttle_sources & (1 << source)) {
1568 pi->active_auto_throttle_sources &= ~(1 << source);
1569 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1574 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1576 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1577 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1580 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1582 struct ci_power_info *pi = ci_get_pi(adev);
1583 PPSMC_Result smc_result;
1585 if (!pi->need_update_smu7_dpm_table)
1588 if ((!pi->sclk_dpm_key_disabled) &&
1589 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1590 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1591 if (smc_result != PPSMC_Result_OK)
1595 if ((!pi->mclk_dpm_key_disabled) &&
1596 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1597 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1598 if (smc_result != PPSMC_Result_OK)
1602 pi->need_update_smu7_dpm_table = 0;
1606 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1608 struct ci_power_info *pi = ci_get_pi(adev);
1609 PPSMC_Result smc_result;
1612 if (!pi->sclk_dpm_key_disabled) {
1613 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1614 if (smc_result != PPSMC_Result_OK)
1618 if (!pi->mclk_dpm_key_disabled) {
1619 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1620 if (smc_result != PPSMC_Result_OK)
1623 WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1624 ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1626 WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1627 WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1628 WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1632 WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1633 WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1634 WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1637 if (!pi->sclk_dpm_key_disabled) {
1638 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1639 if (smc_result != PPSMC_Result_OK)
1643 if (!pi->mclk_dpm_key_disabled) {
1644 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1645 if (smc_result != PPSMC_Result_OK)
1653 static int ci_start_dpm(struct amdgpu_device *adev)
1655 struct ci_power_info *pi = ci_get_pi(adev);
1656 PPSMC_Result smc_result;
1660 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1661 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1662 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1664 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1665 tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1666 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1668 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1670 WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1672 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1673 if (smc_result != PPSMC_Result_OK)
1676 ret = ci_enable_sclk_mclk_dpm(adev, true);
1680 if (!pi->pcie_dpm_key_disabled) {
1681 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1682 if (smc_result != PPSMC_Result_OK)
1689 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1691 struct ci_power_info *pi = ci_get_pi(adev);
1692 PPSMC_Result smc_result;
1694 if (!pi->need_update_smu7_dpm_table)
1697 if ((!pi->sclk_dpm_key_disabled) &&
1698 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1699 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1700 if (smc_result != PPSMC_Result_OK)
1704 if ((!pi->mclk_dpm_key_disabled) &&
1705 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1706 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1707 if (smc_result != PPSMC_Result_OK)
1714 static int ci_stop_dpm(struct amdgpu_device *adev)
1716 struct ci_power_info *pi = ci_get_pi(adev);
1717 PPSMC_Result smc_result;
1721 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1722 tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1723 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1725 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1726 tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1727 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1729 if (!pi->pcie_dpm_key_disabled) {
1730 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1731 if (smc_result != PPSMC_Result_OK)
1735 ret = ci_enable_sclk_mclk_dpm(adev, false);
1739 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1740 if (smc_result != PPSMC_Result_OK)
1746 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1748 u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1751 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1753 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1754 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1758 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1761 struct ci_power_info *pi = ci_get_pi(adev);
1762 struct amdgpu_cac_tdp_table *cac_tdp_table =
1763 adev->pm.dpm.dyn_state.cac_tdp_table;
1767 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1769 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1771 ci_set_power_limit(adev, power_limit);
1773 if (pi->caps_automatic_dc_transition) {
1775 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1777 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1784 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1785 PPSMC_Msg msg, u32 parameter)
1787 WREG32(mmSMC_MSG_ARG_0, parameter);
1788 return amdgpu_ci_send_msg_to_smc(adev, msg);
1791 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1792 PPSMC_Msg msg, u32 *parameter)
1794 PPSMC_Result smc_result;
1796 smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1798 if ((smc_result == PPSMC_Result_OK) && parameter)
1799 *parameter = RREG32(mmSMC_MSG_ARG_0);
1804 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1806 struct ci_power_info *pi = ci_get_pi(adev);
1808 if (!pi->sclk_dpm_key_disabled) {
1809 PPSMC_Result smc_result =
1810 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1811 if (smc_result != PPSMC_Result_OK)
1818 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1820 struct ci_power_info *pi = ci_get_pi(adev);
1822 if (!pi->mclk_dpm_key_disabled) {
1823 PPSMC_Result smc_result =
1824 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1825 if (smc_result != PPSMC_Result_OK)
1832 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1834 struct ci_power_info *pi = ci_get_pi(adev);
1836 if (!pi->pcie_dpm_key_disabled) {
1837 PPSMC_Result smc_result =
1838 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1839 if (smc_result != PPSMC_Result_OK)
1846 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1848 struct ci_power_info *pi = ci_get_pi(adev);
1850 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1851 PPSMC_Result smc_result =
1852 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1853 if (smc_result != PPSMC_Result_OK)
1860 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1863 PPSMC_Result smc_result =
1864 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1865 if (smc_result != PPSMC_Result_OK)
1871 static int ci_set_boot_state(struct amdgpu_device *adev)
1873 return ci_enable_sclk_mclk_dpm(adev, false);
1877 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1880 PPSMC_Result smc_result =
1881 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1882 PPSMC_MSG_API_GetSclkFrequency,
1884 if (smc_result != PPSMC_Result_OK)
1890 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1893 PPSMC_Result smc_result =
1894 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1895 PPSMC_MSG_API_GetMclkFrequency,
1897 if (smc_result != PPSMC_Result_OK)
1903 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1907 amdgpu_ci_program_jump_on_start(adev);
1908 amdgpu_ci_start_smc_clock(adev);
1909 amdgpu_ci_start_smc(adev);
1910 for (i = 0; i < adev->usec_timeout; i++) {
1911 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1916 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1918 amdgpu_ci_reset_smc(adev);
1919 amdgpu_ci_stop_smc_clock(adev);
1922 static int ci_process_firmware_header(struct amdgpu_device *adev)
1924 struct ci_power_info *pi = ci_get_pi(adev);
1928 ret = amdgpu_ci_read_smc_sram_dword(adev,
1929 SMU7_FIRMWARE_HEADER_LOCATION +
1930 offsetof(SMU7_Firmware_Header, DpmTable),
1931 &tmp, pi->sram_end);
1935 pi->dpm_table_start = tmp;
1937 ret = amdgpu_ci_read_smc_sram_dword(adev,
1938 SMU7_FIRMWARE_HEADER_LOCATION +
1939 offsetof(SMU7_Firmware_Header, SoftRegisters),
1940 &tmp, pi->sram_end);
1944 pi->soft_regs_start = tmp;
1946 ret = amdgpu_ci_read_smc_sram_dword(adev,
1947 SMU7_FIRMWARE_HEADER_LOCATION +
1948 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1949 &tmp, pi->sram_end);
1953 pi->mc_reg_table_start = tmp;
1955 ret = amdgpu_ci_read_smc_sram_dword(adev,
1956 SMU7_FIRMWARE_HEADER_LOCATION +
1957 offsetof(SMU7_Firmware_Header, FanTable),
1958 &tmp, pi->sram_end);
1962 pi->fan_table_start = tmp;
1964 ret = amdgpu_ci_read_smc_sram_dword(adev,
1965 SMU7_FIRMWARE_HEADER_LOCATION +
1966 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1967 &tmp, pi->sram_end);
1971 pi->arb_table_start = tmp;
1976 static void ci_read_clock_registers(struct amdgpu_device *adev)
1978 struct ci_power_info *pi = ci_get_pi(adev);
1980 pi->clock_registers.cg_spll_func_cntl =
1981 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1982 pi->clock_registers.cg_spll_func_cntl_2 =
1983 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1984 pi->clock_registers.cg_spll_func_cntl_3 =
1985 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
1986 pi->clock_registers.cg_spll_func_cntl_4 =
1987 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
1988 pi->clock_registers.cg_spll_spread_spectrum =
1989 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
1990 pi->clock_registers.cg_spll_spread_spectrum_2 =
1991 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
1992 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
1993 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
1994 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
1995 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
1996 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
1997 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
1998 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
1999 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
2000 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
2003 static void ci_init_sclk_t(struct amdgpu_device *adev)
2005 struct ci_power_info *pi = ci_get_pi(adev);
2007 pi->low_sclk_interrupt_t = 0;
2010 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2013 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2016 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2018 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2019 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2022 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2024 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2026 tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2028 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2032 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2035 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2042 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2046 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2050 for (i = 0; i < adev->usec_timeout; i++) {
2051 if (RREG32(mmSMC_RESP_0) == 1)
2060 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2063 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2065 return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
2068 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2071 struct ci_power_info *pi = ci_get_pi(adev);
2074 if (pi->caps_sclk_ds) {
2075 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2078 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2082 if (pi->caps_sclk_ds) {
2083 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2091 static void ci_program_display_gap(struct amdgpu_device *adev)
2093 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2094 u32 pre_vbi_time_in_us;
2095 u32 frame_time_in_us;
2096 u32 ref_clock = adev->clock.spll.reference_freq;
2097 u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2098 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2100 tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2101 if (adev->pm.dpm.new_active_crtc_count > 0)
2102 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2104 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2105 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2107 if (refresh_rate == 0)
2109 if (vblank_time == 0xffffffff)
2111 frame_time_in_us = 1000000 / refresh_rate;
2112 pre_vbi_time_in_us =
2113 frame_time_in_us - 200 - vblank_time;
2114 tmp = pre_vbi_time_in_us * (ref_clock / 100);
2116 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2117 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2118 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2121 ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2125 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2127 struct ci_power_info *pi = ci_get_pi(adev);
2131 if (pi->caps_sclk_ss_support) {
2132 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2133 tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2134 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2137 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2138 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2139 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2141 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2142 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2143 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2147 static void ci_program_sstp(struct amdgpu_device *adev)
2149 WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2150 ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2151 (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2154 static void ci_enable_display_gap(struct amdgpu_device *adev)
2156 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2158 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2159 CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2160 tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2161 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2163 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2166 static void ci_program_vc(struct amdgpu_device *adev)
2170 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2171 tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2172 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2174 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2175 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2176 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2177 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2178 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2179 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2180 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2181 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2184 static void ci_clear_vc(struct amdgpu_device *adev)
2188 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2189 tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2190 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2192 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2193 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2194 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2195 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2196 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2197 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2198 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2199 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2202 static int ci_upload_firmware(struct amdgpu_device *adev)
2204 struct ci_power_info *pi = ci_get_pi(adev);
2207 for (i = 0; i < adev->usec_timeout; i++) {
2208 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2211 WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2213 amdgpu_ci_stop_smc_clock(adev);
2214 amdgpu_ci_reset_smc(adev);
2216 ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end);
2222 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2223 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2224 struct atom_voltage_table *voltage_table)
2228 if (voltage_dependency_table == NULL)
2231 voltage_table->mask_low = 0;
2232 voltage_table->phase_delay = 0;
2234 voltage_table->count = voltage_dependency_table->count;
2235 for (i = 0; i < voltage_table->count; i++) {
2236 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2237 voltage_table->entries[i].smio_low = 0;
2243 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2245 struct ci_power_info *pi = ci_get_pi(adev);
2248 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2249 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2250 VOLTAGE_OBJ_GPIO_LUT,
2251 &pi->vddc_voltage_table);
2254 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2255 ret = ci_get_svi2_voltage_table(adev,
2256 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2257 &pi->vddc_voltage_table);
2262 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2263 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2264 &pi->vddc_voltage_table);
2266 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2267 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2268 VOLTAGE_OBJ_GPIO_LUT,
2269 &pi->vddci_voltage_table);
2272 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2273 ret = ci_get_svi2_voltage_table(adev,
2274 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2275 &pi->vddci_voltage_table);
2280 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2281 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2282 &pi->vddci_voltage_table);
2284 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2285 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2286 VOLTAGE_OBJ_GPIO_LUT,
2287 &pi->mvdd_voltage_table);
2290 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2291 ret = ci_get_svi2_voltage_table(adev,
2292 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2293 &pi->mvdd_voltage_table);
2298 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2299 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2300 &pi->mvdd_voltage_table);
2305 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2306 struct atom_voltage_table_entry *voltage_table,
2307 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2311 ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2312 &smc_voltage_table->StdVoltageHiSidd,
2313 &smc_voltage_table->StdVoltageLoSidd);
2316 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2317 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2320 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2321 smc_voltage_table->StdVoltageHiSidd =
2322 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2323 smc_voltage_table->StdVoltageLoSidd =
2324 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2327 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2328 SMU7_Discrete_DpmTable *table)
2330 struct ci_power_info *pi = ci_get_pi(adev);
2333 table->VddcLevelCount = pi->vddc_voltage_table.count;
2334 for (count = 0; count < table->VddcLevelCount; count++) {
2335 ci_populate_smc_voltage_table(adev,
2336 &pi->vddc_voltage_table.entries[count],
2337 &table->VddcLevel[count]);
2339 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2340 table->VddcLevel[count].Smio |=
2341 pi->vddc_voltage_table.entries[count].smio_low;
2343 table->VddcLevel[count].Smio = 0;
2345 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2350 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2351 SMU7_Discrete_DpmTable *table)
2354 struct ci_power_info *pi = ci_get_pi(adev);
2356 table->VddciLevelCount = pi->vddci_voltage_table.count;
2357 for (count = 0; count < table->VddciLevelCount; count++) {
2358 ci_populate_smc_voltage_table(adev,
2359 &pi->vddci_voltage_table.entries[count],
2360 &table->VddciLevel[count]);
2362 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2363 table->VddciLevel[count].Smio |=
2364 pi->vddci_voltage_table.entries[count].smio_low;
2366 table->VddciLevel[count].Smio = 0;
2368 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2373 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2374 SMU7_Discrete_DpmTable *table)
2376 struct ci_power_info *pi = ci_get_pi(adev);
2379 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2380 for (count = 0; count < table->MvddLevelCount; count++) {
2381 ci_populate_smc_voltage_table(adev,
2382 &pi->mvdd_voltage_table.entries[count],
2383 &table->MvddLevel[count]);
2385 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2386 table->MvddLevel[count].Smio |=
2387 pi->mvdd_voltage_table.entries[count].smio_low;
2389 table->MvddLevel[count].Smio = 0;
2391 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2396 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2397 SMU7_Discrete_DpmTable *table)
2401 ret = ci_populate_smc_vddc_table(adev, table);
2405 ret = ci_populate_smc_vddci_table(adev, table);
2409 ret = ci_populate_smc_mvdd_table(adev, table);
2416 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2417 SMU7_Discrete_VoltageLevel *voltage)
2419 struct ci_power_info *pi = ci_get_pi(adev);
2422 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2423 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2424 if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2425 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2430 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2437 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2438 struct atom_voltage_table_entry *voltage_table,
2439 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2442 bool voltage_found = false;
2443 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2444 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2446 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2449 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2450 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2451 if (voltage_table->value ==
2452 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2453 voltage_found = true;
2454 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2457 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2458 *std_voltage_lo_sidd =
2459 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2460 *std_voltage_hi_sidd =
2461 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2466 if (!voltage_found) {
2467 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2468 if (voltage_table->value <=
2469 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2470 voltage_found = true;
2471 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2474 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2475 *std_voltage_lo_sidd =
2476 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2477 *std_voltage_hi_sidd =
2478 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2488 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2489 const struct amdgpu_phase_shedding_limits_table *limits,
2491 u32 *phase_shedding)
2495 *phase_shedding = 1;
2497 for (i = 0; i < limits->count; i++) {
2498 if (sclk < limits->entries[i].sclk) {
2499 *phase_shedding = i;
2505 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2506 const struct amdgpu_phase_shedding_limits_table *limits,
2508 u32 *phase_shedding)
2512 *phase_shedding = 1;
2514 for (i = 0; i < limits->count; i++) {
2515 if (mclk < limits->entries[i].mclk) {
2516 *phase_shedding = i;
2522 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2524 struct ci_power_info *pi = ci_get_pi(adev);
2528 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2529 &tmp, pi->sram_end);
2534 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2536 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2540 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2541 struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2542 u32 clock, u32 *voltage)
2546 if (allowed_clock_voltage_table->count == 0)
2549 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2550 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2551 *voltage = allowed_clock_voltage_table->entries[i].v;
2556 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2561 static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2565 u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2570 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2572 if (tmp >= min || i == 0)
2579 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2581 return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2584 static int ci_reset_to_default(struct amdgpu_device *adev)
2586 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2590 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2594 tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2596 if (tmp == MC_CG_ARB_FREQ_F0)
2599 return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2602 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2603 const u32 engine_clock,
2604 const u32 memory_clock,
2610 tmp = RREG32(mmMC_SEQ_MISC0);
2611 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2614 ((adev->pdev->device == 0x67B0) ||
2615 (adev->pdev->device == 0x67B1))) {
2616 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2617 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2618 *dram_timimg2 &= ~0x00ff0000;
2619 *dram_timimg2 |= tmp2 << 16;
2620 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2621 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2622 *dram_timimg2 &= ~0x00ff0000;
2623 *dram_timimg2 |= tmp2 << 16;
2628 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2631 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2637 amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2639 dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
2640 dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2641 burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2643 ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2645 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2646 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2647 arb_regs->McArbBurstTime = (u8)burst_time;
2652 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2654 struct ci_power_info *pi = ci_get_pi(adev);
2655 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2659 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2661 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2662 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2663 ret = ci_populate_memory_timing_parameters(adev,
2664 pi->dpm_table.sclk_table.dpm_levels[i].value,
2665 pi->dpm_table.mclk_table.dpm_levels[j].value,
2666 &arb_regs.entries[i][j]);
2673 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2674 pi->arb_table_start,
2676 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2682 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2684 struct ci_power_info *pi = ci_get_pi(adev);
2686 if (pi->need_update_smu7_dpm_table == 0)
2689 return ci_do_program_memory_timing_parameters(adev);
2692 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2693 struct amdgpu_ps *amdgpu_boot_state)
2695 struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2696 struct ci_power_info *pi = ci_get_pi(adev);
2699 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2700 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2701 boot_state->performance_levels[0].sclk) {
2702 pi->smc_state_table.GraphicsBootLevel = level;
2707 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2708 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2709 boot_state->performance_levels[0].mclk) {
2710 pi->smc_state_table.MemoryBootLevel = level;
2716 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2721 for (i = dpm_table->count; i > 0; i--) {
2722 mask_value = mask_value << 1;
2723 if (dpm_table->dpm_levels[i-1].enabled)
2726 mask_value &= 0xFFFFFFFE;
2732 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2733 SMU7_Discrete_DpmTable *table)
2735 struct ci_power_info *pi = ci_get_pi(adev);
2736 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2739 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2740 table->LinkLevel[i].PcieGenSpeed =
2741 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2742 table->LinkLevel[i].PcieLaneCount =
2743 amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2744 table->LinkLevel[i].EnabledForActivity = 1;
2745 table->LinkLevel[i].DownT = cpu_to_be32(5);
2746 table->LinkLevel[i].UpT = cpu_to_be32(30);
2749 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2750 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2751 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2754 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2755 SMU7_Discrete_DpmTable *table)
2758 struct atom_clock_dividers dividers;
2761 table->UvdLevelCount =
2762 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2764 for (count = 0; count < table->UvdLevelCount; count++) {
2765 table->UvdLevel[count].VclkFrequency =
2766 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2767 table->UvdLevel[count].DclkFrequency =
2768 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2769 table->UvdLevel[count].MinVddc =
2770 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2771 table->UvdLevel[count].MinVddcPhases = 1;
2773 ret = amdgpu_atombios_get_clock_dividers(adev,
2774 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2775 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2779 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2781 ret = amdgpu_atombios_get_clock_dividers(adev,
2782 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2783 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2787 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2789 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2790 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2791 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2797 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2798 SMU7_Discrete_DpmTable *table)
2801 struct atom_clock_dividers dividers;
2804 table->VceLevelCount =
2805 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2807 for (count = 0; count < table->VceLevelCount; count++) {
2808 table->VceLevel[count].Frequency =
2809 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2810 table->VceLevel[count].MinVoltage =
2811 (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2812 table->VceLevel[count].MinPhases = 1;
2814 ret = amdgpu_atombios_get_clock_dividers(adev,
2815 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2816 table->VceLevel[count].Frequency, false, ÷rs);
2820 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2822 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2823 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2830 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2831 SMU7_Discrete_DpmTable *table)
2834 struct atom_clock_dividers dividers;
2837 table->AcpLevelCount = (u8)
2838 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2840 for (count = 0; count < table->AcpLevelCount; count++) {
2841 table->AcpLevel[count].Frequency =
2842 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2843 table->AcpLevel[count].MinVoltage =
2844 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2845 table->AcpLevel[count].MinPhases = 1;
2847 ret = amdgpu_atombios_get_clock_dividers(adev,
2848 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2849 table->AcpLevel[count].Frequency, false, ÷rs);
2853 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2855 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2856 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2862 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2863 SMU7_Discrete_DpmTable *table)
2866 struct atom_clock_dividers dividers;
2869 table->SamuLevelCount =
2870 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2872 for (count = 0; count < table->SamuLevelCount; count++) {
2873 table->SamuLevel[count].Frequency =
2874 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2875 table->SamuLevel[count].MinVoltage =
2876 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2877 table->SamuLevel[count].MinPhases = 1;
2879 ret = amdgpu_atombios_get_clock_dividers(adev,
2880 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2881 table->SamuLevel[count].Frequency, false, ÷rs);
2885 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2887 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2888 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2894 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2896 SMU7_Discrete_MemoryLevel *mclk,
2900 struct ci_power_info *pi = ci_get_pi(adev);
2901 u32 dll_cntl = pi->clock_registers.dll_cntl;
2902 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2903 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2904 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2905 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2906 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2907 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2908 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2909 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2910 struct atom_mpll_param mpll_param;
2913 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2917 mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2918 mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2920 mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2921 MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2922 mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2923 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2924 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2926 mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2927 mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2929 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2930 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2931 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2932 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2933 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2936 if (pi->caps_mclk_ss_support) {
2937 struct amdgpu_atom_ss ss;
2940 u32 reference_clock = adev->clock.mpll.reference_freq;
2942 if (mpll_param.qdr == 1)
2943 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2945 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2947 tmp = (freq_nom / reference_clock);
2949 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2950 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2951 u32 clks = reference_clock * 5 / ss.rate;
2952 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2954 mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2955 mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2957 mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2958 mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2962 mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2963 mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2966 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2967 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2969 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2970 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2972 mclk->MclkFrequency = memory_clock;
2973 mclk->MpllFuncCntl = mpll_func_cntl;
2974 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2975 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2976 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2977 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2978 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2979 mclk->DllCntl = dll_cntl;
2980 mclk->MpllSs1 = mpll_ss1;
2981 mclk->MpllSs2 = mpll_ss2;
2986 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
2988 SMU7_Discrete_MemoryLevel *memory_level)
2990 struct ci_power_info *pi = ci_get_pi(adev);
2994 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2995 ret = ci_get_dependency_volt_by_clk(adev,
2996 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2997 memory_clock, &memory_level->MinVddc);
3002 if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
3003 ret = ci_get_dependency_volt_by_clk(adev,
3004 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3005 memory_clock, &memory_level->MinVddci);
3010 if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3011 ret = ci_get_dependency_volt_by_clk(adev,
3012 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3013 memory_clock, &memory_level->MinMvdd);
3018 memory_level->MinVddcPhases = 1;
3020 if (pi->vddc_phase_shed_control)
3021 ci_populate_phase_value_based_on_mclk(adev,
3022 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3024 &memory_level->MinVddcPhases);
3026 memory_level->EnabledForThrottle = 1;
3027 memory_level->UpH = 0;
3028 memory_level->DownH = 100;
3029 memory_level->VoltageDownH = 0;
3030 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3032 memory_level->StutterEnable = false;
3033 memory_level->StrobeEnable = false;
3034 memory_level->EdcReadEnable = false;
3035 memory_level->EdcWriteEnable = false;
3036 memory_level->RttEnable = false;
3038 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3040 if (pi->mclk_stutter_mode_threshold &&
3041 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3042 (!pi->uvd_enabled) &&
3043 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3044 (adev->pm.dpm.new_active_crtc_count <= 2))
3045 memory_level->StutterEnable = true;
3047 if (pi->mclk_strobe_mode_threshold &&
3048 (memory_clock <= pi->mclk_strobe_mode_threshold))
3049 memory_level->StrobeEnable = 1;
3051 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3052 memory_level->StrobeRatio =
3053 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3054 if (pi->mclk_edc_enable_threshold &&
3055 (memory_clock > pi->mclk_edc_enable_threshold))
3056 memory_level->EdcReadEnable = true;
3058 if (pi->mclk_edc_wr_enable_threshold &&
3059 (memory_clock > pi->mclk_edc_wr_enable_threshold))
3060 memory_level->EdcWriteEnable = true;
3062 if (memory_level->StrobeEnable) {
3063 if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3064 ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3065 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3067 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3069 dll_state_on = pi->dll_default_on;
3072 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3073 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3076 ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3080 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3081 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3082 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3083 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3085 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3086 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3087 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3088 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3089 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3090 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3091 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3092 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3093 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3094 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3095 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3100 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3101 SMU7_Discrete_DpmTable *table)
3103 struct ci_power_info *pi = ci_get_pi(adev);
3104 struct atom_clock_dividers dividers;
3105 SMU7_Discrete_VoltageLevel voltage_level;
3106 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3107 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3108 u32 dll_cntl = pi->clock_registers.dll_cntl;
3109 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3112 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3115 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3117 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3119 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3121 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3123 ret = amdgpu_atombios_get_clock_dividers(adev,
3124 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3125 table->ACPILevel.SclkFrequency, false, ÷rs);
3129 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3130 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3131 table->ACPILevel.DeepSleepDivId = 0;
3133 spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3134 spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3136 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3137 spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3139 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3140 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3141 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3142 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3143 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3144 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3145 table->ACPILevel.CcPwrDynRm = 0;
3146 table->ACPILevel.CcPwrDynRm1 = 0;
3148 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3149 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3150 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3151 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3152 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3153 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3154 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3155 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3156 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3157 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3158 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3160 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3161 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3163 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3165 table->MemoryACPILevel.MinVddci =
3166 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3168 table->MemoryACPILevel.MinVddci =
3169 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3172 if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3173 table->MemoryACPILevel.MinMvdd = 0;
3175 table->MemoryACPILevel.MinMvdd =
3176 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3178 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3179 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3180 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3181 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3183 dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3185 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3186 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3187 table->MemoryACPILevel.MpllAdFuncCntl =
3188 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3189 table->MemoryACPILevel.MpllDqFuncCntl =
3190 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3191 table->MemoryACPILevel.MpllFuncCntl =
3192 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3193 table->MemoryACPILevel.MpllFuncCntl_1 =
3194 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3195 table->MemoryACPILevel.MpllFuncCntl_2 =
3196 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3197 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3198 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3200 table->MemoryACPILevel.EnabledForThrottle = 0;
3201 table->MemoryACPILevel.EnabledForActivity = 0;
3202 table->MemoryACPILevel.UpH = 0;
3203 table->MemoryACPILevel.DownH = 100;
3204 table->MemoryACPILevel.VoltageDownH = 0;
3205 table->MemoryACPILevel.ActivityLevel =
3206 cpu_to_be16((u16)pi->mclk_activity_target);
3208 table->MemoryACPILevel.StutterEnable = false;
3209 table->MemoryACPILevel.StrobeEnable = false;
3210 table->MemoryACPILevel.EdcReadEnable = false;
3211 table->MemoryACPILevel.EdcWriteEnable = false;
3212 table->MemoryACPILevel.RttEnable = false;
3218 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3220 struct ci_power_info *pi = ci_get_pi(adev);
3221 struct ci_ulv_parm *ulv = &pi->ulv;
3223 if (ulv->supported) {
3225 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3228 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3235 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3236 SMU7_Discrete_Ulv *state)
3238 struct ci_power_info *pi = ci_get_pi(adev);
3239 u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3241 state->CcPwrDynRm = 0;
3242 state->CcPwrDynRm1 = 0;
3244 if (ulv_voltage == 0) {
3245 pi->ulv.supported = false;
3249 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3250 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3251 state->VddcOffset = 0;
3254 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3256 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3257 state->VddcOffsetVid = 0;
3259 state->VddcOffsetVid = (u8)
3260 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3261 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3263 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3265 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3266 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3267 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3272 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3274 SMU7_Discrete_GraphicsLevel *sclk)
3276 struct ci_power_info *pi = ci_get_pi(adev);
3277 struct atom_clock_dividers dividers;
3278 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3279 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3280 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3281 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3282 u32 reference_clock = adev->clock.spll.reference_freq;
3283 u32 reference_divider;
3287 ret = amdgpu_atombios_get_clock_dividers(adev,
3288 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3289 engine_clock, false, ÷rs);
3293 reference_divider = 1 + dividers.ref_div;
3294 fbdiv = dividers.fb_div & 0x3FFFFFF;
3296 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3297 spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3298 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3300 if (pi->caps_sclk_ss_support) {
3301 struct amdgpu_atom_ss ss;
3302 u32 vco_freq = engine_clock * dividers.post_div;
3304 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3305 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3306 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3307 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3309 cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3310 cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3311 cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3313 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3314 cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3318 sclk->SclkFrequency = engine_clock;
3319 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3320 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3321 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3322 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3323 sclk->SclkDid = (u8)dividers.post_divider;
3328 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3330 u16 sclk_activity_level_t,
3331 SMU7_Discrete_GraphicsLevel *graphic_level)
3333 struct ci_power_info *pi = ci_get_pi(adev);
3336 ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3340 ret = ci_get_dependency_volt_by_clk(adev,
3341 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3342 engine_clock, &graphic_level->MinVddc);
3346 graphic_level->SclkFrequency = engine_clock;
3348 graphic_level->Flags = 0;
3349 graphic_level->MinVddcPhases = 1;
3351 if (pi->vddc_phase_shed_control)
3352 ci_populate_phase_value_based_on_sclk(adev,
3353 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3355 &graphic_level->MinVddcPhases);
3357 graphic_level->ActivityLevel = sclk_activity_level_t;
3359 graphic_level->CcPwrDynRm = 0;
3360 graphic_level->CcPwrDynRm1 = 0;
3361 graphic_level->EnabledForThrottle = 1;
3362 graphic_level->UpH = 0;
3363 graphic_level->DownH = 0;
3364 graphic_level->VoltageDownH = 0;
3365 graphic_level->PowerThrottle = 0;
3367 if (pi->caps_sclk_ds)
3368 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
3369 CISLAND_MINIMUM_ENGINE_CLOCK);
3371 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3373 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3374 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3375 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3376 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3377 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3378 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3379 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3380 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3381 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3382 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3383 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3388 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3390 struct ci_power_info *pi = ci_get_pi(adev);
3391 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3392 u32 level_array_address = pi->dpm_table_start +
3393 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3394 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3395 SMU7_MAX_LEVELS_GRAPHICS;
3396 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3399 memset(levels, 0, level_array_size);
3401 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3402 ret = ci_populate_single_graphic_level(adev,
3403 dpm_table->sclk_table.dpm_levels[i].value,
3404 (u16)pi->activity_target[i],
3405 &pi->smc_state_table.GraphicsLevel[i]);
3409 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3410 if (i == (dpm_table->sclk_table.count - 1))
3411 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3412 PPSMC_DISPLAY_WATERMARK_HIGH;
3414 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3416 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3417 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3418 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3420 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3421 (u8 *)levels, level_array_size,
3429 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3430 SMU7_Discrete_Ulv *ulv_level)
3432 return ci_populate_ulv_level(adev, ulv_level);
3435 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3437 struct ci_power_info *pi = ci_get_pi(adev);
3438 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3439 u32 level_array_address = pi->dpm_table_start +
3440 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3441 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3442 SMU7_MAX_LEVELS_MEMORY;
3443 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3446 memset(levels, 0, level_array_size);
3448 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3449 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3451 ret = ci_populate_single_memory_level(adev,
3452 dpm_table->mclk_table.dpm_levels[i].value,
3453 &pi->smc_state_table.MemoryLevel[i]);
3458 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3460 if ((dpm_table->mclk_table.count >= 2) &&
3461 ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3462 pi->smc_state_table.MemoryLevel[1].MinVddc =
3463 pi->smc_state_table.MemoryLevel[0].MinVddc;
3464 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3465 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3468 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3470 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3471 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3472 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3474 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3475 PPSMC_DISPLAY_WATERMARK_HIGH;
3477 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3478 (u8 *)levels, level_array_size,
3486 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3487 struct ci_single_dpm_table* dpm_table,
3492 dpm_table->count = count;
3493 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3494 dpm_table->dpm_levels[i].enabled = false;
3497 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3498 u32 index, u32 pcie_gen, u32 pcie_lanes)
3500 dpm_table->dpm_levels[index].value = pcie_gen;
3501 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3502 dpm_table->dpm_levels[index].enabled = true;
3505 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3507 struct ci_power_info *pi = ci_get_pi(adev);
3509 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3512 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3513 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3514 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3515 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3516 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3517 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3520 ci_reset_single_dpm_table(adev,
3521 &pi->dpm_table.pcie_speed_table,
3522 SMU7_MAX_LEVELS_LINK);
3524 if (adev->asic_type == CHIP_BONAIRE)
3525 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3526 pi->pcie_gen_powersaving.min,
3527 pi->pcie_lane_powersaving.max);
3529 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3530 pi->pcie_gen_powersaving.min,
3531 pi->pcie_lane_powersaving.min);
3532 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3533 pi->pcie_gen_performance.min,
3534 pi->pcie_lane_performance.min);
3535 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3536 pi->pcie_gen_powersaving.min,
3537 pi->pcie_lane_powersaving.max);
3538 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3539 pi->pcie_gen_performance.min,
3540 pi->pcie_lane_performance.max);
3541 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3542 pi->pcie_gen_powersaving.max,
3543 pi->pcie_lane_powersaving.max);
3544 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3545 pi->pcie_gen_performance.max,
3546 pi->pcie_lane_performance.max);
3548 pi->dpm_table.pcie_speed_table.count = 6;
3553 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3555 struct ci_power_info *pi = ci_get_pi(adev);
3556 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3557 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3558 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3559 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3560 struct amdgpu_cac_leakage_table *std_voltage_table =
3561 &adev->pm.dpm.dyn_state.cac_leakage_table;
3564 if (allowed_sclk_vddc_table == NULL)
3566 if (allowed_sclk_vddc_table->count < 1)
3568 if (allowed_mclk_table == NULL)
3570 if (allowed_mclk_table->count < 1)
3573 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3575 ci_reset_single_dpm_table(adev,
3576 &pi->dpm_table.sclk_table,
3577 SMU7_MAX_LEVELS_GRAPHICS);
3578 ci_reset_single_dpm_table(adev,
3579 &pi->dpm_table.mclk_table,
3580 SMU7_MAX_LEVELS_MEMORY);
3581 ci_reset_single_dpm_table(adev,
3582 &pi->dpm_table.vddc_table,
3583 SMU7_MAX_LEVELS_VDDC);
3584 ci_reset_single_dpm_table(adev,
3585 &pi->dpm_table.vddci_table,
3586 SMU7_MAX_LEVELS_VDDCI);
3587 ci_reset_single_dpm_table(adev,
3588 &pi->dpm_table.mvdd_table,
3589 SMU7_MAX_LEVELS_MVDD);
3591 pi->dpm_table.sclk_table.count = 0;
3592 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3594 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3595 allowed_sclk_vddc_table->entries[i].clk)) {
3596 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3597 allowed_sclk_vddc_table->entries[i].clk;
3598 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3599 (i == 0) ? true : false;
3600 pi->dpm_table.sclk_table.count++;
3604 pi->dpm_table.mclk_table.count = 0;
3605 for (i = 0; i < allowed_mclk_table->count; i++) {
3607 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3608 allowed_mclk_table->entries[i].clk)) {
3609 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3610 allowed_mclk_table->entries[i].clk;
3611 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3612 (i == 0) ? true : false;
3613 pi->dpm_table.mclk_table.count++;
3617 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3618 pi->dpm_table.vddc_table.dpm_levels[i].value =
3619 allowed_sclk_vddc_table->entries[i].v;
3620 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3621 std_voltage_table->entries[i].leakage;
3622 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3624 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3626 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3627 if (allowed_mclk_table) {
3628 for (i = 0; i < allowed_mclk_table->count; i++) {
3629 pi->dpm_table.vddci_table.dpm_levels[i].value =
3630 allowed_mclk_table->entries[i].v;
3631 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3633 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3636 allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3637 if (allowed_mclk_table) {
3638 for (i = 0; i < allowed_mclk_table->count; i++) {
3639 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3640 allowed_mclk_table->entries[i].v;
3641 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3643 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3646 ci_setup_default_pcie_tables(adev);
3648 /* save a copy of the default DPM table */
3649 memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),
3650 sizeof(struct ci_dpm_table));
3655 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3656 u32 value, u32 *boot_level)
3661 for(i = 0; i < table->count; i++) {
3662 if (value == table->dpm_levels[i].value) {
3671 static int ci_init_smc_table(struct amdgpu_device *adev)
3673 struct ci_power_info *pi = ci_get_pi(adev);
3674 struct ci_ulv_parm *ulv = &pi->ulv;
3675 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3676 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3679 ret = ci_setup_default_dpm_tables(adev);
3683 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3684 ci_populate_smc_voltage_tables(adev, table);
3686 ci_init_fps_limits(adev);
3688 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3689 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3691 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3692 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3694 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3695 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3697 if (ulv->supported) {
3698 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3701 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3704 ret = ci_populate_all_graphic_levels(adev);
3708 ret = ci_populate_all_memory_levels(adev);
3712 ci_populate_smc_link_level(adev, table);
3714 ret = ci_populate_smc_acpi_level(adev, table);
3718 ret = ci_populate_smc_vce_level(adev, table);
3722 ret = ci_populate_smc_acp_level(adev, table);
3726 ret = ci_populate_smc_samu_level(adev, table);
3730 ret = ci_do_program_memory_timing_parameters(adev);
3734 ret = ci_populate_smc_uvd_level(adev, table);
3738 table->UvdBootLevel = 0;
3739 table->VceBootLevel = 0;
3740 table->AcpBootLevel = 0;
3741 table->SamuBootLevel = 0;
3742 table->GraphicsBootLevel = 0;
3743 table->MemoryBootLevel = 0;
3745 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3746 pi->vbios_boot_state.sclk_bootup_value,
3747 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3749 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3750 pi->vbios_boot_state.mclk_bootup_value,
3751 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3753 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3754 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3755 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3757 ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3759 ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3763 table->UVDInterval = 1;
3764 table->VCEInterval = 1;
3765 table->ACPInterval = 1;
3766 table->SAMUInterval = 1;
3767 table->GraphicsVoltageChangeEnable = 1;
3768 table->GraphicsThermThrottleEnable = 1;
3769 table->GraphicsInterval = 1;
3770 table->VoltageInterval = 1;
3771 table->ThermalInterval = 1;
3772 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3773 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3774 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3775 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3776 table->MemoryVoltageChangeEnable = 1;
3777 table->MemoryInterval = 1;
3778 table->VoltageResponseTime = 0;
3779 table->VddcVddciDelta = 4000;
3780 table->PhaseResponseTime = 0;
3781 table->MemoryThermThrottleEnable = 1;
3782 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3783 table->PCIeGenInterval = 1;
3784 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3785 table->SVI2Enable = 1;
3787 table->SVI2Enable = 0;
3789 table->ThermGpio = 17;
3790 table->SclkStepSize = 0x4000;
3792 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3793 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3794 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3795 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3796 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3797 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3798 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3799 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3800 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3801 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3802 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3803 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3804 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3805 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3807 ret = amdgpu_ci_copy_bytes_to_smc(adev,
3808 pi->dpm_table_start +
3809 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3810 (u8 *)&table->SystemFlags,
3811 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3819 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3820 struct ci_single_dpm_table *dpm_table,
3821 u32 low_limit, u32 high_limit)
3825 for (i = 0; i < dpm_table->count; i++) {
3826 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3827 (dpm_table->dpm_levels[i].value > high_limit))
3828 dpm_table->dpm_levels[i].enabled = false;
3830 dpm_table->dpm_levels[i].enabled = true;
3834 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3835 u32 speed_low, u32 lanes_low,
3836 u32 speed_high, u32 lanes_high)
3838 struct ci_power_info *pi = ci_get_pi(adev);
3839 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3842 for (i = 0; i < pcie_table->count; i++) {
3843 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3844 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3845 (pcie_table->dpm_levels[i].value > speed_high) ||
3846 (pcie_table->dpm_levels[i].param1 > lanes_high))
3847 pcie_table->dpm_levels[i].enabled = false;
3849 pcie_table->dpm_levels[i].enabled = true;
3852 for (i = 0; i < pcie_table->count; i++) {
3853 if (pcie_table->dpm_levels[i].enabled) {
3854 for (j = i + 1; j < pcie_table->count; j++) {
3855 if (pcie_table->dpm_levels[j].enabled) {
3856 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3857 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3858 pcie_table->dpm_levels[j].enabled = false;
3865 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3866 struct amdgpu_ps *amdgpu_state)
3868 struct ci_ps *state = ci_get_ps(amdgpu_state);
3869 struct ci_power_info *pi = ci_get_pi(adev);
3870 u32 high_limit_count;
3872 if (state->performance_level_count < 1)
3875 if (state->performance_level_count == 1)
3876 high_limit_count = 0;
3878 high_limit_count = 1;
3880 ci_trim_single_dpm_states(adev,
3881 &pi->dpm_table.sclk_table,
3882 state->performance_levels[0].sclk,
3883 state->performance_levels[high_limit_count].sclk);
3885 ci_trim_single_dpm_states(adev,
3886 &pi->dpm_table.mclk_table,
3887 state->performance_levels[0].mclk,
3888 state->performance_levels[high_limit_count].mclk);
3890 ci_trim_pcie_dpm_states(adev,
3891 state->performance_levels[0].pcie_gen,
3892 state->performance_levels[0].pcie_lane,
3893 state->performance_levels[high_limit_count].pcie_gen,
3894 state->performance_levels[high_limit_count].pcie_lane);
3899 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3901 struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3902 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3903 struct amdgpu_clock_voltage_dependency_table *vddc_table =
3904 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3905 u32 requested_voltage = 0;
3908 if (disp_voltage_table == NULL)
3910 if (!disp_voltage_table->count)
3913 for (i = 0; i < disp_voltage_table->count; i++) {
3914 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3915 requested_voltage = disp_voltage_table->entries[i].v;
3918 for (i = 0; i < vddc_table->count; i++) {
3919 if (requested_voltage <= vddc_table->entries[i].v) {
3920 requested_voltage = vddc_table->entries[i].v;
3921 return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3922 PPSMC_MSG_VddC_Request,
3923 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3931 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3933 struct ci_power_info *pi = ci_get_pi(adev);
3934 PPSMC_Result result;
3936 ci_apply_disp_minimum_voltage_request(adev);
3938 if (!pi->sclk_dpm_key_disabled) {
3939 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3940 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3941 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3942 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3943 if (result != PPSMC_Result_OK)
3948 if (!pi->mclk_dpm_key_disabled) {
3949 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3950 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3951 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3952 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3953 if (result != PPSMC_Result_OK)
3959 if (!pi->pcie_dpm_key_disabled) {
3960 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3961 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3962 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3963 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3964 if (result != PPSMC_Result_OK)
3973 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
3974 struct amdgpu_ps *amdgpu_state)
3976 struct ci_power_info *pi = ci_get_pi(adev);
3977 struct ci_ps *state = ci_get_ps(amdgpu_state);
3978 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3979 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3980 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3981 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3984 pi->need_update_smu7_dpm_table = 0;
3986 for (i = 0; i < sclk_table->count; i++) {
3987 if (sclk == sclk_table->dpm_levels[i].value)
3991 if (i >= sclk_table->count) {
3992 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3994 /* XXX check display min clock requirements */
3995 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3996 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3999 for (i = 0; i < mclk_table->count; i++) {
4000 if (mclk == mclk_table->dpm_levels[i].value)
4004 if (i >= mclk_table->count)
4005 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4007 if (adev->pm.dpm.current_active_crtc_count !=
4008 adev->pm.dpm.new_active_crtc_count)
4009 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4012 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4013 struct amdgpu_ps *amdgpu_state)
4015 struct ci_power_info *pi = ci_get_pi(adev);
4016 struct ci_ps *state = ci_get_ps(amdgpu_state);
4017 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4018 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4019 struct ci_dpm_table *dpm_table = &pi->dpm_table;
4022 if (!pi->need_update_smu7_dpm_table)
4025 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4026 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4028 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4029 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4031 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4032 ret = ci_populate_all_graphic_levels(adev);
4037 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4038 ret = ci_populate_all_memory_levels(adev);
4046 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4048 struct ci_power_info *pi = ci_get_pi(adev);
4049 const struct amdgpu_clock_and_voltage_limits *max_limits;
4052 if (adev->pm.dpm.ac_power)
4053 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4055 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4058 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4060 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4061 if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4062 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4064 if (!pi->caps_uvd_dpm)
4069 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4070 PPSMC_MSG_UVDDPM_SetEnabledMask,
4071 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4073 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4074 pi->uvd_enabled = true;
4075 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4076 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4077 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4078 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4081 if (pi->uvd_enabled) {
4082 pi->uvd_enabled = false;
4083 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4084 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4085 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4086 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4090 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4091 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4095 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4097 struct ci_power_info *pi = ci_get_pi(adev);
4098 const struct amdgpu_clock_and_voltage_limits *max_limits;
4101 if (adev->pm.dpm.ac_power)
4102 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4104 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4107 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4108 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4109 if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4110 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4112 if (!pi->caps_vce_dpm)
4117 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4118 PPSMC_MSG_VCEDPM_SetEnabledMask,
4119 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4122 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4123 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4128 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4130 struct ci_power_info *pi = ci_get_pi(adev);
4131 const struct amdgpu_clock_and_voltage_limits *max_limits;
4134 if (adev->pm.dpm.ac_power)
4135 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4137 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4140 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4141 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4142 if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4143 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4145 if (!pi->caps_samu_dpm)
4150 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4151 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4152 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4154 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4155 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4159 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4161 struct ci_power_info *pi = ci_get_pi(adev);
4162 const struct amdgpu_clock_and_voltage_limits *max_limits;
4165 if (adev->pm.dpm.ac_power)
4166 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4168 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4171 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4172 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4173 if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4174 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4176 if (!pi->caps_acp_dpm)
4181 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4182 PPSMC_MSG_ACPDPM_SetEnabledMask,
4183 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4186 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4187 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4192 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4194 struct ci_power_info *pi = ci_get_pi(adev);
4198 if (pi->caps_uvd_dpm ||
4199 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4200 pi->smc_state_table.UvdBootLevel = 0;
4202 pi->smc_state_table.UvdBootLevel =
4203 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4205 tmp = RREG32_SMC(ixDPM_TABLE_475);
4206 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4207 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4208 WREG32_SMC(ixDPM_TABLE_475, tmp);
4211 return ci_enable_uvd_dpm(adev, !gate);
4214 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4217 u32 min_evclk = 30000; /* ??? */
4218 struct amdgpu_vce_clock_voltage_dependency_table *table =
4219 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4221 for (i = 0; i < table->count; i++) {
4222 if (table->entries[i].evclk >= min_evclk)
4226 return table->count - 1;
4229 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4230 struct amdgpu_ps *amdgpu_new_state,
4231 struct amdgpu_ps *amdgpu_current_state)
4233 struct ci_power_info *pi = ci_get_pi(adev);
4237 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4238 if (amdgpu_new_state->evclk) {
4239 /* turn the clocks on when encoding */
4240 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4241 AMD_CG_STATE_UNGATE);
4245 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4246 tmp = RREG32_SMC(ixDPM_TABLE_475);
4247 tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4248 tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4249 WREG32_SMC(ixDPM_TABLE_475, tmp);
4251 ret = ci_enable_vce_dpm(adev, true);
4253 /* turn the clocks off when not encoding */
4254 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4259 ret = ci_enable_vce_dpm(adev, false);
4266 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4268 return ci_enable_samu_dpm(adev, gate);
4271 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4273 struct ci_power_info *pi = ci_get_pi(adev);
4277 pi->smc_state_table.AcpBootLevel = 0;
4279 tmp = RREG32_SMC(ixDPM_TABLE_475);
4280 tmp &= ~AcpBootLevel_MASK;
4281 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4282 WREG32_SMC(ixDPM_TABLE_475, tmp);
4285 return ci_enable_acp_dpm(adev, !gate);
4289 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4290 struct amdgpu_ps *amdgpu_state)
4292 struct ci_power_info *pi = ci_get_pi(adev);
4295 ret = ci_trim_dpm_states(adev, amdgpu_state);
4299 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4300 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4301 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4302 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4303 pi->last_mclk_dpm_enable_mask =
4304 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4305 if (pi->uvd_enabled) {
4306 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4307 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4309 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4310 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4315 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4320 while ((level_mask & (1 << level)) == 0)
4327 static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4328 enum amdgpu_dpm_forced_level level)
4330 struct ci_power_info *pi = ci_get_pi(adev);
4334 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
4335 if ((!pi->pcie_dpm_key_disabled) &&
4336 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4338 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4342 ret = ci_dpm_force_state_pcie(adev, level);
4345 for (i = 0; i < adev->usec_timeout; i++) {
4346 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4347 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4348 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4355 if ((!pi->sclk_dpm_key_disabled) &&
4356 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4358 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4362 ret = ci_dpm_force_state_sclk(adev, levels);
4365 for (i = 0; i < adev->usec_timeout; i++) {
4366 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4367 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4368 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4375 if ((!pi->mclk_dpm_key_disabled) &&
4376 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4378 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4382 ret = ci_dpm_force_state_mclk(adev, levels);
4385 for (i = 0; i < adev->usec_timeout; i++) {
4386 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4387 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4388 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4395 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
4396 if ((!pi->sclk_dpm_key_disabled) &&
4397 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4398 levels = ci_get_lowest_enabled_level(adev,
4399 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4400 ret = ci_dpm_force_state_sclk(adev, levels);
4403 for (i = 0; i < adev->usec_timeout; i++) {
4404 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4405 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4406 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4412 if ((!pi->mclk_dpm_key_disabled) &&
4413 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4414 levels = ci_get_lowest_enabled_level(adev,
4415 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4416 ret = ci_dpm_force_state_mclk(adev, levels);
4419 for (i = 0; i < adev->usec_timeout; i++) {
4420 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4421 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4422 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4428 if ((!pi->pcie_dpm_key_disabled) &&
4429 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4430 levels = ci_get_lowest_enabled_level(adev,
4431 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4432 ret = ci_dpm_force_state_pcie(adev, levels);
4435 for (i = 0; i < adev->usec_timeout; i++) {
4436 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4437 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4438 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4444 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
4445 if (!pi->pcie_dpm_key_disabled) {
4446 PPSMC_Result smc_result;
4448 smc_result = amdgpu_ci_send_msg_to_smc(adev,
4449 PPSMC_MSG_PCIeDPM_UnForceLevel);
4450 if (smc_result != PPSMC_Result_OK)
4453 ret = ci_upload_dpm_level_enable_mask(adev);
4458 adev->pm.dpm.forced_level = level;
4463 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4464 struct ci_mc_reg_table *table)
4469 for (i = 0, j = table->last; i < table->last; i++) {
4470 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4472 switch(table->mc_reg_address[i].s1) {
4473 case mmMC_SEQ_MISC1:
4474 temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4475 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4476 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4477 for (k = 0; k < table->num_entries; k++) {
4478 table->mc_reg_table_entry[k].mc_data[j] =
4479 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4482 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4485 temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4486 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4487 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4488 for (k = 0; k < table->num_entries; k++) {
4489 table->mc_reg_table_entry[k].mc_data[j] =
4490 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4491 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4492 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4495 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4498 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4499 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4500 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4501 for (k = 0; k < table->num_entries; k++) {
4502 table->mc_reg_table_entry[k].mc_data[j] =
4503 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4506 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4510 case mmMC_SEQ_RESERVE_M:
4511 temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4512 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4513 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4514 for (k = 0; k < table->num_entries; k++) {
4515 table->mc_reg_table_entry[k].mc_data[j] =
4516 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4519 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4533 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4538 case mmMC_SEQ_RAS_TIMING:
4539 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4541 case mmMC_SEQ_DLL_STBY:
4542 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4544 case mmMC_SEQ_G5PDX_CMD0:
4545 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4547 case mmMC_SEQ_G5PDX_CMD1:
4548 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4550 case mmMC_SEQ_G5PDX_CTRL:
4551 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4553 case mmMC_SEQ_CAS_TIMING:
4554 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4556 case mmMC_SEQ_MISC_TIMING:
4557 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4559 case mmMC_SEQ_MISC_TIMING2:
4560 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4562 case mmMC_SEQ_PMG_DVS_CMD:
4563 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4565 case mmMC_SEQ_PMG_DVS_CTL:
4566 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4568 case mmMC_SEQ_RD_CTL_D0:
4569 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4571 case mmMC_SEQ_RD_CTL_D1:
4572 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4574 case mmMC_SEQ_WR_CTL_D0:
4575 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4577 case mmMC_SEQ_WR_CTL_D1:
4578 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4580 case mmMC_PMG_CMD_EMRS:
4581 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4583 case mmMC_PMG_CMD_MRS:
4584 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4586 case mmMC_PMG_CMD_MRS1:
4587 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4589 case mmMC_SEQ_PMG_TIMING:
4590 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4592 case mmMC_PMG_CMD_MRS2:
4593 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4595 case mmMC_SEQ_WR_CTL_2:
4596 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4606 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4610 for (i = 0; i < table->last; i++) {
4611 for (j = 1; j < table->num_entries; j++) {
4612 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4613 table->mc_reg_table_entry[j].mc_data[i]) {
4614 table->valid_flag |= 1 << i;
4621 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4626 for (i = 0; i < table->last; i++) {
4627 table->mc_reg_address[i].s0 =
4628 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4629 address : table->mc_reg_address[i].s1;
4633 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4634 struct ci_mc_reg_table *ci_table)
4638 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4640 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4643 for (i = 0; i < table->last; i++)
4644 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4646 ci_table->last = table->last;
4648 for (i = 0; i < table->num_entries; i++) {
4649 ci_table->mc_reg_table_entry[i].mclk_max =
4650 table->mc_reg_table_entry[i].mclk_max;
4651 for (j = 0; j < table->last; j++)
4652 ci_table->mc_reg_table_entry[i].mc_data[j] =
4653 table->mc_reg_table_entry[i].mc_data[j];
4655 ci_table->num_entries = table->num_entries;
4660 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4661 struct ci_mc_reg_table *table)
4667 tmp = RREG32(mmMC_SEQ_MISC0);
4668 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4671 ((adev->pdev->device == 0x67B0) ||
4672 (adev->pdev->device == 0x67B1))) {
4673 for (i = 0; i < table->last; i++) {
4674 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4676 switch (table->mc_reg_address[i].s1) {
4677 case mmMC_SEQ_MISC1:
4678 for (k = 0; k < table->num_entries; k++) {
4679 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4680 (table->mc_reg_table_entry[k].mclk_max == 137500))
4681 table->mc_reg_table_entry[k].mc_data[i] =
4682 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4686 case mmMC_SEQ_WR_CTL_D0:
4687 for (k = 0; k < table->num_entries; k++) {
4688 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4689 (table->mc_reg_table_entry[k].mclk_max == 137500))
4690 table->mc_reg_table_entry[k].mc_data[i] =
4691 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4695 case mmMC_SEQ_WR_CTL_D1:
4696 for (k = 0; k < table->num_entries; k++) {
4697 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4698 (table->mc_reg_table_entry[k].mclk_max == 137500))
4699 table->mc_reg_table_entry[k].mc_data[i] =
4700 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4704 case mmMC_SEQ_WR_CTL_2:
4705 for (k = 0; k < table->num_entries; k++) {
4706 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4707 (table->mc_reg_table_entry[k].mclk_max == 137500))
4708 table->mc_reg_table_entry[k].mc_data[i] = 0;
4711 case mmMC_SEQ_CAS_TIMING:
4712 for (k = 0; k < table->num_entries; k++) {
4713 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4714 table->mc_reg_table_entry[k].mc_data[i] =
4715 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4717 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4718 table->mc_reg_table_entry[k].mc_data[i] =
4719 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4723 case mmMC_SEQ_MISC_TIMING:
4724 for (k = 0; k < table->num_entries; k++) {
4725 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4726 table->mc_reg_table_entry[k].mc_data[i] =
4727 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4729 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4730 table->mc_reg_table_entry[k].mc_data[i] =
4731 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4740 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4741 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4742 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4743 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4744 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4750 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4752 struct ci_power_info *pi = ci_get_pi(adev);
4753 struct atom_mc_reg_table *table;
4754 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4755 u8 module_index = ci_get_memory_module_index(adev);
4758 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4762 WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4763 WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4764 WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4765 WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4766 WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4767 WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4768 WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4769 WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4770 WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4771 WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4772 WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4773 WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4774 WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4775 WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4776 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4777 WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4778 WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4779 WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4780 WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4781 WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4783 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4787 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4791 ci_set_s0_mc_reg_index(ci_table);
4793 ret = ci_register_patching_mc_seq(adev, ci_table);
4797 ret = ci_set_mc_special_registers(adev, ci_table);
4801 ci_set_valid_flag(ci_table);
4809 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4810 SMU7_Discrete_MCRegisters *mc_reg_table)
4812 struct ci_power_info *pi = ci_get_pi(adev);
4815 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4816 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4817 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4819 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4820 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4825 mc_reg_table->last = (u8)i;
4830 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4831 SMU7_Discrete_MCRegisterSet *data,
4832 u32 num_entries, u32 valid_flag)
4836 for (i = 0, j = 0; j < num_entries; j++) {
4837 if (valid_flag & (1 << j)) {
4838 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4844 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4845 const u32 memory_clock,
4846 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4848 struct ci_power_info *pi = ci_get_pi(adev);
4851 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4852 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4856 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4859 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4860 mc_reg_table_data, pi->mc_reg_table.last,
4861 pi->mc_reg_table.valid_flag);
4864 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4865 SMU7_Discrete_MCRegisters *mc_reg_table)
4867 struct ci_power_info *pi = ci_get_pi(adev);
4870 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4871 ci_convert_mc_reg_table_entry_to_smc(adev,
4872 pi->dpm_table.mclk_table.dpm_levels[i].value,
4873 &mc_reg_table->data[i]);
4876 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4878 struct ci_power_info *pi = ci_get_pi(adev);
4881 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4883 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4886 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4888 return amdgpu_ci_copy_bytes_to_smc(adev,
4889 pi->mc_reg_table_start,
4890 (u8 *)&pi->smc_mc_reg_table,
4891 sizeof(SMU7_Discrete_MCRegisters),
4895 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4897 struct ci_power_info *pi = ci_get_pi(adev);
4899 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4902 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4904 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4906 return amdgpu_ci_copy_bytes_to_smc(adev,
4907 pi->mc_reg_table_start +
4908 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4909 (u8 *)&pi->smc_mc_reg_table.data[0],
4910 sizeof(SMU7_Discrete_MCRegisterSet) *
4911 pi->dpm_table.mclk_table.count,
4915 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4917 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4919 tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4920 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4923 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4924 struct amdgpu_ps *amdgpu_state)
4926 struct ci_ps *state = ci_get_ps(amdgpu_state);
4928 u16 pcie_speed, max_speed = 0;
4930 for (i = 0; i < state->performance_level_count; i++) {
4931 pcie_speed = state->performance_levels[i].pcie_gen;
4932 if (max_speed < pcie_speed)
4933 max_speed = pcie_speed;
4939 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4943 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4944 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4945 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4947 return (u16)speed_cntl;
4950 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
4954 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
4955 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
4956 link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4958 switch (link_width) {
4974 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
4975 struct amdgpu_ps *amdgpu_new_state,
4976 struct amdgpu_ps *amdgpu_current_state)
4978 struct ci_power_info *pi = ci_get_pi(adev);
4979 enum amdgpu_pcie_gen target_link_speed =
4980 ci_get_maximum_link_speed(adev, amdgpu_new_state);
4981 enum amdgpu_pcie_gen current_link_speed;
4983 if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
4984 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
4986 current_link_speed = pi->force_pcie_gen;
4988 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
4989 pi->pspp_notify_required = false;
4990 if (target_link_speed > current_link_speed) {
4991 switch (target_link_speed) {
4993 case AMDGPU_PCIE_GEN3:
4994 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4996 pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
4997 if (current_link_speed == AMDGPU_PCIE_GEN2)
4999 case AMDGPU_PCIE_GEN2:
5000 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5004 pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
5008 if (target_link_speed < current_link_speed)
5009 pi->pspp_notify_required = true;
5013 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5014 struct amdgpu_ps *amdgpu_new_state,
5015 struct amdgpu_ps *amdgpu_current_state)
5017 struct ci_power_info *pi = ci_get_pi(adev);
5018 enum amdgpu_pcie_gen target_link_speed =
5019 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5022 if (pi->pspp_notify_required) {
5023 if (target_link_speed == AMDGPU_PCIE_GEN3)
5024 request = PCIE_PERF_REQ_PECI_GEN3;
5025 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5026 request = PCIE_PERF_REQ_PECI_GEN2;
5028 request = PCIE_PERF_REQ_PECI_GEN1;
5030 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5031 (ci_get_current_pcie_speed(adev) > 0))
5035 amdgpu_acpi_pcie_performance_request(adev, request, false);
5040 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5042 struct ci_power_info *pi = ci_get_pi(adev);
5043 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5044 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5045 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5046 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5047 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5048 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5050 if (allowed_sclk_vddc_table == NULL)
5052 if (allowed_sclk_vddc_table->count < 1)
5054 if (allowed_mclk_vddc_table == NULL)
5056 if (allowed_mclk_vddc_table->count < 1)
5058 if (allowed_mclk_vddci_table == NULL)
5060 if (allowed_mclk_vddci_table->count < 1)
5063 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5064 pi->max_vddc_in_pp_table =
5065 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5067 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5068 pi->max_vddci_in_pp_table =
5069 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5071 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5072 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5073 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5074 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5075 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5076 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5077 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5078 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5083 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5085 struct ci_power_info *pi = ci_get_pi(adev);
5086 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5089 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5090 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5091 *vddc = leakage_table->actual_voltage[leakage_index];
5097 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5099 struct ci_power_info *pi = ci_get_pi(adev);
5100 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5103 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5104 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5105 *vddci = leakage_table->actual_voltage[leakage_index];
5111 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5112 struct amdgpu_clock_voltage_dependency_table *table)
5117 for (i = 0; i < table->count; i++)
5118 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5122 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5123 struct amdgpu_clock_voltage_dependency_table *table)
5128 for (i = 0; i < table->count; i++)
5129 ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5133 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5134 struct amdgpu_vce_clock_voltage_dependency_table *table)
5139 for (i = 0; i < table->count; i++)
5140 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5144 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5145 struct amdgpu_uvd_clock_voltage_dependency_table *table)
5150 for (i = 0; i < table->count; i++)
5151 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5155 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5156 struct amdgpu_phase_shedding_limits_table *table)
5161 for (i = 0; i < table->count; i++)
5162 ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5166 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5167 struct amdgpu_clock_and_voltage_limits *table)
5170 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5171 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5175 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5176 struct amdgpu_cac_leakage_table *table)
5181 for (i = 0; i < table->count; i++)
5182 ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5186 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5189 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5190 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5191 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5192 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5193 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5194 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5195 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5196 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5197 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5198 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5199 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5200 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5201 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5202 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5203 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5204 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5205 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5206 &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5207 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5208 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5209 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5210 &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5211 ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5212 &adev->pm.dpm.dyn_state.cac_leakage_table);
5216 static void ci_update_current_ps(struct amdgpu_device *adev,
5217 struct amdgpu_ps *rps)
5219 struct ci_ps *new_ps = ci_get_ps(rps);
5220 struct ci_power_info *pi = ci_get_pi(adev);
5222 pi->current_rps = *rps;
5223 pi->current_ps = *new_ps;
5224 pi->current_rps.ps_priv = &pi->current_ps;
5227 static void ci_update_requested_ps(struct amdgpu_device *adev,
5228 struct amdgpu_ps *rps)
5230 struct ci_ps *new_ps = ci_get_ps(rps);
5231 struct ci_power_info *pi = ci_get_pi(adev);
5233 pi->requested_rps = *rps;
5234 pi->requested_ps = *new_ps;
5235 pi->requested_rps.ps_priv = &pi->requested_ps;
5238 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5240 struct ci_power_info *pi = ci_get_pi(adev);
5241 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5242 struct amdgpu_ps *new_ps = &requested_ps;
5244 ci_update_requested_ps(adev, new_ps);
5246 ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5251 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5253 struct ci_power_info *pi = ci_get_pi(adev);
5254 struct amdgpu_ps *new_ps = &pi->requested_rps;
5256 ci_update_current_ps(adev, new_ps);
5260 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5262 ci_read_clock_registers(adev);
5263 ci_enable_acpi_power_management(adev);
5264 ci_init_sclk_t(adev);
5267 static int ci_dpm_enable(struct amdgpu_device *adev)
5269 struct ci_power_info *pi = ci_get_pi(adev);
5270 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5273 if (amdgpu_ci_is_smc_running(adev))
5275 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5276 ci_enable_voltage_control(adev);
5277 ret = ci_construct_voltage_tables(adev);
5279 DRM_ERROR("ci_construct_voltage_tables failed\n");
5283 if (pi->caps_dynamic_ac_timing) {
5284 ret = ci_initialize_mc_reg_table(adev);
5286 pi->caps_dynamic_ac_timing = false;
5289 ci_enable_spread_spectrum(adev, true);
5290 if (pi->thermal_protection)
5291 ci_enable_thermal_protection(adev, true);
5292 ci_program_sstp(adev);
5293 ci_enable_display_gap(adev);
5294 ci_program_vc(adev);
5295 ret = ci_upload_firmware(adev);
5297 DRM_ERROR("ci_upload_firmware failed\n");
5300 ret = ci_process_firmware_header(adev);
5302 DRM_ERROR("ci_process_firmware_header failed\n");
5305 ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5307 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5310 ret = ci_init_smc_table(adev);
5312 DRM_ERROR("ci_init_smc_table failed\n");
5315 ret = ci_init_arb_table_index(adev);
5317 DRM_ERROR("ci_init_arb_table_index failed\n");
5320 if (pi->caps_dynamic_ac_timing) {
5321 ret = ci_populate_initial_mc_reg_table(adev);
5323 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5327 ret = ci_populate_pm_base(adev);
5329 DRM_ERROR("ci_populate_pm_base failed\n");
5332 ci_dpm_start_smc(adev);
5333 ci_enable_vr_hot_gpio_interrupt(adev);
5334 ret = ci_notify_smc_display_change(adev, false);
5336 DRM_ERROR("ci_notify_smc_display_change failed\n");
5339 ci_enable_sclk_control(adev, true);
5340 ret = ci_enable_ulv(adev, true);
5342 DRM_ERROR("ci_enable_ulv failed\n");
5345 ret = ci_enable_ds_master_switch(adev, true);
5347 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5350 ret = ci_start_dpm(adev);
5352 DRM_ERROR("ci_start_dpm failed\n");
5355 ret = ci_enable_didt(adev, true);
5357 DRM_ERROR("ci_enable_didt failed\n");
5360 ret = ci_enable_smc_cac(adev, true);
5362 DRM_ERROR("ci_enable_smc_cac failed\n");
5365 ret = ci_enable_power_containment(adev, true);
5367 DRM_ERROR("ci_enable_power_containment failed\n");
5371 ret = ci_power_control_set_level(adev);
5373 DRM_ERROR("ci_power_control_set_level failed\n");
5377 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5379 ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5381 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5385 ci_thermal_start_thermal_controller(adev);
5387 ci_update_current_ps(adev, boot_ps);
5392 static void ci_dpm_disable(struct amdgpu_device *adev)
5394 struct ci_power_info *pi = ci_get_pi(adev);
5395 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5397 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5398 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5399 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5400 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5402 ci_dpm_powergate_uvd(adev, true);
5404 if (!amdgpu_ci_is_smc_running(adev))
5407 ci_thermal_stop_thermal_controller(adev);
5409 if (pi->thermal_protection)
5410 ci_enable_thermal_protection(adev, false);
5411 ci_enable_power_containment(adev, false);
5412 ci_enable_smc_cac(adev, false);
5413 ci_enable_didt(adev, false);
5414 ci_enable_spread_spectrum(adev, false);
5415 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5417 ci_enable_ds_master_switch(adev, false);
5418 ci_enable_ulv(adev, false);
5420 ci_reset_to_default(adev);
5421 ci_dpm_stop_smc(adev);
5422 ci_force_switch_to_arb_f0(adev);
5423 ci_enable_thermal_based_sclk_dpm(adev, false);
5425 ci_update_current_ps(adev, boot_ps);
5428 static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5430 struct ci_power_info *pi = ci_get_pi(adev);
5431 struct amdgpu_ps *new_ps = &pi->requested_rps;
5432 struct amdgpu_ps *old_ps = &pi->current_rps;
5435 ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5436 if (pi->pcie_performance_request)
5437 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5438 ret = ci_freeze_sclk_mclk_dpm(adev);
5440 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5443 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5445 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5448 ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5450 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5454 ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5456 DRM_ERROR("ci_update_vce_dpm failed\n");
5460 ret = ci_update_sclk_t(adev);
5462 DRM_ERROR("ci_update_sclk_t failed\n");
5465 if (pi->caps_dynamic_ac_timing) {
5466 ret = ci_update_and_upload_mc_reg_table(adev);
5468 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5472 ret = ci_program_memory_timing_parameters(adev);
5474 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5477 ret = ci_unfreeze_sclk_mclk_dpm(adev);
5479 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5482 ret = ci_upload_dpm_level_enable_mask(adev);
5484 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5487 if (pi->pcie_performance_request)
5488 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5494 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5496 ci_set_boot_state(adev);
5500 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5502 ci_program_display_gap(adev);
5506 struct _ATOM_POWERPLAY_INFO info;
5507 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5508 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5509 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5510 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5511 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5514 union pplib_clock_info {
5515 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5516 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5517 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5518 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5519 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5520 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5523 union pplib_power_state {
5524 struct _ATOM_PPLIB_STATE v1;
5525 struct _ATOM_PPLIB_STATE_V2 v2;
5528 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5529 struct amdgpu_ps *rps,
5530 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5533 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5534 rps->class = le16_to_cpu(non_clock_info->usClassification);
5535 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5537 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5538 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5539 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5545 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5546 adev->pm.dpm.boot_ps = rps;
5547 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5548 adev->pm.dpm.uvd_ps = rps;
5551 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5552 struct amdgpu_ps *rps, int index,
5553 union pplib_clock_info *clock_info)
5555 struct ci_power_info *pi = ci_get_pi(adev);
5556 struct ci_ps *ps = ci_get_ps(rps);
5557 struct ci_pl *pl = &ps->performance_levels[index];
5559 ps->performance_level_count = index + 1;
5561 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5562 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5563 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5564 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5566 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5568 pi->vbios_boot_state.pcie_gen_bootup_value,
5569 clock_info->ci.ucPCIEGen);
5570 pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5571 pi->vbios_boot_state.pcie_lane_bootup_value,
5572 le16_to_cpu(clock_info->ci.usPCIELane));
5574 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5575 pi->acpi_pcie_gen = pl->pcie_gen;
5578 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5579 pi->ulv.supported = true;
5581 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5584 /* patch up boot state */
5585 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5586 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5587 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5588 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5589 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5592 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5593 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5594 pi->use_pcie_powersaving_levels = true;
5595 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5596 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5597 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5598 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5599 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5600 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5601 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5602 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5604 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5605 pi->use_pcie_performance_levels = true;
5606 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5607 pi->pcie_gen_performance.max = pl->pcie_gen;
5608 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5609 pi->pcie_gen_performance.min = pl->pcie_gen;
5610 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5611 pi->pcie_lane_performance.max = pl->pcie_lane;
5612 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5613 pi->pcie_lane_performance.min = pl->pcie_lane;
5620 static int ci_parse_power_table(struct amdgpu_device *adev)
5622 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5623 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5624 union pplib_power_state *power_state;
5625 int i, j, k, non_clock_array_index, clock_array_index;
5626 union pplib_clock_info *clock_info;
5627 struct _StateArray *state_array;
5628 struct _ClockInfoArray *clock_info_array;
5629 struct _NonClockInfoArray *non_clock_info_array;
5630 union power_info *power_info;
5631 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5634 u8 *power_state_offset;
5637 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5638 &frev, &crev, &data_offset))
5640 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5642 amdgpu_add_thermal_controller(adev);
5644 state_array = (struct _StateArray *)
5645 (mode_info->atom_context->bios + data_offset +
5646 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5647 clock_info_array = (struct _ClockInfoArray *)
5648 (mode_info->atom_context->bios + data_offset +
5649 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5650 non_clock_info_array = (struct _NonClockInfoArray *)
5651 (mode_info->atom_context->bios + data_offset +
5652 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5654 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5655 state_array->ucNumEntries, GFP_KERNEL);
5656 if (!adev->pm.dpm.ps)
5658 power_state_offset = (u8 *)state_array->states;
5659 for (i = 0; i < state_array->ucNumEntries; i++) {
5661 power_state = (union pplib_power_state *)power_state_offset;
5662 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5663 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5664 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5665 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5667 kfree(adev->pm.dpm.ps);
5670 adev->pm.dpm.ps[i].ps_priv = ps;
5671 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5673 non_clock_info_array->ucEntrySize);
5675 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5676 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5677 clock_array_index = idx[j];
5678 if (clock_array_index >= clock_info_array->ucNumEntries)
5680 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5682 clock_info = (union pplib_clock_info *)
5683 ((u8 *)&clock_info_array->clockInfo[0] +
5684 (clock_array_index * clock_info_array->ucEntrySize));
5685 ci_parse_pplib_clock_info(adev,
5686 &adev->pm.dpm.ps[i], k,
5690 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5692 adev->pm.dpm.num_ps = state_array->ucNumEntries;
5694 /* fill in the vce power states */
5695 for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
5697 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5698 clock_info = (union pplib_clock_info *)
5699 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5700 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5701 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5702 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5703 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5704 adev->pm.dpm.vce_states[i].sclk = sclk;
5705 adev->pm.dpm.vce_states[i].mclk = mclk;
5711 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5712 struct ci_vbios_boot_state *boot_state)
5714 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5715 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5716 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5720 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5721 &frev, &crev, &data_offset)) {
5723 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5725 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5726 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5727 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5728 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5729 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5730 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5731 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5738 static void ci_dpm_fini(struct amdgpu_device *adev)
5742 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5743 kfree(adev->pm.dpm.ps[i].ps_priv);
5745 kfree(adev->pm.dpm.ps);
5746 kfree(adev->pm.dpm.priv);
5747 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5748 amdgpu_free_extended_power_table(adev);
5752 * ci_dpm_init_microcode - load ucode images from disk
5754 * @adev: amdgpu_device pointer
5756 * Use the firmware interface to load the ucode images into
5757 * the driver (not loaded into hw).
5758 * Returns 0 on success, error on failure.
5760 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5762 const char *chip_name;
5768 switch (adev->asic_type) {
5770 if ((adev->pdev->revision == 0x80) ||
5771 (adev->pdev->revision == 0x81) ||
5772 (adev->pdev->device == 0x665f))
5773 chip_name = "bonaire_k";
5775 chip_name = "bonaire";
5778 if (adev->pdev->revision == 0x80)
5779 chip_name = "hawaii_k";
5781 chip_name = "hawaii";
5789 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
5790 err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
5793 err = amdgpu_ucode_validate(adev->pm.fw);
5798 "cik_smc: Failed to load firmware \"%s\"\n",
5800 release_firmware(adev->pm.fw);
5806 static int ci_dpm_init(struct amdgpu_device *adev)
5808 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5809 SMU7_Discrete_DpmTable *dpm_table;
5810 struct amdgpu_gpio_rec gpio;
5811 u16 data_offset, size;
5813 struct ci_power_info *pi;
5816 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5819 adev->pm.dpm.priv = pi;
5822 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5823 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5825 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5827 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5828 pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5829 pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5830 pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5832 pi->pcie_lane_performance.max = 0;
5833 pi->pcie_lane_performance.min = 16;
5834 pi->pcie_lane_powersaving.max = 0;
5835 pi->pcie_lane_powersaving.min = 16;
5837 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5843 ret = amdgpu_get_platform_caps(adev);
5849 ret = amdgpu_parse_extended_power_table(adev);
5855 ret = ci_parse_power_table(adev);
5861 pi->dll_default_on = false;
5862 pi->sram_end = SMC_RAM_END;
5864 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5865 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5866 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5867 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5868 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5869 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5870 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5871 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5873 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5875 pi->sclk_dpm_key_disabled = 0;
5876 pi->mclk_dpm_key_disabled = 0;
5877 pi->pcie_dpm_key_disabled = 0;
5878 pi->thermal_sclk_dpm_enabled = 0;
5880 if (amdgpu_sclk_deep_sleep_en)
5881 pi->caps_sclk_ds = true;
5883 pi->caps_sclk_ds = false;
5885 pi->mclk_strobe_mode_threshold = 40000;
5886 pi->mclk_stutter_mode_threshold = 40000;
5887 pi->mclk_edc_enable_threshold = 40000;
5888 pi->mclk_edc_wr_enable_threshold = 40000;
5890 ci_initialize_powertune_defaults(adev);
5892 pi->caps_fps = false;
5894 pi->caps_sclk_throttle_low_notification = false;
5896 pi->caps_uvd_dpm = true;
5897 pi->caps_vce_dpm = true;
5899 ci_get_leakage_voltages(adev);
5900 ci_patch_dependency_tables_with_leakage(adev);
5901 ci_set_private_data_variables_based_on_pptable(adev);
5903 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5904 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5905 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5909 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5910 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5911 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5912 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5913 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5914 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5915 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5916 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5917 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5919 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5920 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5921 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5923 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5924 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5925 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5926 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5928 if (adev->asic_type == CHIP_HAWAII) {
5929 pi->thermal_temp_setting.temperature_low = 94500;
5930 pi->thermal_temp_setting.temperature_high = 95000;
5931 pi->thermal_temp_setting.temperature_shutdown = 104000;
5933 pi->thermal_temp_setting.temperature_low = 99500;
5934 pi->thermal_temp_setting.temperature_high = 100000;
5935 pi->thermal_temp_setting.temperature_shutdown = 104000;
5938 pi->uvd_enabled = false;
5940 dpm_table = &pi->smc_state_table;
5942 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5944 dpm_table->VRHotGpio = gpio.shift;
5945 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5947 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5948 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5951 gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
5953 dpm_table->AcDcGpio = gpio.shift;
5954 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5956 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5957 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5960 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
5962 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
5964 switch (gpio.shift) {
5966 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5967 tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5970 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5971 tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5974 tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
5977 tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
5980 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
5983 DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
5986 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
5989 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5990 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5991 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5992 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5993 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5994 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5995 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5997 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5998 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5999 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6000 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
6001 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6003 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
6006 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
6007 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
6008 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6009 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
6010 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6012 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
6015 pi->vddc_phase_shed_control = true;
6017 #if defined(CONFIG_ACPI)
6018 pi->pcie_performance_request =
6019 amdgpu_acpi_is_pcie_performance_request_supported(adev);
6021 pi->pcie_performance_request = false;
6024 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6025 &frev, &crev, &data_offset)) {
6026 pi->caps_sclk_ss_support = true;
6027 pi->caps_mclk_ss_support = true;
6028 pi->dynamic_ss = true;
6030 pi->caps_sclk_ss_support = false;
6031 pi->caps_mclk_ss_support = false;
6032 pi->dynamic_ss = true;
6035 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6036 pi->thermal_protection = true;
6038 pi->thermal_protection = false;
6040 pi->caps_dynamic_ac_timing = true;
6042 pi->uvd_power_gated = true;
6044 /* make sure dc limits are valid */
6045 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6046 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6047 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6048 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6050 pi->fan_ctrl_is_in_default_mode = true;
6056 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6059 struct ci_power_info *pi = ci_get_pi(adev);
6060 struct amdgpu_ps *rps = &pi->current_rps;
6061 u32 sclk = ci_get_average_sclk_freq(adev);
6062 u32 mclk = ci_get_average_mclk_freq(adev);
6063 u32 activity_percent = 50;
6066 ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6070 activity_percent += 0x80;
6071 activity_percent >>= 8;
6072 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6075 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
6076 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6077 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
6079 seq_printf(m, "GPU load: %u %%\n", activity_percent);
6082 static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6083 struct amdgpu_ps *rps)
6085 struct ci_ps *ps = ci_get_ps(rps);
6089 amdgpu_dpm_print_class_info(rps->class, rps->class2);
6090 amdgpu_dpm_print_cap_info(rps->caps);
6091 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6092 for (i = 0; i < ps->performance_level_count; i++) {
6093 pl = &ps->performance_levels[i];
6094 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6095 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6097 amdgpu_dpm_print_ps_status(adev, rps);
6100 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6102 struct ci_power_info *pi = ci_get_pi(adev);
6103 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6106 return requested_state->performance_levels[0].sclk;
6108 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6111 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6113 struct ci_power_info *pi = ci_get_pi(adev);
6114 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6117 return requested_state->performance_levels[0].mclk;
6119 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6122 /* get temperature in millidegrees */
6123 static int ci_dpm_get_temp(struct amdgpu_device *adev)
6126 int actual_temp = 0;
6128 temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6129 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6134 actual_temp = temp & 0x1ff;
6136 actual_temp = actual_temp * 1000;
6141 static int ci_set_temperature_range(struct amdgpu_device *adev)
6145 ret = ci_thermal_enable_alert(adev, false);
6148 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6149 CISLANDS_TEMP_RANGE_MAX);
6152 ret = ci_thermal_enable_alert(adev, true);
6158 static int ci_dpm_early_init(void *handle)
6160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6162 ci_dpm_set_dpm_funcs(adev);
6163 ci_dpm_set_irq_funcs(adev);
6168 static int ci_dpm_late_init(void *handle)
6171 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6176 /* init the sysfs and debugfs files late */
6177 ret = amdgpu_pm_sysfs_init(adev);
6181 ret = ci_set_temperature_range(adev);
6188 static int ci_dpm_sw_init(void *handle)
6191 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6193 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
6197 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
6201 /* default to balanced state */
6202 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6203 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6204 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
6205 adev->pm.default_sclk = adev->clock.default_sclk;
6206 adev->pm.default_mclk = adev->clock.default_mclk;
6207 adev->pm.current_sclk = adev->clock.default_sclk;
6208 adev->pm.current_mclk = adev->clock.default_mclk;
6209 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6211 if (amdgpu_dpm == 0)
6214 ret = ci_dpm_init_microcode(adev);
6218 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6219 mutex_lock(&adev->pm.mutex);
6220 ret = ci_dpm_init(adev);
6223 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6224 if (amdgpu_dpm == 1)
6225 amdgpu_pm_print_power_states(adev);
6226 mutex_unlock(&adev->pm.mutex);
6227 DRM_INFO("amdgpu: dpm initialized\n");
6233 mutex_unlock(&adev->pm.mutex);
6234 DRM_ERROR("amdgpu: dpm initialization failed\n");
6238 static int ci_dpm_sw_fini(void *handle)
6240 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6242 flush_work(&adev->pm.dpm.thermal.work);
6244 mutex_lock(&adev->pm.mutex);
6245 amdgpu_pm_sysfs_fini(adev);
6247 mutex_unlock(&adev->pm.mutex);
6249 release_firmware(adev->pm.fw);
6255 static int ci_dpm_hw_init(void *handle)
6259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6264 mutex_lock(&adev->pm.mutex);
6265 ci_dpm_setup_asic(adev);
6266 ret = ci_dpm_enable(adev);
6268 adev->pm.dpm_enabled = false;
6270 adev->pm.dpm_enabled = true;
6271 mutex_unlock(&adev->pm.mutex);
6276 static int ci_dpm_hw_fini(void *handle)
6278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6280 if (adev->pm.dpm_enabled) {
6281 mutex_lock(&adev->pm.mutex);
6282 ci_dpm_disable(adev);
6283 mutex_unlock(&adev->pm.mutex);
6289 static int ci_dpm_suspend(void *handle)
6291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6293 if (adev->pm.dpm_enabled) {
6294 mutex_lock(&adev->pm.mutex);
6296 ci_dpm_disable(adev);
6297 /* reset the power state */
6298 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6299 mutex_unlock(&adev->pm.mutex);
6304 static int ci_dpm_resume(void *handle)
6307 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6309 if (adev->pm.dpm_enabled) {
6310 /* asic init will reset to the boot state */
6311 mutex_lock(&adev->pm.mutex);
6312 ci_dpm_setup_asic(adev);
6313 ret = ci_dpm_enable(adev);
6315 adev->pm.dpm_enabled = false;
6317 adev->pm.dpm_enabled = true;
6318 mutex_unlock(&adev->pm.mutex);
6319 if (adev->pm.dpm_enabled)
6320 amdgpu_pm_compute_clocks(adev);
6325 static bool ci_dpm_is_idle(void *handle)
6331 static int ci_dpm_wait_for_idle(void *handle)
6337 static int ci_dpm_soft_reset(void *handle)
6342 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6343 struct amdgpu_irq_src *source,
6345 enum amdgpu_interrupt_state state)
6350 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6352 case AMDGPU_IRQ_STATE_DISABLE:
6353 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6354 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6355 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6357 case AMDGPU_IRQ_STATE_ENABLE:
6358 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6359 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6360 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6367 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6369 case AMDGPU_IRQ_STATE_DISABLE:
6370 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6371 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6372 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6374 case AMDGPU_IRQ_STATE_ENABLE:
6375 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6376 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6377 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6390 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6391 struct amdgpu_irq_src *source,
6392 struct amdgpu_iv_entry *entry)
6394 bool queue_thermal = false;
6399 switch (entry->src_id) {
6400 case 230: /* thermal low to high */
6401 DRM_DEBUG("IH: thermal low to high\n");
6402 adev->pm.dpm.thermal.high_to_low = false;
6403 queue_thermal = true;
6405 case 231: /* thermal high to low */
6406 DRM_DEBUG("IH: thermal high to low\n");
6407 adev->pm.dpm.thermal.high_to_low = true;
6408 queue_thermal = true;
6415 schedule_work(&adev->pm.dpm.thermal.work);
6420 static int ci_dpm_set_clockgating_state(void *handle,
6421 enum amd_clockgating_state state)
6426 static int ci_dpm_set_powergating_state(void *handle,
6427 enum amd_powergating_state state)
6432 static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
6433 enum pp_clock_type type, char *buf)
6435 struct ci_power_info *pi = ci_get_pi(adev);
6436 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
6437 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
6438 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
6440 int i, now, size = 0;
6441 uint32_t clock, pcie_speed;
6445 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
6446 clock = RREG32(mmSMC_MSG_ARG_0);
6448 for (i = 0; i < sclk_table->count; i++) {
6449 if (clock > sclk_table->dpm_levels[i].value)
6455 for (i = 0; i < sclk_table->count; i++)
6456 size += sprintf(buf + size, "%d: %uMhz %s\n",
6457 i, sclk_table->dpm_levels[i].value / 100,
6458 (i == now) ? "*" : "");
6461 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
6462 clock = RREG32(mmSMC_MSG_ARG_0);
6464 for (i = 0; i < mclk_table->count; i++) {
6465 if (clock > mclk_table->dpm_levels[i].value)
6471 for (i = 0; i < mclk_table->count; i++)
6472 size += sprintf(buf + size, "%d: %uMhz %s\n",
6473 i, mclk_table->dpm_levels[i].value / 100,
6474 (i == now) ? "*" : "");
6477 pcie_speed = ci_get_current_pcie_speed(adev);
6478 for (i = 0; i < pcie_table->count; i++) {
6479 if (pcie_speed != pcie_table->dpm_levels[i].value)
6485 for (i = 0; i < pcie_table->count; i++)
6486 size += sprintf(buf + size, "%d: %s %s\n", i,
6487 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
6488 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6489 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6490 (i == now) ? "*" : "");
6499 static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
6500 enum pp_clock_type type, uint32_t mask)
6502 struct ci_power_info *pi = ci_get_pi(adev);
6504 if (adev->pm.dpm.forced_level
6505 != AMDGPU_DPM_FORCED_LEVEL_MANUAL)
6510 if (!pi->sclk_dpm_key_disabled)
6511 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6512 PPSMC_MSG_SCLKDPM_SetEnabledMask,
6513 pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
6517 if (!pi->mclk_dpm_key_disabled)
6518 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6519 PPSMC_MSG_MCLKDPM_SetEnabledMask,
6520 pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
6525 uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
6531 if (!pi->pcie_dpm_key_disabled)
6532 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6533 PPSMC_MSG_PCIeDPM_ForceLevel,
6544 static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
6546 struct ci_power_info *pi = ci_get_pi(adev);
6547 struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
6548 struct ci_single_dpm_table *golden_sclk_table =
6549 &(pi->golden_dpm_table.sclk_table);
6552 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
6553 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
6555 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6560 static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
6562 struct ci_power_info *pi = ci_get_pi(adev);
6563 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6564 struct ci_single_dpm_table *golden_sclk_table =
6565 &(pi->golden_dpm_table.sclk_table);
6570 ps->performance_levels[ps->performance_level_count - 1].sclk =
6571 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
6573 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6578 static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
6580 struct ci_power_info *pi = ci_get_pi(adev);
6581 struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
6582 struct ci_single_dpm_table *golden_mclk_table =
6583 &(pi->golden_dpm_table.mclk_table);
6586 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
6587 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
6589 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6594 static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
6596 struct ci_power_info *pi = ci_get_pi(adev);
6597 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6598 struct ci_single_dpm_table *golden_mclk_table =
6599 &(pi->golden_dpm_table.mclk_table);
6604 ps->performance_levels[ps->performance_level_count - 1].mclk =
6605 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
6607 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6612 const struct amd_ip_funcs ci_dpm_ip_funcs = {
6614 .early_init = ci_dpm_early_init,
6615 .late_init = ci_dpm_late_init,
6616 .sw_init = ci_dpm_sw_init,
6617 .sw_fini = ci_dpm_sw_fini,
6618 .hw_init = ci_dpm_hw_init,
6619 .hw_fini = ci_dpm_hw_fini,
6620 .suspend = ci_dpm_suspend,
6621 .resume = ci_dpm_resume,
6622 .is_idle = ci_dpm_is_idle,
6623 .wait_for_idle = ci_dpm_wait_for_idle,
6624 .soft_reset = ci_dpm_soft_reset,
6625 .set_clockgating_state = ci_dpm_set_clockgating_state,
6626 .set_powergating_state = ci_dpm_set_powergating_state,
6629 static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
6630 .get_temperature = &ci_dpm_get_temp,
6631 .pre_set_power_state = &ci_dpm_pre_set_power_state,
6632 .set_power_state = &ci_dpm_set_power_state,
6633 .post_set_power_state = &ci_dpm_post_set_power_state,
6634 .display_configuration_changed = &ci_dpm_display_configuration_changed,
6635 .get_sclk = &ci_dpm_get_sclk,
6636 .get_mclk = &ci_dpm_get_mclk,
6637 .print_power_state = &ci_dpm_print_power_state,
6638 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
6639 .force_performance_level = &ci_dpm_force_performance_level,
6640 .vblank_too_short = &ci_dpm_vblank_too_short,
6641 .powergate_uvd = &ci_dpm_powergate_uvd,
6642 .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
6643 .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
6644 .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
6645 .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
6646 .print_clock_levels = ci_dpm_print_clock_levels,
6647 .force_clock_level = ci_dpm_force_clock_level,
6648 .get_sclk_od = ci_dpm_get_sclk_od,
6649 .set_sclk_od = ci_dpm_set_sclk_od,
6650 .get_mclk_od = ci_dpm_get_mclk_od,
6651 .set_mclk_od = ci_dpm_set_mclk_od,
6654 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
6656 if (adev->pm.funcs == NULL)
6657 adev->pm.funcs = &ci_dpm_funcs;
6660 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
6661 .set = ci_dpm_set_interrupt_state,
6662 .process = ci_dpm_process_interrupt,
6665 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6667 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6668 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;