drivers/gpu/drm/amd/amdgpu/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_ucode.h"
  29 #include "cikd.h"
  30 #include "amdgpu_dpm.h"
  31 #include "ci_dpm.h"
  32 #include "gfx_v7_0.h"
  33 #include "atom.h"
  34 #include "amd_pcie.h"
  35 #include <linux/seq_file.h>
  36
  37 #include "smu/smu_7_0_1_d.h"
  38 #include "smu/smu_7_0_1_sh_mask.h"
  39
  40 #include "dce/dce_8_0_d.h"
  41 #include "dce/dce_8_0_sh_mask.h"
  42
  43 #include "bif/bif_4_1_d.h"
  44 #include "bif/bif_4_1_sh_mask.h"
  45
  46 #include "gca/gfx_7_2_d.h"
  47 #include "gca/gfx_7_2_sh_mask.h"
  48
  49 #include "gmc/gmc_7_1_d.h"
  50 #include "gmc/gmc_7_1_sh_mask.h"
  51
  52 /*(DEBLOBBED)*/
  53
  54 #define MC_CG_ARB_FREQ_F0           0x0a
  55 #define MC_CG_ARB_FREQ_F1           0x0b
  56 #define MC_CG_ARB_FREQ_F2           0x0c
  57 #define MC_CG_ARB_FREQ_F3           0x0d
  58
  59 #define SMC_RAM_END 0x40000
  60
  61 #define VOLTAGE_SCALE               4
  62 #define VOLTAGE_VID_OFFSET_SCALE1    625
  63 #define VOLTAGE_VID_OFFSET_SCALE2    100
  64
  65 static const struct ci_pt_defaults defaults_hawaii_xt =
  66 {
  67         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  68         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  69         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  70 };
  71
  72 static const struct ci_pt_defaults defaults_hawaii_pro =
  73 {
  74         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  75         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  76         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  77 };
  78
  79 static const struct ci_pt_defaults defaults_bonaire_xt =
  80 {
  81         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  82         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  83         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  84 };
  85
  86 #if 0
  87 static const struct ci_pt_defaults defaults_bonaire_pro =
  88 {
  89         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  90         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  91         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  92 };
  93 #endif
  94
  95 static const struct ci_pt_defaults defaults_saturn_xt =
  96 {
  97         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  98         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  99         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
 100 };
 101
 102 #if 0
 103 static const struct ci_pt_defaults defaults_saturn_pro =
 104 {
 105         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
 106         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
 107         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
 108 };
 109 #endif
 110
 111 static const struct ci_pt_config_reg didt_config_ci[] =
 112 {
 113         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 162         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 163         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 164         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 165         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 166         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 167         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 168         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 169         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 170         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 171         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 172         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 173         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 174         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 175         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 176         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 177         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 178         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 179         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 180         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 181         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 182         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 183         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 184         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 185         { 0xFFFFFFFF }
 186 };
 187
 188 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
 189 {
 190         return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
 191 }
 192
 193 #define MC_CG_ARB_FREQ_F0           0x0a
 194 #define MC_CG_ARB_FREQ_F1           0x0b
 195 #define MC_CG_ARB_FREQ_F2           0x0c
 196 #define MC_CG_ARB_FREQ_F3           0x0d
 197
 198 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
 199                                        u32 arb_freq_src, u32 arb_freq_dest)
 200 {
 201         u32 mc_arb_dram_timing;
 202         u32 mc_arb_dram_timing2;
 203         u32 burst_time;
 204         u32 mc_cg_config;
 205
 206         switch (arb_freq_src) {
 207         case MC_CG_ARB_FREQ_F0:
 208                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
 209                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
 210                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
 211                          MC_ARB_BURST_TIME__STATE0__SHIFT;
 212                 break;
 213         case MC_CG_ARB_FREQ_F1:
 214                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING_1);
 215                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
 216                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
 217                          MC_ARB_BURST_TIME__STATE1__SHIFT;
 218                 break;
 219         default:
 220                 return -EINVAL;
 221         }
 222
 223         switch (arb_freq_dest) {
 224         case MC_CG_ARB_FREQ_F0:
 225                 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 226                 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 227                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
 228                         ~MC_ARB_BURST_TIME__STATE0_MASK);
 229                 break;
 230         case MC_CG_ARB_FREQ_F1:
 231                 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 232                 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 233                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
 234                         ~MC_ARB_BURST_TIME__STATE1_MASK);
 235                 break;
 236         default:
 237                 return -EINVAL;
 238         }
 239
 240         mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
 241         WREG32(mmMC_CG_CONFIG, mc_cg_config);
 242         WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
 243                 ~MC_ARB_CG__CG_ARB_REQ_MASK);
 244
 245         return 0;
 246 }
 247
 248 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
 249 {
 250         u8 mc_para_index;
 251
 252         if (memory_clock < 10000)
 253                 mc_para_index = 0;
 254         else if (memory_clock >= 80000)
 255                 mc_para_index = 0x0f;
 256         else
 257                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
 258         return mc_para_index;
 259 }
 260
 261 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
 262 {
 263         u8 mc_para_index;
 264
 265         if (strobe_mode) {
 266                 if (memory_clock < 12500)
 267                         mc_para_index = 0x00;
 268                 else if (memory_clock > 47500)
 269                         mc_para_index = 0x0f;
 270                 else
 271                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
 272         } else {
 273                 if (memory_clock < 65000)
 274                         mc_para_index = 0x00;
 275                 else if (memory_clock > 135000)
 276                         mc_para_index = 0x0f;
 277                 else
 278                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
 279         }
 280         return mc_para_index;
 281 }
 282
 283 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
 284                                                      u32 max_voltage_steps,
 285                                                      struct atom_voltage_table *voltage_table)
 286 {
 287         unsigned int i, diff;
 288
 289         if (voltage_table->count <= max_voltage_steps)
 290                 return;
 291
 292         diff = voltage_table->count - max_voltage_steps;
 293
 294         for (i = 0; i < max_voltage_steps; i++)
 295                 voltage_table->entries[i] = voltage_table->entries[i + diff];
 296
 297         voltage_table->count = max_voltage_steps;
 298 }
 299
 300 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
 301                                          struct atom_voltage_table_entry *voltage_table,
 302                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 303 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
 304 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
 305                                        u32 target_tdp);
 306 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
 307 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
 308 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
 309
 310 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
 311                                                              PPSMC_Msg msg, u32 parameter);
 312 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
 313 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
 314
 315 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
 316 {
 317         struct ci_power_info *pi = adev->pm.dpm.priv;
 318
 319         return pi;
 320 }
 321
 322 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
 323 {
 324         struct ci_ps *ps = rps->ps_priv;
 325
 326         return ps;
 327 }
 328
 329 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
 330 {
 331         struct ci_power_info *pi = ci_get_pi(adev);
 332
 333         switch (adev->pdev->device) {
 334         case 0x6649:
 335         case 0x6650:
 336         case 0x6651:
 337         case 0x6658:
 338         case 0x665C:
 339         case 0x665D:
 340         default:
 341                 pi->powertune_defaults = &defaults_bonaire_xt;
 342                 break;
 343         case 0x6640:
 344         case 0x6641:
 345         case 0x6646:
 346         case 0x6647:
 347                 pi->powertune_defaults = &defaults_saturn_xt;
 348                 break;
 349         case 0x67B8:
 350         case 0x67B0:
 351                 pi->powertune_defaults = &defaults_hawaii_xt;
 352                 break;
 353         case 0x67BA:
 354         case 0x67B1:
 355                 pi->powertune_defaults = &defaults_hawaii_pro;
 356                 break;
 357         case 0x67A0:
 358         case 0x67A1:
 359         case 0x67A2:
 360         case 0x67A8:
 361         case 0x67A9:
 362         case 0x67AA:
 363         case 0x67B9:
 364         case 0x67BE:
 365                 pi->powertune_defaults = &defaults_bonaire_xt;
 366                 break;
 367         }
 368
 369         pi->dte_tj_offset = 0;
 370
 371         pi->caps_power_containment = true;
 372         pi->caps_cac = false;
 373         pi->caps_sq_ramping = false;
 374         pi->caps_db_ramping = false;
 375         pi->caps_td_ramping = false;
 376         pi->caps_tcp_ramping = false;
 377
 378         if (pi->caps_power_containment) {
 379                 pi->caps_cac = true;
 380                 if (adev->asic_type == CHIP_HAWAII)
 381                         pi->enable_bapm_feature = false;
 382                 else
 383                         pi->enable_bapm_feature = true;
 384                 pi->enable_tdc_limit_feature = true;
 385                 pi->enable_pkg_pwr_tracking_feature = true;
 386         }
 387 }
 388
 389 static u8 ci_convert_to_vid(u16 vddc)
 390 {
 391         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 392 }
 393
 394 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
 395 {
 396         struct ci_power_info *pi = ci_get_pi(adev);
 397         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 398         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 399         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 400         u32 i;
 401
 402         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 403                 return -EINVAL;
 404         if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 405                 return -EINVAL;
 406         if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
 407             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 408                 return -EINVAL;
 409
 410         for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 411                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 412                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 413                         hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 414                         hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 415                 } else {
 416                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 417                         hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 418                 }
 419         }
 420         return 0;
 421 }
 422
 423 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
 424 {
 425         struct ci_power_info *pi = ci_get_pi(adev);
 426         u8 *vid = pi->smc_powertune_table.VddCVid;
 427         u32 i;
 428
 429         if (pi->vddc_voltage_table.count > 8)
 430                 return -EINVAL;
 431
 432         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 433                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 434
 435         return 0;
 436 }
 437
 438 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
 439 {
 440         struct ci_power_info *pi = ci_get_pi(adev);
 441         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 442
 443         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 444         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 445         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 446         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 447
 448         return 0;
 449 }
 450
 451 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
 452 {
 453         struct ci_power_info *pi = ci_get_pi(adev);
 454         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 455         u16 tdc_limit;
 456
 457         tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 458         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 459         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 460                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 461         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 462
 463         return 0;
 464 }
 465
 466 static int ci_populate_dw8(struct amdgpu_device *adev)
 467 {
 468         struct ci_power_info *pi = ci_get_pi(adev);
 469         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 470         int ret;
 471
 472         ret = amdgpu_ci_read_smc_sram_dword(adev,
 473                                      SMU7_FIRMWARE_HEADER_LOCATION +
 474                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 475                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 476                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 477                                      pi->sram_end);
 478         if (ret)
 479                 return -EINVAL;
 480         else
 481                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 482
 483         return 0;
 484 }
 485
 486 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
 487 {
 488         struct ci_power_info *pi = ci_get_pi(adev);
 489
 490         if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
 491             (adev->pm.dpm.fan.fan_output_sensitivity == 0))
 492                 adev->pm.dpm.fan.fan_output_sensitivity =
 493                         adev->pm.dpm.fan.default_fan_output_sensitivity;
 494
 495         pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
 496                 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
 497
 498         return 0;
 499 }
 500
 501 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
 502 {
 503         struct ci_power_info *pi = ci_get_pi(adev);
 504         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 505         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 506         int i, min, max;
 507
 508         min = max = hi_vid[0];
 509         for (i = 0; i < 8; i++) {
 510                 if (0 != hi_vid[i]) {
 511                         if (min > hi_vid[i])
 512                                 min = hi_vid[i];
 513                         if (max < hi_vid[i])
 514                                 max = hi_vid[i];
 515                 }
 516
 517                 if (0 != lo_vid[i]) {
 518                         if (min > lo_vid[i])
 519                                 min = lo_vid[i];
 520                         if (max < lo_vid[i])
 521                                 max = lo_vid[i];
 522                 }
 523         }
 524
 525         if ((min == 0) || (max == 0))
 526                 return -EINVAL;
 527         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 528         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 529
 530         return 0;
 531 }
 532
 533 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
 534 {
 535         struct ci_power_info *pi = ci_get_pi(adev);
 536         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 537         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 538         struct amdgpu_cac_tdp_table *cac_tdp_table =
 539                 adev->pm.dpm.dyn_state.cac_tdp_table;
 540
 541         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 542         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 543
 544         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 545         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 546
 547         return 0;
 548 }
 549
 550 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
 551 {
 552         struct ci_power_info *pi = ci_get_pi(adev);
 553         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 554         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 555         struct amdgpu_cac_tdp_table *cac_tdp_table =
 556                 adev->pm.dpm.dyn_state.cac_tdp_table;
 557         struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
 558         int i, j, k;
 559         const u16 *def1;
 560         const u16 *def2;
 561
 562         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 563         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 564
 565         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 566         dpm_table->GpuTjMax =
 567                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 568         dpm_table->GpuTjHyst = 8;
 569
 570         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 571
 572         if (ppm) {
 573                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 574                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 575         } else {
 576                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 577                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 578         }
 579
 580         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 581         def1 = pt_defaults->bapmti_r;
 582         def2 = pt_defaults->bapmti_rc;
 583
 584         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 585                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 586                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 587                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 588                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 589                                 def1++;
 590                                 def2++;
 591                         }
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int ci_populate_pm_base(struct amdgpu_device *adev)
 599 {
 600         struct ci_power_info *pi = ci_get_pi(adev);
 601         u32 pm_fuse_table_offset;
 602         int ret;
 603
 604         if (pi->caps_power_containment) {
 605                 ret = amdgpu_ci_read_smc_sram_dword(adev,
 606                                              SMU7_FIRMWARE_HEADER_LOCATION +
 607                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 608                                              &pm_fuse_table_offset, pi->sram_end);
 609                 if (ret)
 610                         return ret;
 611                 ret = ci_populate_bapm_vddc_vid_sidd(adev);
 612                 if (ret)
 613                         return ret;
 614                 ret = ci_populate_vddc_vid(adev);
 615                 if (ret)
 616                         return ret;
 617                 ret = ci_populate_svi_load_line(adev);
 618                 if (ret)
 619                         return ret;
 620                 ret = ci_populate_tdc_limit(adev);
 621                 if (ret)
 622                         return ret;
 623                 ret = ci_populate_dw8(adev);
 624                 if (ret)
 625                         return ret;
 626                 ret = ci_populate_fuzzy_fan(adev);
 627                 if (ret)
 628                         return ret;
 629                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
 630                 if (ret)
 631                         return ret;
 632                 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
 633                 if (ret)
 634                         return ret;
 635                 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
 636                                            (u8 *)&pi->smc_powertune_table,
 637                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 638                 if (ret)
 639                         return ret;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
 646 {
 647         struct ci_power_info *pi = ci_get_pi(adev);
 648         u32 data;
 649
 650         if (pi->caps_sq_ramping) {
 651                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 652                 if (enable)
 653                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 654                 else
 655                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 656                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 657         }
 658
 659         if (pi->caps_db_ramping) {
 660                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 661                 if (enable)
 662                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 663                 else
 664                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 665                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 666         }
 667
 668         if (pi->caps_td_ramping) {
 669                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 670                 if (enable)
 671                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 672                 else
 673                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 674                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 675         }
 676
 677         if (pi->caps_tcp_ramping) {
 678                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 679                 if (enable)
 680                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 681                 else
 682                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 683                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 684         }
 685 }
 686
 687 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
 688                                           const struct ci_pt_config_reg *cac_config_regs)
 689 {
 690         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 691         u32 data;
 692         u32 cache = 0;
 693
 694         if (config_regs == NULL)
 695                 return -EINVAL;
 696
 697         while (config_regs->offset != 0xFFFFFFFF) {
 698                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 699                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 700                 } else {
 701                         switch (config_regs->type) {
 702                         case CISLANDS_CONFIGREG_SMC_IND:
 703                                 data = RREG32_SMC(config_regs->offset);
 704                                 break;
 705                         case CISLANDS_CONFIGREG_DIDT_IND:
 706                                 data = RREG32_DIDT(config_regs->offset);
 707                                 break;
 708                         default:
 709                                 data = RREG32(config_regs->offset);
 710                                 break;
 711                         }
 712
 713                         data &= ~config_regs->mask;
 714                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 715                         data |= cache;
 716
 717                         switch (config_regs->type) {
 718                         case CISLANDS_CONFIGREG_SMC_IND:
 719                                 WREG32_SMC(config_regs->offset, data);
 720                                 break;
 721                         case CISLANDS_CONFIGREG_DIDT_IND:
 722                                 WREG32_DIDT(config_regs->offset, data);
 723                                 break;
 724                         default:
 725                                 WREG32(config_regs->offset, data);
 726                                 break;
 727                         }
 728                         cache = 0;
 729                 }
 730                 config_regs++;
 731         }
 732         return 0;
 733 }
 734
 735 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
 736 {
 737         struct ci_power_info *pi = ci_get_pi(adev);
 738         int ret;
 739
 740         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 741             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 742                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 743
 744                 if (enable) {
 745                         ret = ci_program_pt_config_registers(adev, didt_config_ci);
 746                         if (ret) {
 747                                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 748                                 return ret;
 749                         }
 750                 }
 751
 752                 ci_do_enable_didt(adev, enable);
 753
 754                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
 761 {
 762         struct ci_power_info *pi = ci_get_pi(adev);
 763         PPSMC_Result smc_result;
 764         int ret = 0;
 765
 766         if (enable) {
 767                 pi->power_containment_features = 0;
 768                 if (pi->caps_power_containment) {
 769                         if (pi->enable_bapm_feature) {
 770                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
 771                                 if (smc_result != PPSMC_Result_OK)
 772                                         ret = -EINVAL;
 773                                 else
 774                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 775                         }
 776
 777                         if (pi->enable_tdc_limit_feature) {
 778                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
 779                                 if (smc_result != PPSMC_Result_OK)
 780                                         ret = -EINVAL;
 781                                 else
 782                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 783                         }
 784
 785                         if (pi->enable_pkg_pwr_tracking_feature) {
 786                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
 787                                 if (smc_result != PPSMC_Result_OK) {
 788                                         ret = -EINVAL;
 789                                 } else {
 790                                         struct amdgpu_cac_tdp_table *cac_tdp_table =
 791                                                 adev->pm.dpm.dyn_state.cac_tdp_table;
 792                                         u32 default_pwr_limit =
 793                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 794
 795                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 796
 797                                         ci_set_power_limit(adev, default_pwr_limit);
 798                                 }
 799                         }
 800                 }
 801         } else {
 802                 if (pi->caps_power_containment && pi->power_containment_features) {
 803                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 804                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
 805
 806                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 807                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
 808
 809                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 810                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
 811                         pi->power_containment_features = 0;
 812                 }
 813         }
 814
 815         return ret;
 816 }
 817
 818 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 819 {
 820         struct ci_power_info *pi = ci_get_pi(adev);
 821         PPSMC_Result smc_result;
 822         int ret = 0;
 823
 824         if (pi->caps_cac) {
 825                 if (enable) {
 826                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
 827                         if (smc_result != PPSMC_Result_OK) {
 828                                 ret = -EINVAL;
 829                                 pi->cac_enabled = false;
 830                         } else {
 831                                 pi->cac_enabled = true;
 832                         }
 833                 } else if (pi->cac_enabled) {
 834                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
 835                         pi->cac_enabled = false;
 836                 }
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
 843                                             bool enable)
 844 {
 845         struct ci_power_info *pi = ci_get_pi(adev);
 846         PPSMC_Result smc_result = PPSMC_Result_OK;
 847
 848         if (pi->thermal_sclk_dpm_enabled) {
 849                 if (enable)
 850                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
 851                 else
 852                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
 853         }
 854
 855         if (smc_result == PPSMC_Result_OK)
 856                 return 0;
 857         else
 858                 return -EINVAL;
 859 }
 860
 861 static int ci_power_control_set_level(struct amdgpu_device *adev)
 862 {
 863         struct ci_power_info *pi = ci_get_pi(adev);
 864         struct amdgpu_cac_tdp_table *cac_tdp_table =
 865                 adev->pm.dpm.dyn_state.cac_tdp_table;
 866         s32 adjust_percent;
 867         s32 target_tdp;
 868         int ret = 0;
 869         bool adjust_polarity = false; /* ??? */
 870
 871         if (pi->caps_power_containment) {
 872                 adjust_percent = adjust_polarity ?
 873                         adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
 874                 target_tdp = ((100 + adjust_percent) *
 875                               (s32)cac_tdp_table->configurable_tdp) / 100;
 876
 877                 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
 878         }
 879
 880         return ret;
 881 }
 882
 883 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 884 {
 885         struct ci_power_info *pi = ci_get_pi(adev);
 886
 887         if (pi->uvd_power_gated == gate)
 888                 return;
 889
 890         pi->uvd_power_gated = gate;
 891
 892         ci_update_uvd_dpm(adev, gate);
 893 }
 894
 895 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
 896 {
 897         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
 898         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
 899
 900         /* disable mclk switching if the refresh is >120Hz, even if the
 901          * blanking period would allow it
 902          */
 903         if (amdgpu_dpm_get_vrefresh(adev) > 120)
 904                 return true;
 905
 906         if (vblank_time < switch_limit)
 907                 return true;
 908         else
 909                 return false;
 910
 911 }
 912
 913 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
 914                                         struct amdgpu_ps *rps)
 915 {
 916         struct ci_ps *ps = ci_get_ps(rps);
 917         struct ci_power_info *pi = ci_get_pi(adev);
 918         struct amdgpu_clock_and_voltage_limits *max_limits;
 919         bool disable_mclk_switching;
 920         u32 sclk, mclk;
 921         int i;
 922
 923         if (rps->vce_active) {
 924                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
 925                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
 926         } else {
 927                 rps->evclk = 0;
 928                 rps->ecclk = 0;
 929         }
 930
 931         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
 932             ci_dpm_vblank_too_short(adev))
 933                 disable_mclk_switching = true;
 934         else
 935                 disable_mclk_switching = false;
 936
 937         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 938                 pi->battery_state = true;
 939         else
 940                 pi->battery_state = false;
 941
 942         if (adev->pm.dpm.ac_power)
 943                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 944         else
 945                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 946
 947         if (adev->pm.dpm.ac_power == false) {
 948                 for (i = 0; i < ps->performance_level_count; i++) {
 949                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 950                                 ps->performance_levels[i].mclk = max_limits->mclk;
 951                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 952                                 ps->performance_levels[i].sclk = max_limits->sclk;
 953                 }
 954         }
 955
 956         /* XXX validate the min clocks required for display */
 957
 958         if (disable_mclk_switching) {
 959                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 960                 sclk = ps->performance_levels[0].sclk;
 961         } else {
 962                 mclk = ps->performance_levels[0].mclk;
 963                 sclk = ps->performance_levels[0].sclk;
 964         }
 965
 966         if (rps->vce_active) {
 967                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
 968                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
 969                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
 970                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
 971         }
 972
 973         ps->performance_levels[0].sclk = sclk;
 974         ps->performance_levels[0].mclk = mclk;
 975
 976         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 977                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 978
 979         if (disable_mclk_switching) {
 980                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 981                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 982         } else {
 983                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 984                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 985         }
 986 }
 987
 988 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
 989                                             int min_temp, int max_temp)
 990 {
 991         int low_temp = 0 * 1000;
 992         int high_temp = 255 * 1000;
 993         u32 tmp;
 994
 995         if (low_temp < min_temp)
 996                 low_temp = min_temp;
 997         if (high_temp > max_temp)
 998                 high_temp = max_temp;
 999         if (high_temp < low_temp) {
1000                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1001                 return -EINVAL;
1002         }
1003
1004         tmp = RREG32_SMC(ixCG_THERMAL_INT);
1005         tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
1006         tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1007                 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1008         WREG32_SMC(ixCG_THERMAL_INT, tmp);
1009
1010 #if 0
1011         /* XXX: need to figure out how to handle this properly */
1012         tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1013         tmp &= DIG_THERM_DPM_MASK;
1014         tmp |= DIG_THERM_DPM(high_temp / 1000);
1015         WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1016 #endif
1017
1018         adev->pm.dpm.thermal.min_temp = low_temp;
1019         adev->pm.dpm.thermal.max_temp = high_temp;
1020         return 0;
1021 }
1022
1023 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1024                                    bool enable)
1025 {
1026         u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1027         PPSMC_Result result;
1028
1029         if (enable) {
1030                 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1031                                  CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1032                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1033                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1034                 if (result != PPSMC_Result_OK) {
1035                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1036                         return -EINVAL;
1037                 }
1038         } else {
1039                 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1040                         CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1041                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1042                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1043                 if (result != PPSMC_Result_OK) {
1044                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1045                         return -EINVAL;
1046                 }
1047         }
1048
1049         return 0;
1050 }
1051
1052 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1053 {
1054         struct ci_power_info *pi = ci_get_pi(adev);
1055         u32 tmp;
1056
1057         if (pi->fan_ctrl_is_in_default_mode) {
1058                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1059                         >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1060                 pi->fan_ctrl_default_mode = tmp;
1061                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1062                         >> CG_FDO_CTRL2__TMIN__SHIFT;
1063                 pi->t_min = tmp;
1064                 pi->fan_ctrl_is_in_default_mode = false;
1065         }
1066
1067         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1068         tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1069         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1070
1071         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1072         tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1073         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1074 }
1075
1076 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1077 {
1078         struct ci_power_info *pi = ci_get_pi(adev);
1079         SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1080         u32 duty100;
1081         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1082         u16 fdo_min, slope1, slope2;
1083         u32 reference_clock, tmp;
1084         int ret;
1085         u64 tmp64;
1086
1087         if (!pi->fan_table_start) {
1088                 adev->pm.dpm.fan.ucode_fan_control = false;
1089                 return 0;
1090         }
1091
1092         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1093                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1094
1095         if (duty100 == 0) {
1096                 adev->pm.dpm.fan.ucode_fan_control = false;
1097                 return 0;
1098         }
1099
1100         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1101         do_div(tmp64, 10000);
1102         fdo_min = (u16)tmp64;
1103
1104         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1105         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1106
1107         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1108         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1109
1110         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1111         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1112
1113         fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1114         fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1115         fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1116
1117         fan_table.Slope1 = cpu_to_be16(slope1);
1118         fan_table.Slope2 = cpu_to_be16(slope2);
1119
1120         fan_table.FdoMin = cpu_to_be16(fdo_min);
1121
1122         fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1123
1124         fan_table.HystUp = cpu_to_be16(1);
1125
1126         fan_table.HystSlope = cpu_to_be16(1);
1127
1128         fan_table.TempRespLim = cpu_to_be16(5);
1129
1130         reference_clock = amdgpu_asic_get_xclk(adev);
1131
1132         fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1133                                                reference_clock) / 1600);
1134
1135         fan_table.FdoMax = cpu_to_be16((u16)duty100);
1136
1137         tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1138                 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1139         fan_table.TempSrc = (uint8_t)tmp;
1140
1141         ret = amdgpu_ci_copy_bytes_to_smc(adev,
1142                                           pi->fan_table_start,
1143                                           (u8 *)(&fan_table),
1144                                           sizeof(fan_table),
1145                                           pi->sram_end);
1146
1147         if (ret) {
1148                 DRM_ERROR("Failed to load fan table to the SMC.");
1149                 adev->pm.dpm.fan.ucode_fan_control = false;
1150         }
1151
1152         return 0;
1153 }
1154
1155 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1156 {
1157         struct ci_power_info *pi = ci_get_pi(adev);
1158         PPSMC_Result ret;
1159
1160         if (pi->caps_od_fuzzy_fan_control_support) {
1161                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1162                                                                PPSMC_StartFanControl,
1163                                                                FAN_CONTROL_FUZZY);
1164                 if (ret != PPSMC_Result_OK)
1165                         return -EINVAL;
1166                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1167                                                                PPSMC_MSG_SetFanPwmMax,
1168                                                                adev->pm.dpm.fan.default_max_fan_pwm);
1169                 if (ret != PPSMC_Result_OK)
1170                         return -EINVAL;
1171         } else {
1172                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1173                                                                PPSMC_StartFanControl,
1174                                                                FAN_CONTROL_TABLE);
1175                 if (ret != PPSMC_Result_OK)
1176                         return -EINVAL;
1177         }
1178
1179         pi->fan_is_controlled_by_smc = true;
1180         return 0;
1181 }
1182
1183
1184 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1185 {
1186         PPSMC_Result ret;
1187         struct ci_power_info *pi = ci_get_pi(adev);
1188
1189         ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1190         if (ret == PPSMC_Result_OK) {
1191                 pi->fan_is_controlled_by_smc = false;
1192                 return 0;
1193         } else {
1194                 return -EINVAL;
1195         }
1196 }
1197
1198 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1199                                         u32 *speed)
1200 {
1201         u32 duty, duty100;
1202         u64 tmp64;
1203
1204         if (adev->pm.no_fan)
1205                 return -ENOENT;
1206
1207         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1208                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1209         duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1210                 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1211
1212         if (duty100 == 0)
1213                 return -EINVAL;
1214
1215         tmp64 = (u64)duty * 100;
1216         do_div(tmp64, duty100);
1217         *speed = (u32)tmp64;
1218
1219         if (*speed > 100)
1220                 *speed = 100;
1221
1222         return 0;
1223 }
1224
1225 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1226                                         u32 speed)
1227 {
1228         u32 tmp;
1229         u32 duty, duty100;
1230         u64 tmp64;
1231         struct ci_power_info *pi = ci_get_pi(adev);
1232
1233         if (adev->pm.no_fan)
1234                 return -ENOENT;
1235
1236         if (pi->fan_is_controlled_by_smc)
1237                 return -EINVAL;
1238
1239         if (speed > 100)
1240                 return -EINVAL;
1241
1242         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1243                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1244
1245         if (duty100 == 0)
1246                 return -EINVAL;
1247
1248         tmp64 = (u64)speed * duty100;
1249         do_div(tmp64, 100);
1250         duty = (u32)tmp64;
1251
1252         tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1253         tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1254         WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1255
1256         return 0;
1257 }
1258
1259 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1260 {
1261         if (mode) {
1262                 /* stop auto-manage */
1263                 if (adev->pm.dpm.fan.ucode_fan_control)
1264                         ci_fan_ctrl_stop_smc_fan_control(adev);
1265                 ci_fan_ctrl_set_static_mode(adev, mode);
1266         } else {
1267                 /* restart auto-manage */
1268                 if (adev->pm.dpm.fan.ucode_fan_control)
1269                         ci_thermal_start_smc_fan_control(adev);
1270                 else
1271                         ci_fan_ctrl_set_default_mode(adev);
1272         }
1273 }
1274
1275 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1276 {
1277         struct ci_power_info *pi = ci_get_pi(adev);
1278         u32 tmp;
1279
1280         if (pi->fan_is_controlled_by_smc)
1281                 return 0;
1282
1283         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1284         return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
1285 }
1286
1287 #if 0
1288 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1289                                          u32 *speed)
1290 {
1291         u32 tach_period;
1292         u32 xclk = amdgpu_asic_get_xclk(adev);
1293
1294         if (adev->pm.no_fan)
1295                 return -ENOENT;
1296
1297         if (adev->pm.fan_pulses_per_revolution == 0)
1298                 return -ENOENT;
1299
1300         tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1301                 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1302         if (tach_period == 0)
1303                 return -ENOENT;
1304
1305         *speed = 60 * xclk * 10000 / tach_period;
1306
1307         return 0;
1308 }
1309
1310 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1311                                          u32 speed)
1312 {
1313         u32 tach_period, tmp;
1314         u32 xclk = amdgpu_asic_get_xclk(adev);
1315
1316         if (adev->pm.no_fan)
1317                 return -ENOENT;
1318
1319         if (adev->pm.fan_pulses_per_revolution == 0)
1320                 return -ENOENT;
1321
1322         if ((speed < adev->pm.fan_min_rpm) ||
1323             (speed > adev->pm.fan_max_rpm))
1324                 return -EINVAL;
1325
1326         if (adev->pm.dpm.fan.ucode_fan_control)
1327                 ci_fan_ctrl_stop_smc_fan_control(adev);
1328
1329         tach_period = 60 * xclk * 10000 / (8 * speed);
1330         tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1331         tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1332         WREG32_SMC(CG_TACH_CTRL, tmp);
1333
1334         ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1335
1336         return 0;
1337 }
1338 #endif
1339
1340 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1341 {
1342         struct ci_power_info *pi = ci_get_pi(adev);
1343         u32 tmp;
1344
1345         if (!pi->fan_ctrl_is_in_default_mode) {
1346                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1347                 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1348                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1349
1350                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1351                 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1352                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1353                 pi->fan_ctrl_is_in_default_mode = true;
1354         }
1355 }
1356
1357 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1358 {
1359         if (adev->pm.dpm.fan.ucode_fan_control) {
1360                 ci_fan_ctrl_start_smc_fan_control(adev);
1361                 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1362         }
1363 }
1364
1365 static void ci_thermal_initialize(struct amdgpu_device *adev)
1366 {
1367         u32 tmp;
1368
1369         if (adev->pm.fan_pulses_per_revolution) {
1370                 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1371                 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1372                         << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1373                 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1374         }
1375
1376         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1377         tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1378         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1379 }
1380
1381 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1382 {
1383         int ret;
1384
1385         ci_thermal_initialize(adev);
1386         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1387         if (ret)
1388                 return ret;
1389         ret = ci_thermal_enable_alert(adev, true);
1390         if (ret)
1391                 return ret;
1392         if (adev->pm.dpm.fan.ucode_fan_control) {
1393                 ret = ci_thermal_setup_fan_table(adev);
1394                 if (ret)
1395                         return ret;
1396                 ci_thermal_start_smc_fan_control(adev);
1397         }
1398
1399         return 0;
1400 }
1401
1402 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1403 {
1404         if (!adev->pm.no_fan)
1405                 ci_fan_ctrl_set_default_mode(adev);
1406 }
1407
1408 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1409                                      u16 reg_offset, u32 *value)
1410 {
1411         struct ci_power_info *pi = ci_get_pi(adev);
1412
1413         return amdgpu_ci_read_smc_sram_dword(adev,
1414                                       pi->soft_regs_start + reg_offset,
1415                                       value, pi->sram_end);
1416 }
1417
1418 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1419                                       u16 reg_offset, u32 value)
1420 {
1421         struct ci_power_info *pi = ci_get_pi(adev);
1422
1423         return amdgpu_ci_write_smc_sram_dword(adev,
1424                                        pi->soft_regs_start + reg_offset,
1425                                        value, pi->sram_end);
1426 }
1427
1428 static void ci_init_fps_limits(struct amdgpu_device *adev)
1429 {
1430         struct ci_power_info *pi = ci_get_pi(adev);
1431         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1432
1433         if (pi->caps_fps) {
1434                 u16 tmp;
1435
1436                 tmp = 45;
1437                 table->FpsHighT = cpu_to_be16(tmp);
1438
1439                 tmp = 30;
1440                 table->FpsLowT = cpu_to_be16(tmp);
1441         }
1442 }
1443
1444 static int ci_update_sclk_t(struct amdgpu_device *adev)
1445 {
1446         struct ci_power_info *pi = ci_get_pi(adev);
1447         int ret = 0;
1448         u32 low_sclk_interrupt_t = 0;
1449
1450         if (pi->caps_sclk_throttle_low_notification) {
1451                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1452
1453                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1454                                            pi->dpm_table_start +
1455                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1456                                            (u8 *)&low_sclk_interrupt_t,
1457                                            sizeof(u32), pi->sram_end);
1458
1459         }
1460
1461         return ret;
1462 }
1463
1464 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1465 {
1466         struct ci_power_info *pi = ci_get_pi(adev);
1467         u16 leakage_id, virtual_voltage_id;
1468         u16 vddc, vddci;
1469         int i;
1470
1471         pi->vddc_leakage.count = 0;
1472         pi->vddci_leakage.count = 0;
1473
1474         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1475                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1476                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1477                         if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1478                                 continue;
1479                         if (vddc != 0 && vddc != virtual_voltage_id) {
1480                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1481                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1482                                 pi->vddc_leakage.count++;
1483                         }
1484                 }
1485         } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1486                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1487                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1488                         if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1489                                                                                      virtual_voltage_id,
1490                                                                                      leakage_id) == 0) {
1491                                 if (vddc != 0 && vddc != virtual_voltage_id) {
1492                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1493                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1494                                         pi->vddc_leakage.count++;
1495                                 }
1496                                 if (vddci != 0 && vddci != virtual_voltage_id) {
1497                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1498                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1499                                         pi->vddci_leakage.count++;
1500                                 }
1501                         }
1502                 }
1503         }
1504 }
1505
1506 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1507 {
1508         struct ci_power_info *pi = ci_get_pi(adev);
1509         bool want_thermal_protection;
1510         enum amdgpu_dpm_event_src dpm_event_src;
1511         u32 tmp;
1512
1513         switch (sources) {
1514         case 0:
1515         default:
1516                 want_thermal_protection = false;
1517                 break;
1518         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1519                 want_thermal_protection = true;
1520                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1521                 break;
1522         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1523                 want_thermal_protection = true;
1524                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1525                 break;
1526         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1527               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1528                 want_thermal_protection = true;
1529                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1530                 break;
1531         }
1532
1533         if (want_thermal_protection) {
1534 #if 0
1535                 /* XXX: need to figure out how to handle this properly */
1536                 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1537                 tmp &= DPM_EVENT_SRC_MASK;
1538                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1539                 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1540 #endif
1541
1542                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1543                 if (pi->thermal_protection)
1544                         tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1545                 else
1546                         tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1547                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1548         } else {
1549                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1550                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1551                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1552         }
1553 }
1554
1555 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1556                                            enum amdgpu_dpm_auto_throttle_src source,
1557                                            bool enable)
1558 {
1559         struct ci_power_info *pi = ci_get_pi(adev);
1560
1561         if (enable) {
1562                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1563                         pi->active_auto_throttle_sources |= 1 << source;
1564                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1565                 }
1566         } else {
1567                 if (pi->active_auto_throttle_sources & (1 << source)) {
1568                         pi->active_auto_throttle_sources &= ~(1 << source);
1569                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1570                 }
1571         }
1572 }
1573
1574 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1575 {
1576         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1577                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1578 }
1579
1580 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1581 {
1582         struct ci_power_info *pi = ci_get_pi(adev);
1583         PPSMC_Result smc_result;
1584
1585         if (!pi->need_update_smu7_dpm_table)
1586                 return 0;
1587
1588         if ((!pi->sclk_dpm_key_disabled) &&
1589             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1590                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1591                 if (smc_result != PPSMC_Result_OK)
1592                         return -EINVAL;
1593         }
1594
1595         if ((!pi->mclk_dpm_key_disabled) &&
1596             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1597                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1598                 if (smc_result != PPSMC_Result_OK)
1599                         return -EINVAL;
1600         }
1601
1602         pi->need_update_smu7_dpm_table = 0;
1603         return 0;
1604 }
1605
1606 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1607 {
1608         struct ci_power_info *pi = ci_get_pi(adev);
1609         PPSMC_Result smc_result;
1610
1611         if (enable) {
1612                 if (!pi->sclk_dpm_key_disabled) {
1613                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1614                         if (smc_result != PPSMC_Result_OK)
1615                                 return -EINVAL;
1616                 }
1617
1618                 if (!pi->mclk_dpm_key_disabled) {
1619                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1620                         if (smc_result != PPSMC_Result_OK)
1621                                 return -EINVAL;
1622
1623                         WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1624                                         ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1625
1626                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1627                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1628                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1629
1630                         udelay(10);
1631
1632                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1633                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1634                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1635                 }
1636         } else {
1637                 if (!pi->sclk_dpm_key_disabled) {
1638                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1639                         if (smc_result != PPSMC_Result_OK)
1640                                 return -EINVAL;
1641                 }
1642
1643                 if (!pi->mclk_dpm_key_disabled) {
1644                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1645                         if (smc_result != PPSMC_Result_OK)
1646                                 return -EINVAL;
1647                 }
1648         }
1649
1650         return 0;
1651 }
1652
1653 static int ci_start_dpm(struct amdgpu_device *adev)
1654 {
1655         struct ci_power_info *pi = ci_get_pi(adev);
1656         PPSMC_Result smc_result;
1657         int ret;
1658         u32 tmp;
1659
1660         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1661         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1662         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1663
1664         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1665         tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1666         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1667
1668         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1669
1670         WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1671
1672         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1673         if (smc_result != PPSMC_Result_OK)
1674                 return -EINVAL;
1675
1676         ret = ci_enable_sclk_mclk_dpm(adev, true);
1677         if (ret)
1678                 return ret;
1679
1680         if (!pi->pcie_dpm_key_disabled) {
1681                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1682                 if (smc_result != PPSMC_Result_OK)
1683                         return -EINVAL;
1684         }
1685
1686         return 0;
1687 }
1688
1689 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1690 {
1691         struct ci_power_info *pi = ci_get_pi(adev);
1692         PPSMC_Result smc_result;
1693
1694         if (!pi->need_update_smu7_dpm_table)
1695                 return 0;
1696
1697         if ((!pi->sclk_dpm_key_disabled) &&
1698             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1699                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1700                 if (smc_result != PPSMC_Result_OK)
1701                         return -EINVAL;
1702         }
1703
1704         if ((!pi->mclk_dpm_key_disabled) &&
1705             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1706                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1707                 if (smc_result != PPSMC_Result_OK)
1708                         return -EINVAL;
1709         }
1710
1711         return 0;
1712 }
1713
1714 static int ci_stop_dpm(struct amdgpu_device *adev)
1715 {
1716         struct ci_power_info *pi = ci_get_pi(adev);
1717         PPSMC_Result smc_result;
1718         int ret;
1719         u32 tmp;
1720
1721         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1722         tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1723         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1724
1725         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1726         tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1727         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1728
1729         if (!pi->pcie_dpm_key_disabled) {
1730                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1731                 if (smc_result != PPSMC_Result_OK)
1732                         return -EINVAL;
1733         }
1734
1735         ret = ci_enable_sclk_mclk_dpm(adev, false);
1736         if (ret)
1737                 return ret;
1738
1739         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1740         if (smc_result != PPSMC_Result_OK)
1741                 return -EINVAL;
1742
1743         return 0;
1744 }
1745
1746 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1747 {
1748         u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1749
1750         if (enable)
1751                 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1752         else
1753                 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1754         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1755 }
1756
1757 #if 0
1758 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1759                                         bool ac_power)
1760 {
1761         struct ci_power_info *pi = ci_get_pi(adev);
1762         struct amdgpu_cac_tdp_table *cac_tdp_table =
1763                 adev->pm.dpm.dyn_state.cac_tdp_table;
1764         u32 power_limit;
1765
1766         if (ac_power)
1767                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1768         else
1769                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1770
1771         ci_set_power_limit(adev, power_limit);
1772
1773         if (pi->caps_automatic_dc_transition) {
1774                 if (ac_power)
1775                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1776                 else
1777                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1778         }
1779
1780         return 0;
1781 }
1782 #endif
1783
1784 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1785                                                       PPSMC_Msg msg, u32 parameter)
1786 {
1787         WREG32(mmSMC_MSG_ARG_0, parameter);
1788         return amdgpu_ci_send_msg_to_smc(adev, msg);
1789 }
1790
1791 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1792                                                         PPSMC_Msg msg, u32 *parameter)
1793 {
1794         PPSMC_Result smc_result;
1795
1796         smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1797
1798         if ((smc_result == PPSMC_Result_OK) && parameter)
1799                 *parameter = RREG32(mmSMC_MSG_ARG_0);
1800
1801         return smc_result;
1802 }
1803
1804 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1805 {
1806         struct ci_power_info *pi = ci_get_pi(adev);
1807
1808         if (!pi->sclk_dpm_key_disabled) {
1809                 PPSMC_Result smc_result =
1810                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1811                 if (smc_result != PPSMC_Result_OK)
1812                         return -EINVAL;
1813         }
1814
1815         return 0;
1816 }
1817
1818 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1819 {
1820         struct ci_power_info *pi = ci_get_pi(adev);
1821
1822         if (!pi->mclk_dpm_key_disabled) {
1823                 PPSMC_Result smc_result =
1824                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1825                 if (smc_result != PPSMC_Result_OK)
1826                         return -EINVAL;
1827         }
1828
1829         return 0;
1830 }
1831
1832 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1833 {
1834         struct ci_power_info *pi = ci_get_pi(adev);
1835
1836         if (!pi->pcie_dpm_key_disabled) {
1837                 PPSMC_Result smc_result =
1838                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1839                 if (smc_result != PPSMC_Result_OK)
1840                         return -EINVAL;
1841         }
1842
1843         return 0;
1844 }
1845
1846 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1847 {
1848         struct ci_power_info *pi = ci_get_pi(adev);
1849
1850         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1851                 PPSMC_Result smc_result =
1852                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1853                 if (smc_result != PPSMC_Result_OK)
1854                         return -EINVAL;
1855         }
1856
1857         return 0;
1858 }
1859
1860 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1861                                        u32 target_tdp)
1862 {
1863         PPSMC_Result smc_result =
1864                 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1865         if (smc_result != PPSMC_Result_OK)
1866                 return -EINVAL;
1867         return 0;
1868 }
1869
1870 #if 0
1871 static int ci_set_boot_state(struct amdgpu_device *adev)
1872 {
1873         return ci_enable_sclk_mclk_dpm(adev, false);
1874 }
1875 #endif
1876
1877 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1878 {
1879         u32 sclk_freq;
1880         PPSMC_Result smc_result =
1881                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1882                                                     PPSMC_MSG_API_GetSclkFrequency,
1883                                                     &sclk_freq);
1884         if (smc_result != PPSMC_Result_OK)
1885                 sclk_freq = 0;
1886
1887         return sclk_freq;
1888 }
1889
1890 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1891 {
1892         u32 mclk_freq;
1893         PPSMC_Result smc_result =
1894                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1895                                                     PPSMC_MSG_API_GetMclkFrequency,
1896                                                     &mclk_freq);
1897         if (smc_result != PPSMC_Result_OK)
1898                 mclk_freq = 0;
1899
1900         return mclk_freq;
1901 }
1902
1903 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1904 {
1905         int i;
1906
1907         amdgpu_ci_program_jump_on_start(adev);
1908         amdgpu_ci_start_smc_clock(adev);
1909         amdgpu_ci_start_smc(adev);
1910         for (i = 0; i < adev->usec_timeout; i++) {
1911                 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1912                         break;
1913         }
1914 }
1915
1916 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1917 {
1918         amdgpu_ci_reset_smc(adev);
1919         amdgpu_ci_stop_smc_clock(adev);
1920 }
1921
1922 static int ci_process_firmware_header(struct amdgpu_device *adev)
1923 {
1924         struct ci_power_info *pi = ci_get_pi(adev);
1925         u32 tmp;
1926         int ret;
1927
1928         ret = amdgpu_ci_read_smc_sram_dword(adev,
1929                                      SMU7_FIRMWARE_HEADER_LOCATION +
1930                                      offsetof(SMU7_Firmware_Header, DpmTable),
1931                                      &tmp, pi->sram_end);
1932         if (ret)
1933                 return ret;
1934
1935         pi->dpm_table_start = tmp;
1936
1937         ret = amdgpu_ci_read_smc_sram_dword(adev,
1938                                      SMU7_FIRMWARE_HEADER_LOCATION +
1939                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1940                                      &tmp, pi->sram_end);
1941         if (ret)
1942                 return ret;
1943
1944         pi->soft_regs_start = tmp;
1945
1946         ret = amdgpu_ci_read_smc_sram_dword(adev,
1947                                      SMU7_FIRMWARE_HEADER_LOCATION +
1948                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1949                                      &tmp, pi->sram_end);
1950         if (ret)
1951                 return ret;
1952
1953         pi->mc_reg_table_start = tmp;
1954
1955         ret = amdgpu_ci_read_smc_sram_dword(adev,
1956                                      SMU7_FIRMWARE_HEADER_LOCATION +
1957                                      offsetof(SMU7_Firmware_Header, FanTable),
1958                                      &tmp, pi->sram_end);
1959         if (ret)
1960                 return ret;
1961
1962         pi->fan_table_start = tmp;
1963
1964         ret = amdgpu_ci_read_smc_sram_dword(adev,
1965                                      SMU7_FIRMWARE_HEADER_LOCATION +
1966                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1967                                      &tmp, pi->sram_end);
1968         if (ret)
1969                 return ret;
1970
1971         pi->arb_table_start = tmp;
1972
1973         return 0;
1974 }
1975
1976 static void ci_read_clock_registers(struct amdgpu_device *adev)
1977 {
1978         struct ci_power_info *pi = ci_get_pi(adev);
1979
1980         pi->clock_registers.cg_spll_func_cntl =
1981                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1982         pi->clock_registers.cg_spll_func_cntl_2 =
1983                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1984         pi->clock_registers.cg_spll_func_cntl_3 =
1985                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
1986         pi->clock_registers.cg_spll_func_cntl_4 =
1987                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
1988         pi->clock_registers.cg_spll_spread_spectrum =
1989                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
1990         pi->clock_registers.cg_spll_spread_spectrum_2 =
1991                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
1992         pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
1993         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
1994         pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
1995         pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
1996         pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
1997         pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
1998         pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
1999         pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
2000         pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
2001 }
2002
2003 static void ci_init_sclk_t(struct amdgpu_device *adev)
2004 {
2005         struct ci_power_info *pi = ci_get_pi(adev);
2006
2007         pi->low_sclk_interrupt_t = 0;
2008 }
2009
2010 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2011                                          bool enable)
2012 {
2013         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2014
2015         if (enable)
2016                 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2017         else
2018                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2019         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2020 }
2021
2022 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2023 {
2024         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2025
2026         tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2027
2028         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2029 }
2030
2031 #if 0
2032 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2033 {
2034
2035         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2036
2037         udelay(25000);
2038
2039         return 0;
2040 }
2041
2042 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2043 {
2044         int i;
2045
2046         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2047
2048         udelay(7000);
2049
2050         for (i = 0; i < adev->usec_timeout; i++) {
2051                 if (RREG32(mmSMC_RESP_0) == 1)
2052                         break;
2053                 udelay(1000);
2054         }
2055
2056         return 0;
2057 }
2058 #endif
2059
2060 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2061                                         bool has_display)
2062 {
2063         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2064
2065         return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
2066 }
2067
2068 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2069                                       bool enable)
2070 {
2071         struct ci_power_info *pi = ci_get_pi(adev);
2072
2073         if (enable) {
2074                 if (pi->caps_sclk_ds) {
2075                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2076                                 return -EINVAL;
2077                 } else {
2078                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2079                                 return -EINVAL;
2080                 }
2081         } else {
2082                 if (pi->caps_sclk_ds) {
2083                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2084                                 return -EINVAL;
2085                 }
2086         }
2087
2088         return 0;
2089 }
2090
2091 static void ci_program_display_gap(struct amdgpu_device *adev)
2092 {
2093         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2094         u32 pre_vbi_time_in_us;
2095         u32 frame_time_in_us;
2096         u32 ref_clock = adev->clock.spll.reference_freq;
2097         u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2098         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2099
2100         tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2101         if (adev->pm.dpm.new_active_crtc_count > 0)
2102                 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2103         else
2104                 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2105         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2106
2107         if (refresh_rate == 0)
2108                 refresh_rate = 60;
2109         if (vblank_time == 0xffffffff)
2110                 vblank_time = 500;
2111         frame_time_in_us = 1000000 / refresh_rate;
2112         pre_vbi_time_in_us =
2113                 frame_time_in_us - 200 - vblank_time;
2114         tmp = pre_vbi_time_in_us * (ref_clock / 100);
2115
2116         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2117         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2118         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2119
2120
2121         ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2122
2123 }
2124
2125 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2126 {
2127         struct ci_power_info *pi = ci_get_pi(adev);
2128         u32 tmp;
2129
2130         if (enable) {
2131                 if (pi->caps_sclk_ss_support) {
2132                         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2133                         tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2134                         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2135                 }
2136         } else {
2137                 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2138                 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2139                 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2140
2141                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2142                 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2143                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2144         }
2145 }
2146
2147 static void ci_program_sstp(struct amdgpu_device *adev)
2148 {
2149         WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2150         ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2151          (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2152 }
2153
2154 static void ci_enable_display_gap(struct amdgpu_device *adev)
2155 {
2156         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2157
2158         tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2159                         CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2160         tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2161                 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2162
2163         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2164 }
2165
2166 static void ci_program_vc(struct amdgpu_device *adev)
2167 {
2168         u32 tmp;
2169
2170         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2171         tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2172         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2173
2174         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2175         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2176         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2177         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2178         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2179         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2180         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2181         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2182 }
2183
2184 static void ci_clear_vc(struct amdgpu_device *adev)
2185 {
2186         u32 tmp;
2187
2188         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2189         tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2190         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2191
2192         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2193         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2194         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2195         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2196         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2197         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2198         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2199         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2200 }
2201
2202 static int ci_upload_firmware(struct amdgpu_device *adev)
2203 {
2204         struct ci_power_info *pi = ci_get_pi(adev);
2205         int i, ret;
2206
2207         for (i = 0; i < adev->usec_timeout; i++) {
2208                 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2209                         break;
2210         }
2211         WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2212
2213         amdgpu_ci_stop_smc_clock(adev);
2214         amdgpu_ci_reset_smc(adev);
2215
2216         ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end);
2217
2218         return ret;
2219
2220 }
2221
2222 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2223                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2224                                      struct atom_voltage_table *voltage_table)
2225 {
2226         u32 i;
2227
2228         if (voltage_dependency_table == NULL)
2229                 return -EINVAL;
2230
2231         voltage_table->mask_low = 0;
2232         voltage_table->phase_delay = 0;
2233
2234         voltage_table->count = voltage_dependency_table->count;
2235         for (i = 0; i < voltage_table->count; i++) {
2236                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2237                 voltage_table->entries[i].smio_low = 0;
2238         }
2239
2240         return 0;
2241 }
2242
2243 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2244 {
2245         struct ci_power_info *pi = ci_get_pi(adev);
2246         int ret;
2247
2248         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2249                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2250                                                         VOLTAGE_OBJ_GPIO_LUT,
2251                                                         &pi->vddc_voltage_table);
2252                 if (ret)
2253                         return ret;
2254         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2255                 ret = ci_get_svi2_voltage_table(adev,
2256                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2257                                                 &pi->vddc_voltage_table);
2258                 if (ret)
2259                         return ret;
2260         }
2261
2262         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2263                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2264                                                          &pi->vddc_voltage_table);
2265
2266         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2267                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2268                                                         VOLTAGE_OBJ_GPIO_LUT,
2269                                                         &pi->vddci_voltage_table);
2270                 if (ret)
2271                         return ret;
2272         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2273                 ret = ci_get_svi2_voltage_table(adev,
2274                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2275                                                 &pi->vddci_voltage_table);
2276                 if (ret)
2277                         return ret;
2278         }
2279
2280         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2281                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2282                                                          &pi->vddci_voltage_table);
2283
2284         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2285                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2286                                                         VOLTAGE_OBJ_GPIO_LUT,
2287                                                         &pi->mvdd_voltage_table);
2288                 if (ret)
2289                         return ret;
2290         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2291                 ret = ci_get_svi2_voltage_table(adev,
2292                                                 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2293                                                 &pi->mvdd_voltage_table);
2294                 if (ret)
2295                         return ret;
2296         }
2297
2298         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2299                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2300                                                          &pi->mvdd_voltage_table);
2301
2302         return 0;
2303 }
2304
2305 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2306                                           struct atom_voltage_table_entry *voltage_table,
2307                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
2308 {
2309         int ret;
2310
2311         ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2312                                             &smc_voltage_table->StdVoltageHiSidd,
2313                                             &smc_voltage_table->StdVoltageLoSidd);
2314
2315         if (ret) {
2316                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2317                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2318         }
2319
2320         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2321         smc_voltage_table->StdVoltageHiSidd =
2322                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2323         smc_voltage_table->StdVoltageLoSidd =
2324                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2325 }
2326
2327 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2328                                       SMU7_Discrete_DpmTable *table)
2329 {
2330         struct ci_power_info *pi = ci_get_pi(adev);
2331         unsigned int count;
2332
2333         table->VddcLevelCount = pi->vddc_voltage_table.count;
2334         for (count = 0; count < table->VddcLevelCount; count++) {
2335                 ci_populate_smc_voltage_table(adev,
2336                                               &pi->vddc_voltage_table.entries[count],
2337                                               &table->VddcLevel[count]);
2338
2339                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2340                         table->VddcLevel[count].Smio |=
2341                                 pi->vddc_voltage_table.entries[count].smio_low;
2342                 else
2343                         table->VddcLevel[count].Smio = 0;
2344         }
2345         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2346
2347         return 0;
2348 }
2349
2350 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2351                                        SMU7_Discrete_DpmTable *table)
2352 {
2353         unsigned int count;
2354         struct ci_power_info *pi = ci_get_pi(adev);
2355
2356         table->VddciLevelCount = pi->vddci_voltage_table.count;
2357         for (count = 0; count < table->VddciLevelCount; count++) {
2358                 ci_populate_smc_voltage_table(adev,
2359                                               &pi->vddci_voltage_table.entries[count],
2360                                               &table->VddciLevel[count]);
2361
2362                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2363                         table->VddciLevel[count].Smio |=
2364                                 pi->vddci_voltage_table.entries[count].smio_low;
2365                 else
2366                         table->VddciLevel[count].Smio = 0;
2367         }
2368         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2369
2370         return 0;
2371 }
2372
2373 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2374                                       SMU7_Discrete_DpmTable *table)
2375 {
2376         struct ci_power_info *pi = ci_get_pi(adev);
2377         unsigned int count;
2378
2379         table->MvddLevelCount = pi->mvdd_voltage_table.count;
2380         for (count = 0; count < table->MvddLevelCount; count++) {
2381                 ci_populate_smc_voltage_table(adev,
2382                                               &pi->mvdd_voltage_table.entries[count],
2383                                               &table->MvddLevel[count]);
2384
2385                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2386                         table->MvddLevel[count].Smio |=
2387                                 pi->mvdd_voltage_table.entries[count].smio_low;
2388                 else
2389                         table->MvddLevel[count].Smio = 0;
2390         }
2391         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2392
2393         return 0;
2394 }
2395
2396 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2397                                           SMU7_Discrete_DpmTable *table)
2398 {
2399         int ret;
2400
2401         ret = ci_populate_smc_vddc_table(adev, table);
2402         if (ret)
2403                 return ret;
2404
2405         ret = ci_populate_smc_vddci_table(adev, table);
2406         if (ret)
2407                 return ret;
2408
2409         ret = ci_populate_smc_mvdd_table(adev, table);
2410         if (ret)
2411                 return ret;
2412
2413         return 0;
2414 }
2415
2416 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2417                                   SMU7_Discrete_VoltageLevel *voltage)
2418 {
2419         struct ci_power_info *pi = ci_get_pi(adev);
2420         u32 i = 0;
2421
2422         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2423                 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2424                         if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2425                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2426                                 break;
2427                         }
2428                 }
2429
2430                 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2431                         return -EINVAL;
2432         }
2433
2434         return -EINVAL;
2435 }
2436
2437 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2438                                          struct atom_voltage_table_entry *voltage_table,
2439                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2440 {
2441         u16 v_index, idx;
2442         bool voltage_found = false;
2443         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2444         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2445
2446         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2447                 return -EINVAL;
2448
2449         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2450                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2451                         if (voltage_table->value ==
2452                             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2453                                 voltage_found = true;
2454                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2455                                         idx = v_index;
2456                                 else
2457                                         idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2458                                 *std_voltage_lo_sidd =
2459                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2460                                 *std_voltage_hi_sidd =
2461                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2462                                 break;
2463                         }
2464                 }
2465
2466                 if (!voltage_found) {
2467                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2468                                 if (voltage_table->value <=
2469                                     adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2470                                         voltage_found = true;
2471                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2472                                                 idx = v_index;
2473                                         else
2474                                                 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2475                                         *std_voltage_lo_sidd =
2476                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2477                                         *std_voltage_hi_sidd =
2478                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2479                                         break;
2480                                 }
2481                         }
2482                 }
2483         }
2484
2485         return 0;
2486 }
2487
2488 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2489                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2490                                                   u32 sclk,
2491                                                   u32 *phase_shedding)
2492 {
2493         unsigned int i;
2494
2495         *phase_shedding = 1;
2496
2497         for (i = 0; i < limits->count; i++) {
2498                 if (sclk < limits->entries[i].sclk) {
2499                         *phase_shedding = i;
2500                         break;
2501                 }
2502         }
2503 }
2504
2505 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2506                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2507                                                   u32 mclk,
2508                                                   u32 *phase_shedding)
2509 {
2510         unsigned int i;
2511
2512         *phase_shedding = 1;
2513
2514         for (i = 0; i < limits->count; i++) {
2515                 if (mclk < limits->entries[i].mclk) {
2516                         *phase_shedding = i;
2517                         break;
2518                 }
2519         }
2520 }
2521
2522 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2523 {
2524         struct ci_power_info *pi = ci_get_pi(adev);
2525         u32 tmp;
2526         int ret;
2527
2528         ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2529                                      &tmp, pi->sram_end);
2530         if (ret)
2531                 return ret;
2532
2533         tmp &= 0x00FFFFFF;
2534         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2535
2536         return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2537                                        tmp, pi->sram_end);
2538 }
2539
2540 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2541                                          struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2542                                          u32 clock, u32 *voltage)
2543 {
2544         u32 i = 0;
2545
2546         if (allowed_clock_voltage_table->count == 0)
2547                 return -EINVAL;
2548
2549         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2550                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2551                         *voltage = allowed_clock_voltage_table->entries[i].v;
2552                         return 0;
2553                 }
2554         }
2555
2556         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2557
2558         return 0;
2559 }
2560
2561 static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2562 {
2563         u32 i;
2564         u32 tmp;
2565         u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2566
2567         if (sclk < min)
2568                 return 0;
2569
2570         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2571                 tmp = sclk >> i;
2572                 if (tmp >= min || i == 0)
2573                         break;
2574         }
2575
2576         return (u8)i;
2577 }
2578
2579 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2580 {
2581         return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2582 }
2583
2584 static int ci_reset_to_default(struct amdgpu_device *adev)
2585 {
2586         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2587                 0 : -EINVAL;
2588 }
2589
2590 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2591 {
2592         u32 tmp;
2593
2594         tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2595
2596         if (tmp == MC_CG_ARB_FREQ_F0)
2597                 return 0;
2598
2599         return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2600 }
2601
2602 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2603                                         const u32 engine_clock,
2604                                         const u32 memory_clock,
2605                                         u32 *dram_timimg2)
2606 {
2607         bool patch;
2608         u32 tmp, tmp2;
2609
2610         tmp = RREG32(mmMC_SEQ_MISC0);
2611         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2612
2613         if (patch &&
2614             ((adev->pdev->device == 0x67B0) ||
2615              (adev->pdev->device == 0x67B1))) {
2616                 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2617                         tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2618                         *dram_timimg2 &= ~0x00ff0000;
2619                         *dram_timimg2 |= tmp2 << 16;
2620                 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2621                         tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2622                         *dram_timimg2 &= ~0x00ff0000;
2623                         *dram_timimg2 |= tmp2 << 16;
2624                 }
2625         }
2626 }
2627
2628 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2629                                                 u32 sclk,
2630                                                 u32 mclk,
2631                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2632 {
2633         u32 dram_timing;
2634         u32 dram_timing2;
2635         u32 burst_time;
2636
2637         amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2638
2639         dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
2640         dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2641         burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2642
2643         ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2644
2645         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2646         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2647         arb_regs->McArbBurstTime = (u8)burst_time;
2648
2649         return 0;
2650 }
2651
2652 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2653 {
2654         struct ci_power_info *pi = ci_get_pi(adev);
2655         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2656         u32 i, j;
2657         int ret =  0;
2658
2659         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2660
2661         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2662                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2663                         ret = ci_populate_memory_timing_parameters(adev,
2664                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2665                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2666                                                                    &arb_regs.entries[i][j]);
2667                         if (ret)
2668                                 break;
2669                 }
2670         }
2671
2672         if (ret == 0)
2673                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2674                                            pi->arb_table_start,
2675                                            (u8 *)&arb_regs,
2676                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2677                                            pi->sram_end);
2678
2679         return ret;
2680 }
2681
2682 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2683 {
2684         struct ci_power_info *pi = ci_get_pi(adev);
2685
2686         if (pi->need_update_smu7_dpm_table == 0)
2687                 return 0;
2688
2689         return ci_do_program_memory_timing_parameters(adev);
2690 }
2691
2692 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2693                                           struct amdgpu_ps *amdgpu_boot_state)
2694 {
2695         struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2696         struct ci_power_info *pi = ci_get_pi(adev);
2697         u32 level = 0;
2698
2699         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2700                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2701                     boot_state->performance_levels[0].sclk) {
2702                         pi->smc_state_table.GraphicsBootLevel = level;
2703                         break;
2704                 }
2705         }
2706
2707         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2708                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2709                     boot_state->performance_levels[0].mclk) {
2710                         pi->smc_state_table.MemoryBootLevel = level;
2711                         break;
2712                 }
2713         }
2714 }
2715
2716 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2717 {
2718         u32 i;
2719         u32 mask_value = 0;
2720
2721         for (i = dpm_table->count; i > 0; i--) {
2722                 mask_value = mask_value << 1;
2723                 if (dpm_table->dpm_levels[i-1].enabled)
2724                         mask_value |= 0x1;
2725                 else
2726                         mask_value &= 0xFFFFFFFE;
2727         }
2728
2729         return mask_value;
2730 }
2731
2732 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2733                                        SMU7_Discrete_DpmTable *table)
2734 {
2735         struct ci_power_info *pi = ci_get_pi(adev);
2736         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2737         u32 i;
2738
2739         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2740                 table->LinkLevel[i].PcieGenSpeed =
2741                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2742                 table->LinkLevel[i].PcieLaneCount =
2743                         amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2744                 table->LinkLevel[i].EnabledForActivity = 1;
2745                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2746                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2747         }
2748
2749         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2750         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2751                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2752 }
2753
2754 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2755                                      SMU7_Discrete_DpmTable *table)
2756 {
2757         u32 count;
2758         struct atom_clock_dividers dividers;
2759         int ret = -EINVAL;
2760
2761         table->UvdLevelCount =
2762                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2763
2764         for (count = 0; count < table->UvdLevelCount; count++) {
2765                 table->UvdLevel[count].VclkFrequency =
2766                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2767                 table->UvdLevel[count].DclkFrequency =
2768                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2769                 table->UvdLevel[count].MinVddc =
2770                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2771                 table->UvdLevel[count].MinVddcPhases = 1;
2772
2773                 ret = amdgpu_atombios_get_clock_dividers(adev,
2774                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2775                                                          table->UvdLevel[count].VclkFrequency, false, &dividers);
2776                 if (ret)
2777                         return ret;
2778
2779                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2780
2781                 ret = amdgpu_atombios_get_clock_dividers(adev,
2782                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2783                                                          table->UvdLevel[count].DclkFrequency, false, &dividers);
2784                 if (ret)
2785                         return ret;
2786
2787                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2788
2789                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2790                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2791                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2792         }
2793
2794         return ret;
2795 }
2796
2797 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2798                                      SMU7_Discrete_DpmTable *table)
2799 {
2800         u32 count;
2801         struct atom_clock_dividers dividers;
2802         int ret = -EINVAL;
2803
2804         table->VceLevelCount =
2805                 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2806
2807         for (count = 0; count < table->VceLevelCount; count++) {
2808                 table->VceLevel[count].Frequency =
2809                         adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2810                 table->VceLevel[count].MinVoltage =
2811                         (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2812                 table->VceLevel[count].MinPhases = 1;
2813
2814                 ret = amdgpu_atombios_get_clock_dividers(adev,
2815                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2816                                                          table->VceLevel[count].Frequency, false, &dividers);
2817                 if (ret)
2818                         return ret;
2819
2820                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2821
2822                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2823                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2824         }
2825
2826         return ret;
2827
2828 }
2829
2830 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2831                                      SMU7_Discrete_DpmTable *table)
2832 {
2833         u32 count;
2834         struct atom_clock_dividers dividers;
2835         int ret = -EINVAL;
2836
2837         table->AcpLevelCount = (u8)
2838                 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2839
2840         for (count = 0; count < table->AcpLevelCount; count++) {
2841                 table->AcpLevel[count].Frequency =
2842                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2843                 table->AcpLevel[count].MinVoltage =
2844                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2845                 table->AcpLevel[count].MinPhases = 1;
2846
2847                 ret = amdgpu_atombios_get_clock_dividers(adev,
2848                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2849                                                          table->AcpLevel[count].Frequency, false, &dividers);
2850                 if (ret)
2851                         return ret;
2852
2853                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2854
2855                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2856                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2857         }
2858
2859         return ret;
2860 }
2861
2862 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2863                                       SMU7_Discrete_DpmTable *table)
2864 {
2865         u32 count;
2866         struct atom_clock_dividers dividers;
2867         int ret = -EINVAL;
2868
2869         table->SamuLevelCount =
2870                 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2871
2872         for (count = 0; count < table->SamuLevelCount; count++) {
2873                 table->SamuLevel[count].Frequency =
2874                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2875                 table->SamuLevel[count].MinVoltage =
2876                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2877                 table->SamuLevel[count].MinPhases = 1;
2878
2879                 ret = amdgpu_atombios_get_clock_dividers(adev,
2880                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2881                                                          table->SamuLevel[count].Frequency, false, &dividers);
2882                 if (ret)
2883                         return ret;
2884
2885                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2886
2887                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2888                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2889         }
2890
2891         return ret;
2892 }
2893
2894 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2895                                     u32 memory_clock,
2896                                     SMU7_Discrete_MemoryLevel *mclk,
2897                                     bool strobe_mode,
2898                                     bool dll_state_on)
2899 {
2900         struct ci_power_info *pi = ci_get_pi(adev);
2901         u32  dll_cntl = pi->clock_registers.dll_cntl;
2902         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2903         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2904         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2905         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2906         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2907         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2908         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2909         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2910         struct atom_mpll_param mpll_param;
2911         int ret;
2912
2913         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2914         if (ret)
2915                 return ret;
2916
2917         mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2918         mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2919
2920         mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2921                         MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2922         mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2923                 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2924                 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2925
2926         mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2927         mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2928
2929         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2930                 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2931                                 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2932                 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2933                                 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2934         }
2935
2936         if (pi->caps_mclk_ss_support) {
2937                 struct amdgpu_atom_ss ss;
2938                 u32 freq_nom;
2939                 u32 tmp;
2940                 u32 reference_clock = adev->clock.mpll.reference_freq;
2941
2942                 if (mpll_param.qdr == 1)
2943                         freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2944                 else
2945                         freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2946
2947                 tmp = (freq_nom / reference_clock);
2948                 tmp = tmp * tmp;
2949                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2950                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2951                         u32 clks = reference_clock * 5 / ss.rate;
2952                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2953
2954                         mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2955                         mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2956
2957                         mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2958                         mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2959                 }
2960         }
2961
2962         mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2963         mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2964
2965         if (dll_state_on)
2966                 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2967                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2968         else
2969                 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2970                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2971
2972         mclk->MclkFrequency = memory_clock;
2973         mclk->MpllFuncCntl = mpll_func_cntl;
2974         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2975         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2976         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2977         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2978         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2979         mclk->DllCntl = dll_cntl;
2980         mclk->MpllSs1 = mpll_ss1;
2981         mclk->MpllSs2 = mpll_ss2;
2982
2983         return 0;
2984 }
2985
2986 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
2987                                            u32 memory_clock,
2988                                            SMU7_Discrete_MemoryLevel *memory_level)
2989 {
2990         struct ci_power_info *pi = ci_get_pi(adev);
2991         int ret;
2992         bool dll_state_on;
2993
2994         if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2995                 ret = ci_get_dependency_volt_by_clk(adev,
2996                                                     &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2997                                                     memory_clock, &memory_level->MinVddc);
2998                 if (ret)
2999                         return ret;
3000         }
3001
3002         if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
3003                 ret = ci_get_dependency_volt_by_clk(adev,
3004                                                     &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3005                                                     memory_clock, &memory_level->MinVddci);
3006                 if (ret)
3007                         return ret;
3008         }
3009
3010         if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3011                 ret = ci_get_dependency_volt_by_clk(adev,
3012                                                     &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3013                                                     memory_clock, &memory_level->MinMvdd);
3014                 if (ret)
3015                         return ret;
3016         }
3017
3018         memory_level->MinVddcPhases = 1;
3019
3020         if (pi->vddc_phase_shed_control)
3021                 ci_populate_phase_value_based_on_mclk(adev,
3022                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3023                                                       memory_clock,
3024                                                       &memory_level->MinVddcPhases);
3025
3026         memory_level->EnabledForThrottle = 1;
3027         memory_level->UpH = 0;
3028         memory_level->DownH = 100;
3029         memory_level->VoltageDownH = 0;
3030         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3031
3032         memory_level->StutterEnable = false;
3033         memory_level->StrobeEnable = false;
3034         memory_level->EdcReadEnable = false;
3035         memory_level->EdcWriteEnable = false;
3036         memory_level->RttEnable = false;
3037
3038         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3039
3040         if (pi->mclk_stutter_mode_threshold &&
3041             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3042             (!pi->uvd_enabled) &&
3043             (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3044             (adev->pm.dpm.new_active_crtc_count <= 2))
3045                 memory_level->StutterEnable = true;
3046
3047         if (pi->mclk_strobe_mode_threshold &&
3048             (memory_clock <= pi->mclk_strobe_mode_threshold))
3049                 memory_level->StrobeEnable = 1;
3050
3051         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3052                 memory_level->StrobeRatio =
3053                         ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3054                 if (pi->mclk_edc_enable_threshold &&
3055                     (memory_clock > pi->mclk_edc_enable_threshold))
3056                         memory_level->EdcReadEnable = true;
3057
3058                 if (pi->mclk_edc_wr_enable_threshold &&
3059                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
3060                         memory_level->EdcWriteEnable = true;
3061
3062                 if (memory_level->StrobeEnable) {
3063                         if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3064                             ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3065                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3066                         else
3067                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3068                 } else {
3069                         dll_state_on = pi->dll_default_on;
3070                 }
3071         } else {
3072                 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3073                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3074         }
3075
3076         ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3077         if (ret)
3078                 return ret;
3079
3080         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3081         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3082         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3083         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3084
3085         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3086         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3087         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3088         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3089         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3090         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3091         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3092         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3093         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3094         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3095         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3096
3097         return 0;
3098 }
3099
3100 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3101                                       SMU7_Discrete_DpmTable *table)
3102 {
3103         struct ci_power_info *pi = ci_get_pi(adev);
3104         struct atom_clock_dividers dividers;
3105         SMU7_Discrete_VoltageLevel voltage_level;
3106         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3107         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3108         u32 dll_cntl = pi->clock_registers.dll_cntl;
3109         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3110         int ret;
3111
3112         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3113
3114         if (pi->acpi_vddc)
3115                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3116         else
3117                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3118
3119         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3120
3121         table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3122
3123         ret = amdgpu_atombios_get_clock_dividers(adev,
3124                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3125                                                  table->ACPILevel.SclkFrequency, false, &dividers);
3126         if (ret)
3127                 return ret;
3128
3129         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3130         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3131         table->ACPILevel.DeepSleepDivId = 0;
3132
3133         spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3134         spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3135
3136         spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3137         spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3138
3139         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3140         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3141         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3142         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3143         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3144         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3145         table->ACPILevel.CcPwrDynRm = 0;
3146         table->ACPILevel.CcPwrDynRm1 = 0;
3147
3148         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3149         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3150         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3151         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3152         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3153         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3154         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3155         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3156         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3157         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3158         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3159
3160         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3161         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3162
3163         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3164                 if (pi->acpi_vddci)
3165                         table->MemoryACPILevel.MinVddci =
3166                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3167                 else
3168                         table->MemoryACPILevel.MinVddci =
3169                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3170         }
3171
3172         if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3173                 table->MemoryACPILevel.MinMvdd = 0;
3174         else
3175                 table->MemoryACPILevel.MinMvdd =
3176                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3177
3178         mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3179                 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3180         mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3181                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3182
3183         dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3184
3185         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3186         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3187         table->MemoryACPILevel.MpllAdFuncCntl =
3188                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3189         table->MemoryACPILevel.MpllDqFuncCntl =
3190                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3191         table->MemoryACPILevel.MpllFuncCntl =
3192                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3193         table->MemoryACPILevel.MpllFuncCntl_1 =
3194                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3195         table->MemoryACPILevel.MpllFuncCntl_2 =
3196                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3197         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3198         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3199
3200         table->MemoryACPILevel.EnabledForThrottle = 0;
3201         table->MemoryACPILevel.EnabledForActivity = 0;
3202         table->MemoryACPILevel.UpH = 0;
3203         table->MemoryACPILevel.DownH = 100;
3204         table->MemoryACPILevel.VoltageDownH = 0;
3205         table->MemoryACPILevel.ActivityLevel =
3206                 cpu_to_be16((u16)pi->mclk_activity_target);
3207
3208         table->MemoryACPILevel.StutterEnable = false;
3209         table->MemoryACPILevel.StrobeEnable = false;
3210         table->MemoryACPILevel.EdcReadEnable = false;
3211         table->MemoryACPILevel.EdcWriteEnable = false;
3212         table->MemoryACPILevel.RttEnable = false;
3213
3214         return 0;
3215 }
3216
3217
3218 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3219 {
3220         struct ci_power_info *pi = ci_get_pi(adev);
3221         struct ci_ulv_parm *ulv = &pi->ulv;
3222
3223         if (ulv->supported) {
3224                 if (enable)
3225                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3226                                 0 : -EINVAL;
3227                 else
3228                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3229                                 0 : -EINVAL;
3230         }
3231
3232         return 0;
3233 }
3234
3235 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3236                                  SMU7_Discrete_Ulv *state)
3237 {
3238         struct ci_power_info *pi = ci_get_pi(adev);
3239         u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3240
3241         state->CcPwrDynRm = 0;
3242         state->CcPwrDynRm1 = 0;
3243
3244         if (ulv_voltage == 0) {
3245                 pi->ulv.supported = false;
3246                 return 0;
3247         }
3248
3249         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3250                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3251                         state->VddcOffset = 0;
3252                 else
3253                         state->VddcOffset =
3254                                 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3255         } else {
3256                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3257                         state->VddcOffsetVid = 0;
3258                 else
3259                         state->VddcOffsetVid = (u8)
3260                                 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3261                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3262         }
3263         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3264
3265         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3266         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3267         state->VddcOffset = cpu_to_be16(state->VddcOffset);
3268
3269         return 0;
3270 }
3271
3272 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3273                                     u32 engine_clock,
3274                                     SMU7_Discrete_GraphicsLevel *sclk)
3275 {
3276         struct ci_power_info *pi = ci_get_pi(adev);
3277         struct atom_clock_dividers dividers;
3278         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3279         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3280         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3281         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3282         u32 reference_clock = adev->clock.spll.reference_freq;
3283         u32 reference_divider;
3284         u32 fbdiv;
3285         int ret;
3286
3287         ret = amdgpu_atombios_get_clock_dividers(adev,
3288                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3289                                                  engine_clock, false, &dividers);
3290         if (ret)
3291                 return ret;
3292
3293         reference_divider = 1 + dividers.ref_div;
3294         fbdiv = dividers.fb_div & 0x3FFFFFF;
3295
3296         spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3297         spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3298         spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3299
3300         if (pi->caps_sclk_ss_support) {
3301                 struct amdgpu_atom_ss ss;
3302                 u32 vco_freq = engine_clock * dividers.post_div;
3303
3304                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3305                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3306                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3307                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3308
3309                         cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3310                         cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3311                         cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3312
3313                         cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3314                         cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3315                 }
3316         }
3317
3318         sclk->SclkFrequency = engine_clock;
3319         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3320         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3321         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3322         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
3323         sclk->SclkDid = (u8)dividers.post_divider;
3324
3325         return 0;
3326 }
3327
3328 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3329                                             u32 engine_clock,
3330                                             u16 sclk_activity_level_t,
3331                                             SMU7_Discrete_GraphicsLevel *graphic_level)
3332 {
3333         struct ci_power_info *pi = ci_get_pi(adev);
3334         int ret;
3335
3336         ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3337         if (ret)
3338                 return ret;
3339
3340         ret = ci_get_dependency_volt_by_clk(adev,
3341                                             &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3342                                             engine_clock, &graphic_level->MinVddc);
3343         if (ret)
3344                 return ret;
3345
3346         graphic_level->SclkFrequency = engine_clock;
3347
3348         graphic_level->Flags =  0;
3349         graphic_level->MinVddcPhases = 1;
3350
3351         if (pi->vddc_phase_shed_control)
3352                 ci_populate_phase_value_based_on_sclk(adev,
3353                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3354                                                       engine_clock,
3355                                                       &graphic_level->MinVddcPhases);
3356
3357         graphic_level->ActivityLevel = sclk_activity_level_t;
3358
3359         graphic_level->CcPwrDynRm = 0;
3360         graphic_level->CcPwrDynRm1 = 0;
3361         graphic_level->EnabledForThrottle = 1;
3362         graphic_level->UpH = 0;
3363         graphic_level->DownH = 0;
3364         graphic_level->VoltageDownH = 0;
3365         graphic_level->PowerThrottle = 0;
3366
3367         if (pi->caps_sclk_ds)
3368                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
3369                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
3370
3371         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3372
3373         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3374         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3375         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3376         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3377         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3378         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3379         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3380         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3381         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3382         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3383         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3384
3385         return 0;
3386 }
3387
3388 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3389 {
3390         struct ci_power_info *pi = ci_get_pi(adev);
3391         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3392         u32 level_array_address = pi->dpm_table_start +
3393                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3394         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3395                 SMU7_MAX_LEVELS_GRAPHICS;
3396         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3397         u32 i, ret;
3398
3399         memset(levels, 0, level_array_size);
3400
3401         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3402                 ret = ci_populate_single_graphic_level(adev,
3403                                                        dpm_table->sclk_table.dpm_levels[i].value,
3404                                                        (u16)pi->activity_target[i],
3405                                                        &pi->smc_state_table.GraphicsLevel[i]);
3406                 if (ret)
3407                         return ret;
3408                 if (i > 1)
3409                         pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3410                 if (i == (dpm_table->sclk_table.count - 1))
3411                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3412                                 PPSMC_DISPLAY_WATERMARK_HIGH;
3413         }
3414         pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3415
3416         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3417         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3418                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3419
3420         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3421                                    (u8 *)levels, level_array_size,
3422                                    pi->sram_end);
3423         if (ret)
3424                 return ret;
3425
3426         return 0;
3427 }
3428
3429 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3430                                  SMU7_Discrete_Ulv *ulv_level)
3431 {
3432         return ci_populate_ulv_level(adev, ulv_level);
3433 }
3434
3435 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3436 {
3437         struct ci_power_info *pi = ci_get_pi(adev);
3438         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3439         u32 level_array_address = pi->dpm_table_start +
3440                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3441         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3442                 SMU7_MAX_LEVELS_MEMORY;
3443         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3444         u32 i, ret;
3445
3446         memset(levels, 0, level_array_size);
3447
3448         for (i = 0; i < dpm_table->mclk_table.count; i++) {
3449                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3450                         return -EINVAL;
3451                 ret = ci_populate_single_memory_level(adev,
3452                                                       dpm_table->mclk_table.dpm_levels[i].value,
3453                                                       &pi->smc_state_table.MemoryLevel[i]);
3454                 if (ret)
3455                         return ret;
3456         }
3457
3458         pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3459
3460         if ((dpm_table->mclk_table.count >= 2) &&
3461             ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3462                 pi->smc_state_table.MemoryLevel[1].MinVddc =
3463                         pi->smc_state_table.MemoryLevel[0].MinVddc;
3464                 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3465                         pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3466         }
3467
3468         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3469
3470         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3471         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3472                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3473
3474         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3475                 PPSMC_DISPLAY_WATERMARK_HIGH;
3476
3477         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3478                                    (u8 *)levels, level_array_size,
3479                                    pi->sram_end);
3480         if (ret)
3481                 return ret;
3482
3483         return 0;
3484 }
3485
3486 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3487                                       struct ci_single_dpm_table* dpm_table,
3488                                       u32 count)
3489 {
3490         u32 i;
3491
3492         dpm_table->count = count;
3493         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3494                 dpm_table->dpm_levels[i].enabled = false;
3495 }
3496
3497 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3498                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
3499 {
3500         dpm_table->dpm_levels[index].value = pcie_gen;
3501         dpm_table->dpm_levels[index].param1 = pcie_lanes;
3502         dpm_table->dpm_levels[index].enabled = true;
3503 }
3504
3505 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3506 {
3507         struct ci_power_info *pi = ci_get_pi(adev);
3508
3509         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3510                 return -EINVAL;
3511
3512         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3513                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3514                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3515         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3516                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3517                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3518         }
3519
3520         ci_reset_single_dpm_table(adev,
3521                                   &pi->dpm_table.pcie_speed_table,
3522                                   SMU7_MAX_LEVELS_LINK);
3523
3524         if (adev->asic_type == CHIP_BONAIRE)
3525                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3526                                           pi->pcie_gen_powersaving.min,
3527                                           pi->pcie_lane_powersaving.max);
3528         else
3529                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3530                                           pi->pcie_gen_powersaving.min,
3531                                           pi->pcie_lane_powersaving.min);
3532         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3533                                   pi->pcie_gen_performance.min,
3534                                   pi->pcie_lane_performance.min);
3535         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3536                                   pi->pcie_gen_powersaving.min,
3537                                   pi->pcie_lane_powersaving.max);
3538         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3539                                   pi->pcie_gen_performance.min,
3540                                   pi->pcie_lane_performance.max);
3541         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3542                                   pi->pcie_gen_powersaving.max,
3543                                   pi->pcie_lane_powersaving.max);
3544         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3545                                   pi->pcie_gen_performance.max,
3546                                   pi->pcie_lane_performance.max);
3547
3548         pi->dpm_table.pcie_speed_table.count = 6;
3549
3550         return 0;
3551 }
3552
3553 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3554 {
3555         struct ci_power_info *pi = ci_get_pi(adev);
3556         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3557                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3558         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3559                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3560         struct amdgpu_cac_leakage_table *std_voltage_table =
3561                 &adev->pm.dpm.dyn_state.cac_leakage_table;
3562         u32 i;
3563
3564         if (allowed_sclk_vddc_table == NULL)
3565                 return -EINVAL;
3566         if (allowed_sclk_vddc_table->count < 1)
3567                 return -EINVAL;
3568         if (allowed_mclk_table == NULL)
3569                 return -EINVAL;
3570         if (allowed_mclk_table->count < 1)
3571                 return -EINVAL;
3572
3573         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3574
3575         ci_reset_single_dpm_table(adev,
3576                                   &pi->dpm_table.sclk_table,
3577                                   SMU7_MAX_LEVELS_GRAPHICS);
3578         ci_reset_single_dpm_table(adev,
3579                                   &pi->dpm_table.mclk_table,
3580                                   SMU7_MAX_LEVELS_MEMORY);
3581         ci_reset_single_dpm_table(adev,
3582                                   &pi->dpm_table.vddc_table,
3583                                   SMU7_MAX_LEVELS_VDDC);
3584         ci_reset_single_dpm_table(adev,
3585                                   &pi->dpm_table.vddci_table,
3586                                   SMU7_MAX_LEVELS_VDDCI);
3587         ci_reset_single_dpm_table(adev,
3588                                   &pi->dpm_table.mvdd_table,
3589                                   SMU7_MAX_LEVELS_MVDD);
3590
3591         pi->dpm_table.sclk_table.count = 0;
3592         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3593                 if ((i == 0) ||
3594                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3595                      allowed_sclk_vddc_table->entries[i].clk)) {
3596                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3597                                 allowed_sclk_vddc_table->entries[i].clk;
3598                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3599                                 (i == 0) ? true : false;
3600                         pi->dpm_table.sclk_table.count++;
3601                 }
3602         }
3603
3604         pi->dpm_table.mclk_table.count = 0;
3605         for (i = 0; i < allowed_mclk_table->count; i++) {
3606                 if ((i == 0) ||
3607                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3608                      allowed_mclk_table->entries[i].clk)) {
3609                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3610                                 allowed_mclk_table->entries[i].clk;
3611                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3612                                 (i == 0) ? true : false;
3613                         pi->dpm_table.mclk_table.count++;
3614                 }
3615         }
3616
3617         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3618                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3619                         allowed_sclk_vddc_table->entries[i].v;
3620                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3621                         std_voltage_table->entries[i].leakage;
3622                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3623         }
3624         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3625
3626         allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3627         if (allowed_mclk_table) {
3628                 for (i = 0; i < allowed_mclk_table->count; i++) {
3629                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3630                                 allowed_mclk_table->entries[i].v;
3631                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3632                 }
3633                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3634         }
3635
3636         allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3637         if (allowed_mclk_table) {
3638                 for (i = 0; i < allowed_mclk_table->count; i++) {
3639                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3640                                 allowed_mclk_table->entries[i].v;
3641                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3642                 }
3643                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3644         }
3645
3646         ci_setup_default_pcie_tables(adev);
3647
3648         /* save a copy of the default DPM table */
3649         memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),
3650                         sizeof(struct ci_dpm_table));
3651
3652         return 0;
3653 }
3654
3655 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3656                               u32 value, u32 *boot_level)
3657 {
3658         u32 i;
3659         int ret = -EINVAL;
3660
3661         for(i = 0; i < table->count; i++) {
3662                 if (value == table->dpm_levels[i].value) {
3663                         *boot_level = i;
3664                         ret = 0;
3665                 }
3666         }
3667
3668         return ret;
3669 }
3670
3671 static int ci_init_smc_table(struct amdgpu_device *adev)
3672 {
3673         struct ci_power_info *pi = ci_get_pi(adev);
3674         struct ci_ulv_parm *ulv = &pi->ulv;
3675         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3676         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3677         int ret;
3678
3679         ret = ci_setup_default_dpm_tables(adev);
3680         if (ret)
3681                 return ret;
3682
3683         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3684                 ci_populate_smc_voltage_tables(adev, table);
3685
3686         ci_init_fps_limits(adev);
3687
3688         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3689                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3690
3691         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3692                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3693
3694         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3695                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3696
3697         if (ulv->supported) {
3698                 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3699                 if (ret)
3700                         return ret;
3701                 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3702         }
3703
3704         ret = ci_populate_all_graphic_levels(adev);
3705         if (ret)
3706                 return ret;
3707
3708         ret = ci_populate_all_memory_levels(adev);
3709         if (ret)
3710                 return ret;
3711
3712         ci_populate_smc_link_level(adev, table);
3713
3714         ret = ci_populate_smc_acpi_level(adev, table);
3715         if (ret)
3716                 return ret;
3717
3718         ret = ci_populate_smc_vce_level(adev, table);
3719         if (ret)
3720                 return ret;
3721
3722         ret = ci_populate_smc_acp_level(adev, table);
3723         if (ret)
3724                 return ret;
3725
3726         ret = ci_populate_smc_samu_level(adev, table);
3727         if (ret)
3728                 return ret;
3729
3730         ret = ci_do_program_memory_timing_parameters(adev);
3731         if (ret)
3732                 return ret;
3733
3734         ret = ci_populate_smc_uvd_level(adev, table);
3735         if (ret)
3736                 return ret;
3737
3738         table->UvdBootLevel  = 0;
3739         table->VceBootLevel  = 0;
3740         table->AcpBootLevel  = 0;
3741         table->SamuBootLevel  = 0;
3742         table->GraphicsBootLevel  = 0;
3743         table->MemoryBootLevel  = 0;
3744
3745         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3746                                  pi->vbios_boot_state.sclk_bootup_value,
3747                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3748
3749         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3750                                  pi->vbios_boot_state.mclk_bootup_value,
3751                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3752
3753         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3754         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3755         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3756
3757         ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3758
3759         ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3760         if (ret)
3761                 return ret;
3762
3763         table->UVDInterval = 1;
3764         table->VCEInterval = 1;
3765         table->ACPInterval = 1;
3766         table->SAMUInterval = 1;
3767         table->GraphicsVoltageChangeEnable = 1;
3768         table->GraphicsThermThrottleEnable = 1;
3769         table->GraphicsInterval = 1;
3770         table->VoltageInterval = 1;
3771         table->ThermalInterval = 1;
3772         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3773                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3774         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3775                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3776         table->MemoryVoltageChangeEnable = 1;
3777         table->MemoryInterval = 1;
3778         table->VoltageResponseTime = 0;
3779         table->VddcVddciDelta = 4000;
3780         table->PhaseResponseTime = 0;
3781         table->MemoryThermThrottleEnable = 1;
3782         table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3783         table->PCIeGenInterval = 1;
3784         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3785                 table->SVI2Enable  = 1;
3786         else
3787                 table->SVI2Enable  = 0;
3788
3789         table->ThermGpio = 17;
3790         table->SclkStepSize = 0x4000;
3791
3792         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3793         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3794         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3795         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3796         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3797         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3798         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3799         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3800         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3801         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3802         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3803         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3804         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3805         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3806
3807         ret = amdgpu_ci_copy_bytes_to_smc(adev,
3808                                    pi->dpm_table_start +
3809                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3810                                    (u8 *)&table->SystemFlags,
3811                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3812                                    pi->sram_end);
3813         if (ret)
3814                 return ret;
3815
3816         return 0;
3817 }
3818
3819 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3820                                       struct ci_single_dpm_table *dpm_table,
3821                                       u32 low_limit, u32 high_limit)
3822 {
3823         u32 i;
3824
3825         for (i = 0; i < dpm_table->count; i++) {
3826                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3827                     (dpm_table->dpm_levels[i].value > high_limit))
3828                         dpm_table->dpm_levels[i].enabled = false;
3829                 else
3830                         dpm_table->dpm_levels[i].enabled = true;
3831         }
3832 }
3833
3834 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3835                                     u32 speed_low, u32 lanes_low,
3836                                     u32 speed_high, u32 lanes_high)
3837 {
3838         struct ci_power_info *pi = ci_get_pi(adev);
3839         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3840         u32 i, j;
3841
3842         for (i = 0; i < pcie_table->count; i++) {
3843                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3844                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3845                     (pcie_table->dpm_levels[i].value > speed_high) ||
3846                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3847                         pcie_table->dpm_levels[i].enabled = false;
3848                 else
3849                         pcie_table->dpm_levels[i].enabled = true;
3850         }
3851
3852         for (i = 0; i < pcie_table->count; i++) {
3853                 if (pcie_table->dpm_levels[i].enabled) {
3854                         for (j = i + 1; j < pcie_table->count; j++) {
3855                                 if (pcie_table->dpm_levels[j].enabled) {
3856                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3857                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3858                                                 pcie_table->dpm_levels[j].enabled = false;
3859                                 }
3860                         }
3861                 }
3862         }
3863 }
3864
3865 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3866                               struct amdgpu_ps *amdgpu_state)
3867 {
3868         struct ci_ps *state = ci_get_ps(amdgpu_state);
3869         struct ci_power_info *pi = ci_get_pi(adev);
3870         u32 high_limit_count;
3871
3872         if (state->performance_level_count < 1)
3873                 return -EINVAL;
3874
3875         if (state->performance_level_count == 1)
3876                 high_limit_count = 0;
3877         else
3878                 high_limit_count = 1;
3879
3880         ci_trim_single_dpm_states(adev,
3881                                   &pi->dpm_table.sclk_table,
3882                                   state->performance_levels[0].sclk,
3883                                   state->performance_levels[high_limit_count].sclk);
3884
3885         ci_trim_single_dpm_states(adev,
3886                                   &pi->dpm_table.mclk_table,
3887                                   state->performance_levels[0].mclk,
3888                                   state->performance_levels[high_limit_count].mclk);
3889
3890         ci_trim_pcie_dpm_states(adev,
3891                                 state->performance_levels[0].pcie_gen,
3892                                 state->performance_levels[0].pcie_lane,
3893                                 state->performance_levels[high_limit_count].pcie_gen,
3894                                 state->performance_levels[high_limit_count].pcie_lane);
3895
3896         return 0;
3897 }
3898
3899 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3900 {
3901         struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3902                 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3903         struct amdgpu_clock_voltage_dependency_table *vddc_table =
3904                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3905         u32 requested_voltage = 0;
3906         u32 i;
3907
3908         if (disp_voltage_table == NULL)
3909                 return -EINVAL;
3910         if (!disp_voltage_table->count)
3911                 return -EINVAL;
3912
3913         for (i = 0; i < disp_voltage_table->count; i++) {
3914                 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3915                         requested_voltage = disp_voltage_table->entries[i].v;
3916         }
3917
3918         for (i = 0; i < vddc_table->count; i++) {
3919                 if (requested_voltage <= vddc_table->entries[i].v) {
3920                         requested_voltage = vddc_table->entries[i].v;
3921                         return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3922                                                                   PPSMC_MSG_VddC_Request,
3923                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3924                                 0 : -EINVAL;
3925                 }
3926         }
3927
3928         return -EINVAL;
3929 }
3930
3931 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3932 {
3933         struct ci_power_info *pi = ci_get_pi(adev);
3934         PPSMC_Result result;
3935
3936         ci_apply_disp_minimum_voltage_request(adev);
3937
3938         if (!pi->sclk_dpm_key_disabled) {
3939                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3940                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3941                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3942                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3943                         if (result != PPSMC_Result_OK)
3944                                 return -EINVAL;
3945                 }
3946         }
3947
3948         if (!pi->mclk_dpm_key_disabled) {
3949                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3950                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3951                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3952                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3953                         if (result != PPSMC_Result_OK)
3954                                 return -EINVAL;
3955                 }
3956         }
3957
3958 #if 0
3959         if (!pi->pcie_dpm_key_disabled) {
3960                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3961                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3962                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3963                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3964                         if (result != PPSMC_Result_OK)
3965                                 return -EINVAL;
3966                 }
3967         }
3968 #endif
3969
3970         return 0;
3971 }
3972
3973 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
3974                                                    struct amdgpu_ps *amdgpu_state)
3975 {
3976         struct ci_power_info *pi = ci_get_pi(adev);
3977         struct ci_ps *state = ci_get_ps(amdgpu_state);
3978         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3979         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3980         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3981         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3982         u32 i;
3983
3984         pi->need_update_smu7_dpm_table = 0;
3985
3986         for (i = 0; i < sclk_table->count; i++) {
3987                 if (sclk == sclk_table->dpm_levels[i].value)
3988                         break;
3989         }
3990
3991         if (i >= sclk_table->count) {
3992                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3993         } else {
3994                 /* XXX check display min clock requirements */
3995                 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3996                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3997         }
3998
3999         for (i = 0; i < mclk_table->count; i++) {
4000                 if (mclk == mclk_table->dpm_levels[i].value)
4001                         break;
4002         }
4003
4004         if (i >= mclk_table->count)
4005                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4006
4007         if (adev->pm.dpm.current_active_crtc_count !=
4008             adev->pm.dpm.new_active_crtc_count)
4009                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4010 }
4011
4012 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4013                                                        struct amdgpu_ps *amdgpu_state)
4014 {
4015         struct ci_power_info *pi = ci_get_pi(adev);
4016         struct ci_ps *state = ci_get_ps(amdgpu_state);
4017         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4018         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4019         struct ci_dpm_table *dpm_table = &pi->dpm_table;
4020         int ret;
4021
4022         if (!pi->need_update_smu7_dpm_table)
4023                 return 0;
4024
4025         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4026                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4027
4028         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4029                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4030
4031         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4032                 ret = ci_populate_all_graphic_levels(adev);
4033                 if (ret)
4034                         return ret;
4035         }
4036
4037         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4038                 ret = ci_populate_all_memory_levels(adev);
4039                 if (ret)
4040                         return ret;
4041         }
4042
4043         return 0;
4044 }
4045
4046 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4047 {
4048         struct ci_power_info *pi = ci_get_pi(adev);
4049         const struct amdgpu_clock_and_voltage_limits *max_limits;
4050         int i;
4051
4052         if (adev->pm.dpm.ac_power)
4053                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4054         else
4055                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4056
4057         if (enable) {
4058                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4059
4060                 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4061                         if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4062                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4063
4064                                 if (!pi->caps_uvd_dpm)
4065                                         break;
4066                         }
4067                 }
4068
4069                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4070                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
4071                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4072
4073                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4074                         pi->uvd_enabled = true;
4075                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4076                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4077                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4078                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4079                 }
4080         } else {
4081                 if (pi->uvd_enabled) {
4082                         pi->uvd_enabled = false;
4083                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4084                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4085                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4086                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4087                 }
4088         }
4089
4090         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4091                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4092                 0 : -EINVAL;
4093 }
4094
4095 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4096 {
4097         struct ci_power_info *pi = ci_get_pi(adev);
4098         const struct amdgpu_clock_and_voltage_limits *max_limits;
4099         int i;
4100
4101         if (adev->pm.dpm.ac_power)
4102                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4103         else
4104                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4105
4106         if (enable) {
4107                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4108                 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4109                         if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4110                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4111
4112                                 if (!pi->caps_vce_dpm)
4113                                         break;
4114                         }
4115                 }
4116
4117                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4118                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
4119                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4120         }
4121
4122         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4123                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4124                 0 : -EINVAL;
4125 }
4126
4127 #if 0
4128 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4129 {
4130         struct ci_power_info *pi = ci_get_pi(adev);
4131         const struct amdgpu_clock_and_voltage_limits *max_limits;
4132         int i;
4133
4134         if (adev->pm.dpm.ac_power)
4135                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4136         else
4137                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4138
4139         if (enable) {
4140                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4141                 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4142                         if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4143                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4144
4145                                 if (!pi->caps_samu_dpm)
4146                                         break;
4147                         }
4148                 }
4149
4150                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4151                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
4152                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4153         }
4154         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4155                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4156                 0 : -EINVAL;
4157 }
4158
4159 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4160 {
4161         struct ci_power_info *pi = ci_get_pi(adev);
4162         const struct amdgpu_clock_and_voltage_limits *max_limits;
4163         int i;
4164
4165         if (adev->pm.dpm.ac_power)
4166                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4167         else
4168                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4169
4170         if (enable) {
4171                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4172                 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4173                         if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4174                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4175
4176                                 if (!pi->caps_acp_dpm)
4177                                         break;
4178                         }
4179                 }
4180
4181                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4182                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
4183                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4184         }
4185
4186         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4187                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4188                 0 : -EINVAL;
4189 }
4190 #endif
4191
4192 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4193 {
4194         struct ci_power_info *pi = ci_get_pi(adev);
4195         u32 tmp;
4196
4197         if (!gate) {
4198                 if (pi->caps_uvd_dpm ||
4199                     (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4200                         pi->smc_state_table.UvdBootLevel = 0;
4201                 else
4202                         pi->smc_state_table.UvdBootLevel =
4203                                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4204
4205                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4206                 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4207                 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4208                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4209         }
4210
4211         return ci_enable_uvd_dpm(adev, !gate);
4212 }
4213
4214 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4215 {
4216         u8 i;
4217         u32 min_evclk = 30000; /* ??? */
4218         struct amdgpu_vce_clock_voltage_dependency_table *table =
4219                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4220
4221         for (i = 0; i < table->count; i++) {
4222                 if (table->entries[i].evclk >= min_evclk)
4223                         return i;
4224         }
4225
4226         return table->count - 1;
4227 }
4228
4229 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4230                              struct amdgpu_ps *amdgpu_new_state,
4231                              struct amdgpu_ps *amdgpu_current_state)
4232 {
4233         struct ci_power_info *pi = ci_get_pi(adev);
4234         int ret = 0;
4235         u32 tmp;
4236
4237         if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4238                 if (amdgpu_new_state->evclk) {
4239                         /* turn the clocks on when encoding */
4240                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4241                                                             AMD_CG_STATE_UNGATE);
4242                         if (ret)
4243                                 return ret;
4244
4245                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4246                         tmp = RREG32_SMC(ixDPM_TABLE_475);
4247                         tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4248                         tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4249                         WREG32_SMC(ixDPM_TABLE_475, tmp);
4250
4251                         ret = ci_enable_vce_dpm(adev, true);
4252                 } else {
4253                         /* turn the clocks off when not encoding */
4254                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4255                                                             AMD_CG_STATE_GATE);
4256                         if (ret)
4257                                 return ret;
4258
4259                         ret = ci_enable_vce_dpm(adev, false);
4260                 }
4261         }
4262         return ret;
4263 }
4264
4265 #if 0
4266 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4267 {
4268         return ci_enable_samu_dpm(adev, gate);
4269 }
4270
4271 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4272 {
4273         struct ci_power_info *pi = ci_get_pi(adev);
4274         u32 tmp;
4275
4276         if (!gate) {
4277                 pi->smc_state_table.AcpBootLevel = 0;
4278
4279                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4280                 tmp &= ~AcpBootLevel_MASK;
4281                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4282                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4283         }
4284
4285         return ci_enable_acp_dpm(adev, !gate);
4286 }
4287 #endif
4288
4289 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4290                                              struct amdgpu_ps *amdgpu_state)
4291 {
4292         struct ci_power_info *pi = ci_get_pi(adev);
4293         int ret;
4294
4295         ret = ci_trim_dpm_states(adev, amdgpu_state);
4296         if (ret)
4297                 return ret;
4298
4299         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4300                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4301         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4302                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4303         pi->last_mclk_dpm_enable_mask =
4304                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4305         if (pi->uvd_enabled) {
4306                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4307                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4308         }
4309         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4310                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4311
4312         return 0;
4313 }
4314
4315 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4316                                        u32 level_mask)
4317 {
4318         u32 level = 0;
4319
4320         while ((level_mask & (1 << level)) == 0)
4321                 level++;
4322
4323         return level;
4324 }
4325
4326
4327 static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4328                                           enum amdgpu_dpm_forced_level level)
4329 {
4330         struct ci_power_info *pi = ci_get_pi(adev);
4331         u32 tmp, levels, i;
4332         int ret;
4333
4334         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
4335                 if ((!pi->pcie_dpm_key_disabled) &&
4336                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4337                         levels = 0;
4338                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4339                         while (tmp >>= 1)
4340                                 levels++;
4341                         if (levels) {
4342                                 ret = ci_dpm_force_state_pcie(adev, level);
4343                                 if (ret)
4344                                         return ret;
4345                                 for (i = 0; i < adev->usec_timeout; i++) {
4346                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4347                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4348                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4349                                         if (tmp == levels)
4350                                                 break;
4351                                         udelay(1);
4352                                 }
4353                         }
4354                 }
4355                 if ((!pi->sclk_dpm_key_disabled) &&
4356                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4357                         levels = 0;
4358                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4359                         while (tmp >>= 1)
4360                                 levels++;
4361                         if (levels) {
4362                                 ret = ci_dpm_force_state_sclk(adev, levels);
4363                                 if (ret)
4364                                         return ret;
4365                                 for (i = 0; i < adev->usec_timeout; i++) {
4366                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4367                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4368                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4369                                         if (tmp == levels)
4370                                                 break;
4371                                         udelay(1);
4372                                 }
4373                         }
4374                 }
4375                 if ((!pi->mclk_dpm_key_disabled) &&
4376                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4377                         levels = 0;
4378                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4379                         while (tmp >>= 1)
4380                                 levels++;
4381                         if (levels) {
4382                                 ret = ci_dpm_force_state_mclk(adev, levels);
4383                                 if (ret)
4384                                         return ret;
4385                                 for (i = 0; i < adev->usec_timeout; i++) {
4386                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4387                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4388                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4389                                         if (tmp == levels)
4390                                                 break;
4391                                         udelay(1);
4392                                 }
4393                         }
4394                 }
4395         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
4396                 if ((!pi->sclk_dpm_key_disabled) &&
4397                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4398                         levels = ci_get_lowest_enabled_level(adev,
4399                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4400                         ret = ci_dpm_force_state_sclk(adev, levels);
4401                         if (ret)
4402                                 return ret;
4403                         for (i = 0; i < adev->usec_timeout; i++) {
4404                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4405                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4406                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4407                                 if (tmp == levels)
4408                                         break;
4409                                 udelay(1);
4410                         }
4411                 }
4412                 if ((!pi->mclk_dpm_key_disabled) &&
4413                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4414                         levels = ci_get_lowest_enabled_level(adev,
4415                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4416                         ret = ci_dpm_force_state_mclk(adev, levels);
4417                         if (ret)
4418                                 return ret;
4419                         for (i = 0; i < adev->usec_timeout; i++) {
4420                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4421                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4422                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4423                                 if (tmp == levels)
4424                                         break;
4425                                 udelay(1);
4426                         }
4427                 }
4428                 if ((!pi->pcie_dpm_key_disabled) &&
4429                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4430                         levels = ci_get_lowest_enabled_level(adev,
4431                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4432                         ret = ci_dpm_force_state_pcie(adev, levels);
4433                         if (ret)
4434                                 return ret;
4435                         for (i = 0; i < adev->usec_timeout; i++) {
4436                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4437                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4438                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4439                                 if (tmp == levels)
4440                                         break;
4441                                 udelay(1);
4442                         }
4443                 }
4444         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
4445                 if (!pi->pcie_dpm_key_disabled) {
4446                         PPSMC_Result smc_result;
4447
4448                         smc_result = amdgpu_ci_send_msg_to_smc(adev,
4449                                                                PPSMC_MSG_PCIeDPM_UnForceLevel);
4450                         if (smc_result != PPSMC_Result_OK)
4451                                 return -EINVAL;
4452                 }
4453                 ret = ci_upload_dpm_level_enable_mask(adev);
4454                 if (ret)
4455                         return ret;
4456         }
4457
4458         adev->pm.dpm.forced_level = level;
4459
4460         return 0;
4461 }
4462
4463 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4464                                        struct ci_mc_reg_table *table)
4465 {
4466         u8 i, j, k;
4467         u32 temp_reg;
4468
4469         for (i = 0, j = table->last; i < table->last; i++) {
4470                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4471                         return -EINVAL;
4472                 switch(table->mc_reg_address[i].s1) {
4473                 case mmMC_SEQ_MISC1:
4474                         temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4475                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4476                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4477                         for (k = 0; k < table->num_entries; k++) {
4478                                 table->mc_reg_table_entry[k].mc_data[j] =
4479                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4480                         }
4481                         j++;
4482                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4483                                 return -EINVAL;
4484
4485                         temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4486                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4487                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4488                         for (k = 0; k < table->num_entries; k++) {
4489                                 table->mc_reg_table_entry[k].mc_data[j] =
4490                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4491                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4492                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4493                         }
4494                         j++;
4495                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4496                                 return -EINVAL;
4497
4498                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4499                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4500                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4501                                 for (k = 0; k < table->num_entries; k++) {
4502                                         table->mc_reg_table_entry[k].mc_data[j] =
4503                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4504                                 }
4505                                 j++;
4506                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4507                                         return -EINVAL;
4508                         }
4509                         break;
4510                 case mmMC_SEQ_RESERVE_M:
4511                         temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4512                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4513                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4514                         for (k = 0; k < table->num_entries; k++) {
4515                                 table->mc_reg_table_entry[k].mc_data[j] =
4516                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4517                         }
4518                         j++;
4519                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4520                                 return -EINVAL;
4521                         break;
4522                 default:
4523                         break;
4524                 }
4525
4526         }
4527
4528         table->last = j;
4529
4530         return 0;
4531 }
4532
4533 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4534 {
4535         bool result = true;
4536
4537         switch(in_reg) {
4538         case mmMC_SEQ_RAS_TIMING:
4539                 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4540                 break;
4541         case mmMC_SEQ_DLL_STBY:
4542                 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4543                 break;
4544         case mmMC_SEQ_G5PDX_CMD0:
4545                 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4546                 break;
4547         case mmMC_SEQ_G5PDX_CMD1:
4548                 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4549                 break;
4550         case mmMC_SEQ_G5PDX_CTRL:
4551                 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4552                 break;
4553         case mmMC_SEQ_CAS_TIMING:
4554                 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4555             break;
4556         case mmMC_SEQ_MISC_TIMING:
4557                 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4558                 break;
4559         case mmMC_SEQ_MISC_TIMING2:
4560                 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4561                 break;
4562         case mmMC_SEQ_PMG_DVS_CMD:
4563                 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4564                 break;
4565         case mmMC_SEQ_PMG_DVS_CTL:
4566                 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4567                 break;
4568         case mmMC_SEQ_RD_CTL_D0:
4569                 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4570                 break;
4571         case mmMC_SEQ_RD_CTL_D1:
4572                 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4573                 break;
4574         case mmMC_SEQ_WR_CTL_D0:
4575                 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4576                 break;
4577         case mmMC_SEQ_WR_CTL_D1:
4578                 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4579                 break;
4580         case mmMC_PMG_CMD_EMRS:
4581                 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4582                 break;
4583         case mmMC_PMG_CMD_MRS:
4584                 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4585                 break;
4586         case mmMC_PMG_CMD_MRS1:
4587                 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4588                 break;
4589         case mmMC_SEQ_PMG_TIMING:
4590                 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4591                 break;
4592         case mmMC_PMG_CMD_MRS2:
4593                 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4594                 break;
4595         case mmMC_SEQ_WR_CTL_2:
4596                 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4597                 break;
4598         default:
4599                 result = false;
4600                 break;
4601         }
4602
4603         return result;
4604 }
4605
4606 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4607 {
4608         u8 i, j;
4609
4610         for (i = 0; i < table->last; i++) {
4611                 for (j = 1; j < table->num_entries; j++) {
4612                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4613                             table->mc_reg_table_entry[j].mc_data[i]) {
4614                                 table->valid_flag |= 1 << i;
4615                                 break;
4616                         }
4617                 }
4618         }
4619 }
4620
4621 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4622 {
4623         u32 i;
4624         u16 address;
4625
4626         for (i = 0; i < table->last; i++) {
4627                 table->mc_reg_address[i].s0 =
4628                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4629                         address : table->mc_reg_address[i].s1;
4630         }
4631 }
4632
4633 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4634                                       struct ci_mc_reg_table *ci_table)
4635 {
4636         u8 i, j;
4637
4638         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4639                 return -EINVAL;
4640         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4641                 return -EINVAL;
4642
4643         for (i = 0; i < table->last; i++)
4644                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4645
4646         ci_table->last = table->last;
4647
4648         for (i = 0; i < table->num_entries; i++) {
4649                 ci_table->mc_reg_table_entry[i].mclk_max =
4650                         table->mc_reg_table_entry[i].mclk_max;
4651                 for (j = 0; j < table->last; j++)
4652                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4653                                 table->mc_reg_table_entry[i].mc_data[j];
4654         }
4655         ci_table->num_entries = table->num_entries;
4656
4657         return 0;
4658 }
4659
4660 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4661                                        struct ci_mc_reg_table *table)
4662 {
4663         u8 i, k;
4664         u32 tmp;
4665         bool patch;
4666
4667         tmp = RREG32(mmMC_SEQ_MISC0);
4668         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4669
4670         if (patch &&
4671             ((adev->pdev->device == 0x67B0) ||
4672              (adev->pdev->device == 0x67B1))) {
4673                 for (i = 0; i < table->last; i++) {
4674                         if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4675                                 return -EINVAL;
4676                         switch (table->mc_reg_address[i].s1) {
4677                         case mmMC_SEQ_MISC1:
4678                                 for (k = 0; k < table->num_entries; k++) {
4679                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4680                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4681                                                 table->mc_reg_table_entry[k].mc_data[i] =
4682                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4683                                                         0x00000007;
4684                                 }
4685                                 break;
4686                         case mmMC_SEQ_WR_CTL_D0:
4687                                 for (k = 0; k < table->num_entries; k++) {
4688                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4689                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4690                                                 table->mc_reg_table_entry[k].mc_data[i] =
4691                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4692                                                         0x0000D0DD;
4693                                 }
4694                                 break;
4695                         case mmMC_SEQ_WR_CTL_D1:
4696                                 for (k = 0; k < table->num_entries; k++) {
4697                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4698                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4699                                                 table->mc_reg_table_entry[k].mc_data[i] =
4700                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4701                                                         0x0000D0DD;
4702                                 }
4703                                 break;
4704                         case mmMC_SEQ_WR_CTL_2:
4705                                 for (k = 0; k < table->num_entries; k++) {
4706                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4707                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4708                                                 table->mc_reg_table_entry[k].mc_data[i] = 0;
4709                                 }
4710                                 break;
4711                         case mmMC_SEQ_CAS_TIMING:
4712                                 for (k = 0; k < table->num_entries; k++) {
4713                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4714                                                 table->mc_reg_table_entry[k].mc_data[i] =
4715                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4716                                                         0x000C0140;
4717                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4718                                                 table->mc_reg_table_entry[k].mc_data[i] =
4719                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4720                                                         0x000C0150;
4721                                 }
4722                                 break;
4723                         case mmMC_SEQ_MISC_TIMING:
4724                                 for (k = 0; k < table->num_entries; k++) {
4725                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4726                                                 table->mc_reg_table_entry[k].mc_data[i] =
4727                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4728                                                         0x00000030;
4729                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4730                                                 table->mc_reg_table_entry[k].mc_data[i] =
4731                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4732                                                         0x00000035;
4733                                 }
4734                                 break;
4735                         default:
4736                                 break;
4737                         }
4738                 }
4739
4740                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4741                 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4742                 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4743                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4744                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4745         }
4746
4747         return 0;
4748 }
4749
4750 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4751 {
4752         struct ci_power_info *pi = ci_get_pi(adev);
4753         struct atom_mc_reg_table *table;
4754         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4755         u8 module_index = ci_get_memory_module_index(adev);
4756         int ret;
4757
4758         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4759         if (!table)
4760                 return -ENOMEM;
4761
4762         WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4763         WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4764         WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4765         WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4766         WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4767         WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4768         WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4769         WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4770         WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4771         WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4772         WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4773         WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4774         WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4775         WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4776         WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4777         WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4778         WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4779         WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4780         WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4781         WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4782
4783         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4784         if (ret)
4785                 goto init_mc_done;
4786
4787         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4788         if (ret)
4789                 goto init_mc_done;
4790
4791         ci_set_s0_mc_reg_index(ci_table);
4792
4793         ret = ci_register_patching_mc_seq(adev, ci_table);
4794         if (ret)
4795                 goto init_mc_done;
4796
4797         ret = ci_set_mc_special_registers(adev, ci_table);
4798         if (ret)
4799                 goto init_mc_done;
4800
4801         ci_set_valid_flag(ci_table);
4802
4803 init_mc_done:
4804         kfree(table);
4805
4806         return ret;
4807 }
4808
4809 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4810                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4811 {
4812         struct ci_power_info *pi = ci_get_pi(adev);
4813         u32 i, j;
4814
4815         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4816                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4817                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4818                                 return -EINVAL;
4819                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4820                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4821                         i++;
4822                 }
4823         }
4824
4825         mc_reg_table->last = (u8)i;
4826
4827         return 0;
4828 }
4829
4830 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4831                                     SMU7_Discrete_MCRegisterSet *data,
4832                                     u32 num_entries, u32 valid_flag)
4833 {
4834         u32 i, j;
4835
4836         for (i = 0, j = 0; j < num_entries; j++) {
4837                 if (valid_flag & (1 << j)) {
4838                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4839                         i++;
4840                 }
4841         }
4842 }
4843
4844 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4845                                                  const u32 memory_clock,
4846                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4847 {
4848         struct ci_power_info *pi = ci_get_pi(adev);
4849         u32 i = 0;
4850
4851         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4852                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4853                         break;
4854         }
4855
4856         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4857                 --i;
4858
4859         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4860                                 mc_reg_table_data, pi->mc_reg_table.last,
4861                                 pi->mc_reg_table.valid_flag);
4862 }
4863
4864 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4865                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4866 {
4867         struct ci_power_info *pi = ci_get_pi(adev);
4868         u32 i;
4869
4870         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4871                 ci_convert_mc_reg_table_entry_to_smc(adev,
4872                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4873                                                      &mc_reg_table->data[i]);
4874 }
4875
4876 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4877 {
4878         struct ci_power_info *pi = ci_get_pi(adev);
4879         int ret;
4880
4881         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4882
4883         ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4884         if (ret)
4885                 return ret;
4886         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4887
4888         return amdgpu_ci_copy_bytes_to_smc(adev,
4889                                     pi->mc_reg_table_start,
4890                                     (u8 *)&pi->smc_mc_reg_table,
4891                                     sizeof(SMU7_Discrete_MCRegisters),
4892                                     pi->sram_end);
4893 }
4894
4895 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4896 {
4897         struct ci_power_info *pi = ci_get_pi(adev);
4898
4899         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4900                 return 0;
4901
4902         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4903
4904         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4905
4906         return amdgpu_ci_copy_bytes_to_smc(adev,
4907                                     pi->mc_reg_table_start +
4908                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4909                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4910                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4911                                     pi->dpm_table.mclk_table.count,
4912                                     pi->sram_end);
4913 }
4914
4915 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4916 {
4917         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4918
4919         tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4920         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4921 }
4922
4923 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4924                                                       struct amdgpu_ps *amdgpu_state)
4925 {
4926         struct ci_ps *state = ci_get_ps(amdgpu_state);
4927         int i;
4928         u16 pcie_speed, max_speed = 0;
4929
4930         for (i = 0; i < state->performance_level_count; i++) {
4931                 pcie_speed = state->performance_levels[i].pcie_gen;
4932                 if (max_speed < pcie_speed)
4933                         max_speed = pcie_speed;
4934         }
4935
4936         return max_speed;
4937 }
4938
4939 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4940 {
4941         u32 speed_cntl = 0;
4942
4943         speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4944                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4945         speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4946
4947         return (u16)speed_cntl;
4948 }
4949
4950 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
4951 {
4952         u32 link_width = 0;
4953
4954         link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
4955                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
4956         link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4957
4958         switch (link_width) {
4959         case 1:
4960                 return 1;
4961         case 2:
4962                 return 2;
4963         case 3:
4964                 return 4;
4965         case 4:
4966                 return 8;
4967         case 0:
4968         case 6:
4969         default:
4970                 return 16;
4971         }
4972 }
4973
4974 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
4975                                                              struct amdgpu_ps *amdgpu_new_state,
4976                                                              struct amdgpu_ps *amdgpu_current_state)
4977 {
4978         struct ci_power_info *pi = ci_get_pi(adev);
4979         enum amdgpu_pcie_gen target_link_speed =
4980                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
4981         enum amdgpu_pcie_gen current_link_speed;
4982
4983         if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
4984                 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
4985         else
4986                 current_link_speed = pi->force_pcie_gen;
4987
4988         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
4989         pi->pspp_notify_required = false;
4990         if (target_link_speed > current_link_speed) {
4991                 switch (target_link_speed) {
4992 #ifdef CONFIG_ACPI
4993                 case AMDGPU_PCIE_GEN3:
4994                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4995                                 break;
4996                         pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
4997                         if (current_link_speed == AMDGPU_PCIE_GEN2)
4998                                 break;
4999                 case AMDGPU_PCIE_GEN2:
5000                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5001                                 break;
5002 #endif
5003                 default:
5004                         pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
5005                         break;
5006                 }
5007         } else {
5008                 if (target_link_speed < current_link_speed)
5009                         pi->pspp_notify_required = true;
5010         }
5011 }
5012
5013 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5014                                                            struct amdgpu_ps *amdgpu_new_state,
5015                                                            struct amdgpu_ps *amdgpu_current_state)
5016 {
5017         struct ci_power_info *pi = ci_get_pi(adev);
5018         enum amdgpu_pcie_gen target_link_speed =
5019                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5020         u8 request;
5021
5022         if (pi->pspp_notify_required) {
5023                 if (target_link_speed == AMDGPU_PCIE_GEN3)
5024                         request = PCIE_PERF_REQ_PECI_GEN3;
5025                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5026                         request = PCIE_PERF_REQ_PECI_GEN2;
5027                 else
5028                         request = PCIE_PERF_REQ_PECI_GEN1;
5029
5030                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5031                     (ci_get_current_pcie_speed(adev) > 0))
5032                         return;
5033
5034 #ifdef CONFIG_ACPI
5035                 amdgpu_acpi_pcie_performance_request(adev, request, false);
5036 #endif
5037         }
5038 }
5039
5040 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5041 {
5042         struct ci_power_info *pi = ci_get_pi(adev);
5043         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5044                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5045         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5046                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5047         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5048                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5049
5050         if (allowed_sclk_vddc_table == NULL)
5051                 return -EINVAL;
5052         if (allowed_sclk_vddc_table->count < 1)
5053                 return -EINVAL;
5054         if (allowed_mclk_vddc_table == NULL)
5055                 return -EINVAL;
5056         if (allowed_mclk_vddc_table->count < 1)
5057                 return -EINVAL;
5058         if (allowed_mclk_vddci_table == NULL)
5059                 return -EINVAL;
5060         if (allowed_mclk_vddci_table->count < 1)
5061                 return -EINVAL;
5062
5063         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5064         pi->max_vddc_in_pp_table =
5065                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5066
5067         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5068         pi->max_vddci_in_pp_table =
5069                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5070
5071         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5072                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5073         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5074                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5075         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5076                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5077         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5078                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5079
5080         return 0;
5081 }
5082
5083 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5084 {
5085         struct ci_power_info *pi = ci_get_pi(adev);
5086         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5087         u32 leakage_index;
5088
5089         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5090                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5091                         *vddc = leakage_table->actual_voltage[leakage_index];
5092                         break;
5093                 }
5094         }
5095 }
5096
5097 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5098 {
5099         struct ci_power_info *pi = ci_get_pi(adev);
5100         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5101         u32 leakage_index;
5102
5103         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5104                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5105                         *vddci = leakage_table->actual_voltage[leakage_index];
5106                         break;
5107                 }
5108         }
5109 }
5110
5111 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5112                                                                       struct amdgpu_clock_voltage_dependency_table *table)
5113 {
5114         u32 i;
5115
5116         if (table) {
5117                 for (i = 0; i < table->count; i++)
5118                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5119         }
5120 }
5121
5122 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5123                                                                        struct amdgpu_clock_voltage_dependency_table *table)
5124 {
5125         u32 i;
5126
5127         if (table) {
5128                 for (i = 0; i < table->count; i++)
5129                         ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5130         }
5131 }
5132
5133 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5134                                                                           struct amdgpu_vce_clock_voltage_dependency_table *table)
5135 {
5136         u32 i;
5137
5138         if (table) {
5139                 for (i = 0; i < table->count; i++)
5140                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5141         }
5142 }
5143
5144 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5145                                                                           struct amdgpu_uvd_clock_voltage_dependency_table *table)
5146 {
5147         u32 i;
5148
5149         if (table) {
5150                 for (i = 0; i < table->count; i++)
5151                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5152         }
5153 }
5154
5155 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5156                                                                    struct amdgpu_phase_shedding_limits_table *table)
5157 {
5158         u32 i;
5159
5160         if (table) {
5161                 for (i = 0; i < table->count; i++)
5162                         ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5163         }
5164 }
5165
5166 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5167                                                             struct amdgpu_clock_and_voltage_limits *table)
5168 {
5169         if (table) {
5170                 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5171                 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5172         }
5173 }
5174
5175 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5176                                                          struct amdgpu_cac_leakage_table *table)
5177 {
5178         u32 i;
5179
5180         if (table) {
5181                 for (i = 0; i < table->count; i++)
5182                         ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5183         }
5184 }
5185
5186 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5187 {
5188
5189         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5190                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5191         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5192                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5193         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5194                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5195         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5196                                                                    &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5197         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5198                                                                       &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5199         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5200                                                                       &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5201         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5202                                                                   &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5203         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5204                                                                   &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5205         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5206                                                                &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5207         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5208                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5209         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5210                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5211         ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5212                                                      &adev->pm.dpm.dyn_state.cac_leakage_table);
5213
5214 }
5215
5216 static void ci_update_current_ps(struct amdgpu_device *adev,
5217                                  struct amdgpu_ps *rps)
5218 {
5219         struct ci_ps *new_ps = ci_get_ps(rps);
5220         struct ci_power_info *pi = ci_get_pi(adev);
5221
5222         pi->current_rps = *rps;
5223         pi->current_ps = *new_ps;
5224         pi->current_rps.ps_priv = &pi->current_ps;
5225 }
5226
5227 static void ci_update_requested_ps(struct amdgpu_device *adev,
5228                                    struct amdgpu_ps *rps)
5229 {
5230         struct ci_ps *new_ps = ci_get_ps(rps);
5231         struct ci_power_info *pi = ci_get_pi(adev);
5232
5233         pi->requested_rps = *rps;
5234         pi->requested_ps = *new_ps;
5235         pi->requested_rps.ps_priv = &pi->requested_ps;
5236 }
5237
5238 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5239 {
5240         struct ci_power_info *pi = ci_get_pi(adev);
5241         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5242         struct amdgpu_ps *new_ps = &requested_ps;
5243
5244         ci_update_requested_ps(adev, new_ps);
5245
5246         ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5247
5248         return 0;
5249 }
5250
5251 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5252 {
5253         struct ci_power_info *pi = ci_get_pi(adev);
5254         struct amdgpu_ps *new_ps = &pi->requested_rps;
5255
5256         ci_update_current_ps(adev, new_ps);
5257 }
5258
5259
5260 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5261 {
5262         ci_read_clock_registers(adev);
5263         ci_enable_acpi_power_management(adev);
5264         ci_init_sclk_t(adev);
5265 }
5266
5267 static int ci_dpm_enable(struct amdgpu_device *adev)
5268 {
5269         struct ci_power_info *pi = ci_get_pi(adev);
5270         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5271         int ret;
5272
5273         if (amdgpu_ci_is_smc_running(adev))
5274                 return -EINVAL;
5275         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5276                 ci_enable_voltage_control(adev);
5277                 ret = ci_construct_voltage_tables(adev);
5278                 if (ret) {
5279                         DRM_ERROR("ci_construct_voltage_tables failed\n");
5280                         return ret;
5281                 }
5282         }
5283         if (pi->caps_dynamic_ac_timing) {
5284                 ret = ci_initialize_mc_reg_table(adev);
5285                 if (ret)
5286                         pi->caps_dynamic_ac_timing = false;
5287         }
5288         if (pi->dynamic_ss)
5289                 ci_enable_spread_spectrum(adev, true);
5290         if (pi->thermal_protection)
5291                 ci_enable_thermal_protection(adev, true);
5292         ci_program_sstp(adev);
5293         ci_enable_display_gap(adev);
5294         ci_program_vc(adev);
5295         ret = ci_upload_firmware(adev);
5296         if (ret) {
5297                 DRM_ERROR("ci_upload_firmware failed\n");
5298                 return ret;
5299         }
5300         ret = ci_process_firmware_header(adev);
5301         if (ret) {
5302                 DRM_ERROR("ci_process_firmware_header failed\n");
5303                 return ret;
5304         }
5305         ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5306         if (ret) {
5307                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5308                 return ret;
5309         }
5310         ret = ci_init_smc_table(adev);
5311         if (ret) {
5312                 DRM_ERROR("ci_init_smc_table failed\n");
5313                 return ret;
5314         }
5315         ret = ci_init_arb_table_index(adev);
5316         if (ret) {
5317                 DRM_ERROR("ci_init_arb_table_index failed\n");
5318                 return ret;
5319         }
5320         if (pi->caps_dynamic_ac_timing) {
5321                 ret = ci_populate_initial_mc_reg_table(adev);
5322                 if (ret) {
5323                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5324                         return ret;
5325                 }
5326         }
5327         ret = ci_populate_pm_base(adev);
5328         if (ret) {
5329                 DRM_ERROR("ci_populate_pm_base failed\n");
5330                 return ret;
5331         }
5332         ci_dpm_start_smc(adev);
5333         ci_enable_vr_hot_gpio_interrupt(adev);
5334         ret = ci_notify_smc_display_change(adev, false);
5335         if (ret) {
5336                 DRM_ERROR("ci_notify_smc_display_change failed\n");
5337                 return ret;
5338         }
5339         ci_enable_sclk_control(adev, true);
5340         ret = ci_enable_ulv(adev, true);
5341         if (ret) {
5342                 DRM_ERROR("ci_enable_ulv failed\n");
5343                 return ret;
5344         }
5345         ret = ci_enable_ds_master_switch(adev, true);
5346         if (ret) {
5347                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5348                 return ret;
5349         }
5350         ret = ci_start_dpm(adev);
5351         if (ret) {
5352                 DRM_ERROR("ci_start_dpm failed\n");
5353                 return ret;
5354         }
5355         ret = ci_enable_didt(adev, true);
5356         if (ret) {
5357                 DRM_ERROR("ci_enable_didt failed\n");
5358                 return ret;
5359         }
5360         ret = ci_enable_smc_cac(adev, true);
5361         if (ret) {
5362                 DRM_ERROR("ci_enable_smc_cac failed\n");
5363                 return ret;
5364         }
5365         ret = ci_enable_power_containment(adev, true);
5366         if (ret) {
5367                 DRM_ERROR("ci_enable_power_containment failed\n");
5368                 return ret;
5369         }
5370
5371         ret = ci_power_control_set_level(adev);
5372         if (ret) {
5373                 DRM_ERROR("ci_power_control_set_level failed\n");
5374                 return ret;
5375         }
5376
5377         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5378
5379         ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5380         if (ret) {
5381                 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5382                 return ret;
5383         }
5384
5385         ci_thermal_start_thermal_controller(adev);
5386
5387         ci_update_current_ps(adev, boot_ps);
5388
5389         return 0;
5390 }
5391
5392 static void ci_dpm_disable(struct amdgpu_device *adev)
5393 {
5394         struct ci_power_info *pi = ci_get_pi(adev);
5395         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5396
5397         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5398                        AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5399         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5400                        AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5401
5402         ci_dpm_powergate_uvd(adev, true);
5403
5404         if (!amdgpu_ci_is_smc_running(adev))
5405                 return;
5406
5407         ci_thermal_stop_thermal_controller(adev);
5408
5409         if (pi->thermal_protection)
5410                 ci_enable_thermal_protection(adev, false);
5411         ci_enable_power_containment(adev, false);
5412         ci_enable_smc_cac(adev, false);
5413         ci_enable_didt(adev, false);
5414         ci_enable_spread_spectrum(adev, false);
5415         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5416         ci_stop_dpm(adev);
5417         ci_enable_ds_master_switch(adev, false);
5418         ci_enable_ulv(adev, false);
5419         ci_clear_vc(adev);
5420         ci_reset_to_default(adev);
5421         ci_dpm_stop_smc(adev);
5422         ci_force_switch_to_arb_f0(adev);
5423         ci_enable_thermal_based_sclk_dpm(adev, false);
5424
5425         ci_update_current_ps(adev, boot_ps);
5426 }
5427
5428 static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5429 {
5430         struct ci_power_info *pi = ci_get_pi(adev);
5431         struct amdgpu_ps *new_ps = &pi->requested_rps;
5432         struct amdgpu_ps *old_ps = &pi->current_rps;
5433         int ret;
5434
5435         ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5436         if (pi->pcie_performance_request)
5437                 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5438         ret = ci_freeze_sclk_mclk_dpm(adev);
5439         if (ret) {
5440                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5441                 return ret;
5442         }
5443         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5444         if (ret) {
5445                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5446                 return ret;
5447         }
5448         ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5449         if (ret) {
5450                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5451                 return ret;
5452         }
5453
5454         ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5455         if (ret) {
5456                 DRM_ERROR("ci_update_vce_dpm failed\n");
5457                 return ret;
5458         }
5459
5460         ret = ci_update_sclk_t(adev);
5461         if (ret) {
5462                 DRM_ERROR("ci_update_sclk_t failed\n");
5463                 return ret;
5464         }
5465         if (pi->caps_dynamic_ac_timing) {
5466                 ret = ci_update_and_upload_mc_reg_table(adev);
5467                 if (ret) {
5468                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5469                         return ret;
5470                 }
5471         }
5472         ret = ci_program_memory_timing_parameters(adev);
5473         if (ret) {
5474                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5475                 return ret;
5476         }
5477         ret = ci_unfreeze_sclk_mclk_dpm(adev);
5478         if (ret) {
5479                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5480                 return ret;
5481         }
5482         ret = ci_upload_dpm_level_enable_mask(adev);
5483         if (ret) {
5484                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5485                 return ret;
5486         }
5487         if (pi->pcie_performance_request)
5488                 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5489
5490         return 0;
5491 }
5492
5493 #if 0
5494 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5495 {
5496         ci_set_boot_state(adev);
5497 }
5498 #endif
5499
5500 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5501 {
5502         ci_program_display_gap(adev);
5503 }
5504
5505 union power_info {
5506         struct _ATOM_POWERPLAY_INFO info;
5507         struct _ATOM_POWERPLAY_INFO_V2 info_2;
5508         struct _ATOM_POWERPLAY_INFO_V3 info_3;
5509         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5510         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5511         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5512 };
5513
5514 union pplib_clock_info {
5515         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5516         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5517         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5518         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5519         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5520         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5521 };
5522
5523 union pplib_power_state {
5524         struct _ATOM_PPLIB_STATE v1;
5525         struct _ATOM_PPLIB_STATE_V2 v2;
5526 };
5527
5528 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5529                                           struct amdgpu_ps *rps,
5530                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5531                                           u8 table_rev)
5532 {
5533         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5534         rps->class = le16_to_cpu(non_clock_info->usClassification);
5535         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5536
5537         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5538                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5539                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5540         } else {
5541                 rps->vclk = 0;
5542                 rps->dclk = 0;
5543         }
5544
5545         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5546                 adev->pm.dpm.boot_ps = rps;
5547         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5548                 adev->pm.dpm.uvd_ps = rps;
5549 }
5550
5551 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5552                                       struct amdgpu_ps *rps, int index,
5553                                       union pplib_clock_info *clock_info)
5554 {
5555         struct ci_power_info *pi = ci_get_pi(adev);
5556         struct ci_ps *ps = ci_get_ps(rps);
5557         struct ci_pl *pl = &ps->performance_levels[index];
5558
5559         ps->performance_level_count = index + 1;
5560
5561         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5562         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5563         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5564         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5565
5566         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5567                                                    pi->sys_pcie_mask,
5568                                                    pi->vbios_boot_state.pcie_gen_bootup_value,
5569                                                    clock_info->ci.ucPCIEGen);
5570         pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5571                                                      pi->vbios_boot_state.pcie_lane_bootup_value,
5572                                                      le16_to_cpu(clock_info->ci.usPCIELane));
5573
5574         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5575                 pi->acpi_pcie_gen = pl->pcie_gen;
5576         }
5577
5578         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5579                 pi->ulv.supported = true;
5580                 pi->ulv.pl = *pl;
5581                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5582         }
5583
5584         /* patch up boot state */
5585         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5586                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5587                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5588                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5589                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5590         }
5591
5592         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5593         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5594                 pi->use_pcie_powersaving_levels = true;
5595                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5596                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
5597                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5598                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
5599                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5600                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
5601                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5602                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
5603                 break;
5604         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5605                 pi->use_pcie_performance_levels = true;
5606                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5607                         pi->pcie_gen_performance.max = pl->pcie_gen;
5608                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5609                         pi->pcie_gen_performance.min = pl->pcie_gen;
5610                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5611                         pi->pcie_lane_performance.max = pl->pcie_lane;
5612                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5613                         pi->pcie_lane_performance.min = pl->pcie_lane;
5614                 break;
5615         default:
5616                 break;
5617         }
5618 }
5619
5620 static int ci_parse_power_table(struct amdgpu_device *adev)
5621 {
5622         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5623         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5624         union pplib_power_state *power_state;
5625         int i, j, k, non_clock_array_index, clock_array_index;
5626         union pplib_clock_info *clock_info;
5627         struct _StateArray *state_array;
5628         struct _ClockInfoArray *clock_info_array;
5629         struct _NonClockInfoArray *non_clock_info_array;
5630         union power_info *power_info;
5631         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5632         u16 data_offset;
5633         u8 frev, crev;
5634         u8 *power_state_offset;
5635         struct ci_ps *ps;
5636
5637         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5638                                    &frev, &crev, &data_offset))
5639                 return -EINVAL;
5640         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5641
5642         amdgpu_add_thermal_controller(adev);
5643
5644         state_array = (struct _StateArray *)
5645                 (mode_info->atom_context->bios + data_offset +
5646                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
5647         clock_info_array = (struct _ClockInfoArray *)
5648                 (mode_info->atom_context->bios + data_offset +
5649                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5650         non_clock_info_array = (struct _NonClockInfoArray *)
5651                 (mode_info->atom_context->bios + data_offset +
5652                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5653
5654         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5655                                   state_array->ucNumEntries, GFP_KERNEL);
5656         if (!adev->pm.dpm.ps)
5657                 return -ENOMEM;
5658         power_state_offset = (u8 *)state_array->states;
5659         for (i = 0; i < state_array->ucNumEntries; i++) {
5660                 u8 *idx;
5661                 power_state = (union pplib_power_state *)power_state_offset;
5662                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5663                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5664                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5665                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5666                 if (ps == NULL) {
5667                         kfree(adev->pm.dpm.ps);
5668                         return -ENOMEM;
5669                 }
5670                 adev->pm.dpm.ps[i].ps_priv = ps;
5671                 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5672                                               non_clock_info,
5673                                               non_clock_info_array->ucEntrySize);
5674                 k = 0;
5675                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5676                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5677                         clock_array_index = idx[j];
5678                         if (clock_array_index >= clock_info_array->ucNumEntries)
5679                                 continue;
5680                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5681                                 break;
5682                         clock_info = (union pplib_clock_info *)
5683                                 ((u8 *)&clock_info_array->clockInfo[0] +
5684                                  (clock_array_index * clock_info_array->ucEntrySize));
5685                         ci_parse_pplib_clock_info(adev,
5686                                                   &adev->pm.dpm.ps[i], k,
5687                                                   clock_info);
5688                         k++;
5689                 }
5690                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5691         }
5692         adev->pm.dpm.num_ps = state_array->ucNumEntries;
5693
5694         /* fill in the vce power states */
5695         for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
5696                 u32 sclk, mclk;
5697                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5698                 clock_info = (union pplib_clock_info *)
5699                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5700                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5701                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5702                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5703                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5704                 adev->pm.dpm.vce_states[i].sclk = sclk;
5705                 adev->pm.dpm.vce_states[i].mclk = mclk;
5706         }
5707
5708         return 0;
5709 }
5710
5711 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5712                                     struct ci_vbios_boot_state *boot_state)
5713 {
5714         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5715         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5716         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5717         u8 frev, crev;
5718         u16 data_offset;
5719
5720         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5721                                    &frev, &crev, &data_offset)) {
5722                 firmware_info =
5723                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5724                                                     data_offset);
5725                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5726                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5727                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5728                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5729                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5730                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5731                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5732
5733                 return 0;
5734         }
5735         return -EINVAL;
5736 }
5737
5738 static void ci_dpm_fini(struct amdgpu_device *adev)
5739 {
5740         int i;
5741
5742         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5743                 kfree(adev->pm.dpm.ps[i].ps_priv);
5744         }
5745         kfree(adev->pm.dpm.ps);
5746         kfree(adev->pm.dpm.priv);
5747         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5748         amdgpu_free_extended_power_table(adev);
5749 }
5750
5751 /**
5752  * ci_dpm_init_microcode - load ucode images from disk
5753  *
5754  * @adev: amdgpu_device pointer
5755  *
5756  * Use the firmware interface to load the ucode images into
5757  * the driver (not loaded into hw).
5758  * Returns 0 on success, error on failure.
5759  */
5760 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5761 {
5762         const char *chip_name;
5763         char fw_name[30];
5764         int err;
5765
5766         DRM_DEBUG("\n");
5767
5768         switch (adev->asic_type) {
5769         case CHIP_BONAIRE:
5770                 if ((adev->pdev->revision == 0x80) ||
5771                     (adev->pdev->revision == 0x81) ||
5772                     (adev->pdev->device == 0x665f))
5773                         chip_name = "bonaire_k";
5774                 else
5775                         chip_name = "bonaire";
5776                 break;
5777         case CHIP_HAWAII:
5778                 if (adev->pdev->revision == 0x80)
5779                         chip_name = "hawaii_k";
5780                 else
5781                         chip_name = "hawaii";
5782                 break;
5783         case CHIP_KAVERI:
5784         case CHIP_KABINI:
5785         case CHIP_MULLINS:
5786         default: BUG();
5787         }
5788
5789         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
5790         err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
5791         if (err)
5792                 goto out;
5793         err = amdgpu_ucode_validate(adev->pm.fw);
5794
5795 out:
5796         if (err) {
5797                 printk(KERN_ERR
5798                        "cik_smc: Failed to load firmware \"%s\"\n",
5799                        fw_name);
5800                 release_firmware(adev->pm.fw);
5801                 adev->pm.fw = NULL;
5802         }
5803         return err;
5804 }
5805
5806 static int ci_dpm_init(struct amdgpu_device *adev)
5807 {
5808         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5809         SMU7_Discrete_DpmTable *dpm_table;
5810         struct amdgpu_gpio_rec gpio;
5811         u16 data_offset, size;
5812         u8 frev, crev;
5813         struct ci_power_info *pi;
5814         int ret;
5815
5816         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5817         if (pi == NULL)
5818                 return -ENOMEM;
5819         adev->pm.dpm.priv = pi;
5820
5821         pi->sys_pcie_mask =
5822                 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5823                 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5824
5825         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5826
5827         pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5828         pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5829         pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5830         pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5831
5832         pi->pcie_lane_performance.max = 0;
5833         pi->pcie_lane_performance.min = 16;
5834         pi->pcie_lane_powersaving.max = 0;
5835         pi->pcie_lane_powersaving.min = 16;
5836
5837         ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5838         if (ret) {
5839                 ci_dpm_fini(adev);
5840                 return ret;
5841         }
5842
5843         ret = amdgpu_get_platform_caps(adev);
5844         if (ret) {
5845                 ci_dpm_fini(adev);
5846                 return ret;
5847         }
5848
5849         ret = amdgpu_parse_extended_power_table(adev);
5850         if (ret) {
5851                 ci_dpm_fini(adev);
5852                 return ret;
5853         }
5854
5855         ret = ci_parse_power_table(adev);
5856         if (ret) {
5857                 ci_dpm_fini(adev);
5858                 return ret;
5859         }
5860
5861         pi->dll_default_on = false;
5862         pi->sram_end = SMC_RAM_END;
5863
5864         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5865         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5866         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5867         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5868         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5869         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5870         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5871         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5872
5873         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5874
5875         pi->sclk_dpm_key_disabled = 0;
5876         pi->mclk_dpm_key_disabled = 0;
5877         pi->pcie_dpm_key_disabled = 0;
5878         pi->thermal_sclk_dpm_enabled = 0;
5879
5880         if (amdgpu_sclk_deep_sleep_en)
5881                 pi->caps_sclk_ds = true;
5882         else
5883                 pi->caps_sclk_ds = false;
5884
5885         pi->mclk_strobe_mode_threshold = 40000;
5886         pi->mclk_stutter_mode_threshold = 40000;
5887         pi->mclk_edc_enable_threshold = 40000;
5888         pi->mclk_edc_wr_enable_threshold = 40000;
5889
5890         ci_initialize_powertune_defaults(adev);
5891
5892         pi->caps_fps = false;
5893
5894         pi->caps_sclk_throttle_low_notification = false;
5895
5896         pi->caps_uvd_dpm = true;
5897         pi->caps_vce_dpm = true;
5898
5899         ci_get_leakage_voltages(adev);
5900         ci_patch_dependency_tables_with_leakage(adev);
5901         ci_set_private_data_variables_based_on_pptable(adev);
5902
5903         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5904                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5905         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5906                 ci_dpm_fini(adev);
5907                 return -ENOMEM;
5908         }
5909         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5910         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5911         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5912         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5913         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5914         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5915         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5916         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5917         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5918
5919         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5920         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5921         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5922
5923         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5924         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5925         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5926         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5927
5928         if (adev->asic_type == CHIP_HAWAII) {
5929                 pi->thermal_temp_setting.temperature_low = 94500;
5930                 pi->thermal_temp_setting.temperature_high = 95000;
5931                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5932         } else {
5933                 pi->thermal_temp_setting.temperature_low = 99500;
5934                 pi->thermal_temp_setting.temperature_high = 100000;
5935                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5936         }
5937
5938         pi->uvd_enabled = false;
5939
5940         dpm_table = &pi->smc_state_table;
5941
5942         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5943         if (gpio.valid) {
5944                 dpm_table->VRHotGpio = gpio.shift;
5945                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5946         } else {
5947                 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5948                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5949         }
5950
5951         gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
5952         if (gpio.valid) {
5953                 dpm_table->AcDcGpio = gpio.shift;
5954                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5955         } else {
5956                 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5957                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5958         }
5959
5960         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
5961         if (gpio.valid) {
5962                 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
5963
5964                 switch (gpio.shift) {
5965                 case 0:
5966                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5967                         tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5968                         break;
5969                 case 1:
5970                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5971                         tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5972                         break;
5973                 case 2:
5974                         tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
5975                         break;
5976                 case 3:
5977                         tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
5978                         break;
5979                 case 4:
5980                         tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
5981                         break;
5982                 default:
5983                         DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
5984                         break;
5985                 }
5986                 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
5987         }
5988
5989         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5990         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5991         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5992         if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5993                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5994         else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5995                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5996
5997         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5998                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5999                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6000                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
6001                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6002                 else
6003                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
6004         }
6005
6006         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
6007                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
6008                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6009                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
6010                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6011                 else
6012                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
6013         }
6014
6015         pi->vddc_phase_shed_control = true;
6016
6017 #if defined(CONFIG_ACPI)
6018         pi->pcie_performance_request =
6019                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
6020 #else
6021         pi->pcie_performance_request = false;
6022 #endif
6023
6024         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6025                                    &frev, &crev, &data_offset)) {
6026                 pi->caps_sclk_ss_support = true;
6027                 pi->caps_mclk_ss_support = true;
6028                 pi->dynamic_ss = true;
6029         } else {
6030                 pi->caps_sclk_ss_support = false;
6031                 pi->caps_mclk_ss_support = false;
6032                 pi->dynamic_ss = true;
6033         }
6034
6035         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6036                 pi->thermal_protection = true;
6037         else
6038                 pi->thermal_protection = false;
6039
6040         pi->caps_dynamic_ac_timing = true;
6041
6042         pi->uvd_power_gated = true;
6043
6044         /* make sure dc limits are valid */
6045         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6046             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6047                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6048                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6049
6050         pi->fan_ctrl_is_in_default_mode = true;
6051
6052         return 0;
6053 }
6054
6055 static void
6056 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6057                                                struct seq_file *m)
6058 {
6059         struct ci_power_info *pi = ci_get_pi(adev);
6060         struct amdgpu_ps *rps = &pi->current_rps;
6061         u32 sclk = ci_get_average_sclk_freq(adev);
6062         u32 mclk = ci_get_average_mclk_freq(adev);
6063         u32 activity_percent = 50;
6064         int ret;
6065
6066         ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6067                                         &activity_percent);
6068
6069         if (ret == 0) {
6070                 activity_percent += 0x80;
6071                 activity_percent >>= 8;
6072                 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6073         }
6074
6075         seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
6076         seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6077         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
6078                    sclk, mclk);
6079         seq_printf(m, "GPU load: %u %%\n", activity_percent);
6080 }
6081
6082 static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6083                                      struct amdgpu_ps *rps)
6084 {
6085         struct ci_ps *ps = ci_get_ps(rps);
6086         struct ci_pl *pl;
6087         int i;
6088
6089         amdgpu_dpm_print_class_info(rps->class, rps->class2);
6090         amdgpu_dpm_print_cap_info(rps->caps);
6091         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6092         for (i = 0; i < ps->performance_level_count; i++) {
6093                 pl = &ps->performance_levels[i];
6094                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6095                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6096         }
6097         amdgpu_dpm_print_ps_status(adev, rps);
6098 }
6099
6100 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6101 {
6102         struct ci_power_info *pi = ci_get_pi(adev);
6103         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6104
6105         if (low)
6106                 return requested_state->performance_levels[0].sclk;
6107         else
6108                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6109 }
6110
6111 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6112 {
6113         struct ci_power_info *pi = ci_get_pi(adev);
6114         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6115
6116         if (low)
6117                 return requested_state->performance_levels[0].mclk;
6118         else
6119                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6120 }
6121
6122 /* get temperature in millidegrees */
6123 static int ci_dpm_get_temp(struct amdgpu_device *adev)
6124 {
6125         u32 temp;
6126         int actual_temp = 0;
6127
6128         temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6129                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6130
6131         if (temp & 0x200)
6132                 actual_temp = 255;
6133         else
6134                 actual_temp = temp & 0x1ff;
6135
6136         actual_temp = actual_temp * 1000;
6137
6138         return actual_temp;
6139 }
6140
6141 static int ci_set_temperature_range(struct amdgpu_device *adev)
6142 {
6143         int ret;
6144
6145         ret = ci_thermal_enable_alert(adev, false);
6146         if (ret)
6147                 return ret;
6148         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6149                                                CISLANDS_TEMP_RANGE_MAX);
6150         if (ret)
6151                 return ret;
6152         ret = ci_thermal_enable_alert(adev, true);
6153         if (ret)
6154                 return ret;
6155         return ret;
6156 }
6157
6158 static int ci_dpm_early_init(void *handle)
6159 {
6160         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6161
6162         ci_dpm_set_dpm_funcs(adev);
6163         ci_dpm_set_irq_funcs(adev);
6164
6165         return 0;
6166 }
6167
6168 static int ci_dpm_late_init(void *handle)
6169 {
6170         int ret;
6171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6172
6173         if (!amdgpu_dpm)
6174                 return 0;
6175
6176         /* init the sysfs and debugfs files late */
6177         ret = amdgpu_pm_sysfs_init(adev);
6178         if (ret)
6179                 return ret;
6180
6181         ret = ci_set_temperature_range(adev);
6182         if (ret)
6183                 return ret;
6184
6185         return 0;
6186 }
6187
6188 static int ci_dpm_sw_init(void *handle)
6189 {
6190         int ret;
6191         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6192
6193         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
6194         if (ret)
6195                 return ret;
6196
6197         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
6198         if (ret)
6199                 return ret;
6200
6201         /* default to balanced state */
6202         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6203         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6204         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
6205         adev->pm.default_sclk = adev->clock.default_sclk;
6206         adev->pm.default_mclk = adev->clock.default_mclk;
6207         adev->pm.current_sclk = adev->clock.default_sclk;
6208         adev->pm.current_mclk = adev->clock.default_mclk;
6209         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6210
6211         if (amdgpu_dpm == 0)
6212                 return 0;
6213
6214         ret = ci_dpm_init_microcode(adev);
6215         if (ret)
6216                 return ret;
6217
6218         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6219         mutex_lock(&adev->pm.mutex);
6220         ret = ci_dpm_init(adev);
6221         if (ret)
6222                 goto dpm_failed;
6223         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6224         if (amdgpu_dpm == 1)
6225                 amdgpu_pm_print_power_states(adev);
6226         mutex_unlock(&adev->pm.mutex);
6227         DRM_INFO("amdgpu: dpm initialized\n");
6228
6229         return 0;
6230
6231 dpm_failed:
6232         ci_dpm_fini(adev);
6233         mutex_unlock(&adev->pm.mutex);
6234         DRM_ERROR("amdgpu: dpm initialization failed\n");
6235         return ret;
6236 }
6237
6238 static int ci_dpm_sw_fini(void *handle)
6239 {
6240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6241
6242         flush_work(&adev->pm.dpm.thermal.work);
6243
6244         mutex_lock(&adev->pm.mutex);
6245         amdgpu_pm_sysfs_fini(adev);
6246         ci_dpm_fini(adev);
6247         mutex_unlock(&adev->pm.mutex);
6248
6249         release_firmware(adev->pm.fw);
6250         adev->pm.fw = NULL;
6251
6252         return 0;
6253 }
6254
6255 static int ci_dpm_hw_init(void *handle)
6256 {
6257         int ret;
6258
6259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6260
6261         if (!amdgpu_dpm)
6262                 return 0;
6263
6264         mutex_lock(&adev->pm.mutex);
6265         ci_dpm_setup_asic(adev);
6266         ret = ci_dpm_enable(adev);
6267         if (ret)
6268                 adev->pm.dpm_enabled = false;
6269         else
6270                 adev->pm.dpm_enabled = true;
6271         mutex_unlock(&adev->pm.mutex);
6272
6273         return ret;
6274 }
6275
6276 static int ci_dpm_hw_fini(void *handle)
6277 {
6278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6279
6280         if (adev->pm.dpm_enabled) {
6281                 mutex_lock(&adev->pm.mutex);
6282                 ci_dpm_disable(adev);
6283                 mutex_unlock(&adev->pm.mutex);
6284         }
6285
6286         return 0;
6287 }
6288
6289 static int ci_dpm_suspend(void *handle)
6290 {
6291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6292
6293         if (adev->pm.dpm_enabled) {
6294                 mutex_lock(&adev->pm.mutex);
6295                 /* disable dpm */
6296                 ci_dpm_disable(adev);
6297                 /* reset the power state */
6298                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6299                 mutex_unlock(&adev->pm.mutex);
6300         }
6301         return 0;
6302 }
6303
6304 static int ci_dpm_resume(void *handle)
6305 {
6306         int ret;
6307         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6308
6309         if (adev->pm.dpm_enabled) {
6310                 /* asic init will reset to the boot state */
6311                 mutex_lock(&adev->pm.mutex);
6312                 ci_dpm_setup_asic(adev);
6313                 ret = ci_dpm_enable(adev);
6314                 if (ret)
6315                         adev->pm.dpm_enabled = false;
6316                 else
6317                         adev->pm.dpm_enabled = true;
6318                 mutex_unlock(&adev->pm.mutex);
6319                 if (adev->pm.dpm_enabled)
6320                         amdgpu_pm_compute_clocks(adev);
6321         }
6322         return 0;
6323 }
6324
6325 static bool ci_dpm_is_idle(void *handle)
6326 {
6327         /* XXX */
6328         return true;
6329 }
6330
6331 static int ci_dpm_wait_for_idle(void *handle)
6332 {
6333         /* XXX */
6334         return 0;
6335 }
6336
6337 static int ci_dpm_soft_reset(void *handle)
6338 {
6339         return 0;
6340 }
6341
6342 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6343                                       struct amdgpu_irq_src *source,
6344                                       unsigned type,
6345                                       enum amdgpu_interrupt_state state)
6346 {
6347         u32 cg_thermal_int;
6348
6349         switch (type) {
6350         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6351                 switch (state) {
6352                 case AMDGPU_IRQ_STATE_DISABLE:
6353                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6354                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6355                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6356                         break;
6357                 case AMDGPU_IRQ_STATE_ENABLE:
6358                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6359                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6360                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6361                         break;
6362                 default:
6363                         break;
6364                 }
6365                 break;
6366
6367         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6368                 switch (state) {
6369                 case AMDGPU_IRQ_STATE_DISABLE:
6370                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6371                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6372                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6373                         break;
6374                 case AMDGPU_IRQ_STATE_ENABLE:
6375                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6376                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6377                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6378                         break;
6379                 default:
6380                         break;
6381                 }
6382                 break;
6383
6384         default:
6385                 break;
6386         }
6387         return 0;
6388 }
6389
6390 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6391                                     struct amdgpu_irq_src *source,
6392                                     struct amdgpu_iv_entry *entry)
6393 {
6394         bool queue_thermal = false;
6395
6396         if (entry == NULL)
6397                 return -EINVAL;
6398
6399         switch (entry->src_id) {
6400         case 230: /* thermal low to high */
6401                 DRM_DEBUG("IH: thermal low to high\n");
6402                 adev->pm.dpm.thermal.high_to_low = false;
6403                 queue_thermal = true;
6404                 break;
6405         case 231: /* thermal high to low */
6406                 DRM_DEBUG("IH: thermal high to low\n");
6407                 adev->pm.dpm.thermal.high_to_low = true;
6408                 queue_thermal = true;
6409                 break;
6410         default:
6411                 break;
6412         }
6413
6414         if (queue_thermal)
6415                 schedule_work(&adev->pm.dpm.thermal.work);
6416
6417         return 0;
6418 }
6419
6420 static int ci_dpm_set_clockgating_state(void *handle,
6421                                           enum amd_clockgating_state state)
6422 {
6423         return 0;
6424 }
6425
6426 static int ci_dpm_set_powergating_state(void *handle,
6427                                           enum amd_powergating_state state)
6428 {
6429         return 0;
6430 }
6431
6432 static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
6433                 enum pp_clock_type type, char *buf)
6434 {
6435         struct ci_power_info *pi = ci_get_pi(adev);
6436         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
6437         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
6438         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
6439
6440         int i, now, size = 0;
6441         uint32_t clock, pcie_speed;
6442
6443         switch (type) {
6444         case PP_SCLK:
6445                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
6446                 clock = RREG32(mmSMC_MSG_ARG_0);
6447
6448                 for (i = 0; i < sclk_table->count; i++) {
6449                         if (clock > sclk_table->dpm_levels[i].value)
6450                                 continue;
6451                         break;
6452                 }
6453                 now = i;
6454
6455                 for (i = 0; i < sclk_table->count; i++)
6456                         size += sprintf(buf + size, "%d: %uMhz %s\n",
6457                                         i, sclk_table->dpm_levels[i].value / 100,
6458                                         (i == now) ? "*" : "");
6459                 break;
6460         case PP_MCLK:
6461                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
6462                 clock = RREG32(mmSMC_MSG_ARG_0);
6463
6464                 for (i = 0; i < mclk_table->count; i++) {
6465                         if (clock > mclk_table->dpm_levels[i].value)
6466                                 continue;
6467                         break;
6468                 }
6469                 now = i;
6470
6471                 for (i = 0; i < mclk_table->count; i++)
6472                         size += sprintf(buf + size, "%d: %uMhz %s\n",
6473                                         i, mclk_table->dpm_levels[i].value / 100,
6474                                         (i == now) ? "*" : "");
6475                 break;
6476         case PP_PCIE:
6477                 pcie_speed = ci_get_current_pcie_speed(adev);
6478                 for (i = 0; i < pcie_table->count; i++) {
6479                         if (pcie_speed != pcie_table->dpm_levels[i].value)
6480                                 continue;
6481                         break;
6482                 }
6483                 now = i;
6484
6485                 for (i = 0; i < pcie_table->count; i++)
6486                         size += sprintf(buf + size, "%d: %s %s\n", i,
6487                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
6488                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6489                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6490                                         (i == now) ? "*" : "");
6491                 break;
6492         default:
6493                 break;
6494         }
6495
6496         return size;
6497 }
6498
6499 static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
6500                 enum pp_clock_type type, uint32_t mask)
6501 {
6502         struct ci_power_info *pi = ci_get_pi(adev);
6503
6504         if (adev->pm.dpm.forced_level
6505                         != AMDGPU_DPM_FORCED_LEVEL_MANUAL)
6506                 return -EINVAL;
6507
6508         switch (type) {
6509         case PP_SCLK:
6510                 if (!pi->sclk_dpm_key_disabled)
6511                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6512                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
6513                                         pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
6514                 break;
6515
6516         case PP_MCLK:
6517                 if (!pi->mclk_dpm_key_disabled)
6518                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6519                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
6520                                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
6521                 break;
6522
6523         case PP_PCIE:
6524         {
6525                 uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
6526                 uint32_t level = 0;
6527
6528                 while (tmp >>= 1)
6529                         level++;
6530
6531                 if (!pi->pcie_dpm_key_disabled)
6532                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6533                                         PPSMC_MSG_PCIeDPM_ForceLevel,
6534                                         level);
6535                 break;
6536         }
6537         default:
6538                 break;
6539         }
6540
6541         return 0;
6542 }
6543
6544 static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
6545 {
6546         struct ci_power_info *pi = ci_get_pi(adev);
6547         struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
6548         struct ci_single_dpm_table *golden_sclk_table =
6549                         &(pi->golden_dpm_table.sclk_table);
6550         int value;
6551
6552         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
6553                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
6554                         100 /
6555                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6556
6557         return value;
6558 }
6559
6560 static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
6561 {
6562         struct ci_power_info *pi = ci_get_pi(adev);
6563         struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6564         struct ci_single_dpm_table *golden_sclk_table =
6565                         &(pi->golden_dpm_table.sclk_table);
6566
6567         if (value > 20)
6568                 value = 20;
6569
6570         ps->performance_levels[ps->performance_level_count - 1].sclk =
6571                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
6572                         value / 100 +
6573                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6574
6575         return 0;
6576 }
6577
6578 static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
6579 {
6580         struct ci_power_info *pi = ci_get_pi(adev);
6581         struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
6582         struct ci_single_dpm_table *golden_mclk_table =
6583                         &(pi->golden_dpm_table.mclk_table);
6584         int value;
6585
6586         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
6587                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
6588                         100 /
6589                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6590
6591         return value;
6592 }
6593
6594 static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
6595 {
6596         struct ci_power_info *pi = ci_get_pi(adev);
6597         struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6598         struct ci_single_dpm_table *golden_mclk_table =
6599                         &(pi->golden_dpm_table.mclk_table);
6600
6601         if (value > 20)
6602                 value = 20;
6603
6604         ps->performance_levels[ps->performance_level_count - 1].mclk =
6605                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
6606                         value / 100 +
6607                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6608
6609         return 0;
6610 }
6611
6612 const struct amd_ip_funcs ci_dpm_ip_funcs = {
6613         .name = "ci_dpm",
6614         .early_init = ci_dpm_early_init,
6615         .late_init = ci_dpm_late_init,
6616         .sw_init = ci_dpm_sw_init,
6617         .sw_fini = ci_dpm_sw_fini,
6618         .hw_init = ci_dpm_hw_init,
6619         .hw_fini = ci_dpm_hw_fini,
6620         .suspend = ci_dpm_suspend,
6621         .resume = ci_dpm_resume,
6622         .is_idle = ci_dpm_is_idle,
6623         .wait_for_idle = ci_dpm_wait_for_idle,
6624         .soft_reset = ci_dpm_soft_reset,
6625         .set_clockgating_state = ci_dpm_set_clockgating_state,
6626         .set_powergating_state = ci_dpm_set_powergating_state,
6627 };
6628
6629 static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
6630         .get_temperature = &ci_dpm_get_temp,
6631         .pre_set_power_state = &ci_dpm_pre_set_power_state,
6632         .set_power_state = &ci_dpm_set_power_state,
6633         .post_set_power_state = &ci_dpm_post_set_power_state,
6634         .display_configuration_changed = &ci_dpm_display_configuration_changed,
6635         .get_sclk = &ci_dpm_get_sclk,
6636         .get_mclk = &ci_dpm_get_mclk,
6637         .print_power_state = &ci_dpm_print_power_state,
6638         .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
6639         .force_performance_level = &ci_dpm_force_performance_level,
6640         .vblank_too_short = &ci_dpm_vblank_too_short,
6641         .powergate_uvd = &ci_dpm_powergate_uvd,
6642         .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
6643         .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
6644         .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
6645         .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
6646         .print_clock_levels = ci_dpm_print_clock_levels,
6647         .force_clock_level = ci_dpm_force_clock_level,
6648         .get_sclk_od = ci_dpm_get_sclk_od,
6649         .set_sclk_od = ci_dpm_set_sclk_od,
6650         .get_mclk_od = ci_dpm_get_mclk_od,
6651         .set_mclk_od = ci_dpm_set_mclk_od,
6652 };
6653
6654 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
6655 {
6656         if (adev->pm.funcs == NULL)
6657                 adev->pm.funcs = &ci_dpm_funcs;
6658 }
6659
6660 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
6661         .set = ci_dpm_set_interrupt_state,
6662         .process = ci_dpm_process_interrupt,
6663 };
6664
6665 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6666 {
6667         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6668         adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
6669 }