drivers/gpu/drm/amd/amdgpu/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_ucode.h"
  29 #include "cikd.h"
  30 #include "amdgpu_dpm.h"
  31 #include "ci_dpm.h"
  32 #include "gfx_v7_0.h"
  33 #include "atom.h"
  34 #include "amd_pcie.h"
  35 #include <linux/seq_file.h>
  36
  37 #include "smu/smu_7_0_1_d.h"
  38 #include "smu/smu_7_0_1_sh_mask.h"
  39
  40 #include "dce/dce_8_0_d.h"
  41 #include "dce/dce_8_0_sh_mask.h"
  42
  43 #include "bif/bif_4_1_d.h"
  44 #include "bif/bif_4_1_sh_mask.h"
  45
  46 #include "gca/gfx_7_2_d.h"
  47 #include "gca/gfx_7_2_sh_mask.h"
  48
  49 #include "gmc/gmc_7_1_d.h"
  50 #include "gmc/gmc_7_1_sh_mask.h"
  51
  52 /*(DEBLOBBED)*/
  53
  54 #define MC_CG_ARB_FREQ_F0           0x0a
  55 #define MC_CG_ARB_FREQ_F1           0x0b
  56 #define MC_CG_ARB_FREQ_F2           0x0c
  57 #define MC_CG_ARB_FREQ_F3           0x0d
  58
  59 #define SMC_RAM_END 0x40000
  60
  61 #define VOLTAGE_SCALE               4
  62 #define VOLTAGE_VID_OFFSET_SCALE1    625
  63 #define VOLTAGE_VID_OFFSET_SCALE2    100
  64
  65 static const struct ci_pt_defaults defaults_hawaii_xt =
  66 {
  67         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  68         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  69         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  70 };
  71
  72 static const struct ci_pt_defaults defaults_hawaii_pro =
  73 {
  74         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  75         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  76         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  77 };
  78
  79 static const struct ci_pt_defaults defaults_bonaire_xt =
  80 {
  81         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  82         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  83         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  84 };
  85
  86 #if 0
  87 static const struct ci_pt_defaults defaults_bonaire_pro =
  88 {
  89         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  90         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  91         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  92 };
  93 #endif
  94
  95 static const struct ci_pt_defaults defaults_saturn_xt =
  96 {
  97         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  98         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  99         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
 100 };
 101
 102 #if 0
 103 static const struct ci_pt_defaults defaults_saturn_pro =
 104 {
 105         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
 106         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
 107         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
 108 };
 109 #endif
 110
 111 static const struct ci_pt_config_reg didt_config_ci[] =
 112 {
 113         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 162         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 163         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 164         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 165         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 166         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 167         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 168         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 169         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 170         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 171         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 172         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 173         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 174         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 175         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 176         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 177         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 178         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 179         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 180         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 181         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 182         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 183         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 184         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 185         { 0xFFFFFFFF }
 186 };
 187
 188 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
 189 {
 190         return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
 191 }
 192
 193 #define MC_CG_ARB_FREQ_F0           0x0a
 194 #define MC_CG_ARB_FREQ_F1           0x0b
 195 #define MC_CG_ARB_FREQ_F2           0x0c
 196 #define MC_CG_ARB_FREQ_F3           0x0d
 197
 198 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
 199                                        u32 arb_freq_src, u32 arb_freq_dest)
 200 {
 201         u32 mc_arb_dram_timing;
 202         u32 mc_arb_dram_timing2;
 203         u32 burst_time;
 204         u32 mc_cg_config;
 205
 206         switch (arb_freq_src) {
 207         case MC_CG_ARB_FREQ_F0:
 208                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
 209                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
 210                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
 211                          MC_ARB_BURST_TIME__STATE0__SHIFT;
 212                 break;
 213         case MC_CG_ARB_FREQ_F1:
 214                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING_1);
 215                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
 216                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
 217                          MC_ARB_BURST_TIME__STATE1__SHIFT;
 218                 break;
 219         default:
 220                 return -EINVAL;
 221         }
 222
 223         switch (arb_freq_dest) {
 224         case MC_CG_ARB_FREQ_F0:
 225                 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 226                 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 227                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
 228                         ~MC_ARB_BURST_TIME__STATE0_MASK);
 229                 break;
 230         case MC_CG_ARB_FREQ_F1:
 231                 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 232                 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 233                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
 234                         ~MC_ARB_BURST_TIME__STATE1_MASK);
 235                 break;
 236         default:
 237                 return -EINVAL;
 238         }
 239
 240         mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
 241         WREG32(mmMC_CG_CONFIG, mc_cg_config);
 242         WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
 243                 ~MC_ARB_CG__CG_ARB_REQ_MASK);
 244
 245         return 0;
 246 }
 247
 248 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
 249 {
 250         u8 mc_para_index;
 251
 252         if (memory_clock < 10000)
 253                 mc_para_index = 0;
 254         else if (memory_clock >= 80000)
 255                 mc_para_index = 0x0f;
 256         else
 257                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
 258         return mc_para_index;
 259 }
 260
 261 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
 262 {
 263         u8 mc_para_index;
 264
 265         if (strobe_mode) {
 266                 if (memory_clock < 12500)
 267                         mc_para_index = 0x00;
 268                 else if (memory_clock > 47500)
 269                         mc_para_index = 0x0f;
 270                 else
 271                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
 272         } else {
 273                 if (memory_clock < 65000)
 274                         mc_para_index = 0x00;
 275                 else if (memory_clock > 135000)
 276                         mc_para_index = 0x0f;
 277                 else
 278                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
 279         }
 280         return mc_para_index;
 281 }
 282
 283 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
 284                                                      u32 max_voltage_steps,
 285                                                      struct atom_voltage_table *voltage_table)
 286 {
 287         unsigned int i, diff;
 288
 289         if (voltage_table->count <= max_voltage_steps)
 290                 return;
 291
 292         diff = voltage_table->count - max_voltage_steps;
 293
 294         for (i = 0; i < max_voltage_steps; i++)
 295                 voltage_table->entries[i] = voltage_table->entries[i + diff];
 296
 297         voltage_table->count = max_voltage_steps;
 298 }
 299
 300 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
 301                                          struct atom_voltage_table_entry *voltage_table,
 302                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 303 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
 304 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
 305                                        u32 target_tdp);
 306 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
 307 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
 308 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
 309
 310 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
 311                                                              PPSMC_Msg msg, u32 parameter);
 312 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
 313 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
 314
 315 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
 316 {
 317         struct ci_power_info *pi = adev->pm.dpm.priv;
 318
 319         return pi;
 320 }
 321
 322 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
 323 {
 324         struct ci_ps *ps = rps->ps_priv;
 325
 326         return ps;
 327 }
 328
 329 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
 330 {
 331         struct ci_power_info *pi = ci_get_pi(adev);
 332
 333         switch (adev->pdev->device) {
 334         case 0x6649:
 335         case 0x6650:
 336         case 0x6651:
 337         case 0x6658:
 338         case 0x665C:
 339         case 0x665D:
 340         default:
 341                 pi->powertune_defaults = &defaults_bonaire_xt;
 342                 break;
 343         case 0x6640:
 344         case 0x6641:
 345         case 0x6646:
 346         case 0x6647:
 347                 pi->powertune_defaults = &defaults_saturn_xt;
 348                 break;
 349         case 0x67B8:
 350         case 0x67B0:
 351                 pi->powertune_defaults = &defaults_hawaii_xt;
 352                 break;
 353         case 0x67BA:
 354         case 0x67B1:
 355                 pi->powertune_defaults = &defaults_hawaii_pro;
 356                 break;
 357         case 0x67A0:
 358         case 0x67A1:
 359         case 0x67A2:
 360         case 0x67A8:
 361         case 0x67A9:
 362         case 0x67AA:
 363         case 0x67B9:
 364         case 0x67BE:
 365                 pi->powertune_defaults = &defaults_bonaire_xt;
 366                 break;
 367         }
 368
 369         pi->dte_tj_offset = 0;
 370
 371         pi->caps_power_containment = true;
 372         pi->caps_cac = false;
 373         pi->caps_sq_ramping = false;
 374         pi->caps_db_ramping = false;
 375         pi->caps_td_ramping = false;
 376         pi->caps_tcp_ramping = false;
 377
 378         if (pi->caps_power_containment) {
 379                 pi->caps_cac = true;
 380                 if (adev->asic_type == CHIP_HAWAII)
 381                         pi->enable_bapm_feature = false;
 382                 else
 383                         pi->enable_bapm_feature = true;
 384                 pi->enable_tdc_limit_feature = true;
 385                 pi->enable_pkg_pwr_tracking_feature = true;
 386         }
 387 }
 388
 389 static u8 ci_convert_to_vid(u16 vddc)
 390 {
 391         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 392 }
 393
 394 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
 395 {
 396         struct ci_power_info *pi = ci_get_pi(adev);
 397         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 398         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 399         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 400         u32 i;
 401
 402         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 403                 return -EINVAL;
 404         if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 405                 return -EINVAL;
 406         if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
 407             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 408                 return -EINVAL;
 409
 410         for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 411                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 412                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 413                         hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 414                         hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 415                 } else {
 416                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 417                         hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 418                 }
 419         }
 420         return 0;
 421 }
 422
 423 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
 424 {
 425         struct ci_power_info *pi = ci_get_pi(adev);
 426         u8 *vid = pi->smc_powertune_table.VddCVid;
 427         u32 i;
 428
 429         if (pi->vddc_voltage_table.count > 8)
 430                 return -EINVAL;
 431
 432         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 433                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 434
 435         return 0;
 436 }
 437
 438 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
 439 {
 440         struct ci_power_info *pi = ci_get_pi(adev);
 441         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 442
 443         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 444         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 445         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 446         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 447
 448         return 0;
 449 }
 450
 451 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
 452 {
 453         struct ci_power_info *pi = ci_get_pi(adev);
 454         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 455         u16 tdc_limit;
 456
 457         tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 458         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 459         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 460                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 461         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 462
 463         return 0;
 464 }
 465
 466 static int ci_populate_dw8(struct amdgpu_device *adev)
 467 {
 468         struct ci_power_info *pi = ci_get_pi(adev);
 469         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 470         int ret;
 471
 472         ret = amdgpu_ci_read_smc_sram_dword(adev,
 473                                      SMU7_FIRMWARE_HEADER_LOCATION +
 474                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 475                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 476                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 477                                      pi->sram_end);
 478         if (ret)
 479                 return -EINVAL;
 480         else
 481                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 482
 483         return 0;
 484 }
 485
 486 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
 487 {
 488         struct ci_power_info *pi = ci_get_pi(adev);
 489
 490         if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
 491             (adev->pm.dpm.fan.fan_output_sensitivity == 0))
 492                 adev->pm.dpm.fan.fan_output_sensitivity =
 493                         adev->pm.dpm.fan.default_fan_output_sensitivity;
 494
 495         pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
 496                 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
 497
 498         return 0;
 499 }
 500
 501 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
 502 {
 503         struct ci_power_info *pi = ci_get_pi(adev);
 504         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 505         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 506         int i, min, max;
 507
 508         min = max = hi_vid[0];
 509         for (i = 0; i < 8; i++) {
 510                 if (0 != hi_vid[i]) {
 511                         if (min > hi_vid[i])
 512                                 min = hi_vid[i];
 513                         if (max < hi_vid[i])
 514                                 max = hi_vid[i];
 515                 }
 516
 517                 if (0 != lo_vid[i]) {
 518                         if (min > lo_vid[i])
 519                                 min = lo_vid[i];
 520                         if (max < lo_vid[i])
 521                                 max = lo_vid[i];
 522                 }
 523         }
 524
 525         if ((min == 0) || (max == 0))
 526                 return -EINVAL;
 527         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 528         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 529
 530         return 0;
 531 }
 532
 533 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
 534 {
 535         struct ci_power_info *pi = ci_get_pi(adev);
 536         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 537         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 538         struct amdgpu_cac_tdp_table *cac_tdp_table =
 539                 adev->pm.dpm.dyn_state.cac_tdp_table;
 540
 541         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 542         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 543
 544         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 545         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 546
 547         return 0;
 548 }
 549
 550 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
 551 {
 552         struct ci_power_info *pi = ci_get_pi(adev);
 553         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 554         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 555         struct amdgpu_cac_tdp_table *cac_tdp_table =
 556                 adev->pm.dpm.dyn_state.cac_tdp_table;
 557         struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
 558         int i, j, k;
 559         const u16 *def1;
 560         const u16 *def2;
 561
 562         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 563         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 564
 565         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 566         dpm_table->GpuTjMax =
 567                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 568         dpm_table->GpuTjHyst = 8;
 569
 570         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 571
 572         if (ppm) {
 573                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 574                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 575         } else {
 576                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 577                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 578         }
 579
 580         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 581         def1 = pt_defaults->bapmti_r;
 582         def2 = pt_defaults->bapmti_rc;
 583
 584         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 585                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 586                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 587                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 588                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 589                                 def1++;
 590                                 def2++;
 591                         }
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int ci_populate_pm_base(struct amdgpu_device *adev)
 599 {
 600         struct ci_power_info *pi = ci_get_pi(adev);
 601         u32 pm_fuse_table_offset;
 602         int ret;
 603
 604         if (pi->caps_power_containment) {
 605                 ret = amdgpu_ci_read_smc_sram_dword(adev,
 606                                              SMU7_FIRMWARE_HEADER_LOCATION +
 607                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 608                                              &pm_fuse_table_offset, pi->sram_end);
 609                 if (ret)
 610                         return ret;
 611                 ret = ci_populate_bapm_vddc_vid_sidd(adev);
 612                 if (ret)
 613                         return ret;
 614                 ret = ci_populate_vddc_vid(adev);
 615                 if (ret)
 616                         return ret;
 617                 ret = ci_populate_svi_load_line(adev);
 618                 if (ret)
 619                         return ret;
 620                 ret = ci_populate_tdc_limit(adev);
 621                 if (ret)
 622                         return ret;
 623                 ret = ci_populate_dw8(adev);
 624                 if (ret)
 625                         return ret;
 626                 ret = ci_populate_fuzzy_fan(adev);
 627                 if (ret)
 628                         return ret;
 629                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
 630                 if (ret)
 631                         return ret;
 632                 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
 633                 if (ret)
 634                         return ret;
 635                 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
 636                                            (u8 *)&pi->smc_powertune_table,
 637                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 638                 if (ret)
 639                         return ret;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
 646 {
 647         struct ci_power_info *pi = ci_get_pi(adev);
 648         u32 data;
 649
 650         if (pi->caps_sq_ramping) {
 651                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 652                 if (enable)
 653                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 654                 else
 655                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 656                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 657         }
 658
 659         if (pi->caps_db_ramping) {
 660                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 661                 if (enable)
 662                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 663                 else
 664                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 665                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 666         }
 667
 668         if (pi->caps_td_ramping) {
 669                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 670                 if (enable)
 671                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 672                 else
 673                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 674                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 675         }
 676
 677         if (pi->caps_tcp_ramping) {
 678                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 679                 if (enable)
 680                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 681                 else
 682                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 683                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 684         }
 685 }
 686
 687 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
 688                                           const struct ci_pt_config_reg *cac_config_regs)
 689 {
 690         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 691         u32 data;
 692         u32 cache = 0;
 693
 694         if (config_regs == NULL)
 695                 return -EINVAL;
 696
 697         while (config_regs->offset != 0xFFFFFFFF) {
 698                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 699                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 700                 } else {
 701                         switch (config_regs->type) {
 702                         case CISLANDS_CONFIGREG_SMC_IND:
 703                                 data = RREG32_SMC(config_regs->offset);
 704                                 break;
 705                         case CISLANDS_CONFIGREG_DIDT_IND:
 706                                 data = RREG32_DIDT(config_regs->offset);
 707                                 break;
 708                         default:
 709                                 data = RREG32(config_regs->offset);
 710                                 break;
 711                         }
 712
 713                         data &= ~config_regs->mask;
 714                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 715                         data |= cache;
 716
 717                         switch (config_regs->type) {
 718                         case CISLANDS_CONFIGREG_SMC_IND:
 719                                 WREG32_SMC(config_regs->offset, data);
 720                                 break;
 721                         case CISLANDS_CONFIGREG_DIDT_IND:
 722                                 WREG32_DIDT(config_regs->offset, data);
 723                                 break;
 724                         default:
 725                                 WREG32(config_regs->offset, data);
 726                                 break;
 727                         }
 728                         cache = 0;
 729                 }
 730                 config_regs++;
 731         }
 732         return 0;
 733 }
 734
 735 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
 736 {
 737         struct ci_power_info *pi = ci_get_pi(adev);
 738         int ret;
 739
 740         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 741             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 742                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 743
 744                 if (enable) {
 745                         ret = ci_program_pt_config_registers(adev, didt_config_ci);
 746                         if (ret) {
 747                                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 748                                 return ret;
 749                         }
 750                 }
 751
 752                 ci_do_enable_didt(adev, enable);
 753
 754                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
 761 {
 762         struct ci_power_info *pi = ci_get_pi(adev);
 763         PPSMC_Result smc_result;
 764         int ret = 0;
 765
 766         if (enable) {
 767                 pi->power_containment_features = 0;
 768                 if (pi->caps_power_containment) {
 769                         if (pi->enable_bapm_feature) {
 770                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
 771                                 if (smc_result != PPSMC_Result_OK)
 772                                         ret = -EINVAL;
 773                                 else
 774                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 775                         }
 776
 777                         if (pi->enable_tdc_limit_feature) {
 778                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
 779                                 if (smc_result != PPSMC_Result_OK)
 780                                         ret = -EINVAL;
 781                                 else
 782                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 783                         }
 784
 785                         if (pi->enable_pkg_pwr_tracking_feature) {
 786                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
 787                                 if (smc_result != PPSMC_Result_OK) {
 788                                         ret = -EINVAL;
 789                                 } else {
 790                                         struct amdgpu_cac_tdp_table *cac_tdp_table =
 791                                                 adev->pm.dpm.dyn_state.cac_tdp_table;
 792                                         u32 default_pwr_limit =
 793                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 794
 795                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 796
 797                                         ci_set_power_limit(adev, default_pwr_limit);
 798                                 }
 799                         }
 800                 }
 801         } else {
 802                 if (pi->caps_power_containment && pi->power_containment_features) {
 803                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 804                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
 805
 806                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 807                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
 808
 809                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 810                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
 811                         pi->power_containment_features = 0;
 812                 }
 813         }
 814
 815         return ret;
 816 }
 817
 818 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 819 {
 820         struct ci_power_info *pi = ci_get_pi(adev);
 821         PPSMC_Result smc_result;
 822         int ret = 0;
 823
 824         if (pi->caps_cac) {
 825                 if (enable) {
 826                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
 827                         if (smc_result != PPSMC_Result_OK) {
 828                                 ret = -EINVAL;
 829                                 pi->cac_enabled = false;
 830                         } else {
 831                                 pi->cac_enabled = true;
 832                         }
 833                 } else if (pi->cac_enabled) {
 834                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
 835                         pi->cac_enabled = false;
 836                 }
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
 843                                             bool enable)
 844 {
 845         struct ci_power_info *pi = ci_get_pi(adev);
 846         PPSMC_Result smc_result = PPSMC_Result_OK;
 847
 848         if (pi->thermal_sclk_dpm_enabled) {
 849                 if (enable)
 850                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
 851                 else
 852                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
 853         }
 854
 855         if (smc_result == PPSMC_Result_OK)
 856                 return 0;
 857         else
 858                 return -EINVAL;
 859 }
 860
 861 static int ci_power_control_set_level(struct amdgpu_device *adev)
 862 {
 863         struct ci_power_info *pi = ci_get_pi(adev);
 864         struct amdgpu_cac_tdp_table *cac_tdp_table =
 865                 adev->pm.dpm.dyn_state.cac_tdp_table;
 866         s32 adjust_percent;
 867         s32 target_tdp;
 868         int ret = 0;
 869         bool adjust_polarity = false; /* ??? */
 870
 871         if (pi->caps_power_containment) {
 872                 adjust_percent = adjust_polarity ?
 873                         adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
 874                 target_tdp = ((100 + adjust_percent) *
 875                               (s32)cac_tdp_table->configurable_tdp) / 100;
 876
 877                 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
 878         }
 879
 880         return ret;
 881 }
 882
 883 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 884 {
 885         struct ci_power_info *pi = ci_get_pi(adev);
 886
 887         pi->uvd_power_gated = gate;
 888
 889         if (gate) {
 890                 /* stop the UVD block */
 891                 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 892                                                         AMD_PG_STATE_GATE);
 893                 ci_update_uvd_dpm(adev, gate);
 894         } else {
 895                 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 896                                                         AMD_PG_STATE_UNGATE);
 897                 ci_update_uvd_dpm(adev, gate);
 898         }
 899 }
 900
 901 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
 902 {
 903         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
 904         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
 905
 906         /* disable mclk switching if the refresh is >120Hz, even if the
 907          * blanking period would allow it
 908          */
 909         if (amdgpu_dpm_get_vrefresh(adev) > 120)
 910                 return true;
 911
 912         if (vblank_time < switch_limit)
 913                 return true;
 914         else
 915                 return false;
 916
 917 }
 918
 919 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
 920                                         struct amdgpu_ps *rps)
 921 {
 922         struct ci_ps *ps = ci_get_ps(rps);
 923         struct ci_power_info *pi = ci_get_pi(adev);
 924         struct amdgpu_clock_and_voltage_limits *max_limits;
 925         bool disable_mclk_switching;
 926         u32 sclk, mclk;
 927         int i;
 928
 929         if (rps->vce_active) {
 930                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
 931                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
 932         } else {
 933                 rps->evclk = 0;
 934                 rps->ecclk = 0;
 935         }
 936
 937         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
 938             ci_dpm_vblank_too_short(adev))
 939                 disable_mclk_switching = true;
 940         else
 941                 disable_mclk_switching = false;
 942
 943         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 944                 pi->battery_state = true;
 945         else
 946                 pi->battery_state = false;
 947
 948         if (adev->pm.dpm.ac_power)
 949                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 950         else
 951                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 952
 953         if (adev->pm.dpm.ac_power == false) {
 954                 for (i = 0; i < ps->performance_level_count; i++) {
 955                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 956                                 ps->performance_levels[i].mclk = max_limits->mclk;
 957                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 958                                 ps->performance_levels[i].sclk = max_limits->sclk;
 959                 }
 960         }
 961
 962         /* XXX validate the min clocks required for display */
 963
 964         if (disable_mclk_switching) {
 965                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 966                 sclk = ps->performance_levels[0].sclk;
 967         } else {
 968                 mclk = ps->performance_levels[0].mclk;
 969                 sclk = ps->performance_levels[0].sclk;
 970         }
 971
 972         if (adev->pm.pm_display_cfg.min_core_set_clock > sclk)
 973                 sclk = adev->pm.pm_display_cfg.min_core_set_clock;
 974
 975         if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk)
 976                 mclk = adev->pm.pm_display_cfg.min_mem_set_clock;
 977
 978         if (rps->vce_active) {
 979                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
 980                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
 981                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
 982                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
 983         }
 984
 985         ps->performance_levels[0].sclk = sclk;
 986         ps->performance_levels[0].mclk = mclk;
 987
 988         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 989                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 990
 991         if (disable_mclk_switching) {
 992                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 993                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 994         } else {
 995                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 996                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 997         }
 998 }
 999
1000 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
1001                                             int min_temp, int max_temp)
1002 {
1003         int low_temp = 0 * 1000;
1004         int high_temp = 255 * 1000;
1005         u32 tmp;
1006
1007         if (low_temp < min_temp)
1008                 low_temp = min_temp;
1009         if (high_temp > max_temp)
1010                 high_temp = max_temp;
1011         if (high_temp < low_temp) {
1012                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1013                 return -EINVAL;
1014         }
1015
1016         tmp = RREG32_SMC(ixCG_THERMAL_INT);
1017         tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
1018         tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1019                 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1020         WREG32_SMC(ixCG_THERMAL_INT, tmp);
1021
1022 #if 0
1023         /* XXX: need to figure out how to handle this properly */
1024         tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1025         tmp &= DIG_THERM_DPM_MASK;
1026         tmp |= DIG_THERM_DPM(high_temp / 1000);
1027         WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1028 #endif
1029
1030         adev->pm.dpm.thermal.min_temp = low_temp;
1031         adev->pm.dpm.thermal.max_temp = high_temp;
1032         return 0;
1033 }
1034
1035 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1036                                    bool enable)
1037 {
1038         u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1039         PPSMC_Result result;
1040
1041         if (enable) {
1042                 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1043                                  CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1044                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1045                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1046                 if (result != PPSMC_Result_OK) {
1047                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1048                         return -EINVAL;
1049                 }
1050         } else {
1051                 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1052                         CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1053                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1054                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1055                 if (result != PPSMC_Result_OK) {
1056                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1057                         return -EINVAL;
1058                 }
1059         }
1060
1061         return 0;
1062 }
1063
1064 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1065 {
1066         struct ci_power_info *pi = ci_get_pi(adev);
1067         u32 tmp;
1068
1069         if (pi->fan_ctrl_is_in_default_mode) {
1070                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1071                         >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1072                 pi->fan_ctrl_default_mode = tmp;
1073                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1074                         >> CG_FDO_CTRL2__TMIN__SHIFT;
1075                 pi->t_min = tmp;
1076                 pi->fan_ctrl_is_in_default_mode = false;
1077         }
1078
1079         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1080         tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1081         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1082
1083         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1084         tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1085         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1086 }
1087
1088 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1089 {
1090         struct ci_power_info *pi = ci_get_pi(adev);
1091         SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1092         u32 duty100;
1093         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1094         u16 fdo_min, slope1, slope2;
1095         u32 reference_clock, tmp;
1096         int ret;
1097         u64 tmp64;
1098
1099         if (!pi->fan_table_start) {
1100                 adev->pm.dpm.fan.ucode_fan_control = false;
1101                 return 0;
1102         }
1103
1104         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1105                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1106
1107         if (duty100 == 0) {
1108                 adev->pm.dpm.fan.ucode_fan_control = false;
1109                 return 0;
1110         }
1111
1112         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1113         do_div(tmp64, 10000);
1114         fdo_min = (u16)tmp64;
1115
1116         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1117         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1118
1119         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1120         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1121
1122         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1123         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1124
1125         fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1126         fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1127         fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1128
1129         fan_table.Slope1 = cpu_to_be16(slope1);
1130         fan_table.Slope2 = cpu_to_be16(slope2);
1131
1132         fan_table.FdoMin = cpu_to_be16(fdo_min);
1133
1134         fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1135
1136         fan_table.HystUp = cpu_to_be16(1);
1137
1138         fan_table.HystSlope = cpu_to_be16(1);
1139
1140         fan_table.TempRespLim = cpu_to_be16(5);
1141
1142         reference_clock = amdgpu_asic_get_xclk(adev);
1143
1144         fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1145                                                reference_clock) / 1600);
1146
1147         fan_table.FdoMax = cpu_to_be16((u16)duty100);
1148
1149         tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1150                 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1151         fan_table.TempSrc = (uint8_t)tmp;
1152
1153         ret = amdgpu_ci_copy_bytes_to_smc(adev,
1154                                           pi->fan_table_start,
1155                                           (u8 *)(&fan_table),
1156                                           sizeof(fan_table),
1157                                           pi->sram_end);
1158
1159         if (ret) {
1160                 DRM_ERROR("Failed to load fan table to the SMC.");
1161                 adev->pm.dpm.fan.ucode_fan_control = false;
1162         }
1163
1164         return 0;
1165 }
1166
1167 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1168 {
1169         struct ci_power_info *pi = ci_get_pi(adev);
1170         PPSMC_Result ret;
1171
1172         if (pi->caps_od_fuzzy_fan_control_support) {
1173                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1174                                                                PPSMC_StartFanControl,
1175                                                                FAN_CONTROL_FUZZY);
1176                 if (ret != PPSMC_Result_OK)
1177                         return -EINVAL;
1178                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1179                                                                PPSMC_MSG_SetFanPwmMax,
1180                                                                adev->pm.dpm.fan.default_max_fan_pwm);
1181                 if (ret != PPSMC_Result_OK)
1182                         return -EINVAL;
1183         } else {
1184                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1185                                                                PPSMC_StartFanControl,
1186                                                                FAN_CONTROL_TABLE);
1187                 if (ret != PPSMC_Result_OK)
1188                         return -EINVAL;
1189         }
1190
1191         pi->fan_is_controlled_by_smc = true;
1192         return 0;
1193 }
1194
1195
1196 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1197 {
1198         PPSMC_Result ret;
1199         struct ci_power_info *pi = ci_get_pi(adev);
1200
1201         ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1202         if (ret == PPSMC_Result_OK) {
1203                 pi->fan_is_controlled_by_smc = false;
1204                 return 0;
1205         } else {
1206                 return -EINVAL;
1207         }
1208 }
1209
1210 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1211                                         u32 *speed)
1212 {
1213         u32 duty, duty100;
1214         u64 tmp64;
1215
1216         if (adev->pm.no_fan)
1217                 return -ENOENT;
1218
1219         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1220                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1221         duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1222                 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1223
1224         if (duty100 == 0)
1225                 return -EINVAL;
1226
1227         tmp64 = (u64)duty * 100;
1228         do_div(tmp64, duty100);
1229         *speed = (u32)tmp64;
1230
1231         if (*speed > 100)
1232                 *speed = 100;
1233
1234         return 0;
1235 }
1236
1237 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1238                                         u32 speed)
1239 {
1240         u32 tmp;
1241         u32 duty, duty100;
1242         u64 tmp64;
1243         struct ci_power_info *pi = ci_get_pi(adev);
1244
1245         if (adev->pm.no_fan)
1246                 return -ENOENT;
1247
1248         if (pi->fan_is_controlled_by_smc)
1249                 return -EINVAL;
1250
1251         if (speed > 100)
1252                 return -EINVAL;
1253
1254         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1255                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1256
1257         if (duty100 == 0)
1258                 return -EINVAL;
1259
1260         tmp64 = (u64)speed * duty100;
1261         do_div(tmp64, 100);
1262         duty = (u32)tmp64;
1263
1264         tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1265         tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1266         WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1267
1268         return 0;
1269 }
1270
1271 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1272 {
1273         switch (mode) {
1274         case AMD_FAN_CTRL_NONE:
1275                 if (adev->pm.dpm.fan.ucode_fan_control)
1276                         ci_fan_ctrl_stop_smc_fan_control(adev);
1277                 ci_dpm_set_fan_speed_percent(adev, 100);
1278                 break;
1279         case AMD_FAN_CTRL_MANUAL:
1280                 if (adev->pm.dpm.fan.ucode_fan_control)
1281                         ci_fan_ctrl_stop_smc_fan_control(adev);
1282                 break;
1283         case AMD_FAN_CTRL_AUTO:
1284                 if (adev->pm.dpm.fan.ucode_fan_control)
1285                         ci_thermal_start_smc_fan_control(adev);
1286                 break;
1287         default:
1288                 break;
1289         }
1290 }
1291
1292 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1293 {
1294         struct ci_power_info *pi = ci_get_pi(adev);
1295
1296         if (pi->fan_is_controlled_by_smc)
1297                 return AMD_FAN_CTRL_AUTO;
1298         else
1299                 return AMD_FAN_CTRL_MANUAL;
1300 }
1301
1302 #if 0
1303 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1304                                          u32 *speed)
1305 {
1306         u32 tach_period;
1307         u32 xclk = amdgpu_asic_get_xclk(adev);
1308
1309         if (adev->pm.no_fan)
1310                 return -ENOENT;
1311
1312         if (adev->pm.fan_pulses_per_revolution == 0)
1313                 return -ENOENT;
1314
1315         tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1316                 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1317         if (tach_period == 0)
1318                 return -ENOENT;
1319
1320         *speed = 60 * xclk * 10000 / tach_period;
1321
1322         return 0;
1323 }
1324
1325 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1326                                          u32 speed)
1327 {
1328         u32 tach_period, tmp;
1329         u32 xclk = amdgpu_asic_get_xclk(adev);
1330
1331         if (adev->pm.no_fan)
1332                 return -ENOENT;
1333
1334         if (adev->pm.fan_pulses_per_revolution == 0)
1335                 return -ENOENT;
1336
1337         if ((speed < adev->pm.fan_min_rpm) ||
1338             (speed > adev->pm.fan_max_rpm))
1339                 return -EINVAL;
1340
1341         if (adev->pm.dpm.fan.ucode_fan_control)
1342                 ci_fan_ctrl_stop_smc_fan_control(adev);
1343
1344         tach_period = 60 * xclk * 10000 / (8 * speed);
1345         tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1346         tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1347         WREG32_SMC(CG_TACH_CTRL, tmp);
1348
1349         ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1350
1351         return 0;
1352 }
1353 #endif
1354
1355 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1356 {
1357         struct ci_power_info *pi = ci_get_pi(adev);
1358         u32 tmp;
1359
1360         if (!pi->fan_ctrl_is_in_default_mode) {
1361                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1362                 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1363                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1364
1365                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1366                 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1367                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1368                 pi->fan_ctrl_is_in_default_mode = true;
1369         }
1370 }
1371
1372 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1373 {
1374         if (adev->pm.dpm.fan.ucode_fan_control) {
1375                 ci_fan_ctrl_start_smc_fan_control(adev);
1376                 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1377         }
1378 }
1379
1380 static void ci_thermal_initialize(struct amdgpu_device *adev)
1381 {
1382         u32 tmp;
1383
1384         if (adev->pm.fan_pulses_per_revolution) {
1385                 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1386                 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1387                         << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1388                 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1389         }
1390
1391         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1392         tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1393         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1394 }
1395
1396 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1397 {
1398         int ret;
1399
1400         ci_thermal_initialize(adev);
1401         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1402         if (ret)
1403                 return ret;
1404         ret = ci_thermal_enable_alert(adev, true);
1405         if (ret)
1406                 return ret;
1407         if (adev->pm.dpm.fan.ucode_fan_control) {
1408                 ret = ci_thermal_setup_fan_table(adev);
1409                 if (ret)
1410                         return ret;
1411                 ci_thermal_start_smc_fan_control(adev);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1418 {
1419         if (!adev->pm.no_fan)
1420                 ci_fan_ctrl_set_default_mode(adev);
1421 }
1422
1423 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1424                                      u16 reg_offset, u32 *value)
1425 {
1426         struct ci_power_info *pi = ci_get_pi(adev);
1427
1428         return amdgpu_ci_read_smc_sram_dword(adev,
1429                                       pi->soft_regs_start + reg_offset,
1430                                       value, pi->sram_end);
1431 }
1432
1433 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1434                                       u16 reg_offset, u32 value)
1435 {
1436         struct ci_power_info *pi = ci_get_pi(adev);
1437
1438         return amdgpu_ci_write_smc_sram_dword(adev,
1439                                        pi->soft_regs_start + reg_offset,
1440                                        value, pi->sram_end);
1441 }
1442
1443 static void ci_init_fps_limits(struct amdgpu_device *adev)
1444 {
1445         struct ci_power_info *pi = ci_get_pi(adev);
1446         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1447
1448         if (pi->caps_fps) {
1449                 u16 tmp;
1450
1451                 tmp = 45;
1452                 table->FpsHighT = cpu_to_be16(tmp);
1453
1454                 tmp = 30;
1455                 table->FpsLowT = cpu_to_be16(tmp);
1456         }
1457 }
1458
1459 static int ci_update_sclk_t(struct amdgpu_device *adev)
1460 {
1461         struct ci_power_info *pi = ci_get_pi(adev);
1462         int ret = 0;
1463         u32 low_sclk_interrupt_t = 0;
1464
1465         if (pi->caps_sclk_throttle_low_notification) {
1466                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1467
1468                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1469                                            pi->dpm_table_start +
1470                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1471                                            (u8 *)&low_sclk_interrupt_t,
1472                                            sizeof(u32), pi->sram_end);
1473
1474         }
1475
1476         return ret;
1477 }
1478
1479 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1480 {
1481         struct ci_power_info *pi = ci_get_pi(adev);
1482         u16 leakage_id, virtual_voltage_id;
1483         u16 vddc, vddci;
1484         int i;
1485
1486         pi->vddc_leakage.count = 0;
1487         pi->vddci_leakage.count = 0;
1488
1489         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1490                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1491                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1492                         if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1493                                 continue;
1494                         if (vddc != 0 && vddc != virtual_voltage_id) {
1495                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1496                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1497                                 pi->vddc_leakage.count++;
1498                         }
1499                 }
1500         } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1501                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1502                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1503                         if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1504                                                                                      virtual_voltage_id,
1505                                                                                      leakage_id) == 0) {
1506                                 if (vddc != 0 && vddc != virtual_voltage_id) {
1507                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1508                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1509                                         pi->vddc_leakage.count++;
1510                                 }
1511                                 if (vddci != 0 && vddci != virtual_voltage_id) {
1512                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1513                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1514                                         pi->vddci_leakage.count++;
1515                                 }
1516                         }
1517                 }
1518         }
1519 }
1520
1521 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1522 {
1523         struct ci_power_info *pi = ci_get_pi(adev);
1524         bool want_thermal_protection;
1525         enum amdgpu_dpm_event_src dpm_event_src;
1526         u32 tmp;
1527
1528         switch (sources) {
1529         case 0:
1530         default:
1531                 want_thermal_protection = false;
1532                 break;
1533         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1534                 want_thermal_protection = true;
1535                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1536                 break;
1537         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1538                 want_thermal_protection = true;
1539                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1540                 break;
1541         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1542               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1543                 want_thermal_protection = true;
1544                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1545                 break;
1546         }
1547
1548         if (want_thermal_protection) {
1549 #if 0
1550                 /* XXX: need to figure out how to handle this properly */
1551                 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1552                 tmp &= DPM_EVENT_SRC_MASK;
1553                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1554                 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1555 #endif
1556
1557                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1558                 if (pi->thermal_protection)
1559                         tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1560                 else
1561                         tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1562                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1563         } else {
1564                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1565                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1566                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1567         }
1568 }
1569
1570 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1571                                            enum amdgpu_dpm_auto_throttle_src source,
1572                                            bool enable)
1573 {
1574         struct ci_power_info *pi = ci_get_pi(adev);
1575
1576         if (enable) {
1577                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1578                         pi->active_auto_throttle_sources |= 1 << source;
1579                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1580                 }
1581         } else {
1582                 if (pi->active_auto_throttle_sources & (1 << source)) {
1583                         pi->active_auto_throttle_sources &= ~(1 << source);
1584                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1585                 }
1586         }
1587 }
1588
1589 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1590 {
1591         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1592                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1593 }
1594
1595 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1596 {
1597         struct ci_power_info *pi = ci_get_pi(adev);
1598         PPSMC_Result smc_result;
1599
1600         if (!pi->need_update_smu7_dpm_table)
1601                 return 0;
1602
1603         if ((!pi->sclk_dpm_key_disabled) &&
1604             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1605                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1606                 if (smc_result != PPSMC_Result_OK)
1607                         return -EINVAL;
1608         }
1609
1610         if ((!pi->mclk_dpm_key_disabled) &&
1611             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1612                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1613                 if (smc_result != PPSMC_Result_OK)
1614                         return -EINVAL;
1615         }
1616
1617         pi->need_update_smu7_dpm_table = 0;
1618         return 0;
1619 }
1620
1621 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1622 {
1623         struct ci_power_info *pi = ci_get_pi(adev);
1624         PPSMC_Result smc_result;
1625
1626         if (enable) {
1627                 if (!pi->sclk_dpm_key_disabled) {
1628                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1629                         if (smc_result != PPSMC_Result_OK)
1630                                 return -EINVAL;
1631                 }
1632
1633                 if (!pi->mclk_dpm_key_disabled) {
1634                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1635                         if (smc_result != PPSMC_Result_OK)
1636                                 return -EINVAL;
1637
1638                         WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1639                                         ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1640
1641                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1642                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1643                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1644
1645                         udelay(10);
1646
1647                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1648                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1649                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1650                 }
1651         } else {
1652                 if (!pi->sclk_dpm_key_disabled) {
1653                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1654                         if (smc_result != PPSMC_Result_OK)
1655                                 return -EINVAL;
1656                 }
1657
1658                 if (!pi->mclk_dpm_key_disabled) {
1659                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1660                         if (smc_result != PPSMC_Result_OK)
1661                                 return -EINVAL;
1662                 }
1663         }
1664
1665         return 0;
1666 }
1667
1668 static int ci_start_dpm(struct amdgpu_device *adev)
1669 {
1670         struct ci_power_info *pi = ci_get_pi(adev);
1671         PPSMC_Result smc_result;
1672         int ret;
1673         u32 tmp;
1674
1675         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1676         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1677         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1678
1679         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1680         tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1681         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1682
1683         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1684
1685         WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1686
1687         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1688         if (smc_result != PPSMC_Result_OK)
1689                 return -EINVAL;
1690
1691         ret = ci_enable_sclk_mclk_dpm(adev, true);
1692         if (ret)
1693                 return ret;
1694
1695         if (!pi->pcie_dpm_key_disabled) {
1696                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1697                 if (smc_result != PPSMC_Result_OK)
1698                         return -EINVAL;
1699         }
1700
1701         return 0;
1702 }
1703
1704 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1705 {
1706         struct ci_power_info *pi = ci_get_pi(adev);
1707         PPSMC_Result smc_result;
1708
1709         if (!pi->need_update_smu7_dpm_table)
1710                 return 0;
1711
1712         if ((!pi->sclk_dpm_key_disabled) &&
1713             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1714                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1715                 if (smc_result != PPSMC_Result_OK)
1716                         return -EINVAL;
1717         }
1718
1719         if ((!pi->mclk_dpm_key_disabled) &&
1720             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1721                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1722                 if (smc_result != PPSMC_Result_OK)
1723                         return -EINVAL;
1724         }
1725
1726         return 0;
1727 }
1728
1729 static int ci_stop_dpm(struct amdgpu_device *adev)
1730 {
1731         struct ci_power_info *pi = ci_get_pi(adev);
1732         PPSMC_Result smc_result;
1733         int ret;
1734         u32 tmp;
1735
1736         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1737         tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1738         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1739
1740         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1741         tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1742         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1743
1744         if (!pi->pcie_dpm_key_disabled) {
1745                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1746                 if (smc_result != PPSMC_Result_OK)
1747                         return -EINVAL;
1748         }
1749
1750         ret = ci_enable_sclk_mclk_dpm(adev, false);
1751         if (ret)
1752                 return ret;
1753
1754         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1755         if (smc_result != PPSMC_Result_OK)
1756                 return -EINVAL;
1757
1758         return 0;
1759 }
1760
1761 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1762 {
1763         u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1764
1765         if (enable)
1766                 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1767         else
1768                 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1769         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1770 }
1771
1772 #if 0
1773 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1774                                         bool ac_power)
1775 {
1776         struct ci_power_info *pi = ci_get_pi(adev);
1777         struct amdgpu_cac_tdp_table *cac_tdp_table =
1778                 adev->pm.dpm.dyn_state.cac_tdp_table;
1779         u32 power_limit;
1780
1781         if (ac_power)
1782                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1783         else
1784                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1785
1786         ci_set_power_limit(adev, power_limit);
1787
1788         if (pi->caps_automatic_dc_transition) {
1789                 if (ac_power)
1790                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1791                 else
1792                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1793         }
1794
1795         return 0;
1796 }
1797 #endif
1798
1799 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1800                                                       PPSMC_Msg msg, u32 parameter)
1801 {
1802         WREG32(mmSMC_MSG_ARG_0, parameter);
1803         return amdgpu_ci_send_msg_to_smc(adev, msg);
1804 }
1805
1806 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1807                                                         PPSMC_Msg msg, u32 *parameter)
1808 {
1809         PPSMC_Result smc_result;
1810
1811         smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1812
1813         if ((smc_result == PPSMC_Result_OK) && parameter)
1814                 *parameter = RREG32(mmSMC_MSG_ARG_0);
1815
1816         return smc_result;
1817 }
1818
1819 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1820 {
1821         struct ci_power_info *pi = ci_get_pi(adev);
1822
1823         if (!pi->sclk_dpm_key_disabled) {
1824                 PPSMC_Result smc_result =
1825                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1826                 if (smc_result != PPSMC_Result_OK)
1827                         return -EINVAL;
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1834 {
1835         struct ci_power_info *pi = ci_get_pi(adev);
1836
1837         if (!pi->mclk_dpm_key_disabled) {
1838                 PPSMC_Result smc_result =
1839                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1840                 if (smc_result != PPSMC_Result_OK)
1841                         return -EINVAL;
1842         }
1843
1844         return 0;
1845 }
1846
1847 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1848 {
1849         struct ci_power_info *pi = ci_get_pi(adev);
1850
1851         if (!pi->pcie_dpm_key_disabled) {
1852                 PPSMC_Result smc_result =
1853                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1854                 if (smc_result != PPSMC_Result_OK)
1855                         return -EINVAL;
1856         }
1857
1858         return 0;
1859 }
1860
1861 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1862 {
1863         struct ci_power_info *pi = ci_get_pi(adev);
1864
1865         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1866                 PPSMC_Result smc_result =
1867                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1868                 if (smc_result != PPSMC_Result_OK)
1869                         return -EINVAL;
1870         }
1871
1872         return 0;
1873 }
1874
1875 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1876                                        u32 target_tdp)
1877 {
1878         PPSMC_Result smc_result =
1879                 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1880         if (smc_result != PPSMC_Result_OK)
1881                 return -EINVAL;
1882         return 0;
1883 }
1884
1885 #if 0
1886 static int ci_set_boot_state(struct amdgpu_device *adev)
1887 {
1888         return ci_enable_sclk_mclk_dpm(adev, false);
1889 }
1890 #endif
1891
1892 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1893 {
1894         u32 sclk_freq;
1895         PPSMC_Result smc_result =
1896                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1897                                                     PPSMC_MSG_API_GetSclkFrequency,
1898                                                     &sclk_freq);
1899         if (smc_result != PPSMC_Result_OK)
1900                 sclk_freq = 0;
1901
1902         return sclk_freq;
1903 }
1904
1905 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1906 {
1907         u32 mclk_freq;
1908         PPSMC_Result smc_result =
1909                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1910                                                     PPSMC_MSG_API_GetMclkFrequency,
1911                                                     &mclk_freq);
1912         if (smc_result != PPSMC_Result_OK)
1913                 mclk_freq = 0;
1914
1915         return mclk_freq;
1916 }
1917
1918 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1919 {
1920         int i;
1921
1922         amdgpu_ci_program_jump_on_start(adev);
1923         amdgpu_ci_start_smc_clock(adev);
1924         amdgpu_ci_start_smc(adev);
1925         for (i = 0; i < adev->usec_timeout; i++) {
1926                 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1927                         break;
1928         }
1929 }
1930
1931 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1932 {
1933         amdgpu_ci_reset_smc(adev);
1934         amdgpu_ci_stop_smc_clock(adev);
1935 }
1936
1937 static int ci_process_firmware_header(struct amdgpu_device *adev)
1938 {
1939         struct ci_power_info *pi = ci_get_pi(adev);
1940         u32 tmp;
1941         int ret;
1942
1943         ret = amdgpu_ci_read_smc_sram_dword(adev,
1944                                      SMU7_FIRMWARE_HEADER_LOCATION +
1945                                      offsetof(SMU7_Firmware_Header, DpmTable),
1946                                      &tmp, pi->sram_end);
1947         if (ret)
1948                 return ret;
1949
1950         pi->dpm_table_start = tmp;
1951
1952         ret = amdgpu_ci_read_smc_sram_dword(adev,
1953                                      SMU7_FIRMWARE_HEADER_LOCATION +
1954                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1955                                      &tmp, pi->sram_end);
1956         if (ret)
1957                 return ret;
1958
1959         pi->soft_regs_start = tmp;
1960
1961         ret = amdgpu_ci_read_smc_sram_dword(adev,
1962                                      SMU7_FIRMWARE_HEADER_LOCATION +
1963                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1964                                      &tmp, pi->sram_end);
1965         if (ret)
1966                 return ret;
1967
1968         pi->mc_reg_table_start = tmp;
1969
1970         ret = amdgpu_ci_read_smc_sram_dword(adev,
1971                                      SMU7_FIRMWARE_HEADER_LOCATION +
1972                                      offsetof(SMU7_Firmware_Header, FanTable),
1973                                      &tmp, pi->sram_end);
1974         if (ret)
1975                 return ret;
1976
1977         pi->fan_table_start = tmp;
1978
1979         ret = amdgpu_ci_read_smc_sram_dword(adev,
1980                                      SMU7_FIRMWARE_HEADER_LOCATION +
1981                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1982                                      &tmp, pi->sram_end);
1983         if (ret)
1984                 return ret;
1985
1986         pi->arb_table_start = tmp;
1987
1988         return 0;
1989 }
1990
1991 static void ci_read_clock_registers(struct amdgpu_device *adev)
1992 {
1993         struct ci_power_info *pi = ci_get_pi(adev);
1994
1995         pi->clock_registers.cg_spll_func_cntl =
1996                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1997         pi->clock_registers.cg_spll_func_cntl_2 =
1998                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1999         pi->clock_registers.cg_spll_func_cntl_3 =
2000                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
2001         pi->clock_registers.cg_spll_func_cntl_4 =
2002                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
2003         pi->clock_registers.cg_spll_spread_spectrum =
2004                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2005         pi->clock_registers.cg_spll_spread_spectrum_2 =
2006                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
2007         pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
2008         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
2009         pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
2010         pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
2011         pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
2012         pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
2013         pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
2014         pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
2015         pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
2016 }
2017
2018 static void ci_init_sclk_t(struct amdgpu_device *adev)
2019 {
2020         struct ci_power_info *pi = ci_get_pi(adev);
2021
2022         pi->low_sclk_interrupt_t = 0;
2023 }
2024
2025 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2026                                          bool enable)
2027 {
2028         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2029
2030         if (enable)
2031                 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2032         else
2033                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2034         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2035 }
2036
2037 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2038 {
2039         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2040
2041         tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2042
2043         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2044 }
2045
2046 #if 0
2047 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2048 {
2049
2050         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2051
2052         udelay(25000);
2053
2054         return 0;
2055 }
2056
2057 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2058 {
2059         int i;
2060
2061         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2062
2063         udelay(7000);
2064
2065         for (i = 0; i < adev->usec_timeout; i++) {
2066                 if (RREG32(mmSMC_RESP_0) == 1)
2067                         break;
2068                 udelay(1000);
2069         }
2070
2071         return 0;
2072 }
2073 #endif
2074
2075 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2076                                         bool has_display)
2077 {
2078         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2079
2080         return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
2081 }
2082
2083 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2084                                       bool enable)
2085 {
2086         struct ci_power_info *pi = ci_get_pi(adev);
2087
2088         if (enable) {
2089                 if (pi->caps_sclk_ds) {
2090                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2091                                 return -EINVAL;
2092                 } else {
2093                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2094                                 return -EINVAL;
2095                 }
2096         } else {
2097                 if (pi->caps_sclk_ds) {
2098                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2099                                 return -EINVAL;
2100                 }
2101         }
2102
2103         return 0;
2104 }
2105
2106 static void ci_program_display_gap(struct amdgpu_device *adev)
2107 {
2108         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2109         u32 pre_vbi_time_in_us;
2110         u32 frame_time_in_us;
2111         u32 ref_clock = adev->clock.spll.reference_freq;
2112         u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2113         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2114
2115         tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2116         if (adev->pm.dpm.new_active_crtc_count > 0)
2117                 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2118         else
2119                 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2120         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2121
2122         if (refresh_rate == 0)
2123                 refresh_rate = 60;
2124         if (vblank_time == 0xffffffff)
2125                 vblank_time = 500;
2126         frame_time_in_us = 1000000 / refresh_rate;
2127         pre_vbi_time_in_us =
2128                 frame_time_in_us - 200 - vblank_time;
2129         tmp = pre_vbi_time_in_us * (ref_clock / 100);
2130
2131         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2132         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2133         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2134
2135
2136         ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2137
2138 }
2139
2140 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2141 {
2142         struct ci_power_info *pi = ci_get_pi(adev);
2143         u32 tmp;
2144
2145         if (enable) {
2146                 if (pi->caps_sclk_ss_support) {
2147                         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2148                         tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2149                         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2150                 }
2151         } else {
2152                 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2153                 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2154                 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2155
2156                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2157                 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2158                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2159         }
2160 }
2161
2162 static void ci_program_sstp(struct amdgpu_device *adev)
2163 {
2164         WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2165         ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2166          (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2167 }
2168
2169 static void ci_enable_display_gap(struct amdgpu_device *adev)
2170 {
2171         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2172
2173         tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2174                         CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2175         tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2176                 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2177
2178         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2179 }
2180
2181 static void ci_program_vc(struct amdgpu_device *adev)
2182 {
2183         u32 tmp;
2184
2185         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2186         tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2187         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2188
2189         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2190         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2191         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2192         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2193         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2194         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2195         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2196         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2197 }
2198
2199 static void ci_clear_vc(struct amdgpu_device *adev)
2200 {
2201         u32 tmp;
2202
2203         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2204         tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2205         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2206
2207         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2208         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2209         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2210         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2211         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2212         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2213         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2214         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2215 }
2216
2217 static int ci_upload_firmware(struct amdgpu_device *adev)
2218 {
2219         int i, ret;
2220
2221         if (amdgpu_ci_is_smc_running(adev)) {
2222                 DRM_INFO("smc is running, no need to load smc firmware\n");
2223                 return 0;
2224         }
2225
2226         for (i = 0; i < adev->usec_timeout; i++) {
2227                 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2228                         break;
2229         }
2230         WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2231
2232         amdgpu_ci_stop_smc_clock(adev);
2233         amdgpu_ci_reset_smc(adev);
2234
2235         ret = amdgpu_ci_load_smc_ucode(adev, SMC_RAM_END);
2236
2237         return ret;
2238
2239 }
2240
2241 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2242                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2243                                      struct atom_voltage_table *voltage_table)
2244 {
2245         u32 i;
2246
2247         if (voltage_dependency_table == NULL)
2248                 return -EINVAL;
2249
2250         voltage_table->mask_low = 0;
2251         voltage_table->phase_delay = 0;
2252
2253         voltage_table->count = voltage_dependency_table->count;
2254         for (i = 0; i < voltage_table->count; i++) {
2255                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2256                 voltage_table->entries[i].smio_low = 0;
2257         }
2258
2259         return 0;
2260 }
2261
2262 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2263 {
2264         struct ci_power_info *pi = ci_get_pi(adev);
2265         int ret;
2266
2267         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2268                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2269                                                         VOLTAGE_OBJ_GPIO_LUT,
2270                                                         &pi->vddc_voltage_table);
2271                 if (ret)
2272                         return ret;
2273         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2274                 ret = ci_get_svi2_voltage_table(adev,
2275                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2276                                                 &pi->vddc_voltage_table);
2277                 if (ret)
2278                         return ret;
2279         }
2280
2281         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2282                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2283                                                          &pi->vddc_voltage_table);
2284
2285         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2286                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2287                                                         VOLTAGE_OBJ_GPIO_LUT,
2288                                                         &pi->vddci_voltage_table);
2289                 if (ret)
2290                         return ret;
2291         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2292                 ret = ci_get_svi2_voltage_table(adev,
2293                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2294                                                 &pi->vddci_voltage_table);
2295                 if (ret)
2296                         return ret;
2297         }
2298
2299         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2300                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2301                                                          &pi->vddci_voltage_table);
2302
2303         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2304                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2305                                                         VOLTAGE_OBJ_GPIO_LUT,
2306                                                         &pi->mvdd_voltage_table);
2307                 if (ret)
2308                         return ret;
2309         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2310                 ret = ci_get_svi2_voltage_table(adev,
2311                                                 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2312                                                 &pi->mvdd_voltage_table);
2313                 if (ret)
2314                         return ret;
2315         }
2316
2317         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2318                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2319                                                          &pi->mvdd_voltage_table);
2320
2321         return 0;
2322 }
2323
2324 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2325                                           struct atom_voltage_table_entry *voltage_table,
2326                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
2327 {
2328         int ret;
2329
2330         ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2331                                             &smc_voltage_table->StdVoltageHiSidd,
2332                                             &smc_voltage_table->StdVoltageLoSidd);
2333
2334         if (ret) {
2335                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2336                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2337         }
2338
2339         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2340         smc_voltage_table->StdVoltageHiSidd =
2341                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2342         smc_voltage_table->StdVoltageLoSidd =
2343                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2344 }
2345
2346 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2347                                       SMU7_Discrete_DpmTable *table)
2348 {
2349         struct ci_power_info *pi = ci_get_pi(adev);
2350         unsigned int count;
2351
2352         table->VddcLevelCount = pi->vddc_voltage_table.count;
2353         for (count = 0; count < table->VddcLevelCount; count++) {
2354                 ci_populate_smc_voltage_table(adev,
2355                                               &pi->vddc_voltage_table.entries[count],
2356                                               &table->VddcLevel[count]);
2357
2358                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2359                         table->VddcLevel[count].Smio |=
2360                                 pi->vddc_voltage_table.entries[count].smio_low;
2361                 else
2362                         table->VddcLevel[count].Smio = 0;
2363         }
2364         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2365
2366         return 0;
2367 }
2368
2369 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2370                                        SMU7_Discrete_DpmTable *table)
2371 {
2372         unsigned int count;
2373         struct ci_power_info *pi = ci_get_pi(adev);
2374
2375         table->VddciLevelCount = pi->vddci_voltage_table.count;
2376         for (count = 0; count < table->VddciLevelCount; count++) {
2377                 ci_populate_smc_voltage_table(adev,
2378                                               &pi->vddci_voltage_table.entries[count],
2379                                               &table->VddciLevel[count]);
2380
2381                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2382                         table->VddciLevel[count].Smio |=
2383                                 pi->vddci_voltage_table.entries[count].smio_low;
2384                 else
2385                         table->VddciLevel[count].Smio = 0;
2386         }
2387         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2388
2389         return 0;
2390 }
2391
2392 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2393                                       SMU7_Discrete_DpmTable *table)
2394 {
2395         struct ci_power_info *pi = ci_get_pi(adev);
2396         unsigned int count;
2397
2398         table->MvddLevelCount = pi->mvdd_voltage_table.count;
2399         for (count = 0; count < table->MvddLevelCount; count++) {
2400                 ci_populate_smc_voltage_table(adev,
2401                                               &pi->mvdd_voltage_table.entries[count],
2402                                               &table->MvddLevel[count]);
2403
2404                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2405                         table->MvddLevel[count].Smio |=
2406                                 pi->mvdd_voltage_table.entries[count].smio_low;
2407                 else
2408                         table->MvddLevel[count].Smio = 0;
2409         }
2410         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2411
2412         return 0;
2413 }
2414
2415 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2416                                           SMU7_Discrete_DpmTable *table)
2417 {
2418         int ret;
2419
2420         ret = ci_populate_smc_vddc_table(adev, table);
2421         if (ret)
2422                 return ret;
2423
2424         ret = ci_populate_smc_vddci_table(adev, table);
2425         if (ret)
2426                 return ret;
2427
2428         ret = ci_populate_smc_mvdd_table(adev, table);
2429         if (ret)
2430                 return ret;
2431
2432         return 0;
2433 }
2434
2435 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2436                                   SMU7_Discrete_VoltageLevel *voltage)
2437 {
2438         struct ci_power_info *pi = ci_get_pi(adev);
2439         u32 i = 0;
2440
2441         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2442                 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2443                         if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2444                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2445                                 break;
2446                         }
2447                 }
2448
2449                 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2450                         return -EINVAL;
2451         }
2452
2453         return -EINVAL;
2454 }
2455
2456 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2457                                          struct atom_voltage_table_entry *voltage_table,
2458                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2459 {
2460         u16 v_index, idx;
2461         bool voltage_found = false;
2462         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2463         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2464
2465         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2466                 return -EINVAL;
2467
2468         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2469                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2470                         if (voltage_table->value ==
2471                             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2472                                 voltage_found = true;
2473                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2474                                         idx = v_index;
2475                                 else
2476                                         idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2477                                 *std_voltage_lo_sidd =
2478                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2479                                 *std_voltage_hi_sidd =
2480                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2481                                 break;
2482                         }
2483                 }
2484
2485                 if (!voltage_found) {
2486                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2487                                 if (voltage_table->value <=
2488                                     adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2489                                         voltage_found = true;
2490                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2491                                                 idx = v_index;
2492                                         else
2493                                                 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2494                                         *std_voltage_lo_sidd =
2495                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2496                                         *std_voltage_hi_sidd =
2497                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2498                                         break;
2499                                 }
2500                         }
2501                 }
2502         }
2503
2504         return 0;
2505 }
2506
2507 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2508                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2509                                                   u32 sclk,
2510                                                   u32 *phase_shedding)
2511 {
2512         unsigned int i;
2513
2514         *phase_shedding = 1;
2515
2516         for (i = 0; i < limits->count; i++) {
2517                 if (sclk < limits->entries[i].sclk) {
2518                         *phase_shedding = i;
2519                         break;
2520                 }
2521         }
2522 }
2523
2524 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2525                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2526                                                   u32 mclk,
2527                                                   u32 *phase_shedding)
2528 {
2529         unsigned int i;
2530
2531         *phase_shedding = 1;
2532
2533         for (i = 0; i < limits->count; i++) {
2534                 if (mclk < limits->entries[i].mclk) {
2535                         *phase_shedding = i;
2536                         break;
2537                 }
2538         }
2539 }
2540
2541 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2542 {
2543         struct ci_power_info *pi = ci_get_pi(adev);
2544         u32 tmp;
2545         int ret;
2546
2547         ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2548                                      &tmp, pi->sram_end);
2549         if (ret)
2550                 return ret;
2551
2552         tmp &= 0x00FFFFFF;
2553         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2554
2555         return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2556                                        tmp, pi->sram_end);
2557 }
2558
2559 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2560                                          struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2561                                          u32 clock, u32 *voltage)
2562 {
2563         u32 i = 0;
2564
2565         if (allowed_clock_voltage_table->count == 0)
2566                 return -EINVAL;
2567
2568         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2569                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2570                         *voltage = allowed_clock_voltage_table->entries[i].v;
2571                         return 0;
2572                 }
2573         }
2574
2575         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2576
2577         return 0;
2578 }
2579
2580 static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2581 {
2582         u32 i;
2583         u32 tmp;
2584         u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2585
2586         if (sclk < min)
2587                 return 0;
2588
2589         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2590                 tmp = sclk >> i;
2591                 if (tmp >= min || i == 0)
2592                         break;
2593         }
2594
2595         return (u8)i;
2596 }
2597
2598 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2599 {
2600         return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2601 }
2602
2603 static int ci_reset_to_default(struct amdgpu_device *adev)
2604 {
2605         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2606                 0 : -EINVAL;
2607 }
2608
2609 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2610 {
2611         u32 tmp;
2612
2613         tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2614
2615         if (tmp == MC_CG_ARB_FREQ_F0)
2616                 return 0;
2617
2618         return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2619 }
2620
2621 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2622                                         const u32 engine_clock,
2623                                         const u32 memory_clock,
2624                                         u32 *dram_timimg2)
2625 {
2626         bool patch;
2627         u32 tmp, tmp2;
2628
2629         tmp = RREG32(mmMC_SEQ_MISC0);
2630         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2631
2632         if (patch &&
2633             ((adev->pdev->device == 0x67B0) ||
2634              (adev->pdev->device == 0x67B1))) {
2635                 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2636                         tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2637                         *dram_timimg2 &= ~0x00ff0000;
2638                         *dram_timimg2 |= tmp2 << 16;
2639                 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2640                         tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2641                         *dram_timimg2 &= ~0x00ff0000;
2642                         *dram_timimg2 |= tmp2 << 16;
2643                 }
2644         }
2645 }
2646
2647 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2648                                                 u32 sclk,
2649                                                 u32 mclk,
2650                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2651 {
2652         u32 dram_timing;
2653         u32 dram_timing2;
2654         u32 burst_time;
2655
2656         amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2657
2658         dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
2659         dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2660         burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2661
2662         ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2663
2664         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2665         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2666         arb_regs->McArbBurstTime = (u8)burst_time;
2667
2668         return 0;
2669 }
2670
2671 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2672 {
2673         struct ci_power_info *pi = ci_get_pi(adev);
2674         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2675         u32 i, j;
2676         int ret =  0;
2677
2678         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2679
2680         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2681                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2682                         ret = ci_populate_memory_timing_parameters(adev,
2683                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2684                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2685                                                                    &arb_regs.entries[i][j]);
2686                         if (ret)
2687                                 break;
2688                 }
2689         }
2690
2691         if (ret == 0)
2692                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2693                                            pi->arb_table_start,
2694                                            (u8 *)&arb_regs,
2695                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2696                                            pi->sram_end);
2697
2698         return ret;
2699 }
2700
2701 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2702 {
2703         struct ci_power_info *pi = ci_get_pi(adev);
2704
2705         if (pi->need_update_smu7_dpm_table == 0)
2706                 return 0;
2707
2708         return ci_do_program_memory_timing_parameters(adev);
2709 }
2710
2711 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2712                                           struct amdgpu_ps *amdgpu_boot_state)
2713 {
2714         struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2715         struct ci_power_info *pi = ci_get_pi(adev);
2716         u32 level = 0;
2717
2718         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2719                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2720                     boot_state->performance_levels[0].sclk) {
2721                         pi->smc_state_table.GraphicsBootLevel = level;
2722                         break;
2723                 }
2724         }
2725
2726         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2727                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2728                     boot_state->performance_levels[0].mclk) {
2729                         pi->smc_state_table.MemoryBootLevel = level;
2730                         break;
2731                 }
2732         }
2733 }
2734
2735 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2736 {
2737         u32 i;
2738         u32 mask_value = 0;
2739
2740         for (i = dpm_table->count; i > 0; i--) {
2741                 mask_value = mask_value << 1;
2742                 if (dpm_table->dpm_levels[i-1].enabled)
2743                         mask_value |= 0x1;
2744                 else
2745                         mask_value &= 0xFFFFFFFE;
2746         }
2747
2748         return mask_value;
2749 }
2750
2751 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2752                                        SMU7_Discrete_DpmTable *table)
2753 {
2754         struct ci_power_info *pi = ci_get_pi(adev);
2755         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2756         u32 i;
2757
2758         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2759                 table->LinkLevel[i].PcieGenSpeed =
2760                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2761                 table->LinkLevel[i].PcieLaneCount =
2762                         amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2763                 table->LinkLevel[i].EnabledForActivity = 1;
2764                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2765                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2766         }
2767
2768         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2769         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2770                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2771 }
2772
2773 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2774                                      SMU7_Discrete_DpmTable *table)
2775 {
2776         u32 count;
2777         struct atom_clock_dividers dividers;
2778         int ret = -EINVAL;
2779
2780         table->UvdLevelCount =
2781                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2782
2783         for (count = 0; count < table->UvdLevelCount; count++) {
2784                 table->UvdLevel[count].VclkFrequency =
2785                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2786                 table->UvdLevel[count].DclkFrequency =
2787                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2788                 table->UvdLevel[count].MinVddc =
2789                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2790                 table->UvdLevel[count].MinVddcPhases = 1;
2791
2792                 ret = amdgpu_atombios_get_clock_dividers(adev,
2793                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2794                                                          table->UvdLevel[count].VclkFrequency, false, &dividers);
2795                 if (ret)
2796                         return ret;
2797
2798                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2799
2800                 ret = amdgpu_atombios_get_clock_dividers(adev,
2801                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2802                                                          table->UvdLevel[count].DclkFrequency, false, &dividers);
2803                 if (ret)
2804                         return ret;
2805
2806                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2807
2808                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2809                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2810                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2811         }
2812
2813         return ret;
2814 }
2815
2816 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2817                                      SMU7_Discrete_DpmTable *table)
2818 {
2819         u32 count;
2820         struct atom_clock_dividers dividers;
2821         int ret = -EINVAL;
2822
2823         table->VceLevelCount =
2824                 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2825
2826         for (count = 0; count < table->VceLevelCount; count++) {
2827                 table->VceLevel[count].Frequency =
2828                         adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2829                 table->VceLevel[count].MinVoltage =
2830                         (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2831                 table->VceLevel[count].MinPhases = 1;
2832
2833                 ret = amdgpu_atombios_get_clock_dividers(adev,
2834                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2835                                                          table->VceLevel[count].Frequency, false, &dividers);
2836                 if (ret)
2837                         return ret;
2838
2839                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2840
2841                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2842                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2843         }
2844
2845         return ret;
2846
2847 }
2848
2849 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2850                                      SMU7_Discrete_DpmTable *table)
2851 {
2852         u32 count;
2853         struct atom_clock_dividers dividers;
2854         int ret = -EINVAL;
2855
2856         table->AcpLevelCount = (u8)
2857                 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2858
2859         for (count = 0; count < table->AcpLevelCount; count++) {
2860                 table->AcpLevel[count].Frequency =
2861                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2862                 table->AcpLevel[count].MinVoltage =
2863                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2864                 table->AcpLevel[count].MinPhases = 1;
2865
2866                 ret = amdgpu_atombios_get_clock_dividers(adev,
2867                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2868                                                          table->AcpLevel[count].Frequency, false, &dividers);
2869                 if (ret)
2870                         return ret;
2871
2872                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2873
2874                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2875                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2876         }
2877
2878         return ret;
2879 }
2880
2881 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2882                                       SMU7_Discrete_DpmTable *table)
2883 {
2884         u32 count;
2885         struct atom_clock_dividers dividers;
2886         int ret = -EINVAL;
2887
2888         table->SamuLevelCount =
2889                 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2890
2891         for (count = 0; count < table->SamuLevelCount; count++) {
2892                 table->SamuLevel[count].Frequency =
2893                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2894                 table->SamuLevel[count].MinVoltage =
2895                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2896                 table->SamuLevel[count].MinPhases = 1;
2897
2898                 ret = amdgpu_atombios_get_clock_dividers(adev,
2899                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2900                                                          table->SamuLevel[count].Frequency, false, &dividers);
2901                 if (ret)
2902                         return ret;
2903
2904                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2905
2906                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2907                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2908         }
2909
2910         return ret;
2911 }
2912
2913 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2914                                     u32 memory_clock,
2915                                     SMU7_Discrete_MemoryLevel *mclk,
2916                                     bool strobe_mode,
2917                                     bool dll_state_on)
2918 {
2919         struct ci_power_info *pi = ci_get_pi(adev);
2920         u32  dll_cntl = pi->clock_registers.dll_cntl;
2921         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2922         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2923         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2924         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2925         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2926         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2927         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2928         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2929         struct atom_mpll_param mpll_param;
2930         int ret;
2931
2932         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2933         if (ret)
2934                 return ret;
2935
2936         mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2937         mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2938
2939         mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2940                         MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2941         mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2942                 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2943                 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2944
2945         mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2946         mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2947
2948         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2949                 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2950                                 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2951                 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2952                                 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2953         }
2954
2955         if (pi->caps_mclk_ss_support) {
2956                 struct amdgpu_atom_ss ss;
2957                 u32 freq_nom;
2958                 u32 tmp;
2959                 u32 reference_clock = adev->clock.mpll.reference_freq;
2960
2961                 if (mpll_param.qdr == 1)
2962                         freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2963                 else
2964                         freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2965
2966                 tmp = (freq_nom / reference_clock);
2967                 tmp = tmp * tmp;
2968                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2969                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2970                         u32 clks = reference_clock * 5 / ss.rate;
2971                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2972
2973                         mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2974                         mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2975
2976                         mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2977                         mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2978                 }
2979         }
2980
2981         mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2982         mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2983
2984         if (dll_state_on)
2985                 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2986                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2987         else
2988                 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2989                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2990
2991         mclk->MclkFrequency = memory_clock;
2992         mclk->MpllFuncCntl = mpll_func_cntl;
2993         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2994         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2995         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2996         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2997         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2998         mclk->DllCntl = dll_cntl;
2999         mclk->MpllSs1 = mpll_ss1;
3000         mclk->MpllSs2 = mpll_ss2;
3001
3002         return 0;
3003 }
3004
3005 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
3006                                            u32 memory_clock,
3007                                            SMU7_Discrete_MemoryLevel *memory_level)
3008 {
3009         struct ci_power_info *pi = ci_get_pi(adev);
3010         int ret;
3011         bool dll_state_on;
3012
3013         if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
3014                 ret = ci_get_dependency_volt_by_clk(adev,
3015                                                     &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3016                                                     memory_clock, &memory_level->MinVddc);
3017                 if (ret)
3018                         return ret;
3019         }
3020
3021         if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
3022                 ret = ci_get_dependency_volt_by_clk(adev,
3023                                                     &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3024                                                     memory_clock, &memory_level->MinVddci);
3025                 if (ret)
3026                         return ret;
3027         }
3028
3029         if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3030                 ret = ci_get_dependency_volt_by_clk(adev,
3031                                                     &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3032                                                     memory_clock, &memory_level->MinMvdd);
3033                 if (ret)
3034                         return ret;
3035         }
3036
3037         memory_level->MinVddcPhases = 1;
3038
3039         if (pi->vddc_phase_shed_control)
3040                 ci_populate_phase_value_based_on_mclk(adev,
3041                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3042                                                       memory_clock,
3043                                                       &memory_level->MinVddcPhases);
3044
3045         memory_level->EnabledForActivity = 1;
3046         memory_level->EnabledForThrottle = 1;
3047         memory_level->UpH = 0;
3048         memory_level->DownH = 100;
3049         memory_level->VoltageDownH = 0;
3050         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3051
3052         memory_level->StutterEnable = false;
3053         memory_level->StrobeEnable = false;
3054         memory_level->EdcReadEnable = false;
3055         memory_level->EdcWriteEnable = false;
3056         memory_level->RttEnable = false;
3057
3058         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3059
3060         if (pi->mclk_stutter_mode_threshold &&
3061             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3062             (!pi->uvd_enabled) &&
3063             (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3064             (adev->pm.dpm.new_active_crtc_count <= 2))
3065                 memory_level->StutterEnable = true;
3066
3067         if (pi->mclk_strobe_mode_threshold &&
3068             (memory_clock <= pi->mclk_strobe_mode_threshold))
3069                 memory_level->StrobeEnable = 1;
3070
3071         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3072                 memory_level->StrobeRatio =
3073                         ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3074                 if (pi->mclk_edc_enable_threshold &&
3075                     (memory_clock > pi->mclk_edc_enable_threshold))
3076                         memory_level->EdcReadEnable = true;
3077
3078                 if (pi->mclk_edc_wr_enable_threshold &&
3079                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
3080                         memory_level->EdcWriteEnable = true;
3081
3082                 if (memory_level->StrobeEnable) {
3083                         if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3084                             ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3085                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3086                         else
3087                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3088                 } else {
3089                         dll_state_on = pi->dll_default_on;
3090                 }
3091         } else {
3092                 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3093                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3094         }
3095
3096         ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3097         if (ret)
3098                 return ret;
3099
3100         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3101         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3102         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3103         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3104
3105         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3106         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3107         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3108         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3109         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3110         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3111         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3112         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3113         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3114         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3115         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3116
3117         return 0;
3118 }
3119
3120 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3121                                       SMU7_Discrete_DpmTable *table)
3122 {
3123         struct ci_power_info *pi = ci_get_pi(adev);
3124         struct atom_clock_dividers dividers;
3125         SMU7_Discrete_VoltageLevel voltage_level;
3126         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3127         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3128         u32 dll_cntl = pi->clock_registers.dll_cntl;
3129         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3130         int ret;
3131
3132         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3133
3134         if (pi->acpi_vddc)
3135                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3136         else
3137                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3138
3139         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3140
3141         table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3142
3143         ret = amdgpu_atombios_get_clock_dividers(adev,
3144                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3145                                                  table->ACPILevel.SclkFrequency, false, &dividers);
3146         if (ret)
3147                 return ret;
3148
3149         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3150         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3151         table->ACPILevel.DeepSleepDivId = 0;
3152
3153         spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3154         spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3155
3156         spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3157         spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3158
3159         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3160         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3161         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3162         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3163         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3164         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3165         table->ACPILevel.CcPwrDynRm = 0;
3166         table->ACPILevel.CcPwrDynRm1 = 0;
3167
3168         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3169         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3170         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3171         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3172         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3173         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3174         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3175         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3176         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3177         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3178         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3179
3180         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3181         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3182
3183         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3184                 if (pi->acpi_vddci)
3185                         table->MemoryACPILevel.MinVddci =
3186                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3187                 else
3188                         table->MemoryACPILevel.MinVddci =
3189                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3190         }
3191
3192         if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3193                 table->MemoryACPILevel.MinMvdd = 0;
3194         else
3195                 table->MemoryACPILevel.MinMvdd =
3196                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3197
3198         mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3199                 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3200         mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3201                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3202
3203         dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3204
3205         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3206         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3207         table->MemoryACPILevel.MpllAdFuncCntl =
3208                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3209         table->MemoryACPILevel.MpllDqFuncCntl =
3210                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3211         table->MemoryACPILevel.MpllFuncCntl =
3212                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3213         table->MemoryACPILevel.MpllFuncCntl_1 =
3214                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3215         table->MemoryACPILevel.MpllFuncCntl_2 =
3216                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3217         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3218         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3219
3220         table->MemoryACPILevel.EnabledForThrottle = 0;
3221         table->MemoryACPILevel.EnabledForActivity = 0;
3222         table->MemoryACPILevel.UpH = 0;
3223         table->MemoryACPILevel.DownH = 100;
3224         table->MemoryACPILevel.VoltageDownH = 0;
3225         table->MemoryACPILevel.ActivityLevel =
3226                 cpu_to_be16((u16)pi->mclk_activity_target);
3227
3228         table->MemoryACPILevel.StutterEnable = false;
3229         table->MemoryACPILevel.StrobeEnable = false;
3230         table->MemoryACPILevel.EdcReadEnable = false;
3231         table->MemoryACPILevel.EdcWriteEnable = false;
3232         table->MemoryACPILevel.RttEnable = false;
3233
3234         return 0;
3235 }
3236
3237
3238 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3239 {
3240         struct ci_power_info *pi = ci_get_pi(adev);
3241         struct ci_ulv_parm *ulv = &pi->ulv;
3242
3243         if (ulv->supported) {
3244                 if (enable)
3245                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3246                                 0 : -EINVAL;
3247                 else
3248                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3249                                 0 : -EINVAL;
3250         }
3251
3252         return 0;
3253 }
3254
3255 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3256                                  SMU7_Discrete_Ulv *state)
3257 {
3258         struct ci_power_info *pi = ci_get_pi(adev);
3259         u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3260
3261         state->CcPwrDynRm = 0;
3262         state->CcPwrDynRm1 = 0;
3263
3264         if (ulv_voltage == 0) {
3265                 pi->ulv.supported = false;
3266                 return 0;
3267         }
3268
3269         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3270                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3271                         state->VddcOffset = 0;
3272                 else
3273                         state->VddcOffset =
3274                                 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3275         } else {
3276                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3277                         state->VddcOffsetVid = 0;
3278                 else
3279                         state->VddcOffsetVid = (u8)
3280                                 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3281                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3282         }
3283         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3284
3285         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3286         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3287         state->VddcOffset = cpu_to_be16(state->VddcOffset);
3288
3289         return 0;
3290 }
3291
3292 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3293                                     u32 engine_clock,
3294                                     SMU7_Discrete_GraphicsLevel *sclk)
3295 {
3296         struct ci_power_info *pi = ci_get_pi(adev);
3297         struct atom_clock_dividers dividers;
3298         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3299         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3300         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3301         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3302         u32 reference_clock = adev->clock.spll.reference_freq;
3303         u32 reference_divider;
3304         u32 fbdiv;
3305         int ret;
3306
3307         ret = amdgpu_atombios_get_clock_dividers(adev,
3308                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3309                                                  engine_clock, false, &dividers);
3310         if (ret)
3311                 return ret;
3312
3313         reference_divider = 1 + dividers.ref_div;
3314         fbdiv = dividers.fb_div & 0x3FFFFFF;
3315
3316         spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3317         spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3318         spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3319
3320         if (pi->caps_sclk_ss_support) {
3321                 struct amdgpu_atom_ss ss;
3322                 u32 vco_freq = engine_clock * dividers.post_div;
3323
3324                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3325                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3326                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3327                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3328
3329                         cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3330                         cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3331                         cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3332
3333                         cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3334                         cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3335                 }
3336         }
3337
3338         sclk->SclkFrequency = engine_clock;
3339         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3340         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3341         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3342         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
3343         sclk->SclkDid = (u8)dividers.post_divider;
3344
3345         return 0;
3346 }
3347
3348 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3349                                             u32 engine_clock,
3350                                             u16 sclk_activity_level_t,
3351                                             SMU7_Discrete_GraphicsLevel *graphic_level)
3352 {
3353         struct ci_power_info *pi = ci_get_pi(adev);
3354         int ret;
3355
3356         ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3357         if (ret)
3358                 return ret;
3359
3360         ret = ci_get_dependency_volt_by_clk(adev,
3361                                             &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3362                                             engine_clock, &graphic_level->MinVddc);
3363         if (ret)
3364                 return ret;
3365
3366         graphic_level->SclkFrequency = engine_clock;
3367
3368         graphic_level->Flags =  0;
3369         graphic_level->MinVddcPhases = 1;
3370
3371         if (pi->vddc_phase_shed_control)
3372                 ci_populate_phase_value_based_on_sclk(adev,
3373                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3374                                                       engine_clock,
3375                                                       &graphic_level->MinVddcPhases);
3376
3377         graphic_level->ActivityLevel = sclk_activity_level_t;
3378
3379         graphic_level->CcPwrDynRm = 0;
3380         graphic_level->CcPwrDynRm1 = 0;
3381         graphic_level->EnabledForThrottle = 1;
3382         graphic_level->UpH = 0;
3383         graphic_level->DownH = 0;
3384         graphic_level->VoltageDownH = 0;
3385         graphic_level->PowerThrottle = 0;
3386
3387         if (pi->caps_sclk_ds)
3388                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
3389                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
3390
3391         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3392
3393         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3394         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3395         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3396         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3397         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3398         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3399         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3400         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3401         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3402         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3403         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3404
3405         return 0;
3406 }
3407
3408 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3409 {
3410         struct ci_power_info *pi = ci_get_pi(adev);
3411         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3412         u32 level_array_address = pi->dpm_table_start +
3413                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3414         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3415                 SMU7_MAX_LEVELS_GRAPHICS;
3416         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3417         u32 i, ret;
3418
3419         memset(levels, 0, level_array_size);
3420
3421         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3422                 ret = ci_populate_single_graphic_level(adev,
3423                                                        dpm_table->sclk_table.dpm_levels[i].value,
3424                                                        (u16)pi->activity_target[i],
3425                                                        &pi->smc_state_table.GraphicsLevel[i]);
3426                 if (ret)
3427                         return ret;
3428                 if (i > 1)
3429                         pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3430                 if (i == (dpm_table->sclk_table.count - 1))
3431                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3432                                 PPSMC_DISPLAY_WATERMARK_HIGH;
3433         }
3434         pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3435
3436         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3437         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3438                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3439
3440         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3441                                    (u8 *)levels, level_array_size,
3442                                    pi->sram_end);
3443         if (ret)
3444                 return ret;
3445
3446         return 0;
3447 }
3448
3449 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3450                                  SMU7_Discrete_Ulv *ulv_level)
3451 {
3452         return ci_populate_ulv_level(adev, ulv_level);
3453 }
3454
3455 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3456 {
3457         struct ci_power_info *pi = ci_get_pi(adev);
3458         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3459         u32 level_array_address = pi->dpm_table_start +
3460                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3461         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3462                 SMU7_MAX_LEVELS_MEMORY;
3463         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3464         u32 i, ret;
3465
3466         memset(levels, 0, level_array_size);
3467
3468         for (i = 0; i < dpm_table->mclk_table.count; i++) {
3469                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3470                         return -EINVAL;
3471                 ret = ci_populate_single_memory_level(adev,
3472                                                       dpm_table->mclk_table.dpm_levels[i].value,
3473                                                       &pi->smc_state_table.MemoryLevel[i]);
3474                 if (ret)
3475                         return ret;
3476         }
3477
3478         if ((dpm_table->mclk_table.count >= 2) &&
3479             ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3480                 pi->smc_state_table.MemoryLevel[1].MinVddc =
3481                         pi->smc_state_table.MemoryLevel[0].MinVddc;
3482                 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3483                         pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3484         }
3485
3486         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3487
3488         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3489         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3490                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3491
3492         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3493                 PPSMC_DISPLAY_WATERMARK_HIGH;
3494
3495         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3496                                    (u8 *)levels, level_array_size,
3497                                    pi->sram_end);
3498         if (ret)
3499                 return ret;
3500
3501         return 0;
3502 }
3503
3504 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3505                                       struct ci_single_dpm_table* dpm_table,
3506                                       u32 count)
3507 {
3508         u32 i;
3509
3510         dpm_table->count = count;
3511         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3512                 dpm_table->dpm_levels[i].enabled = false;
3513 }
3514
3515 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3516                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
3517 {
3518         dpm_table->dpm_levels[index].value = pcie_gen;
3519         dpm_table->dpm_levels[index].param1 = pcie_lanes;
3520         dpm_table->dpm_levels[index].enabled = true;
3521 }
3522
3523 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3524 {
3525         struct ci_power_info *pi = ci_get_pi(adev);
3526
3527         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3528                 return -EINVAL;
3529
3530         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3531                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3532                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3533         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3534                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3535                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3536         }
3537
3538         ci_reset_single_dpm_table(adev,
3539                                   &pi->dpm_table.pcie_speed_table,
3540                                   SMU7_MAX_LEVELS_LINK);
3541
3542         if (adev->asic_type == CHIP_BONAIRE)
3543                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3544                                           pi->pcie_gen_powersaving.min,
3545                                           pi->pcie_lane_powersaving.max);
3546         else
3547                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3548                                           pi->pcie_gen_powersaving.min,
3549                                           pi->pcie_lane_powersaving.min);
3550         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3551                                   pi->pcie_gen_performance.min,
3552                                   pi->pcie_lane_performance.min);
3553         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3554                                   pi->pcie_gen_powersaving.min,
3555                                   pi->pcie_lane_powersaving.max);
3556         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3557                                   pi->pcie_gen_performance.min,
3558                                   pi->pcie_lane_performance.max);
3559         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3560                                   pi->pcie_gen_powersaving.max,
3561                                   pi->pcie_lane_powersaving.max);
3562         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3563                                   pi->pcie_gen_performance.max,
3564                                   pi->pcie_lane_performance.max);
3565
3566         pi->dpm_table.pcie_speed_table.count = 6;
3567
3568         return 0;
3569 }
3570
3571 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3572 {
3573         struct ci_power_info *pi = ci_get_pi(adev);
3574         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3575                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3576         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3577                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3578         struct amdgpu_cac_leakage_table *std_voltage_table =
3579                 &adev->pm.dpm.dyn_state.cac_leakage_table;
3580         u32 i;
3581
3582         if (allowed_sclk_vddc_table == NULL)
3583                 return -EINVAL;
3584         if (allowed_sclk_vddc_table->count < 1)
3585                 return -EINVAL;
3586         if (allowed_mclk_table == NULL)
3587                 return -EINVAL;
3588         if (allowed_mclk_table->count < 1)
3589                 return -EINVAL;
3590
3591         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3592
3593         ci_reset_single_dpm_table(adev,
3594                                   &pi->dpm_table.sclk_table,
3595                                   SMU7_MAX_LEVELS_GRAPHICS);
3596         ci_reset_single_dpm_table(adev,
3597                                   &pi->dpm_table.mclk_table,
3598                                   SMU7_MAX_LEVELS_MEMORY);
3599         ci_reset_single_dpm_table(adev,
3600                                   &pi->dpm_table.vddc_table,
3601                                   SMU7_MAX_LEVELS_VDDC);
3602         ci_reset_single_dpm_table(adev,
3603                                   &pi->dpm_table.vddci_table,
3604                                   SMU7_MAX_LEVELS_VDDCI);
3605         ci_reset_single_dpm_table(adev,
3606                                   &pi->dpm_table.mvdd_table,
3607                                   SMU7_MAX_LEVELS_MVDD);
3608
3609         pi->dpm_table.sclk_table.count = 0;
3610         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3611                 if ((i == 0) ||
3612                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3613                      allowed_sclk_vddc_table->entries[i].clk)) {
3614                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3615                                 allowed_sclk_vddc_table->entries[i].clk;
3616                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3617                                 (i == 0) ? true : false;
3618                         pi->dpm_table.sclk_table.count++;
3619                 }
3620         }
3621
3622         pi->dpm_table.mclk_table.count = 0;
3623         for (i = 0; i < allowed_mclk_table->count; i++) {
3624                 if ((i == 0) ||
3625                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3626                      allowed_mclk_table->entries[i].clk)) {
3627                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3628                                 allowed_mclk_table->entries[i].clk;
3629                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3630                                 (i == 0) ? true : false;
3631                         pi->dpm_table.mclk_table.count++;
3632                 }
3633         }
3634
3635         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3636                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3637                         allowed_sclk_vddc_table->entries[i].v;
3638                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3639                         std_voltage_table->entries[i].leakage;
3640                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3641         }
3642         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3643
3644         allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3645         if (allowed_mclk_table) {
3646                 for (i = 0; i < allowed_mclk_table->count; i++) {
3647                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3648                                 allowed_mclk_table->entries[i].v;
3649                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3650                 }
3651                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3652         }
3653
3654         allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3655         if (allowed_mclk_table) {
3656                 for (i = 0; i < allowed_mclk_table->count; i++) {
3657                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3658                                 allowed_mclk_table->entries[i].v;
3659                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3660                 }
3661                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3662         }
3663
3664         ci_setup_default_pcie_tables(adev);
3665
3666         /* save a copy of the default DPM table */
3667         memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),
3668                         sizeof(struct ci_dpm_table));
3669
3670         return 0;
3671 }
3672
3673 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3674                               u32 value, u32 *boot_level)
3675 {
3676         u32 i;
3677         int ret = -EINVAL;
3678
3679         for(i = 0; i < table->count; i++) {
3680                 if (value == table->dpm_levels[i].value) {
3681                         *boot_level = i;
3682                         ret = 0;
3683                 }
3684         }
3685
3686         return ret;
3687 }
3688
3689 static void ci_save_default_power_profile(struct amdgpu_device *adev)
3690 {
3691         struct ci_power_info *pi = ci_get_pi(adev);
3692         struct SMU7_Discrete_GraphicsLevel *levels =
3693                                 pi->smc_state_table.GraphicsLevel;
3694         uint32_t min_level = 0;
3695
3696         pi->default_gfx_power_profile.activity_threshold =
3697                         be16_to_cpu(levels[0].ActivityLevel);
3698         pi->default_gfx_power_profile.up_hyst = levels[0].UpH;
3699         pi->default_gfx_power_profile.down_hyst = levels[0].DownH;
3700         pi->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
3701
3702         pi->default_compute_power_profile = pi->default_gfx_power_profile;
3703         pi->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
3704
3705         /* Optimize compute power profile: Use only highest
3706          * 2 power levels (if more than 2 are available), Hysteresis:
3707          * 0ms up, 5ms down
3708          */
3709         if (pi->smc_state_table.GraphicsDpmLevelCount > 2)
3710                 min_level = pi->smc_state_table.GraphicsDpmLevelCount - 2;
3711         else if (pi->smc_state_table.GraphicsDpmLevelCount == 2)
3712                 min_level = 1;
3713         pi->default_compute_power_profile.min_sclk =
3714                         be32_to_cpu(levels[min_level].SclkFrequency);
3715
3716         pi->default_compute_power_profile.up_hyst = 0;
3717         pi->default_compute_power_profile.down_hyst = 5;
3718
3719         pi->gfx_power_profile = pi->default_gfx_power_profile;
3720         pi->compute_power_profile = pi->default_compute_power_profile;
3721 }
3722
3723 static int ci_init_smc_table(struct amdgpu_device *adev)
3724 {
3725         struct ci_power_info *pi = ci_get_pi(adev);
3726         struct ci_ulv_parm *ulv = &pi->ulv;
3727         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3728         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3729         int ret;
3730
3731         ret = ci_setup_default_dpm_tables(adev);
3732         if (ret)
3733                 return ret;
3734
3735         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3736                 ci_populate_smc_voltage_tables(adev, table);
3737
3738         ci_init_fps_limits(adev);
3739
3740         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3741                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3742
3743         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3744                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3745
3746         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3747                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3748
3749         if (ulv->supported) {
3750                 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3751                 if (ret)
3752                         return ret;
3753                 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3754         }
3755
3756         ret = ci_populate_all_graphic_levels(adev);
3757         if (ret)
3758                 return ret;
3759
3760         ret = ci_populate_all_memory_levels(adev);
3761         if (ret)
3762                 return ret;
3763
3764         ci_populate_smc_link_level(adev, table);
3765
3766         ret = ci_populate_smc_acpi_level(adev, table);
3767         if (ret)
3768                 return ret;
3769
3770         ret = ci_populate_smc_vce_level(adev, table);
3771         if (ret)
3772                 return ret;
3773
3774         ret = ci_populate_smc_acp_level(adev, table);
3775         if (ret)
3776                 return ret;
3777
3778         ret = ci_populate_smc_samu_level(adev, table);
3779         if (ret)
3780                 return ret;
3781
3782         ret = ci_do_program_memory_timing_parameters(adev);
3783         if (ret)
3784                 return ret;
3785
3786         ret = ci_populate_smc_uvd_level(adev, table);
3787         if (ret)
3788                 return ret;
3789
3790         table->UvdBootLevel  = 0;
3791         table->VceBootLevel  = 0;
3792         table->AcpBootLevel  = 0;
3793         table->SamuBootLevel  = 0;
3794         table->GraphicsBootLevel  = 0;
3795         table->MemoryBootLevel  = 0;
3796
3797         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3798                                  pi->vbios_boot_state.sclk_bootup_value,
3799                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3800
3801         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3802                                  pi->vbios_boot_state.mclk_bootup_value,
3803                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3804
3805         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3806         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3807         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3808
3809         ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3810
3811         ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3812         if (ret)
3813                 return ret;
3814
3815         table->UVDInterval = 1;
3816         table->VCEInterval = 1;
3817         table->ACPInterval = 1;
3818         table->SAMUInterval = 1;
3819         table->GraphicsVoltageChangeEnable = 1;
3820         table->GraphicsThermThrottleEnable = 1;
3821         table->GraphicsInterval = 1;
3822         table->VoltageInterval = 1;
3823         table->ThermalInterval = 1;
3824         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3825                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3826         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3827                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3828         table->MemoryVoltageChangeEnable = 1;
3829         table->MemoryInterval = 1;
3830         table->VoltageResponseTime = 0;
3831         table->VddcVddciDelta = 4000;
3832         table->PhaseResponseTime = 0;
3833         table->MemoryThermThrottleEnable = 1;
3834         table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3835         table->PCIeGenInterval = 1;
3836         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3837                 table->SVI2Enable  = 1;
3838         else
3839                 table->SVI2Enable  = 0;
3840
3841         table->ThermGpio = 17;
3842         table->SclkStepSize = 0x4000;
3843
3844         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3845         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3846         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3847         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3848         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3849         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3850         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3851         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3852         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3853         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3854         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3855         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3856         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3857         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3858
3859         ret = amdgpu_ci_copy_bytes_to_smc(adev,
3860                                    pi->dpm_table_start +
3861                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3862                                    (u8 *)&table->SystemFlags,
3863                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3864                                    pi->sram_end);
3865         if (ret)
3866                 return ret;
3867
3868         ci_save_default_power_profile(adev);
3869
3870         return 0;
3871 }
3872
3873 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3874                                       struct ci_single_dpm_table *dpm_table,
3875                                       u32 low_limit, u32 high_limit)
3876 {
3877         u32 i;
3878
3879         for (i = 0; i < dpm_table->count; i++) {
3880                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3881                     (dpm_table->dpm_levels[i].value > high_limit))
3882                         dpm_table->dpm_levels[i].enabled = false;
3883                 else
3884                         dpm_table->dpm_levels[i].enabled = true;
3885         }
3886 }
3887
3888 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3889                                     u32 speed_low, u32 lanes_low,
3890                                     u32 speed_high, u32 lanes_high)
3891 {
3892         struct ci_power_info *pi = ci_get_pi(adev);
3893         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3894         u32 i, j;
3895
3896         for (i = 0; i < pcie_table->count; i++) {
3897                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3898                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3899                     (pcie_table->dpm_levels[i].value > speed_high) ||
3900                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3901                         pcie_table->dpm_levels[i].enabled = false;
3902                 else
3903                         pcie_table->dpm_levels[i].enabled = true;
3904         }
3905
3906         for (i = 0; i < pcie_table->count; i++) {
3907                 if (pcie_table->dpm_levels[i].enabled) {
3908                         for (j = i + 1; j < pcie_table->count; j++) {
3909                                 if (pcie_table->dpm_levels[j].enabled) {
3910                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3911                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3912                                                 pcie_table->dpm_levels[j].enabled = false;
3913                                 }
3914                         }
3915                 }
3916         }
3917 }
3918
3919 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3920                               struct amdgpu_ps *amdgpu_state)
3921 {
3922         struct ci_ps *state = ci_get_ps(amdgpu_state);
3923         struct ci_power_info *pi = ci_get_pi(adev);
3924         u32 high_limit_count;
3925
3926         if (state->performance_level_count < 1)
3927                 return -EINVAL;
3928
3929         if (state->performance_level_count == 1)
3930                 high_limit_count = 0;
3931         else
3932                 high_limit_count = 1;
3933
3934         ci_trim_single_dpm_states(adev,
3935                                   &pi->dpm_table.sclk_table,
3936                                   state->performance_levels[0].sclk,
3937                                   state->performance_levels[high_limit_count].sclk);
3938
3939         ci_trim_single_dpm_states(adev,
3940                                   &pi->dpm_table.mclk_table,
3941                                   state->performance_levels[0].mclk,
3942                                   state->performance_levels[high_limit_count].mclk);
3943
3944         ci_trim_pcie_dpm_states(adev,
3945                                 state->performance_levels[0].pcie_gen,
3946                                 state->performance_levels[0].pcie_lane,
3947                                 state->performance_levels[high_limit_count].pcie_gen,
3948                                 state->performance_levels[high_limit_count].pcie_lane);
3949
3950         return 0;
3951 }
3952
3953 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3954 {
3955         struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3956                 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3957         struct amdgpu_clock_voltage_dependency_table *vddc_table =
3958                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3959         u32 requested_voltage = 0;
3960         u32 i;
3961
3962         if (disp_voltage_table == NULL)
3963                 return -EINVAL;
3964         if (!disp_voltage_table->count)
3965                 return -EINVAL;
3966
3967         for (i = 0; i < disp_voltage_table->count; i++) {
3968                 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3969                         requested_voltage = disp_voltage_table->entries[i].v;
3970         }
3971
3972         for (i = 0; i < vddc_table->count; i++) {
3973                 if (requested_voltage <= vddc_table->entries[i].v) {
3974                         requested_voltage = vddc_table->entries[i].v;
3975                         return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3976                                                                   PPSMC_MSG_VddC_Request,
3977                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3978                                 0 : -EINVAL;
3979                 }
3980         }
3981
3982         return -EINVAL;
3983 }
3984
3985 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3986 {
3987         struct ci_power_info *pi = ci_get_pi(adev);
3988         PPSMC_Result result;
3989
3990         ci_apply_disp_minimum_voltage_request(adev);
3991
3992         if (!pi->sclk_dpm_key_disabled) {
3993                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3994                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3995                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3996                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3997                         if (result != PPSMC_Result_OK)
3998                                 return -EINVAL;
3999                 }
4000         }
4001
4002         if (!pi->mclk_dpm_key_disabled) {
4003                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4004                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4005                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
4006                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4007                         if (result != PPSMC_Result_OK)
4008                                 return -EINVAL;
4009                 }
4010         }
4011
4012 #if 0
4013         if (!pi->pcie_dpm_key_disabled) {
4014                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4015                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4016                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
4017                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4018                         if (result != PPSMC_Result_OK)
4019                                 return -EINVAL;
4020                 }
4021         }
4022 #endif
4023
4024         return 0;
4025 }
4026
4027 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
4028                                                    struct amdgpu_ps *amdgpu_state)
4029 {
4030         struct ci_power_info *pi = ci_get_pi(adev);
4031         struct ci_ps *state = ci_get_ps(amdgpu_state);
4032         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
4033         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4034         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
4035         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4036         u32 i;
4037
4038         pi->need_update_smu7_dpm_table = 0;
4039
4040         for (i = 0; i < sclk_table->count; i++) {
4041                 if (sclk == sclk_table->dpm_levels[i].value)
4042                         break;
4043         }
4044
4045         if (i >= sclk_table->count) {
4046                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4047         } else {
4048                 /* XXX check display min clock requirements */
4049                 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
4050                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4051         }
4052
4053         for (i = 0; i < mclk_table->count; i++) {
4054                 if (mclk == mclk_table->dpm_levels[i].value)
4055                         break;
4056         }
4057
4058         if (i >= mclk_table->count)
4059                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4060
4061         if (adev->pm.dpm.current_active_crtc_count !=
4062             adev->pm.dpm.new_active_crtc_count)
4063                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4064 }
4065
4066 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4067                                                        struct amdgpu_ps *amdgpu_state)
4068 {
4069         struct ci_power_info *pi = ci_get_pi(adev);
4070         struct ci_ps *state = ci_get_ps(amdgpu_state);
4071         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4072         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4073         struct ci_dpm_table *dpm_table = &pi->dpm_table;
4074         int ret;
4075
4076         if (!pi->need_update_smu7_dpm_table)
4077                 return 0;
4078
4079         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4080                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4081
4082         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4083                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4084
4085         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4086                 ret = ci_populate_all_graphic_levels(adev);
4087                 if (ret)
4088                         return ret;
4089         }
4090
4091         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4092                 ret = ci_populate_all_memory_levels(adev);
4093                 if (ret)
4094                         return ret;
4095         }
4096
4097         return 0;
4098 }
4099
4100 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4101 {
4102         struct ci_power_info *pi = ci_get_pi(adev);
4103         const struct amdgpu_clock_and_voltage_limits *max_limits;
4104         int i;
4105
4106         if (adev->pm.dpm.ac_power)
4107                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4108         else
4109                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4110
4111         if (enable) {
4112                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4113
4114                 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4115                         if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4116                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4117
4118                                 if (!pi->caps_uvd_dpm)
4119                                         break;
4120                         }
4121                 }
4122
4123                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4124                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
4125                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4126
4127                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4128                         pi->uvd_enabled = true;
4129                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4130                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4131                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4132                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4133                 }
4134         } else {
4135                 if (pi->uvd_enabled) {
4136                         pi->uvd_enabled = false;
4137                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4138                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4139                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4140                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4141                 }
4142         }
4143
4144         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4145                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4146                 0 : -EINVAL;
4147 }
4148
4149 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4150 {
4151         struct ci_power_info *pi = ci_get_pi(adev);
4152         const struct amdgpu_clock_and_voltage_limits *max_limits;
4153         int i;
4154
4155         if (adev->pm.dpm.ac_power)
4156                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4157         else
4158                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4159
4160         if (enable) {
4161                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4162                 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4163                         if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4164                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4165
4166                                 if (!pi->caps_vce_dpm)
4167                                         break;
4168                         }
4169                 }
4170
4171                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4172                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
4173                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4174         }
4175
4176         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4177                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4178                 0 : -EINVAL;
4179 }
4180
4181 #if 0
4182 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4183 {
4184         struct ci_power_info *pi = ci_get_pi(adev);
4185         const struct amdgpu_clock_and_voltage_limits *max_limits;
4186         int i;
4187
4188         if (adev->pm.dpm.ac_power)
4189                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4190         else
4191                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4192
4193         if (enable) {
4194                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4195                 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4196                         if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4197                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4198
4199                                 if (!pi->caps_samu_dpm)
4200                                         break;
4201                         }
4202                 }
4203
4204                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4205                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
4206                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4207         }
4208         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4209                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4210                 0 : -EINVAL;
4211 }
4212
4213 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4214 {
4215         struct ci_power_info *pi = ci_get_pi(adev);
4216         const struct amdgpu_clock_and_voltage_limits *max_limits;
4217         int i;
4218
4219         if (adev->pm.dpm.ac_power)
4220                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4221         else
4222                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4223
4224         if (enable) {
4225                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4226                 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4227                         if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4228                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4229
4230                                 if (!pi->caps_acp_dpm)
4231                                         break;
4232                         }
4233                 }
4234
4235                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4236                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
4237                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4238         }
4239
4240         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4241                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4242                 0 : -EINVAL;
4243 }
4244 #endif
4245
4246 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4247 {
4248         struct ci_power_info *pi = ci_get_pi(adev);
4249         u32 tmp;
4250         int ret = 0;
4251
4252         if (!gate) {
4253                 /* turn the clocks on when decoding */
4254                 if (pi->caps_uvd_dpm ||
4255                     (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4256                         pi->smc_state_table.UvdBootLevel = 0;
4257                 else
4258                         pi->smc_state_table.UvdBootLevel =
4259                                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4260
4261                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4262                 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4263                 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4264                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4265                 ret = ci_enable_uvd_dpm(adev, true);
4266         } else {
4267                 ret = ci_enable_uvd_dpm(adev, false);
4268                 if (ret)
4269                         return ret;
4270         }
4271
4272         return ret;
4273 }
4274
4275 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4276 {
4277         u8 i;
4278         u32 min_evclk = 30000; /* ??? */
4279         struct amdgpu_vce_clock_voltage_dependency_table *table =
4280                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4281
4282         for (i = 0; i < table->count; i++) {
4283                 if (table->entries[i].evclk >= min_evclk)
4284                         return i;
4285         }
4286
4287         return table->count - 1;
4288 }
4289
4290 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4291                              struct amdgpu_ps *amdgpu_new_state,
4292                              struct amdgpu_ps *amdgpu_current_state)
4293 {
4294         struct ci_power_info *pi = ci_get_pi(adev);
4295         int ret = 0;
4296         u32 tmp;
4297
4298         if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4299                 if (amdgpu_new_state->evclk) {
4300                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4301                         tmp = RREG32_SMC(ixDPM_TABLE_475);
4302                         tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4303                         tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4304                         WREG32_SMC(ixDPM_TABLE_475, tmp);
4305
4306                         ret = ci_enable_vce_dpm(adev, true);
4307                 } else {
4308                         ret = ci_enable_vce_dpm(adev, false);
4309                         if (ret)
4310                                 return ret;
4311                 }
4312         }
4313         return ret;
4314 }
4315
4316 #if 0
4317 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4318 {
4319         return ci_enable_samu_dpm(adev, gate);
4320 }
4321
4322 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4323 {
4324         struct ci_power_info *pi = ci_get_pi(adev);
4325         u32 tmp;
4326
4327         if (!gate) {
4328                 pi->smc_state_table.AcpBootLevel = 0;
4329
4330                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4331                 tmp &= ~AcpBootLevel_MASK;
4332                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4333                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4334         }
4335
4336         return ci_enable_acp_dpm(adev, !gate);
4337 }
4338 #endif
4339
4340 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4341                                              struct amdgpu_ps *amdgpu_state)
4342 {
4343         struct ci_power_info *pi = ci_get_pi(adev);
4344         int ret;
4345
4346         ret = ci_trim_dpm_states(adev, amdgpu_state);
4347         if (ret)
4348                 return ret;
4349
4350         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4351                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4352         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4353                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4354         pi->last_mclk_dpm_enable_mask =
4355                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4356         if (pi->uvd_enabled) {
4357                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4358                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4359         }
4360         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4361                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4362
4363         return 0;
4364 }
4365
4366 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4367                                        u32 level_mask)
4368 {
4369         u32 level = 0;
4370
4371         while ((level_mask & (1 << level)) == 0)
4372                 level++;
4373
4374         return level;
4375 }
4376
4377
4378 static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4379                                           enum amd_dpm_forced_level level)
4380 {
4381         struct ci_power_info *pi = ci_get_pi(adev);
4382         u32 tmp, levels, i;
4383         int ret;
4384
4385         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
4386                 if ((!pi->pcie_dpm_key_disabled) &&
4387                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4388                         levels = 0;
4389                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4390                         while (tmp >>= 1)
4391                                 levels++;
4392                         if (levels) {
4393                                 ret = ci_dpm_force_state_pcie(adev, level);
4394                                 if (ret)
4395                                         return ret;
4396                                 for (i = 0; i < adev->usec_timeout; i++) {
4397                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4398                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4399                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4400                                         if (tmp == levels)
4401                                                 break;
4402                                         udelay(1);
4403                                 }
4404                         }
4405                 }
4406                 if ((!pi->sclk_dpm_key_disabled) &&
4407                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4408                         levels = 0;
4409                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4410                         while (tmp >>= 1)
4411                                 levels++;
4412                         if (levels) {
4413                                 ret = ci_dpm_force_state_sclk(adev, levels);
4414                                 if (ret)
4415                                         return ret;
4416                                 for (i = 0; i < adev->usec_timeout; i++) {
4417                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4418                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4419                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4420                                         if (tmp == levels)
4421                                                 break;
4422                                         udelay(1);
4423                                 }
4424                         }
4425                 }
4426                 if ((!pi->mclk_dpm_key_disabled) &&
4427                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4428                         levels = 0;
4429                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4430                         while (tmp >>= 1)
4431                                 levels++;
4432                         if (levels) {
4433                                 ret = ci_dpm_force_state_mclk(adev, levels);
4434                                 if (ret)
4435                                         return ret;
4436                                 for (i = 0; i < adev->usec_timeout; i++) {
4437                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4438                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4439                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4440                                         if (tmp == levels)
4441                                                 break;
4442                                         udelay(1);
4443                                 }
4444                         }
4445                 }
4446         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
4447                 if ((!pi->sclk_dpm_key_disabled) &&
4448                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4449                         levels = ci_get_lowest_enabled_level(adev,
4450                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4451                         ret = ci_dpm_force_state_sclk(adev, levels);
4452                         if (ret)
4453                                 return ret;
4454                         for (i = 0; i < adev->usec_timeout; i++) {
4455                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4456                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4457                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4458                                 if (tmp == levels)
4459                                         break;
4460                                 udelay(1);
4461                         }
4462                 }
4463                 if ((!pi->mclk_dpm_key_disabled) &&
4464                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4465                         levels = ci_get_lowest_enabled_level(adev,
4466                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4467                         ret = ci_dpm_force_state_mclk(adev, levels);
4468                         if (ret)
4469                                 return ret;
4470                         for (i = 0; i < adev->usec_timeout; i++) {
4471                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4472                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4473                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4474                                 if (tmp == levels)
4475                                         break;
4476                                 udelay(1);
4477                         }
4478                 }
4479                 if ((!pi->pcie_dpm_key_disabled) &&
4480                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4481                         levels = ci_get_lowest_enabled_level(adev,
4482                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4483                         ret = ci_dpm_force_state_pcie(adev, levels);
4484                         if (ret)
4485                                 return ret;
4486                         for (i = 0; i < adev->usec_timeout; i++) {
4487                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4488                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4489                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4490                                 if (tmp == levels)
4491                                         break;
4492                                 udelay(1);
4493                         }
4494                 }
4495         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
4496                 if (!pi->pcie_dpm_key_disabled) {
4497                         PPSMC_Result smc_result;
4498
4499                         smc_result = amdgpu_ci_send_msg_to_smc(adev,
4500                                                                PPSMC_MSG_PCIeDPM_UnForceLevel);
4501                         if (smc_result != PPSMC_Result_OK)
4502                                 return -EINVAL;
4503                 }
4504                 ret = ci_upload_dpm_level_enable_mask(adev);
4505                 if (ret)
4506                         return ret;
4507         }
4508
4509         adev->pm.dpm.forced_level = level;
4510
4511         return 0;
4512 }
4513
4514 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4515                                        struct ci_mc_reg_table *table)
4516 {
4517         u8 i, j, k;
4518         u32 temp_reg;
4519
4520         for (i = 0, j = table->last; i < table->last; i++) {
4521                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4522                         return -EINVAL;
4523                 switch(table->mc_reg_address[i].s1) {
4524                 case mmMC_SEQ_MISC1:
4525                         temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4526                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4527                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4528                         for (k = 0; k < table->num_entries; k++) {
4529                                 table->mc_reg_table_entry[k].mc_data[j] =
4530                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4531                         }
4532                         j++;
4533                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4534                                 return -EINVAL;
4535
4536                         temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4537                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4538                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4539                         for (k = 0; k < table->num_entries; k++) {
4540                                 table->mc_reg_table_entry[k].mc_data[j] =
4541                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4542                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4543                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4544                         }
4545                         j++;
4546                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4547                                 return -EINVAL;
4548
4549                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4550                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4551                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4552                                 for (k = 0; k < table->num_entries; k++) {
4553                                         table->mc_reg_table_entry[k].mc_data[j] =
4554                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4555                                 }
4556                                 j++;
4557                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4558                                         return -EINVAL;
4559                         }
4560                         break;
4561                 case mmMC_SEQ_RESERVE_M:
4562                         temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4563                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4564                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4565                         for (k = 0; k < table->num_entries; k++) {
4566                                 table->mc_reg_table_entry[k].mc_data[j] =
4567                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4568                         }
4569                         j++;
4570                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4571                                 return -EINVAL;
4572                         break;
4573                 default:
4574                         break;
4575                 }
4576
4577         }
4578
4579         table->last = j;
4580
4581         return 0;
4582 }
4583
4584 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4585 {
4586         bool result = true;
4587
4588         switch(in_reg) {
4589         case mmMC_SEQ_RAS_TIMING:
4590                 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4591                 break;
4592         case mmMC_SEQ_DLL_STBY:
4593                 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4594                 break;
4595         case mmMC_SEQ_G5PDX_CMD0:
4596                 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4597                 break;
4598         case mmMC_SEQ_G5PDX_CMD1:
4599                 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4600                 break;
4601         case mmMC_SEQ_G5PDX_CTRL:
4602                 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4603                 break;
4604         case mmMC_SEQ_CAS_TIMING:
4605                 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4606             break;
4607         case mmMC_SEQ_MISC_TIMING:
4608                 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4609                 break;
4610         case mmMC_SEQ_MISC_TIMING2:
4611                 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4612                 break;
4613         case mmMC_SEQ_PMG_DVS_CMD:
4614                 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4615                 break;
4616         case mmMC_SEQ_PMG_DVS_CTL:
4617                 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4618                 break;
4619         case mmMC_SEQ_RD_CTL_D0:
4620                 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4621                 break;
4622         case mmMC_SEQ_RD_CTL_D1:
4623                 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4624                 break;
4625         case mmMC_SEQ_WR_CTL_D0:
4626                 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4627                 break;
4628         case mmMC_SEQ_WR_CTL_D1:
4629                 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4630                 break;
4631         case mmMC_PMG_CMD_EMRS:
4632                 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4633                 break;
4634         case mmMC_PMG_CMD_MRS:
4635                 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4636                 break;
4637         case mmMC_PMG_CMD_MRS1:
4638                 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4639                 break;
4640         case mmMC_SEQ_PMG_TIMING:
4641                 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4642                 break;
4643         case mmMC_PMG_CMD_MRS2:
4644                 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4645                 break;
4646         case mmMC_SEQ_WR_CTL_2:
4647                 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4648                 break;
4649         default:
4650                 result = false;
4651                 break;
4652         }
4653
4654         return result;
4655 }
4656
4657 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4658 {
4659         u8 i, j;
4660
4661         for (i = 0; i < table->last; i++) {
4662                 for (j = 1; j < table->num_entries; j++) {
4663                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4664                             table->mc_reg_table_entry[j].mc_data[i]) {
4665                                 table->valid_flag |= 1 << i;
4666                                 break;
4667                         }
4668                 }
4669         }
4670 }
4671
4672 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4673 {
4674         u32 i;
4675         u16 address;
4676
4677         for (i = 0; i < table->last; i++) {
4678                 table->mc_reg_address[i].s0 =
4679                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4680                         address : table->mc_reg_address[i].s1;
4681         }
4682 }
4683
4684 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4685                                       struct ci_mc_reg_table *ci_table)
4686 {
4687         u8 i, j;
4688
4689         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4690                 return -EINVAL;
4691         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4692                 return -EINVAL;
4693
4694         for (i = 0; i < table->last; i++)
4695                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4696
4697         ci_table->last = table->last;
4698
4699         for (i = 0; i < table->num_entries; i++) {
4700                 ci_table->mc_reg_table_entry[i].mclk_max =
4701                         table->mc_reg_table_entry[i].mclk_max;
4702                 for (j = 0; j < table->last; j++)
4703                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4704                                 table->mc_reg_table_entry[i].mc_data[j];
4705         }
4706         ci_table->num_entries = table->num_entries;
4707
4708         return 0;
4709 }
4710
4711 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4712                                        struct ci_mc_reg_table *table)
4713 {
4714         u8 i, k;
4715         u32 tmp;
4716         bool patch;
4717
4718         tmp = RREG32(mmMC_SEQ_MISC0);
4719         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4720
4721         if (patch &&
4722             ((adev->pdev->device == 0x67B0) ||
4723              (adev->pdev->device == 0x67B1))) {
4724                 for (i = 0; i < table->last; i++) {
4725                         if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4726                                 return -EINVAL;
4727                         switch (table->mc_reg_address[i].s1) {
4728                         case mmMC_SEQ_MISC1:
4729                                 for (k = 0; k < table->num_entries; k++) {
4730                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4731                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4732                                                 table->mc_reg_table_entry[k].mc_data[i] =
4733                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4734                                                         0x00000007;
4735                                 }
4736                                 break;
4737                         case mmMC_SEQ_WR_CTL_D0:
4738                                 for (k = 0; k < table->num_entries; k++) {
4739                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4740                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4741                                                 table->mc_reg_table_entry[k].mc_data[i] =
4742                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4743                                                         0x0000D0DD;
4744                                 }
4745                                 break;
4746                         case mmMC_SEQ_WR_CTL_D1:
4747                                 for (k = 0; k < table->num_entries; k++) {
4748                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4749                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4750                                                 table->mc_reg_table_entry[k].mc_data[i] =
4751                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4752                                                         0x0000D0DD;
4753                                 }
4754                                 break;
4755                         case mmMC_SEQ_WR_CTL_2:
4756                                 for (k = 0; k < table->num_entries; k++) {
4757                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4758                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4759                                                 table->mc_reg_table_entry[k].mc_data[i] = 0;
4760                                 }
4761                                 break;
4762                         case mmMC_SEQ_CAS_TIMING:
4763                                 for (k = 0; k < table->num_entries; k++) {
4764                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4765                                                 table->mc_reg_table_entry[k].mc_data[i] =
4766                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4767                                                         0x000C0140;
4768                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4769                                                 table->mc_reg_table_entry[k].mc_data[i] =
4770                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4771                                                         0x000C0150;
4772                                 }
4773                                 break;
4774                         case mmMC_SEQ_MISC_TIMING:
4775                                 for (k = 0; k < table->num_entries; k++) {
4776                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4777                                                 table->mc_reg_table_entry[k].mc_data[i] =
4778                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4779                                                         0x00000030;
4780                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4781                                                 table->mc_reg_table_entry[k].mc_data[i] =
4782                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4783                                                         0x00000035;
4784                                 }
4785                                 break;
4786                         default:
4787                                 break;
4788                         }
4789                 }
4790
4791                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4792                 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4793                 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4794                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4795                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4796         }
4797
4798         return 0;
4799 }
4800
4801 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4802 {
4803         struct ci_power_info *pi = ci_get_pi(adev);
4804         struct atom_mc_reg_table *table;
4805         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4806         u8 module_index = ci_get_memory_module_index(adev);
4807         int ret;
4808
4809         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4810         if (!table)
4811                 return -ENOMEM;
4812
4813         WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4814         WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4815         WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4816         WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4817         WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4818         WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4819         WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4820         WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4821         WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4822         WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4823         WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4824         WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4825         WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4826         WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4827         WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4828         WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4829         WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4830         WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4831         WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4832         WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4833
4834         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4835         if (ret)
4836                 goto init_mc_done;
4837
4838         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4839         if (ret)
4840                 goto init_mc_done;
4841
4842         ci_set_s0_mc_reg_index(ci_table);
4843
4844         ret = ci_register_patching_mc_seq(adev, ci_table);
4845         if (ret)
4846                 goto init_mc_done;
4847
4848         ret = ci_set_mc_special_registers(adev, ci_table);
4849         if (ret)
4850                 goto init_mc_done;
4851
4852         ci_set_valid_flag(ci_table);
4853
4854 init_mc_done:
4855         kfree(table);
4856
4857         return ret;
4858 }
4859
4860 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4861                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4862 {
4863         struct ci_power_info *pi = ci_get_pi(adev);
4864         u32 i, j;
4865
4866         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4867                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4868                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4869                                 return -EINVAL;
4870                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4871                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4872                         i++;
4873                 }
4874         }
4875
4876         mc_reg_table->last = (u8)i;
4877
4878         return 0;
4879 }
4880
4881 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4882                                     SMU7_Discrete_MCRegisterSet *data,
4883                                     u32 num_entries, u32 valid_flag)
4884 {
4885         u32 i, j;
4886
4887         for (i = 0, j = 0; j < num_entries; j++) {
4888                 if (valid_flag & (1 << j)) {
4889                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4890                         i++;
4891                 }
4892         }
4893 }
4894
4895 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4896                                                  const u32 memory_clock,
4897                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4898 {
4899         struct ci_power_info *pi = ci_get_pi(adev);
4900         u32 i = 0;
4901
4902         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4903                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4904                         break;
4905         }
4906
4907         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4908                 --i;
4909
4910         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4911                                 mc_reg_table_data, pi->mc_reg_table.last,
4912                                 pi->mc_reg_table.valid_flag);
4913 }
4914
4915 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4916                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4917 {
4918         struct ci_power_info *pi = ci_get_pi(adev);
4919         u32 i;
4920
4921         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4922                 ci_convert_mc_reg_table_entry_to_smc(adev,
4923                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4924                                                      &mc_reg_table->data[i]);
4925 }
4926
4927 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4928 {
4929         struct ci_power_info *pi = ci_get_pi(adev);
4930         int ret;
4931
4932         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4933
4934         ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4935         if (ret)
4936                 return ret;
4937         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4938
4939         return amdgpu_ci_copy_bytes_to_smc(adev,
4940                                     pi->mc_reg_table_start,
4941                                     (u8 *)&pi->smc_mc_reg_table,
4942                                     sizeof(SMU7_Discrete_MCRegisters),
4943                                     pi->sram_end);
4944 }
4945
4946 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4947 {
4948         struct ci_power_info *pi = ci_get_pi(adev);
4949
4950         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4951                 return 0;
4952
4953         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4954
4955         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4956
4957         return amdgpu_ci_copy_bytes_to_smc(adev,
4958                                     pi->mc_reg_table_start +
4959                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4960                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4961                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4962                                     pi->dpm_table.mclk_table.count,
4963                                     pi->sram_end);
4964 }
4965
4966 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4967 {
4968         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4969
4970         tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4971         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4972 }
4973
4974 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4975                                                       struct amdgpu_ps *amdgpu_state)
4976 {
4977         struct ci_ps *state = ci_get_ps(amdgpu_state);
4978         int i;
4979         u16 pcie_speed, max_speed = 0;
4980
4981         for (i = 0; i < state->performance_level_count; i++) {
4982                 pcie_speed = state->performance_levels[i].pcie_gen;
4983                 if (max_speed < pcie_speed)
4984                         max_speed = pcie_speed;
4985         }
4986
4987         return max_speed;
4988 }
4989
4990 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4991 {
4992         u32 speed_cntl = 0;
4993
4994         speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4995                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4996         speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4997
4998         return (u16)speed_cntl;
4999 }
5000
5001 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
5002 {
5003         u32 link_width = 0;
5004
5005         link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
5006                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
5007         link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
5008
5009         switch (link_width) {
5010         case 1:
5011                 return 1;
5012         case 2:
5013                 return 2;
5014         case 3:
5015                 return 4;
5016         case 4:
5017                 return 8;
5018         case 0:
5019         case 6:
5020         default:
5021                 return 16;
5022         }
5023 }
5024
5025 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
5026                                                              struct amdgpu_ps *amdgpu_new_state,
5027                                                              struct amdgpu_ps *amdgpu_current_state)
5028 {
5029         struct ci_power_info *pi = ci_get_pi(adev);
5030         enum amdgpu_pcie_gen target_link_speed =
5031                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5032         enum amdgpu_pcie_gen current_link_speed;
5033
5034         if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
5035                 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
5036         else
5037                 current_link_speed = pi->force_pcie_gen;
5038
5039         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5040         pi->pspp_notify_required = false;
5041         if (target_link_speed > current_link_speed) {
5042                 switch (target_link_speed) {
5043 #ifdef CONFIG_ACPI
5044                 case AMDGPU_PCIE_GEN3:
5045                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5046                                 break;
5047                         pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
5048                         if (current_link_speed == AMDGPU_PCIE_GEN2)
5049                                 break;
5050                 case AMDGPU_PCIE_GEN2:
5051                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5052                                 break;
5053 #endif
5054                 default:
5055                         pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
5056                         break;
5057                 }
5058         } else {
5059                 if (target_link_speed < current_link_speed)
5060                         pi->pspp_notify_required = true;
5061         }
5062 }
5063
5064 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5065                                                            struct amdgpu_ps *amdgpu_new_state,
5066                                                            struct amdgpu_ps *amdgpu_current_state)
5067 {
5068         struct ci_power_info *pi = ci_get_pi(adev);
5069         enum amdgpu_pcie_gen target_link_speed =
5070                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5071         u8 request;
5072
5073         if (pi->pspp_notify_required) {
5074                 if (target_link_speed == AMDGPU_PCIE_GEN3)
5075                         request = PCIE_PERF_REQ_PECI_GEN3;
5076                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5077                         request = PCIE_PERF_REQ_PECI_GEN2;
5078                 else
5079                         request = PCIE_PERF_REQ_PECI_GEN1;
5080
5081                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5082                     (ci_get_current_pcie_speed(adev) > 0))
5083                         return;
5084
5085 #ifdef CONFIG_ACPI
5086                 amdgpu_acpi_pcie_performance_request(adev, request, false);
5087 #endif
5088         }
5089 }
5090
5091 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5092 {
5093         struct ci_power_info *pi = ci_get_pi(adev);
5094         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5095                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5096         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5097                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5098         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5099                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5100
5101         if (allowed_sclk_vddc_table == NULL)
5102                 return -EINVAL;
5103         if (allowed_sclk_vddc_table->count < 1)
5104                 return -EINVAL;
5105         if (allowed_mclk_vddc_table == NULL)
5106                 return -EINVAL;
5107         if (allowed_mclk_vddc_table->count < 1)
5108                 return -EINVAL;
5109         if (allowed_mclk_vddci_table == NULL)
5110                 return -EINVAL;
5111         if (allowed_mclk_vddci_table->count < 1)
5112                 return -EINVAL;
5113
5114         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5115         pi->max_vddc_in_pp_table =
5116                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5117
5118         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5119         pi->max_vddci_in_pp_table =
5120                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5121
5122         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5123                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5124         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5125                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5126         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5127                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5128         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5129                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5130
5131         return 0;
5132 }
5133
5134 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5135 {
5136         struct ci_power_info *pi = ci_get_pi(adev);
5137         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5138         u32 leakage_index;
5139
5140         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5141                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5142                         *vddc = leakage_table->actual_voltage[leakage_index];
5143                         break;
5144                 }
5145         }
5146 }
5147
5148 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5149 {
5150         struct ci_power_info *pi = ci_get_pi(adev);
5151         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5152         u32 leakage_index;
5153
5154         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5155                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5156                         *vddci = leakage_table->actual_voltage[leakage_index];
5157                         break;
5158                 }
5159         }
5160 }
5161
5162 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5163                                                                       struct amdgpu_clock_voltage_dependency_table *table)
5164 {
5165         u32 i;
5166
5167         if (table) {
5168                 for (i = 0; i < table->count; i++)
5169                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5170         }
5171 }
5172
5173 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5174                                                                        struct amdgpu_clock_voltage_dependency_table *table)
5175 {
5176         u32 i;
5177
5178         if (table) {
5179                 for (i = 0; i < table->count; i++)
5180                         ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5181         }
5182 }
5183
5184 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5185                                                                           struct amdgpu_vce_clock_voltage_dependency_table *table)
5186 {
5187         u32 i;
5188
5189         if (table) {
5190                 for (i = 0; i < table->count; i++)
5191                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5192         }
5193 }
5194
5195 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5196                                                                           struct amdgpu_uvd_clock_voltage_dependency_table *table)
5197 {
5198         u32 i;
5199
5200         if (table) {
5201                 for (i = 0; i < table->count; i++)
5202                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5203         }
5204 }
5205
5206 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5207                                                                    struct amdgpu_phase_shedding_limits_table *table)
5208 {
5209         u32 i;
5210
5211         if (table) {
5212                 for (i = 0; i < table->count; i++)
5213                         ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5214         }
5215 }
5216
5217 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5218                                                             struct amdgpu_clock_and_voltage_limits *table)
5219 {
5220         if (table) {
5221                 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5222                 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5223         }
5224 }
5225
5226 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5227                                                          struct amdgpu_cac_leakage_table *table)
5228 {
5229         u32 i;
5230
5231         if (table) {
5232                 for (i = 0; i < table->count; i++)
5233                         ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5234         }
5235 }
5236
5237 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5238 {
5239
5240         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5241                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5242         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5243                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5244         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5245                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5246         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5247                                                                    &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5248         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5249                                                                       &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5250         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5251                                                                       &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5252         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5253                                                                   &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5254         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5255                                                                   &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5256         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5257                                                                &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5258         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5259                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5260         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5261                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5262         ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5263                                                      &adev->pm.dpm.dyn_state.cac_leakage_table);
5264
5265 }
5266
5267 static void ci_update_current_ps(struct amdgpu_device *adev,
5268                                  struct amdgpu_ps *rps)
5269 {
5270         struct ci_ps *new_ps = ci_get_ps(rps);
5271         struct ci_power_info *pi = ci_get_pi(adev);
5272
5273         pi->current_rps = *rps;
5274         pi->current_ps = *new_ps;
5275         pi->current_rps.ps_priv = &pi->current_ps;
5276         adev->pm.dpm.current_ps = &pi->current_rps;
5277 }
5278
5279 static void ci_update_requested_ps(struct amdgpu_device *adev,
5280                                    struct amdgpu_ps *rps)
5281 {
5282         struct ci_ps *new_ps = ci_get_ps(rps);
5283         struct ci_power_info *pi = ci_get_pi(adev);
5284
5285         pi->requested_rps = *rps;
5286         pi->requested_ps = *new_ps;
5287         pi->requested_rps.ps_priv = &pi->requested_ps;
5288         adev->pm.dpm.requested_ps = &pi->requested_rps;
5289 }
5290
5291 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5292 {
5293         struct ci_power_info *pi = ci_get_pi(adev);
5294         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5295         struct amdgpu_ps *new_ps = &requested_ps;
5296
5297         ci_update_requested_ps(adev, new_ps);
5298
5299         ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5300
5301         return 0;
5302 }
5303
5304 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5305 {
5306         struct ci_power_info *pi = ci_get_pi(adev);
5307         struct amdgpu_ps *new_ps = &pi->requested_rps;
5308
5309         ci_update_current_ps(adev, new_ps);
5310 }
5311
5312
5313 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5314 {
5315         ci_read_clock_registers(adev);
5316         ci_enable_acpi_power_management(adev);
5317         ci_init_sclk_t(adev);
5318 }
5319
5320 static int ci_dpm_enable(struct amdgpu_device *adev)
5321 {
5322         struct ci_power_info *pi = ci_get_pi(adev);
5323         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5324         int ret;
5325
5326         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5327                 ci_enable_voltage_control(adev);
5328                 ret = ci_construct_voltage_tables(adev);
5329                 if (ret) {
5330                         DRM_ERROR("ci_construct_voltage_tables failed\n");
5331                         return ret;
5332                 }
5333         }
5334         if (pi->caps_dynamic_ac_timing) {
5335                 ret = ci_initialize_mc_reg_table(adev);
5336                 if (ret)
5337                         pi->caps_dynamic_ac_timing = false;
5338         }
5339         if (pi->dynamic_ss)
5340                 ci_enable_spread_spectrum(adev, true);
5341         if (pi->thermal_protection)
5342                 ci_enable_thermal_protection(adev, true);
5343         ci_program_sstp(adev);
5344         ci_enable_display_gap(adev);
5345         ci_program_vc(adev);
5346         ret = ci_upload_firmware(adev);
5347         if (ret) {
5348                 DRM_ERROR("ci_upload_firmware failed\n");
5349                 return ret;
5350         }
5351         ret = ci_process_firmware_header(adev);
5352         if (ret) {
5353                 DRM_ERROR("ci_process_firmware_header failed\n");
5354                 return ret;
5355         }
5356         ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5357         if (ret) {
5358                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5359                 return ret;
5360         }
5361         ret = ci_init_smc_table(adev);
5362         if (ret) {
5363                 DRM_ERROR("ci_init_smc_table failed\n");
5364                 return ret;
5365         }
5366         ret = ci_init_arb_table_index(adev);
5367         if (ret) {
5368                 DRM_ERROR("ci_init_arb_table_index failed\n");
5369                 return ret;
5370         }
5371         if (pi->caps_dynamic_ac_timing) {
5372                 ret = ci_populate_initial_mc_reg_table(adev);
5373                 if (ret) {
5374                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5375                         return ret;
5376                 }
5377         }
5378         ret = ci_populate_pm_base(adev);
5379         if (ret) {
5380                 DRM_ERROR("ci_populate_pm_base failed\n");
5381                 return ret;
5382         }
5383         ci_dpm_start_smc(adev);
5384         ci_enable_vr_hot_gpio_interrupt(adev);
5385         ret = ci_notify_smc_display_change(adev, false);
5386         if (ret) {
5387                 DRM_ERROR("ci_notify_smc_display_change failed\n");
5388                 return ret;
5389         }
5390         ci_enable_sclk_control(adev, true);
5391         ret = ci_enable_ulv(adev, true);
5392         if (ret) {
5393                 DRM_ERROR("ci_enable_ulv failed\n");
5394                 return ret;
5395         }
5396         ret = ci_enable_ds_master_switch(adev, true);
5397         if (ret) {
5398                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5399                 return ret;
5400         }
5401         ret = ci_start_dpm(adev);
5402         if (ret) {
5403                 DRM_ERROR("ci_start_dpm failed\n");
5404                 return ret;
5405         }
5406         ret = ci_enable_didt(adev, true);
5407         if (ret) {
5408                 DRM_ERROR("ci_enable_didt failed\n");
5409                 return ret;
5410         }
5411         ret = ci_enable_smc_cac(adev, true);
5412         if (ret) {
5413                 DRM_ERROR("ci_enable_smc_cac failed\n");
5414                 return ret;
5415         }
5416         ret = ci_enable_power_containment(adev, true);
5417         if (ret) {
5418                 DRM_ERROR("ci_enable_power_containment failed\n");
5419                 return ret;
5420         }
5421
5422         ret = ci_power_control_set_level(adev);
5423         if (ret) {
5424                 DRM_ERROR("ci_power_control_set_level failed\n");
5425                 return ret;
5426         }
5427
5428         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5429
5430         ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5431         if (ret) {
5432                 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5433                 return ret;
5434         }
5435
5436         ci_thermal_start_thermal_controller(adev);
5437
5438         ci_update_current_ps(adev, boot_ps);
5439
5440         return 0;
5441 }
5442
5443 static void ci_dpm_disable(struct amdgpu_device *adev)
5444 {
5445         struct ci_power_info *pi = ci_get_pi(adev);
5446         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5447
5448         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5449                        AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5450         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5451                        AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5452
5453         ci_dpm_powergate_uvd(adev, true);
5454
5455         if (!amdgpu_ci_is_smc_running(adev))
5456                 return;
5457
5458         ci_thermal_stop_thermal_controller(adev);
5459
5460         if (pi->thermal_protection)
5461                 ci_enable_thermal_protection(adev, false);
5462         ci_enable_power_containment(adev, false);
5463         ci_enable_smc_cac(adev, false);
5464         ci_enable_didt(adev, false);
5465         ci_enable_spread_spectrum(adev, false);
5466         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5467         ci_stop_dpm(adev);
5468         ci_enable_ds_master_switch(adev, false);
5469         ci_enable_ulv(adev, false);
5470         ci_clear_vc(adev);
5471         ci_reset_to_default(adev);
5472         ci_dpm_stop_smc(adev);
5473         ci_force_switch_to_arb_f0(adev);
5474         ci_enable_thermal_based_sclk_dpm(adev, false);
5475
5476         ci_update_current_ps(adev, boot_ps);
5477 }
5478
5479 static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5480 {
5481         struct ci_power_info *pi = ci_get_pi(adev);
5482         struct amdgpu_ps *new_ps = &pi->requested_rps;
5483         struct amdgpu_ps *old_ps = &pi->current_rps;
5484         int ret;
5485
5486         ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5487         if (pi->pcie_performance_request)
5488                 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5489         ret = ci_freeze_sclk_mclk_dpm(adev);
5490         if (ret) {
5491                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5492                 return ret;
5493         }
5494         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5495         if (ret) {
5496                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5497                 return ret;
5498         }
5499         ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5500         if (ret) {
5501                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5502                 return ret;
5503         }
5504
5505         ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5506         if (ret) {
5507                 DRM_ERROR("ci_update_vce_dpm failed\n");
5508                 return ret;
5509         }
5510
5511         ret = ci_update_sclk_t(adev);
5512         if (ret) {
5513                 DRM_ERROR("ci_update_sclk_t failed\n");
5514                 return ret;
5515         }
5516         if (pi->caps_dynamic_ac_timing) {
5517                 ret = ci_update_and_upload_mc_reg_table(adev);
5518                 if (ret) {
5519                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5520                         return ret;
5521                 }
5522         }
5523         ret = ci_program_memory_timing_parameters(adev);
5524         if (ret) {
5525                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5526                 return ret;
5527         }
5528         ret = ci_unfreeze_sclk_mclk_dpm(adev);
5529         if (ret) {
5530                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5531                 return ret;
5532         }
5533         ret = ci_upload_dpm_level_enable_mask(adev);
5534         if (ret) {
5535                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5536                 return ret;
5537         }
5538         if (pi->pcie_performance_request)
5539                 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5540
5541         return 0;
5542 }
5543
5544 #if 0
5545 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5546 {
5547         ci_set_boot_state(adev);
5548 }
5549 #endif
5550
5551 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5552 {
5553         ci_program_display_gap(adev);
5554 }
5555
5556 union power_info {
5557         struct _ATOM_POWERPLAY_INFO info;
5558         struct _ATOM_POWERPLAY_INFO_V2 info_2;
5559         struct _ATOM_POWERPLAY_INFO_V3 info_3;
5560         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5561         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5562         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5563 };
5564
5565 union pplib_clock_info {
5566         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5567         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5568         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5569         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5570         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5571         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5572 };
5573
5574 union pplib_power_state {
5575         struct _ATOM_PPLIB_STATE v1;
5576         struct _ATOM_PPLIB_STATE_V2 v2;
5577 };
5578
5579 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5580                                           struct amdgpu_ps *rps,
5581                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5582                                           u8 table_rev)
5583 {
5584         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5585         rps->class = le16_to_cpu(non_clock_info->usClassification);
5586         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5587
5588         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5589                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5590                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5591         } else {
5592                 rps->vclk = 0;
5593                 rps->dclk = 0;
5594         }
5595
5596         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5597                 adev->pm.dpm.boot_ps = rps;
5598         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5599                 adev->pm.dpm.uvd_ps = rps;
5600 }
5601
5602 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5603                                       struct amdgpu_ps *rps, int index,
5604                                       union pplib_clock_info *clock_info)
5605 {
5606         struct ci_power_info *pi = ci_get_pi(adev);
5607         struct ci_ps *ps = ci_get_ps(rps);
5608         struct ci_pl *pl = &ps->performance_levels[index];
5609
5610         ps->performance_level_count = index + 1;
5611
5612         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5613         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5614         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5615         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5616
5617         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5618                                                    pi->sys_pcie_mask,
5619                                                    pi->vbios_boot_state.pcie_gen_bootup_value,
5620                                                    clock_info->ci.ucPCIEGen);
5621         pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5622                                                      pi->vbios_boot_state.pcie_lane_bootup_value,
5623                                                      le16_to_cpu(clock_info->ci.usPCIELane));
5624
5625         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5626                 pi->acpi_pcie_gen = pl->pcie_gen;
5627         }
5628
5629         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5630                 pi->ulv.supported = true;
5631                 pi->ulv.pl = *pl;
5632                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5633         }
5634
5635         /* patch up boot state */
5636         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5637                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5638                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5639                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5640                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5641         }
5642
5643         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5644         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5645                 pi->use_pcie_powersaving_levels = true;
5646                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5647                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
5648                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5649                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
5650                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5651                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
5652                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5653                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
5654                 break;
5655         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5656                 pi->use_pcie_performance_levels = true;
5657                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5658                         pi->pcie_gen_performance.max = pl->pcie_gen;
5659                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5660                         pi->pcie_gen_performance.min = pl->pcie_gen;
5661                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5662                         pi->pcie_lane_performance.max = pl->pcie_lane;
5663                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5664                         pi->pcie_lane_performance.min = pl->pcie_lane;
5665                 break;
5666         default:
5667                 break;
5668         }
5669 }
5670
5671 static int ci_parse_power_table(struct amdgpu_device *adev)
5672 {
5673         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5674         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5675         union pplib_power_state *power_state;
5676         int i, j, k, non_clock_array_index, clock_array_index;
5677         union pplib_clock_info *clock_info;
5678         struct _StateArray *state_array;
5679         struct _ClockInfoArray *clock_info_array;
5680         struct _NonClockInfoArray *non_clock_info_array;
5681         union power_info *power_info;
5682         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5683         u16 data_offset;
5684         u8 frev, crev;
5685         u8 *power_state_offset;
5686         struct ci_ps *ps;
5687
5688         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5689                                    &frev, &crev, &data_offset))
5690                 return -EINVAL;
5691         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5692
5693         amdgpu_add_thermal_controller(adev);
5694
5695         state_array = (struct _StateArray *)
5696                 (mode_info->atom_context->bios + data_offset +
5697                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
5698         clock_info_array = (struct _ClockInfoArray *)
5699                 (mode_info->atom_context->bios + data_offset +
5700                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5701         non_clock_info_array = (struct _NonClockInfoArray *)
5702                 (mode_info->atom_context->bios + data_offset +
5703                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5704
5705         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5706                                   state_array->ucNumEntries, GFP_KERNEL);
5707         if (!adev->pm.dpm.ps)
5708                 return -ENOMEM;
5709         power_state_offset = (u8 *)state_array->states;
5710         for (i = 0; i < state_array->ucNumEntries; i++) {
5711                 u8 *idx;
5712                 power_state = (union pplib_power_state *)power_state_offset;
5713                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5714                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5715                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5716                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5717                 if (ps == NULL) {
5718                         kfree(adev->pm.dpm.ps);
5719                         return -ENOMEM;
5720                 }
5721                 adev->pm.dpm.ps[i].ps_priv = ps;
5722                 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5723                                               non_clock_info,
5724                                               non_clock_info_array->ucEntrySize);
5725                 k = 0;
5726                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5727                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5728                         clock_array_index = idx[j];
5729                         if (clock_array_index >= clock_info_array->ucNumEntries)
5730                                 continue;
5731                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5732                                 break;
5733                         clock_info = (union pplib_clock_info *)
5734                                 ((u8 *)&clock_info_array->clockInfo[0] +
5735                                  (clock_array_index * clock_info_array->ucEntrySize));
5736                         ci_parse_pplib_clock_info(adev,
5737                                                   &adev->pm.dpm.ps[i], k,
5738                                                   clock_info);
5739                         k++;
5740                 }
5741                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5742         }
5743         adev->pm.dpm.num_ps = state_array->ucNumEntries;
5744
5745         /* fill in the vce power states */
5746         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
5747                 u32 sclk, mclk;
5748                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5749                 clock_info = (union pplib_clock_info *)
5750                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5751                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5752                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5753                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5754                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5755                 adev->pm.dpm.vce_states[i].sclk = sclk;
5756                 adev->pm.dpm.vce_states[i].mclk = mclk;
5757         }
5758
5759         return 0;
5760 }
5761
5762 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5763                                     struct ci_vbios_boot_state *boot_state)
5764 {
5765         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5766         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5767         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5768         u8 frev, crev;
5769         u16 data_offset;
5770
5771         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5772                                    &frev, &crev, &data_offset)) {
5773                 firmware_info =
5774                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5775                                                     data_offset);
5776                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5777                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5778                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5779                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5780                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5781                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5782                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5783
5784                 return 0;
5785         }
5786         return -EINVAL;
5787 }
5788
5789 static void ci_dpm_fini(struct amdgpu_device *adev)
5790 {
5791         int i;
5792
5793         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5794                 kfree(adev->pm.dpm.ps[i].ps_priv);
5795         }
5796         kfree(adev->pm.dpm.ps);
5797         kfree(adev->pm.dpm.priv);
5798         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5799         amdgpu_free_extended_power_table(adev);
5800 }
5801
5802 /**
5803  * ci_dpm_init_microcode - load ucode images from disk
5804  *
5805  * @adev: amdgpu_device pointer
5806  *
5807  * Use the firmware interface to load the ucode images into
5808  * the driver (not loaded into hw).
5809  * Returns 0 on success, error on failure.
5810  */
5811 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5812 {
5813         const char *chip_name;
5814         char fw_name[30];
5815         int err;
5816
5817         DRM_DEBUG("\n");
5818
5819         switch (adev->asic_type) {
5820         case CHIP_BONAIRE:
5821                 if ((adev->pdev->revision == 0x80) ||
5822                     (adev->pdev->revision == 0x81) ||
5823                     (adev->pdev->device == 0x665f))
5824                         chip_name = "bonaire_k";
5825                 else
5826                         chip_name = "bonaire";
5827                 break;
5828         case CHIP_HAWAII:
5829                 if (adev->pdev->revision == 0x80)
5830                         chip_name = "hawaii_k";
5831                 else
5832                         chip_name = "hawaii";
5833                 break;
5834         case CHIP_KAVERI:
5835         case CHIP_KABINI:
5836         case CHIP_MULLINS:
5837         default: BUG();
5838         }
5839
5840         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
5841         err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
5842         if (err)
5843                 goto out;
5844         err = amdgpu_ucode_validate(adev->pm.fw);
5845
5846 out:
5847         if (err) {
5848                 pr_err("cik_smc: Failed to load firmware \"%s\"\n", fw_name);
5849                 release_firmware(adev->pm.fw);
5850                 adev->pm.fw = NULL;
5851         }
5852         return err;
5853 }
5854
5855 static int ci_dpm_init(struct amdgpu_device *adev)
5856 {
5857         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5858         SMU7_Discrete_DpmTable *dpm_table;
5859         struct amdgpu_gpio_rec gpio;
5860         u16 data_offset, size;
5861         u8 frev, crev;
5862         struct ci_power_info *pi;
5863         int ret;
5864
5865         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5866         if (pi == NULL)
5867                 return -ENOMEM;
5868         adev->pm.dpm.priv = pi;
5869
5870         pi->sys_pcie_mask =
5871                 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5872                 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5873
5874         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5875
5876         pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5877         pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5878         pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5879         pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5880
5881         pi->pcie_lane_performance.max = 0;
5882         pi->pcie_lane_performance.min = 16;
5883         pi->pcie_lane_powersaving.max = 0;
5884         pi->pcie_lane_powersaving.min = 16;
5885
5886         ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5887         if (ret) {
5888                 ci_dpm_fini(adev);
5889                 return ret;
5890         }
5891
5892         ret = amdgpu_get_platform_caps(adev);
5893         if (ret) {
5894                 ci_dpm_fini(adev);
5895                 return ret;
5896         }
5897
5898         ret = amdgpu_parse_extended_power_table(adev);
5899         if (ret) {
5900                 ci_dpm_fini(adev);
5901                 return ret;
5902         }
5903
5904         ret = ci_parse_power_table(adev);
5905         if (ret) {
5906                 ci_dpm_fini(adev);
5907                 return ret;
5908         }
5909
5910         pi->dll_default_on = false;
5911         pi->sram_end = SMC_RAM_END;
5912
5913         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5914         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5915         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5916         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5917         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5918         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5919         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5920         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5921
5922         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5923
5924         pi->sclk_dpm_key_disabled = 0;
5925         pi->mclk_dpm_key_disabled = 0;
5926         pi->pcie_dpm_key_disabled = 0;
5927         pi->thermal_sclk_dpm_enabled = 0;
5928
5929         if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
5930                 pi->caps_sclk_ds = true;
5931         else
5932                 pi->caps_sclk_ds = false;
5933
5934         pi->mclk_strobe_mode_threshold = 40000;
5935         pi->mclk_stutter_mode_threshold = 40000;
5936         pi->mclk_edc_enable_threshold = 40000;
5937         pi->mclk_edc_wr_enable_threshold = 40000;
5938
5939         ci_initialize_powertune_defaults(adev);
5940
5941         pi->caps_fps = false;
5942
5943         pi->caps_sclk_throttle_low_notification = false;
5944
5945         pi->caps_uvd_dpm = true;
5946         pi->caps_vce_dpm = true;
5947
5948         ci_get_leakage_voltages(adev);
5949         ci_patch_dependency_tables_with_leakage(adev);
5950         ci_set_private_data_variables_based_on_pptable(adev);
5951
5952         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5953                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5954         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5955                 ci_dpm_fini(adev);
5956                 return -ENOMEM;
5957         }
5958         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5959         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5960         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5961         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5962         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5963         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5964         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5965         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5966         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5967
5968         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5969         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5970         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5971
5972         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5973         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5974         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5975         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5976
5977         if (adev->asic_type == CHIP_HAWAII) {
5978                 pi->thermal_temp_setting.temperature_low = 94500;
5979                 pi->thermal_temp_setting.temperature_high = 95000;
5980                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5981         } else {
5982                 pi->thermal_temp_setting.temperature_low = 99500;
5983                 pi->thermal_temp_setting.temperature_high = 100000;
5984                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5985         }
5986
5987         pi->uvd_enabled = false;
5988
5989         dpm_table = &pi->smc_state_table;
5990
5991         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5992         if (gpio.valid) {
5993                 dpm_table->VRHotGpio = gpio.shift;
5994                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5995         } else {
5996                 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5997                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5998         }
5999
6000         gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
6001         if (gpio.valid) {
6002                 dpm_table->AcDcGpio = gpio.shift;
6003                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
6004         } else {
6005                 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
6006                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
6007         }
6008
6009         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
6010         if (gpio.valid) {
6011                 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
6012
6013                 switch (gpio.shift) {
6014                 case 0:
6015                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
6016                         tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
6017                         break;
6018                 case 1:
6019                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
6020                         tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
6021                         break;
6022                 case 2:
6023                         tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
6024                         break;
6025                 case 3:
6026                         tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
6027                         break;
6028                 case 4:
6029                         tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
6030                         break;
6031                 default:
6032                         DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift);
6033                         break;
6034                 }
6035                 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
6036         }
6037
6038         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6039         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6040         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6041         if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
6042                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6043         else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
6044                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6045
6046         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
6047                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
6048                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6049                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
6050                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6051                 else
6052                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
6053         }
6054
6055         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
6056                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
6057                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6058                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
6059                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6060                 else
6061                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
6062         }
6063
6064         pi->vddc_phase_shed_control = true;
6065
6066 #if defined(CONFIG_ACPI)
6067         pi->pcie_performance_request =
6068                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
6069 #else
6070         pi->pcie_performance_request = false;
6071 #endif
6072
6073         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6074                                    &frev, &crev, &data_offset)) {
6075                 pi->caps_sclk_ss_support = true;
6076                 pi->caps_mclk_ss_support = true;
6077                 pi->dynamic_ss = true;
6078         } else {
6079                 pi->caps_sclk_ss_support = false;
6080                 pi->caps_mclk_ss_support = false;
6081                 pi->dynamic_ss = true;
6082         }
6083
6084         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6085                 pi->thermal_protection = true;
6086         else
6087                 pi->thermal_protection = false;
6088
6089         pi->caps_dynamic_ac_timing = true;
6090
6091         pi->uvd_power_gated = true;
6092
6093         /* make sure dc limits are valid */
6094         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6095             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6096                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6097                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6098
6099         pi->fan_ctrl_is_in_default_mode = true;
6100
6101         return 0;
6102 }
6103
6104 static void
6105 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6106                                                struct seq_file *m)
6107 {
6108         struct ci_power_info *pi = ci_get_pi(adev);
6109         struct amdgpu_ps *rps = &pi->current_rps;
6110         u32 sclk = ci_get_average_sclk_freq(adev);
6111         u32 mclk = ci_get_average_mclk_freq(adev);
6112         u32 activity_percent = 50;
6113         int ret;
6114
6115         ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6116                                         &activity_percent);
6117
6118         if (ret == 0) {
6119                 activity_percent += 0x80;
6120                 activity_percent >>= 8;
6121                 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6122         }
6123
6124         seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
6125         seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6126         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
6127                    sclk, mclk);
6128         seq_printf(m, "GPU load: %u %%\n", activity_percent);
6129 }
6130
6131 static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6132                                      struct amdgpu_ps *rps)
6133 {
6134         struct ci_ps *ps = ci_get_ps(rps);
6135         struct ci_pl *pl;
6136         int i;
6137
6138         amdgpu_dpm_print_class_info(rps->class, rps->class2);
6139         amdgpu_dpm_print_cap_info(rps->caps);
6140         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6141         for (i = 0; i < ps->performance_level_count; i++) {
6142                 pl = &ps->performance_levels[i];
6143                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6144                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6145         }
6146         amdgpu_dpm_print_ps_status(adev, rps);
6147 }
6148
6149 static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1,
6150                                                 const struct ci_pl *ci_cpl2)
6151 {
6152         return ((ci_cpl1->mclk == ci_cpl2->mclk) &&
6153                   (ci_cpl1->sclk == ci_cpl2->sclk) &&
6154                   (ci_cpl1->pcie_gen == ci_cpl2->pcie_gen) &&
6155                   (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));
6156 }
6157
6158 static int ci_check_state_equal(struct amdgpu_device *adev,
6159                                 struct amdgpu_ps *cps,
6160                                 struct amdgpu_ps *rps,
6161                                 bool *equal)
6162 {
6163         struct ci_ps *ci_cps;
6164         struct ci_ps *ci_rps;
6165         int i;
6166
6167         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
6168                 return -EINVAL;
6169
6170         ci_cps = ci_get_ps(cps);
6171         ci_rps = ci_get_ps(rps);
6172
6173         if (ci_cps == NULL) {
6174                 *equal = false;
6175                 return 0;
6176         }
6177
6178         if (ci_cps->performance_level_count != ci_rps->performance_level_count) {
6179
6180                 *equal = false;
6181                 return 0;
6182         }
6183
6184         for (i = 0; i < ci_cps->performance_level_count; i++) {
6185                 if (!ci_are_power_levels_equal(&(ci_cps->performance_levels[i]),
6186                                         &(ci_rps->performance_levels[i]))) {
6187                         *equal = false;
6188                         return 0;
6189                 }
6190         }
6191
6192         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6193         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
6194         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
6195
6196         return 0;
6197 }
6198
6199 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6200 {
6201         struct ci_power_info *pi = ci_get_pi(adev);
6202         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6203
6204         if (low)
6205                 return requested_state->performance_levels[0].sclk;
6206         else
6207                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6208 }
6209
6210 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6211 {
6212         struct ci_power_info *pi = ci_get_pi(adev);
6213         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6214
6215         if (low)
6216                 return requested_state->performance_levels[0].mclk;
6217         else
6218                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6219 }
6220
6221 /* get temperature in millidegrees */
6222 static int ci_dpm_get_temp(struct amdgpu_device *adev)
6223 {
6224         u32 temp;
6225         int actual_temp = 0;
6226
6227         temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6228                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6229
6230         if (temp & 0x200)
6231                 actual_temp = 255;
6232         else
6233                 actual_temp = temp & 0x1ff;
6234
6235         actual_temp = actual_temp * 1000;
6236
6237         return actual_temp;
6238 }
6239
6240 static int ci_set_temperature_range(struct amdgpu_device *adev)
6241 {
6242         int ret;
6243
6244         ret = ci_thermal_enable_alert(adev, false);
6245         if (ret)
6246                 return ret;
6247         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6248                                                CISLANDS_TEMP_RANGE_MAX);
6249         if (ret)
6250                 return ret;
6251         ret = ci_thermal_enable_alert(adev, true);
6252         if (ret)
6253                 return ret;
6254         return ret;
6255 }
6256
6257 static int ci_dpm_early_init(void *handle)
6258 {
6259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6260
6261         ci_dpm_set_dpm_funcs(adev);
6262         ci_dpm_set_irq_funcs(adev);
6263
6264         return 0;
6265 }
6266
6267 static int ci_dpm_late_init(void *handle)
6268 {
6269         int ret;
6270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6271
6272         if (!amdgpu_dpm)
6273                 return 0;
6274
6275         /* init the sysfs and debugfs files late */
6276         ret = amdgpu_pm_sysfs_init(adev);
6277         if (ret)
6278                 return ret;
6279
6280         ret = ci_set_temperature_range(adev);
6281         if (ret)
6282                 return ret;
6283
6284         return 0;
6285 }
6286
6287 static int ci_dpm_sw_init(void *handle)
6288 {
6289         int ret;
6290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6291
6292         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
6293                                 &adev->pm.dpm.thermal.irq);
6294         if (ret)
6295                 return ret;
6296
6297         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
6298                                 &adev->pm.dpm.thermal.irq);
6299         if (ret)
6300                 return ret;
6301
6302         /* default to balanced state */
6303         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6304         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6305         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
6306         adev->pm.default_sclk = adev->clock.default_sclk;
6307         adev->pm.default_mclk = adev->clock.default_mclk;
6308         adev->pm.current_sclk = adev->clock.default_sclk;
6309         adev->pm.current_mclk = adev->clock.default_mclk;
6310         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6311
6312         ret = ci_dpm_init_microcode(adev);
6313         if (ret)
6314                 return ret;
6315
6316         if (amdgpu_dpm == 0)
6317                 return 0;
6318
6319         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6320         mutex_lock(&adev->pm.mutex);
6321         ret = ci_dpm_init(adev);
6322         if (ret)
6323                 goto dpm_failed;
6324         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6325         if (amdgpu_dpm == 1)
6326                 amdgpu_pm_print_power_states(adev);
6327         mutex_unlock(&adev->pm.mutex);
6328         DRM_INFO("amdgpu: dpm initialized\n");
6329
6330         return 0;
6331
6332 dpm_failed:
6333         ci_dpm_fini(adev);
6334         mutex_unlock(&adev->pm.mutex);
6335         DRM_ERROR("amdgpu: dpm initialization failed\n");
6336         return ret;
6337 }
6338
6339 static int ci_dpm_sw_fini(void *handle)
6340 {
6341         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6342
6343         flush_work(&adev->pm.dpm.thermal.work);
6344
6345         mutex_lock(&adev->pm.mutex);
6346         amdgpu_pm_sysfs_fini(adev);
6347         ci_dpm_fini(adev);
6348         mutex_unlock(&adev->pm.mutex);
6349
6350         release_firmware(adev->pm.fw);
6351         adev->pm.fw = NULL;
6352
6353         return 0;
6354 }
6355
6356 static int ci_dpm_hw_init(void *handle)
6357 {
6358         int ret;
6359
6360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6361
6362         if (!amdgpu_dpm) {
6363                 ret = ci_upload_firmware(adev);
6364                 if (ret) {
6365                         DRM_ERROR("ci_upload_firmware failed\n");
6366                         return ret;
6367                 }
6368                 ci_dpm_start_smc(adev);
6369                 return 0;
6370         }
6371
6372         mutex_lock(&adev->pm.mutex);
6373         ci_dpm_setup_asic(adev);
6374         ret = ci_dpm_enable(adev);
6375         if (ret)
6376                 adev->pm.dpm_enabled = false;
6377         else
6378                 adev->pm.dpm_enabled = true;
6379         mutex_unlock(&adev->pm.mutex);
6380
6381         return ret;
6382 }
6383
6384 static int ci_dpm_hw_fini(void *handle)
6385 {
6386         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6387
6388         if (adev->pm.dpm_enabled) {
6389                 mutex_lock(&adev->pm.mutex);
6390                 ci_dpm_disable(adev);
6391                 mutex_unlock(&adev->pm.mutex);
6392         } else {
6393                 ci_dpm_stop_smc(adev);
6394         }
6395
6396         return 0;
6397 }
6398
6399 static int ci_dpm_suspend(void *handle)
6400 {
6401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6402
6403         if (adev->pm.dpm_enabled) {
6404                 mutex_lock(&adev->pm.mutex);
6405                 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
6406                                AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
6407                 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
6408                                AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
6409                 adev->pm.dpm.last_user_state = adev->pm.dpm.user_state;
6410                 adev->pm.dpm.last_state = adev->pm.dpm.state;
6411                 adev->pm.dpm.user_state = POWER_STATE_TYPE_INTERNAL_BOOT;
6412                 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_BOOT;
6413                 mutex_unlock(&adev->pm.mutex);
6414                 amdgpu_pm_compute_clocks(adev);
6415
6416         }
6417
6418         return 0;
6419 }
6420
6421 static int ci_dpm_resume(void *handle)
6422 {
6423         int ret;
6424         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6425
6426         if (adev->pm.dpm_enabled) {
6427                 /* asic init will reset to the boot state */
6428                 mutex_lock(&adev->pm.mutex);
6429                 ci_dpm_setup_asic(adev);
6430                 ret = ci_dpm_enable(adev);
6431                 if (ret)
6432                         adev->pm.dpm_enabled = false;
6433                 else
6434                         adev->pm.dpm_enabled = true;
6435                 adev->pm.dpm.user_state = adev->pm.dpm.last_user_state;
6436                 adev->pm.dpm.state = adev->pm.dpm.last_state;
6437                 mutex_unlock(&adev->pm.mutex);
6438                 if (adev->pm.dpm_enabled)
6439                         amdgpu_pm_compute_clocks(adev);
6440         }
6441         return 0;
6442 }
6443
6444 static bool ci_dpm_is_idle(void *handle)
6445 {
6446         /* XXX */
6447         return true;
6448 }
6449
6450 static int ci_dpm_wait_for_idle(void *handle)
6451 {
6452         /* XXX */
6453         return 0;
6454 }
6455
6456 static int ci_dpm_soft_reset(void *handle)
6457 {
6458         return 0;
6459 }
6460
6461 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6462                                       struct amdgpu_irq_src *source,
6463                                       unsigned type,
6464                                       enum amdgpu_interrupt_state state)
6465 {
6466         u32 cg_thermal_int;
6467
6468         switch (type) {
6469         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6470                 switch (state) {
6471                 case AMDGPU_IRQ_STATE_DISABLE:
6472                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6473                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6474                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6475                         break;
6476                 case AMDGPU_IRQ_STATE_ENABLE:
6477                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6478                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6479                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6480                         break;
6481                 default:
6482                         break;
6483                 }
6484                 break;
6485
6486         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6487                 switch (state) {
6488                 case AMDGPU_IRQ_STATE_DISABLE:
6489                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6490                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6491                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6492                         break;
6493                 case AMDGPU_IRQ_STATE_ENABLE:
6494                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6495                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6496                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6497                         break;
6498                 default:
6499                         break;
6500                 }
6501                 break;
6502
6503         default:
6504                 break;
6505         }
6506         return 0;
6507 }
6508
6509 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6510                                     struct amdgpu_irq_src *source,
6511                                     struct amdgpu_iv_entry *entry)
6512 {
6513         bool queue_thermal = false;
6514
6515         if (entry == NULL)
6516                 return -EINVAL;
6517
6518         switch (entry->src_id) {
6519         case 230: /* thermal low to high */
6520                 DRM_DEBUG("IH: thermal low to high\n");
6521                 adev->pm.dpm.thermal.high_to_low = false;
6522                 queue_thermal = true;
6523                 break;
6524         case 231: /* thermal high to low */
6525                 DRM_DEBUG("IH: thermal high to low\n");
6526                 adev->pm.dpm.thermal.high_to_low = true;
6527                 queue_thermal = true;
6528                 break;
6529         default:
6530                 break;
6531         }
6532
6533         if (queue_thermal)
6534                 schedule_work(&adev->pm.dpm.thermal.work);
6535
6536         return 0;
6537 }
6538
6539 static int ci_dpm_set_clockgating_state(void *handle,
6540                                           enum amd_clockgating_state state)
6541 {
6542         return 0;
6543 }
6544
6545 static int ci_dpm_set_powergating_state(void *handle,
6546                                           enum amd_powergating_state state)
6547 {
6548         return 0;
6549 }
6550
6551 static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
6552                 enum pp_clock_type type, char *buf)
6553 {
6554         struct ci_power_info *pi = ci_get_pi(adev);
6555         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
6556         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
6557         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
6558
6559         int i, now, size = 0;
6560         uint32_t clock, pcie_speed;
6561
6562         switch (type) {
6563         case PP_SCLK:
6564                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
6565                 clock = RREG32(mmSMC_MSG_ARG_0);
6566
6567                 for (i = 0; i < sclk_table->count; i++) {
6568                         if (clock > sclk_table->dpm_levels[i].value)
6569                                 continue;
6570                         break;
6571                 }
6572                 now = i;
6573
6574                 for (i = 0; i < sclk_table->count; i++)
6575                         size += sprintf(buf + size, "%d: %uMhz %s\n",
6576                                         i, sclk_table->dpm_levels[i].value / 100,
6577                                         (i == now) ? "*" : "");
6578                 break;
6579         case PP_MCLK:
6580                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
6581                 clock = RREG32(mmSMC_MSG_ARG_0);
6582
6583                 for (i = 0; i < mclk_table->count; i++) {
6584                         if (clock > mclk_table->dpm_levels[i].value)
6585                                 continue;
6586                         break;
6587                 }
6588                 now = i;
6589
6590                 for (i = 0; i < mclk_table->count; i++)
6591                         size += sprintf(buf + size, "%d: %uMhz %s\n",
6592                                         i, mclk_table->dpm_levels[i].value / 100,
6593                                         (i == now) ? "*" : "");
6594                 break;
6595         case PP_PCIE:
6596                 pcie_speed = ci_get_current_pcie_speed(adev);
6597                 for (i = 0; i < pcie_table->count; i++) {
6598                         if (pcie_speed != pcie_table->dpm_levels[i].value)
6599                                 continue;
6600                         break;
6601                 }
6602                 now = i;
6603
6604                 for (i = 0; i < pcie_table->count; i++)
6605                         size += sprintf(buf + size, "%d: %s %s\n", i,
6606                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
6607                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6608                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6609                                         (i == now) ? "*" : "");
6610                 break;
6611         default:
6612                 break;
6613         }
6614
6615         return size;
6616 }
6617
6618 static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
6619                 enum pp_clock_type type, uint32_t mask)
6620 {
6621         struct ci_power_info *pi = ci_get_pi(adev);
6622
6623         if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |
6624                                 AMD_DPM_FORCED_LEVEL_LOW |
6625                                 AMD_DPM_FORCED_LEVEL_HIGH))
6626                 return -EINVAL;
6627
6628         switch (type) {
6629         case PP_SCLK:
6630                 if (!pi->sclk_dpm_key_disabled)
6631                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6632                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
6633                                         pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
6634                 break;
6635
6636         case PP_MCLK:
6637                 if (!pi->mclk_dpm_key_disabled)
6638                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6639                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
6640                                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
6641                 break;
6642
6643         case PP_PCIE:
6644         {
6645                 uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
6646                 uint32_t level = 0;
6647
6648                 while (tmp >>= 1)
6649                         level++;
6650
6651                 if (!pi->pcie_dpm_key_disabled)
6652                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6653                                         PPSMC_MSG_PCIeDPM_ForceLevel,
6654                                         level);
6655                 break;
6656         }
6657         default:
6658                 break;
6659         }
6660
6661         return 0;
6662 }
6663
6664 static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
6665 {
6666         struct ci_power_info *pi = ci_get_pi(adev);
6667         struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
6668         struct ci_single_dpm_table *golden_sclk_table =
6669                         &(pi->golden_dpm_table.sclk_table);
6670         int value;
6671
6672         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
6673                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
6674                         100 /
6675                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6676
6677         return value;
6678 }
6679
6680 static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
6681 {
6682         struct ci_power_info *pi = ci_get_pi(adev);
6683         struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6684         struct ci_single_dpm_table *golden_sclk_table =
6685                         &(pi->golden_dpm_table.sclk_table);
6686
6687         if (value > 20)
6688                 value = 20;
6689
6690         ps->performance_levels[ps->performance_level_count - 1].sclk =
6691                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
6692                         value / 100 +
6693                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6694
6695         return 0;
6696 }
6697
6698 static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
6699 {
6700         struct ci_power_info *pi = ci_get_pi(adev);
6701         struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
6702         struct ci_single_dpm_table *golden_mclk_table =
6703                         &(pi->golden_dpm_table.mclk_table);
6704         int value;
6705
6706         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
6707                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
6708                         100 /
6709                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6710
6711         return value;
6712 }
6713
6714 static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
6715 {
6716         struct ci_power_info *pi = ci_get_pi(adev);
6717         struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6718         struct ci_single_dpm_table *golden_mclk_table =
6719                         &(pi->golden_dpm_table.mclk_table);
6720
6721         if (value > 20)
6722                 value = 20;
6723
6724         ps->performance_levels[ps->performance_level_count - 1].mclk =
6725                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
6726                         value / 100 +
6727                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6728
6729         return 0;
6730 }
6731
6732 static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev,
6733                 struct amd_pp_profile *query)
6734 {
6735         struct ci_power_info *pi = ci_get_pi(adev);
6736
6737         if (!pi || !query)
6738                 return -EINVAL;
6739
6740         if (query->type == AMD_PP_GFX_PROFILE)
6741                 memcpy(query, &pi->gfx_power_profile,
6742                                 sizeof(struct amd_pp_profile));
6743         else if (query->type == AMD_PP_COMPUTE_PROFILE)
6744                 memcpy(query, &pi->compute_power_profile,
6745                                 sizeof(struct amd_pp_profile));
6746         else
6747                 return -EINVAL;
6748
6749         return 0;
6750 }
6751
6752 static int ci_populate_requested_graphic_levels(struct amdgpu_device *adev,
6753                 struct amd_pp_profile *request)
6754 {
6755         struct ci_power_info *pi = ci_get_pi(adev);
6756         struct ci_dpm_table *dpm_table = &(pi->dpm_table);
6757         struct SMU7_Discrete_GraphicsLevel *levels =
6758                         pi->smc_state_table.GraphicsLevel;
6759         uint32_t array = pi->dpm_table_start +
6760                         offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
6761         uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
6762                         SMU7_MAX_LEVELS_GRAPHICS;
6763         uint32_t i;
6764
6765         for (i = 0; i < dpm_table->sclk_table.count; i++) {
6766                 levels[i].ActivityLevel =
6767                                 cpu_to_be16(request->activity_threshold);
6768                 levels[i].EnabledForActivity = 1;
6769                 levels[i].UpH = request->up_hyst;
6770                 levels[i].DownH = request->down_hyst;
6771         }
6772
6773         return amdgpu_ci_copy_bytes_to_smc(adev, array, (uint8_t *)levels,
6774                                 array_size, pi->sram_end);
6775 }
6776
6777 static void ci_find_min_clock_masks(struct amdgpu_device *adev,
6778                 uint32_t *sclk_mask, uint32_t *mclk_mask,
6779                 uint32_t min_sclk, uint32_t min_mclk)
6780 {
6781         struct ci_power_info *pi = ci_get_pi(adev);
6782         struct ci_dpm_table *dpm_table = &(pi->dpm_table);
6783         uint32_t i;
6784
6785         for (i = 0; i < dpm_table->sclk_table.count; i++) {
6786                 if (dpm_table->sclk_table.dpm_levels[i].enabled &&
6787                         dpm_table->sclk_table.dpm_levels[i].value >= min_sclk)
6788                         *sclk_mask |= 1 << i;
6789         }
6790
6791         for (i = 0; i < dpm_table->mclk_table.count; i++) {
6792                 if (dpm_table->mclk_table.dpm_levels[i].enabled &&
6793                         dpm_table->mclk_table.dpm_levels[i].value >= min_mclk)
6794                         *mclk_mask |= 1 << i;
6795         }
6796 }
6797
6798 static int ci_set_power_profile_state(struct amdgpu_device *adev,
6799                 struct amd_pp_profile *request)
6800 {
6801         struct ci_power_info *pi = ci_get_pi(adev);
6802         int tmp_result, result = 0;
6803         uint32_t sclk_mask = 0, mclk_mask = 0;
6804
6805         tmp_result = ci_freeze_sclk_mclk_dpm(adev);
6806         if (tmp_result) {
6807                 DRM_ERROR("Failed to freeze SCLK MCLK DPM!");
6808                 result = tmp_result;
6809         }
6810
6811         tmp_result = ci_populate_requested_graphic_levels(adev,
6812                         request);
6813         if (tmp_result) {
6814                 DRM_ERROR("Failed to populate requested graphic levels!");
6815                 result = tmp_result;
6816         }
6817
6818         tmp_result = ci_unfreeze_sclk_mclk_dpm(adev);
6819         if (tmp_result) {
6820                 DRM_ERROR("Failed to unfreeze SCLK MCLK DPM!");
6821                 result = tmp_result;
6822         }
6823
6824         ci_find_min_clock_masks(adev, &sclk_mask, &mclk_mask,
6825                         request->min_sclk, request->min_mclk);
6826
6827         if (sclk_mask) {
6828                 if (!pi->sclk_dpm_key_disabled)
6829                         amdgpu_ci_send_msg_to_smc_with_parameter(
6830                                 adev,
6831                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
6832                                 pi->dpm_level_enable_mask.
6833                                 sclk_dpm_enable_mask &
6834                                 sclk_mask);
6835         }
6836
6837         if (mclk_mask) {
6838                 if (!pi->mclk_dpm_key_disabled)
6839                         amdgpu_ci_send_msg_to_smc_with_parameter(
6840                                 adev,
6841                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
6842                                 pi->dpm_level_enable_mask.
6843                                 mclk_dpm_enable_mask &
6844                                 mclk_mask);
6845         }
6846
6847
6848         return result;
6849 }
6850
6851 static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev,
6852                 struct amd_pp_profile *request)
6853 {
6854         struct ci_power_info *pi = ci_get_pi(adev);
6855         int ret = -1;
6856
6857         if (!pi || !request)
6858                 return -EINVAL;
6859
6860         if (adev->pm.dpm.forced_level !=
6861                         AMD_DPM_FORCED_LEVEL_AUTO)
6862                 return -EINVAL;
6863
6864         if (request->min_sclk ||
6865                 request->min_mclk ||
6866                 request->activity_threshold ||
6867                 request->up_hyst ||
6868                 request->down_hyst) {
6869                 if (request->type == AMD_PP_GFX_PROFILE)
6870                         memcpy(&pi->gfx_power_profile, request,
6871                                         sizeof(struct amd_pp_profile));
6872                 else if (request->type == AMD_PP_COMPUTE_PROFILE)
6873                         memcpy(&pi->compute_power_profile, request,
6874                                         sizeof(struct amd_pp_profile));
6875                 else
6876                         return -EINVAL;
6877
6878                 if (request->type == pi->current_power_profile)
6879                         ret = ci_set_power_profile_state(
6880                                         adev,
6881                                         request);
6882         } else {
6883                 /* set power profile if it exists */
6884                 switch (request->type) {
6885                 case AMD_PP_GFX_PROFILE:
6886                         ret = ci_set_power_profile_state(
6887                                 adev,
6888                                 &pi->gfx_power_profile);
6889                         break;
6890                 case AMD_PP_COMPUTE_PROFILE:
6891                         ret = ci_set_power_profile_state(
6892                                 adev,
6893                                 &pi->compute_power_profile);
6894                         break;
6895                 default:
6896                         return -EINVAL;
6897                 }
6898         }
6899
6900         if (!ret)
6901                 pi->current_power_profile = request->type;
6902
6903         return 0;
6904 }
6905
6906 static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev,
6907                 struct amd_pp_profile *request)
6908 {
6909         struct ci_power_info *pi = ci_get_pi(adev);
6910
6911         if (!pi || !request)
6912                 return -EINVAL;
6913
6914         if (request->type == AMD_PP_GFX_PROFILE) {
6915                 pi->gfx_power_profile = pi->default_gfx_power_profile;
6916                 return ci_dpm_set_power_profile_state(adev,
6917                                           &pi->gfx_power_profile);
6918         } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
6919                 pi->compute_power_profile =
6920                         pi->default_compute_power_profile;
6921                 return ci_dpm_set_power_profile_state(adev,
6922                                           &pi->compute_power_profile);
6923         } else
6924                 return -EINVAL;
6925 }
6926
6927 static int ci_dpm_switch_power_profile(struct amdgpu_device *adev,
6928                 enum amd_pp_profile_type type)
6929 {
6930         struct ci_power_info *pi = ci_get_pi(adev);
6931         struct amd_pp_profile request = {0};
6932
6933         if (!pi)
6934                 return -EINVAL;
6935
6936         if (pi->current_power_profile != type) {
6937                 request.type = type;
6938                 return ci_dpm_set_power_profile_state(adev, &request);
6939         }
6940
6941         return 0;
6942 }
6943
6944 static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
6945                               void *value, int *size)
6946 {
6947         u32 activity_percent = 50;
6948         int ret;
6949
6950         /* size must be at least 4 bytes for all sensors */
6951         if (*size < 4)
6952                 return -EINVAL;
6953
6954         switch (idx) {
6955         case AMDGPU_PP_SENSOR_GFX_SCLK:
6956                 *((uint32_t *)value) = ci_get_average_sclk_freq(adev);
6957                 *size = 4;
6958                 return 0;
6959         case AMDGPU_PP_SENSOR_GFX_MCLK:
6960                 *((uint32_t *)value) = ci_get_average_mclk_freq(adev);
6961                 *size = 4;
6962                 return 0;
6963         case AMDGPU_PP_SENSOR_GPU_TEMP:
6964                 *((uint32_t *)value) = ci_dpm_get_temp(adev);
6965                 *size = 4;
6966                 return 0;
6967         case AMDGPU_PP_SENSOR_GPU_LOAD:
6968                 ret = ci_read_smc_soft_register(adev,
6969                                                 offsetof(SMU7_SoftRegisters,
6970                                                          AverageGraphicsA),
6971                                                 &activity_percent);
6972                 if (ret == 0) {
6973                         activity_percent += 0x80;
6974                         activity_percent >>= 8;
6975                         activity_percent =
6976                                 activity_percent > 100 ? 100 : activity_percent;
6977                 }
6978                 *((uint32_t *)value) = activity_percent;
6979                 *size = 4;
6980                 return 0;
6981         default:
6982                 return -EINVAL;
6983         }
6984 }
6985
6986 const struct amd_ip_funcs ci_dpm_ip_funcs = {
6987         .name = "ci_dpm",
6988         .early_init = ci_dpm_early_init,
6989         .late_init = ci_dpm_late_init,
6990         .sw_init = ci_dpm_sw_init,
6991         .sw_fini = ci_dpm_sw_fini,
6992         .hw_init = ci_dpm_hw_init,
6993         .hw_fini = ci_dpm_hw_fini,
6994         .suspend = ci_dpm_suspend,
6995         .resume = ci_dpm_resume,
6996         .is_idle = ci_dpm_is_idle,
6997         .wait_for_idle = ci_dpm_wait_for_idle,
6998         .soft_reset = ci_dpm_soft_reset,
6999         .set_clockgating_state = ci_dpm_set_clockgating_state,
7000         .set_powergating_state = ci_dpm_set_powergating_state,
7001 };
7002
7003 static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
7004         .get_temperature = &ci_dpm_get_temp,
7005         .pre_set_power_state = &ci_dpm_pre_set_power_state,
7006         .set_power_state = &ci_dpm_set_power_state,
7007         .post_set_power_state = &ci_dpm_post_set_power_state,
7008         .display_configuration_changed = &ci_dpm_display_configuration_changed,
7009         .get_sclk = &ci_dpm_get_sclk,
7010         .get_mclk = &ci_dpm_get_mclk,
7011         .print_power_state = &ci_dpm_print_power_state,
7012         .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
7013         .force_performance_level = &ci_dpm_force_performance_level,
7014         .vblank_too_short = &ci_dpm_vblank_too_short,
7015         .powergate_uvd = &ci_dpm_powergate_uvd,
7016         .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
7017         .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
7018         .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
7019         .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
7020         .print_clock_levels = ci_dpm_print_clock_levels,
7021         .force_clock_level = ci_dpm_force_clock_level,
7022         .get_sclk_od = ci_dpm_get_sclk_od,
7023         .set_sclk_od = ci_dpm_set_sclk_od,
7024         .get_mclk_od = ci_dpm_get_mclk_od,
7025         .set_mclk_od = ci_dpm_set_mclk_od,
7026         .check_state_equal = ci_check_state_equal,
7027         .get_vce_clock_state = amdgpu_get_vce_clock_state,
7028         .get_power_profile_state = ci_dpm_get_power_profile_state,
7029         .set_power_profile_state = ci_dpm_set_power_profile_state,
7030         .reset_power_profile_state = ci_dpm_reset_power_profile_state,
7031         .switch_power_profile = ci_dpm_switch_power_profile,
7032         .read_sensor = ci_dpm_read_sensor,
7033 };
7034
7035 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
7036 {
7037         if (adev->pm.funcs == NULL)
7038                 adev->pm.funcs = &ci_dpm_funcs;
7039 }
7040
7041 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
7042         .set = ci_dpm_set_interrupt_state,
7043         .process = ci_dpm_process_interrupt,
7044 };
7045
7046 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
7047 {
7048         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
7049         adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
7050 }