2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_pm.h"
28 #include "amdgpu_ucode.h"
30 #include "amdgpu_dpm.h"
35 #include <linux/seq_file.h>
37 #include "smu/smu_7_0_1_d.h"
38 #include "smu/smu_7_0_1_sh_mask.h"
40 #include "dce/dce_8_0_d.h"
41 #include "dce/dce_8_0_sh_mask.h"
43 #include "bif/bif_4_1_d.h"
44 #include "bif/bif_4_1_sh_mask.h"
46 #include "gca/gfx_7_2_d.h"
47 #include "gca/gfx_7_2_sh_mask.h"
49 #include "gmc/gmc_7_1_d.h"
50 #include "gmc/gmc_7_1_sh_mask.h"
54 #define MC_CG_ARB_FREQ_F0 0x0a
55 #define MC_CG_ARB_FREQ_F1 0x0b
56 #define MC_CG_ARB_FREQ_F2 0x0c
57 #define MC_CG_ARB_FREQ_F3 0x0d
59 #define SMC_RAM_END 0x40000
61 #define VOLTAGE_SCALE 4
62 #define VOLTAGE_VID_OFFSET_SCALE1 625
63 #define VOLTAGE_VID_OFFSET_SCALE2 100
65 static const struct ci_pt_defaults defaults_hawaii_xt =
67 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
68 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
69 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
72 static const struct ci_pt_defaults defaults_hawaii_pro =
74 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
75 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
76 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
79 static const struct ci_pt_defaults defaults_bonaire_xt =
81 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
82 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
83 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
87 static const struct ci_pt_defaults defaults_bonaire_pro =
89 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
90 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
91 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
95 static const struct ci_pt_defaults defaults_saturn_xt =
97 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
98 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
99 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
103 static const struct ci_pt_defaults defaults_saturn_pro =
105 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
106 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
107 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
111 static const struct ci_pt_config_reg didt_config_ci[] =
113 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
163 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
164 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
165 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
166 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
167 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
168 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
169 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
170 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
171 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
172 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
173 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
174 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
175 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
176 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
177 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
178 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
179 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
180 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
181 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
182 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
183 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
184 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
188 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
190 return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
193 #define MC_CG_ARB_FREQ_F0 0x0a
194 #define MC_CG_ARB_FREQ_F1 0x0b
195 #define MC_CG_ARB_FREQ_F2 0x0c
196 #define MC_CG_ARB_FREQ_F3 0x0d
198 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
199 u32 arb_freq_src, u32 arb_freq_dest)
201 u32 mc_arb_dram_timing;
202 u32 mc_arb_dram_timing2;
206 switch (arb_freq_src) {
207 case MC_CG_ARB_FREQ_F0:
208 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
209 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
210 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
211 MC_ARB_BURST_TIME__STATE0__SHIFT;
213 case MC_CG_ARB_FREQ_F1:
214 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1);
215 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
216 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
217 MC_ARB_BURST_TIME__STATE1__SHIFT;
223 switch (arb_freq_dest) {
224 case MC_CG_ARB_FREQ_F0:
225 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
226 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
227 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
228 ~MC_ARB_BURST_TIME__STATE0_MASK);
230 case MC_CG_ARB_FREQ_F1:
231 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
232 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
233 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
234 ~MC_ARB_BURST_TIME__STATE1_MASK);
240 mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
241 WREG32(mmMC_CG_CONFIG, mc_cg_config);
242 WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
243 ~MC_ARB_CG__CG_ARB_REQ_MASK);
248 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
252 if (memory_clock < 10000)
254 else if (memory_clock >= 80000)
255 mc_para_index = 0x0f;
257 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
258 return mc_para_index;
261 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
266 if (memory_clock < 12500)
267 mc_para_index = 0x00;
268 else if (memory_clock > 47500)
269 mc_para_index = 0x0f;
271 mc_para_index = (u8)((memory_clock - 10000) / 2500);
273 if (memory_clock < 65000)
274 mc_para_index = 0x00;
275 else if (memory_clock > 135000)
276 mc_para_index = 0x0f;
278 mc_para_index = (u8)((memory_clock - 60000) / 5000);
280 return mc_para_index;
283 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
284 u32 max_voltage_steps,
285 struct atom_voltage_table *voltage_table)
287 unsigned int i, diff;
289 if (voltage_table->count <= max_voltage_steps)
292 diff = voltage_table->count - max_voltage_steps;
294 for (i = 0; i < max_voltage_steps; i++)
295 voltage_table->entries[i] = voltage_table->entries[i + diff];
297 voltage_table->count = max_voltage_steps;
300 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
301 struct atom_voltage_table_entry *voltage_table,
302 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
303 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
304 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
306 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
307 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
308 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
310 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
311 PPSMC_Msg msg, u32 parameter);
312 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
313 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
315 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
317 struct ci_power_info *pi = adev->pm.dpm.priv;
322 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
324 struct ci_ps *ps = rps->ps_priv;
329 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
331 struct ci_power_info *pi = ci_get_pi(adev);
333 switch (adev->pdev->device) {
341 pi->powertune_defaults = &defaults_bonaire_xt;
347 pi->powertune_defaults = &defaults_saturn_xt;
351 pi->powertune_defaults = &defaults_hawaii_xt;
355 pi->powertune_defaults = &defaults_hawaii_pro;
365 pi->powertune_defaults = &defaults_bonaire_xt;
369 pi->dte_tj_offset = 0;
371 pi->caps_power_containment = true;
372 pi->caps_cac = false;
373 pi->caps_sq_ramping = false;
374 pi->caps_db_ramping = false;
375 pi->caps_td_ramping = false;
376 pi->caps_tcp_ramping = false;
378 if (pi->caps_power_containment) {
380 if (adev->asic_type == CHIP_HAWAII)
381 pi->enable_bapm_feature = false;
383 pi->enable_bapm_feature = true;
384 pi->enable_tdc_limit_feature = true;
385 pi->enable_pkg_pwr_tracking_feature = true;
389 static u8 ci_convert_to_vid(u16 vddc)
391 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
394 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
396 struct ci_power_info *pi = ci_get_pi(adev);
397 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
398 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
399 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
402 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
404 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
406 if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
407 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
410 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
411 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
412 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
413 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
414 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
416 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
417 hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
423 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
425 struct ci_power_info *pi = ci_get_pi(adev);
426 u8 *vid = pi->smc_powertune_table.VddCVid;
429 if (pi->vddc_voltage_table.count > 8)
432 for (i = 0; i < pi->vddc_voltage_table.count; i++)
433 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
438 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
440 struct ci_power_info *pi = ci_get_pi(adev);
441 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
443 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
444 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
445 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
446 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
451 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
453 struct ci_power_info *pi = ci_get_pi(adev);
454 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
457 tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
458 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
459 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
460 pt_defaults->tdc_vddc_throttle_release_limit_perc;
461 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
466 static int ci_populate_dw8(struct amdgpu_device *adev)
468 struct ci_power_info *pi = ci_get_pi(adev);
469 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
472 ret = amdgpu_ci_read_smc_sram_dword(adev,
473 SMU7_FIRMWARE_HEADER_LOCATION +
474 offsetof(SMU7_Firmware_Header, PmFuseTable) +
475 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
476 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
481 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
486 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
488 struct ci_power_info *pi = ci_get_pi(adev);
490 if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
491 (adev->pm.dpm.fan.fan_output_sensitivity == 0))
492 adev->pm.dpm.fan.fan_output_sensitivity =
493 adev->pm.dpm.fan.default_fan_output_sensitivity;
495 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
496 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
501 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
503 struct ci_power_info *pi = ci_get_pi(adev);
504 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
505 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
508 min = max = hi_vid[0];
509 for (i = 0; i < 8; i++) {
510 if (0 != hi_vid[i]) {
517 if (0 != lo_vid[i]) {
525 if ((min == 0) || (max == 0))
527 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
528 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
533 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
535 struct ci_power_info *pi = ci_get_pi(adev);
536 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
537 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
538 struct amdgpu_cac_tdp_table *cac_tdp_table =
539 adev->pm.dpm.dyn_state.cac_tdp_table;
541 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
542 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
544 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
545 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
550 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
552 struct ci_power_info *pi = ci_get_pi(adev);
553 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
554 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
555 struct amdgpu_cac_tdp_table *cac_tdp_table =
556 adev->pm.dpm.dyn_state.cac_tdp_table;
557 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
562 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
563 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
565 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
566 dpm_table->GpuTjMax =
567 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
568 dpm_table->GpuTjHyst = 8;
570 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
573 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
574 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
576 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
577 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
580 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
581 def1 = pt_defaults->bapmti_r;
582 def2 = pt_defaults->bapmti_rc;
584 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
585 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
586 for (k = 0; k < SMU7_DTE_SINKS; k++) {
587 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
588 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
598 static int ci_populate_pm_base(struct amdgpu_device *adev)
600 struct ci_power_info *pi = ci_get_pi(adev);
601 u32 pm_fuse_table_offset;
604 if (pi->caps_power_containment) {
605 ret = amdgpu_ci_read_smc_sram_dword(adev,
606 SMU7_FIRMWARE_HEADER_LOCATION +
607 offsetof(SMU7_Firmware_Header, PmFuseTable),
608 &pm_fuse_table_offset, pi->sram_end);
611 ret = ci_populate_bapm_vddc_vid_sidd(adev);
614 ret = ci_populate_vddc_vid(adev);
617 ret = ci_populate_svi_load_line(adev);
620 ret = ci_populate_tdc_limit(adev);
623 ret = ci_populate_dw8(adev);
626 ret = ci_populate_fuzzy_fan(adev);
629 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
632 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
635 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
636 (u8 *)&pi->smc_powertune_table,
637 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
645 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
647 struct ci_power_info *pi = ci_get_pi(adev);
650 if (pi->caps_sq_ramping) {
651 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
653 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
655 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
656 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
659 if (pi->caps_db_ramping) {
660 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
662 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
664 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
665 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
668 if (pi->caps_td_ramping) {
669 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
671 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
673 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
674 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
677 if (pi->caps_tcp_ramping) {
678 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
680 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
682 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
683 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
687 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
688 const struct ci_pt_config_reg *cac_config_regs)
690 const struct ci_pt_config_reg *config_regs = cac_config_regs;
694 if (config_regs == NULL)
697 while (config_regs->offset != 0xFFFFFFFF) {
698 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
699 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
701 switch (config_regs->type) {
702 case CISLANDS_CONFIGREG_SMC_IND:
703 data = RREG32_SMC(config_regs->offset);
705 case CISLANDS_CONFIGREG_DIDT_IND:
706 data = RREG32_DIDT(config_regs->offset);
709 data = RREG32(config_regs->offset);
713 data &= ~config_regs->mask;
714 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
717 switch (config_regs->type) {
718 case CISLANDS_CONFIGREG_SMC_IND:
719 WREG32_SMC(config_regs->offset, data);
721 case CISLANDS_CONFIGREG_DIDT_IND:
722 WREG32_DIDT(config_regs->offset, data);
725 WREG32(config_regs->offset, data);
735 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
737 struct ci_power_info *pi = ci_get_pi(adev);
740 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
741 pi->caps_td_ramping || pi->caps_tcp_ramping) {
742 adev->gfx.rlc.funcs->enter_safe_mode(adev);
745 ret = ci_program_pt_config_registers(adev, didt_config_ci);
747 adev->gfx.rlc.funcs->exit_safe_mode(adev);
752 ci_do_enable_didt(adev, enable);
754 adev->gfx.rlc.funcs->exit_safe_mode(adev);
760 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
762 struct ci_power_info *pi = ci_get_pi(adev);
763 PPSMC_Result smc_result;
767 pi->power_containment_features = 0;
768 if (pi->caps_power_containment) {
769 if (pi->enable_bapm_feature) {
770 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
771 if (smc_result != PPSMC_Result_OK)
774 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
777 if (pi->enable_tdc_limit_feature) {
778 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
779 if (smc_result != PPSMC_Result_OK)
782 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
785 if (pi->enable_pkg_pwr_tracking_feature) {
786 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
787 if (smc_result != PPSMC_Result_OK) {
790 struct amdgpu_cac_tdp_table *cac_tdp_table =
791 adev->pm.dpm.dyn_state.cac_tdp_table;
792 u32 default_pwr_limit =
793 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
795 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
797 ci_set_power_limit(adev, default_pwr_limit);
802 if (pi->caps_power_containment && pi->power_containment_features) {
803 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
804 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
806 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
807 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
809 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
810 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
811 pi->power_containment_features = 0;
818 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
820 struct ci_power_info *pi = ci_get_pi(adev);
821 PPSMC_Result smc_result;
826 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
827 if (smc_result != PPSMC_Result_OK) {
829 pi->cac_enabled = false;
831 pi->cac_enabled = true;
833 } else if (pi->cac_enabled) {
834 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
835 pi->cac_enabled = false;
842 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
845 struct ci_power_info *pi = ci_get_pi(adev);
846 PPSMC_Result smc_result = PPSMC_Result_OK;
848 if (pi->thermal_sclk_dpm_enabled) {
850 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
852 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
855 if (smc_result == PPSMC_Result_OK)
861 static int ci_power_control_set_level(struct amdgpu_device *adev)
863 struct ci_power_info *pi = ci_get_pi(adev);
864 struct amdgpu_cac_tdp_table *cac_tdp_table =
865 adev->pm.dpm.dyn_state.cac_tdp_table;
869 bool adjust_polarity = false; /* ??? */
871 if (pi->caps_power_containment) {
872 adjust_percent = adjust_polarity ?
873 adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
874 target_tdp = ((100 + adjust_percent) *
875 (s32)cac_tdp_table->configurable_tdp) / 100;
877 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
883 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
885 struct ci_power_info *pi = ci_get_pi(adev);
887 pi->uvd_power_gated = gate;
890 /* stop the UVD block */
891 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
893 ci_update_uvd_dpm(adev, gate);
895 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
896 AMD_PG_STATE_UNGATE);
897 ci_update_uvd_dpm(adev, gate);
901 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
903 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
904 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
906 /* disable mclk switching if the refresh is >120Hz, even if the
907 * blanking period would allow it
909 if (amdgpu_dpm_get_vrefresh(adev) > 120)
912 if (vblank_time < switch_limit)
919 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
920 struct amdgpu_ps *rps)
922 struct ci_ps *ps = ci_get_ps(rps);
923 struct ci_power_info *pi = ci_get_pi(adev);
924 struct amdgpu_clock_and_voltage_limits *max_limits;
925 bool disable_mclk_switching;
929 if (rps->vce_active) {
930 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
931 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
937 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
938 ci_dpm_vblank_too_short(adev))
939 disable_mclk_switching = true;
941 disable_mclk_switching = false;
943 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
944 pi->battery_state = true;
946 pi->battery_state = false;
948 if (adev->pm.dpm.ac_power)
949 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
951 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
953 if (adev->pm.dpm.ac_power == false) {
954 for (i = 0; i < ps->performance_level_count; i++) {
955 if (ps->performance_levels[i].mclk > max_limits->mclk)
956 ps->performance_levels[i].mclk = max_limits->mclk;
957 if (ps->performance_levels[i].sclk > max_limits->sclk)
958 ps->performance_levels[i].sclk = max_limits->sclk;
962 /* XXX validate the min clocks required for display */
964 if (disable_mclk_switching) {
965 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
966 sclk = ps->performance_levels[0].sclk;
968 mclk = ps->performance_levels[0].mclk;
969 sclk = ps->performance_levels[0].sclk;
972 if (adev->pm.pm_display_cfg.min_core_set_clock > sclk)
973 sclk = adev->pm.pm_display_cfg.min_core_set_clock;
975 if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk)
976 mclk = adev->pm.pm_display_cfg.min_mem_set_clock;
978 if (rps->vce_active) {
979 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
980 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
981 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
982 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
985 ps->performance_levels[0].sclk = sclk;
986 ps->performance_levels[0].mclk = mclk;
988 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
989 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
991 if (disable_mclk_switching) {
992 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
993 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
995 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
996 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
1000 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
1001 int min_temp, int max_temp)
1003 int low_temp = 0 * 1000;
1004 int high_temp = 255 * 1000;
1007 if (low_temp < min_temp)
1008 low_temp = min_temp;
1009 if (high_temp > max_temp)
1010 high_temp = max_temp;
1011 if (high_temp < low_temp) {
1012 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1016 tmp = RREG32_SMC(ixCG_THERMAL_INT);
1017 tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
1018 tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1019 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1020 WREG32_SMC(ixCG_THERMAL_INT, tmp);
1023 /* XXX: need to figure out how to handle this properly */
1024 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1025 tmp &= DIG_THERM_DPM_MASK;
1026 tmp |= DIG_THERM_DPM(high_temp / 1000);
1027 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1030 adev->pm.dpm.thermal.min_temp = low_temp;
1031 adev->pm.dpm.thermal.max_temp = high_temp;
1035 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1038 u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1039 PPSMC_Result result;
1042 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1043 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1044 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1045 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1046 if (result != PPSMC_Result_OK) {
1047 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1051 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1052 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1053 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1054 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1055 if (result != PPSMC_Result_OK) {
1056 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1064 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1066 struct ci_power_info *pi = ci_get_pi(adev);
1069 if (pi->fan_ctrl_is_in_default_mode) {
1070 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1071 >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1072 pi->fan_ctrl_default_mode = tmp;
1073 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1074 >> CG_FDO_CTRL2__TMIN__SHIFT;
1076 pi->fan_ctrl_is_in_default_mode = false;
1079 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1080 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1081 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1083 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1084 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1085 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1088 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1090 struct ci_power_info *pi = ci_get_pi(adev);
1091 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1093 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1094 u16 fdo_min, slope1, slope2;
1095 u32 reference_clock, tmp;
1099 if (!pi->fan_table_start) {
1100 adev->pm.dpm.fan.ucode_fan_control = false;
1104 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1105 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1108 adev->pm.dpm.fan.ucode_fan_control = false;
1112 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1113 do_div(tmp64, 10000);
1114 fdo_min = (u16)tmp64;
1116 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1117 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1119 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1120 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1122 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1123 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1125 fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1126 fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1127 fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1129 fan_table.Slope1 = cpu_to_be16(slope1);
1130 fan_table.Slope2 = cpu_to_be16(slope2);
1132 fan_table.FdoMin = cpu_to_be16(fdo_min);
1134 fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1136 fan_table.HystUp = cpu_to_be16(1);
1138 fan_table.HystSlope = cpu_to_be16(1);
1140 fan_table.TempRespLim = cpu_to_be16(5);
1142 reference_clock = amdgpu_asic_get_xclk(adev);
1144 fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1145 reference_clock) / 1600);
1147 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1149 tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1150 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1151 fan_table.TempSrc = (uint8_t)tmp;
1153 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1154 pi->fan_table_start,
1160 DRM_ERROR("Failed to load fan table to the SMC.");
1161 adev->pm.dpm.fan.ucode_fan_control = false;
1167 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1169 struct ci_power_info *pi = ci_get_pi(adev);
1172 if (pi->caps_od_fuzzy_fan_control_support) {
1173 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1174 PPSMC_StartFanControl,
1176 if (ret != PPSMC_Result_OK)
1178 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1179 PPSMC_MSG_SetFanPwmMax,
1180 adev->pm.dpm.fan.default_max_fan_pwm);
1181 if (ret != PPSMC_Result_OK)
1184 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1185 PPSMC_StartFanControl,
1187 if (ret != PPSMC_Result_OK)
1191 pi->fan_is_controlled_by_smc = true;
1196 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1199 struct ci_power_info *pi = ci_get_pi(adev);
1201 ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1202 if (ret == PPSMC_Result_OK) {
1203 pi->fan_is_controlled_by_smc = false;
1210 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1216 if (adev->pm.no_fan)
1219 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1220 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1221 duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1222 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1227 tmp64 = (u64)duty * 100;
1228 do_div(tmp64, duty100);
1229 *speed = (u32)tmp64;
1237 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1243 struct ci_power_info *pi = ci_get_pi(adev);
1245 if (adev->pm.no_fan)
1248 if (pi->fan_is_controlled_by_smc)
1254 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1255 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1260 tmp64 = (u64)speed * duty100;
1264 tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1265 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1266 WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1271 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1274 case AMD_FAN_CTRL_NONE:
1275 if (adev->pm.dpm.fan.ucode_fan_control)
1276 ci_fan_ctrl_stop_smc_fan_control(adev);
1277 ci_dpm_set_fan_speed_percent(adev, 100);
1279 case AMD_FAN_CTRL_MANUAL:
1280 if (adev->pm.dpm.fan.ucode_fan_control)
1281 ci_fan_ctrl_stop_smc_fan_control(adev);
1283 case AMD_FAN_CTRL_AUTO:
1284 if (adev->pm.dpm.fan.ucode_fan_control)
1285 ci_thermal_start_smc_fan_control(adev);
1292 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1294 struct ci_power_info *pi = ci_get_pi(adev);
1296 if (pi->fan_is_controlled_by_smc)
1297 return AMD_FAN_CTRL_AUTO;
1299 return AMD_FAN_CTRL_MANUAL;
1303 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1307 u32 xclk = amdgpu_asic_get_xclk(adev);
1309 if (adev->pm.no_fan)
1312 if (adev->pm.fan_pulses_per_revolution == 0)
1315 tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1316 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1317 if (tach_period == 0)
1320 *speed = 60 * xclk * 10000 / tach_period;
1325 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1328 u32 tach_period, tmp;
1329 u32 xclk = amdgpu_asic_get_xclk(adev);
1331 if (adev->pm.no_fan)
1334 if (adev->pm.fan_pulses_per_revolution == 0)
1337 if ((speed < adev->pm.fan_min_rpm) ||
1338 (speed > adev->pm.fan_max_rpm))
1341 if (adev->pm.dpm.fan.ucode_fan_control)
1342 ci_fan_ctrl_stop_smc_fan_control(adev);
1344 tach_period = 60 * xclk * 10000 / (8 * speed);
1345 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1346 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1347 WREG32_SMC(CG_TACH_CTRL, tmp);
1349 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1355 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1357 struct ci_power_info *pi = ci_get_pi(adev);
1360 if (!pi->fan_ctrl_is_in_default_mode) {
1361 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1362 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1363 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1365 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1366 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1367 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1368 pi->fan_ctrl_is_in_default_mode = true;
1372 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1374 if (adev->pm.dpm.fan.ucode_fan_control) {
1375 ci_fan_ctrl_start_smc_fan_control(adev);
1376 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1380 static void ci_thermal_initialize(struct amdgpu_device *adev)
1384 if (adev->pm.fan_pulses_per_revolution) {
1385 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1386 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1387 << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1388 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1391 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1392 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1393 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1396 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1400 ci_thermal_initialize(adev);
1401 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1404 ret = ci_thermal_enable_alert(adev, true);
1407 if (adev->pm.dpm.fan.ucode_fan_control) {
1408 ret = ci_thermal_setup_fan_table(adev);
1411 ci_thermal_start_smc_fan_control(adev);
1417 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1419 if (!adev->pm.no_fan)
1420 ci_fan_ctrl_set_default_mode(adev);
1423 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1424 u16 reg_offset, u32 *value)
1426 struct ci_power_info *pi = ci_get_pi(adev);
1428 return amdgpu_ci_read_smc_sram_dword(adev,
1429 pi->soft_regs_start + reg_offset,
1430 value, pi->sram_end);
1433 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1434 u16 reg_offset, u32 value)
1436 struct ci_power_info *pi = ci_get_pi(adev);
1438 return amdgpu_ci_write_smc_sram_dword(adev,
1439 pi->soft_regs_start + reg_offset,
1440 value, pi->sram_end);
1443 static void ci_init_fps_limits(struct amdgpu_device *adev)
1445 struct ci_power_info *pi = ci_get_pi(adev);
1446 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1452 table->FpsHighT = cpu_to_be16(tmp);
1455 table->FpsLowT = cpu_to_be16(tmp);
1459 static int ci_update_sclk_t(struct amdgpu_device *adev)
1461 struct ci_power_info *pi = ci_get_pi(adev);
1463 u32 low_sclk_interrupt_t = 0;
1465 if (pi->caps_sclk_throttle_low_notification) {
1466 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1468 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1469 pi->dpm_table_start +
1470 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1471 (u8 *)&low_sclk_interrupt_t,
1472 sizeof(u32), pi->sram_end);
1479 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1481 struct ci_power_info *pi = ci_get_pi(adev);
1482 u16 leakage_id, virtual_voltage_id;
1486 pi->vddc_leakage.count = 0;
1487 pi->vddci_leakage.count = 0;
1489 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1490 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1491 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1492 if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1494 if (vddc != 0 && vddc != virtual_voltage_id) {
1495 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1496 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1497 pi->vddc_leakage.count++;
1500 } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1501 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1502 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1503 if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1506 if (vddc != 0 && vddc != virtual_voltage_id) {
1507 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1508 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1509 pi->vddc_leakage.count++;
1511 if (vddci != 0 && vddci != virtual_voltage_id) {
1512 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1513 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1514 pi->vddci_leakage.count++;
1521 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1523 struct ci_power_info *pi = ci_get_pi(adev);
1524 bool want_thermal_protection;
1525 enum amdgpu_dpm_event_src dpm_event_src;
1531 want_thermal_protection = false;
1533 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1534 want_thermal_protection = true;
1535 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1537 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1538 want_thermal_protection = true;
1539 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1541 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1542 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1543 want_thermal_protection = true;
1544 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1548 if (want_thermal_protection) {
1550 /* XXX: need to figure out how to handle this properly */
1551 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1552 tmp &= DPM_EVENT_SRC_MASK;
1553 tmp |= DPM_EVENT_SRC(dpm_event_src);
1554 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1557 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1558 if (pi->thermal_protection)
1559 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1561 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1562 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1564 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1565 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1566 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1570 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1571 enum amdgpu_dpm_auto_throttle_src source,
1574 struct ci_power_info *pi = ci_get_pi(adev);
1577 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1578 pi->active_auto_throttle_sources |= 1 << source;
1579 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1582 if (pi->active_auto_throttle_sources & (1 << source)) {
1583 pi->active_auto_throttle_sources &= ~(1 << source);
1584 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1589 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1591 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1592 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1595 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1597 struct ci_power_info *pi = ci_get_pi(adev);
1598 PPSMC_Result smc_result;
1600 if (!pi->need_update_smu7_dpm_table)
1603 if ((!pi->sclk_dpm_key_disabled) &&
1604 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1605 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1606 if (smc_result != PPSMC_Result_OK)
1610 if ((!pi->mclk_dpm_key_disabled) &&
1611 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1612 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1613 if (smc_result != PPSMC_Result_OK)
1617 pi->need_update_smu7_dpm_table = 0;
1621 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1623 struct ci_power_info *pi = ci_get_pi(adev);
1624 PPSMC_Result smc_result;
1627 if (!pi->sclk_dpm_key_disabled) {
1628 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1629 if (smc_result != PPSMC_Result_OK)
1633 if (!pi->mclk_dpm_key_disabled) {
1634 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1635 if (smc_result != PPSMC_Result_OK)
1638 WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1639 ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1641 WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1642 WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1643 WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1647 WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1648 WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1649 WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1652 if (!pi->sclk_dpm_key_disabled) {
1653 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1654 if (smc_result != PPSMC_Result_OK)
1658 if (!pi->mclk_dpm_key_disabled) {
1659 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1660 if (smc_result != PPSMC_Result_OK)
1668 static int ci_start_dpm(struct amdgpu_device *adev)
1670 struct ci_power_info *pi = ci_get_pi(adev);
1671 PPSMC_Result smc_result;
1675 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1676 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1677 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1679 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1680 tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1681 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1683 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1685 WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1687 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1688 if (smc_result != PPSMC_Result_OK)
1691 ret = ci_enable_sclk_mclk_dpm(adev, true);
1695 if (!pi->pcie_dpm_key_disabled) {
1696 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1697 if (smc_result != PPSMC_Result_OK)
1704 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1706 struct ci_power_info *pi = ci_get_pi(adev);
1707 PPSMC_Result smc_result;
1709 if (!pi->need_update_smu7_dpm_table)
1712 if ((!pi->sclk_dpm_key_disabled) &&
1713 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1714 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1715 if (smc_result != PPSMC_Result_OK)
1719 if ((!pi->mclk_dpm_key_disabled) &&
1720 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1721 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1722 if (smc_result != PPSMC_Result_OK)
1729 static int ci_stop_dpm(struct amdgpu_device *adev)
1731 struct ci_power_info *pi = ci_get_pi(adev);
1732 PPSMC_Result smc_result;
1736 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1737 tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1738 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1740 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1741 tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1742 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1744 if (!pi->pcie_dpm_key_disabled) {
1745 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1746 if (smc_result != PPSMC_Result_OK)
1750 ret = ci_enable_sclk_mclk_dpm(adev, false);
1754 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1755 if (smc_result != PPSMC_Result_OK)
1761 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1763 u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1766 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1768 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1769 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1773 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1776 struct ci_power_info *pi = ci_get_pi(adev);
1777 struct amdgpu_cac_tdp_table *cac_tdp_table =
1778 adev->pm.dpm.dyn_state.cac_tdp_table;
1782 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1784 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1786 ci_set_power_limit(adev, power_limit);
1788 if (pi->caps_automatic_dc_transition) {
1790 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1792 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1799 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1800 PPSMC_Msg msg, u32 parameter)
1802 WREG32(mmSMC_MSG_ARG_0, parameter);
1803 return amdgpu_ci_send_msg_to_smc(adev, msg);
1806 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1807 PPSMC_Msg msg, u32 *parameter)
1809 PPSMC_Result smc_result;
1811 smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1813 if ((smc_result == PPSMC_Result_OK) && parameter)
1814 *parameter = RREG32(mmSMC_MSG_ARG_0);
1819 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1821 struct ci_power_info *pi = ci_get_pi(adev);
1823 if (!pi->sclk_dpm_key_disabled) {
1824 PPSMC_Result smc_result =
1825 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1826 if (smc_result != PPSMC_Result_OK)
1833 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1835 struct ci_power_info *pi = ci_get_pi(adev);
1837 if (!pi->mclk_dpm_key_disabled) {
1838 PPSMC_Result smc_result =
1839 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1840 if (smc_result != PPSMC_Result_OK)
1847 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1849 struct ci_power_info *pi = ci_get_pi(adev);
1851 if (!pi->pcie_dpm_key_disabled) {
1852 PPSMC_Result smc_result =
1853 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1854 if (smc_result != PPSMC_Result_OK)
1861 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1863 struct ci_power_info *pi = ci_get_pi(adev);
1865 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1866 PPSMC_Result smc_result =
1867 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1868 if (smc_result != PPSMC_Result_OK)
1875 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1878 PPSMC_Result smc_result =
1879 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1880 if (smc_result != PPSMC_Result_OK)
1886 static int ci_set_boot_state(struct amdgpu_device *adev)
1888 return ci_enable_sclk_mclk_dpm(adev, false);
1892 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1895 PPSMC_Result smc_result =
1896 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1897 PPSMC_MSG_API_GetSclkFrequency,
1899 if (smc_result != PPSMC_Result_OK)
1905 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1908 PPSMC_Result smc_result =
1909 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1910 PPSMC_MSG_API_GetMclkFrequency,
1912 if (smc_result != PPSMC_Result_OK)
1918 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1922 amdgpu_ci_program_jump_on_start(adev);
1923 amdgpu_ci_start_smc_clock(adev);
1924 amdgpu_ci_start_smc(adev);
1925 for (i = 0; i < adev->usec_timeout; i++) {
1926 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1931 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1933 amdgpu_ci_reset_smc(adev);
1934 amdgpu_ci_stop_smc_clock(adev);
1937 static int ci_process_firmware_header(struct amdgpu_device *adev)
1939 struct ci_power_info *pi = ci_get_pi(adev);
1943 ret = amdgpu_ci_read_smc_sram_dword(adev,
1944 SMU7_FIRMWARE_HEADER_LOCATION +
1945 offsetof(SMU7_Firmware_Header, DpmTable),
1946 &tmp, pi->sram_end);
1950 pi->dpm_table_start = tmp;
1952 ret = amdgpu_ci_read_smc_sram_dword(adev,
1953 SMU7_FIRMWARE_HEADER_LOCATION +
1954 offsetof(SMU7_Firmware_Header, SoftRegisters),
1955 &tmp, pi->sram_end);
1959 pi->soft_regs_start = tmp;
1961 ret = amdgpu_ci_read_smc_sram_dword(adev,
1962 SMU7_FIRMWARE_HEADER_LOCATION +
1963 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1964 &tmp, pi->sram_end);
1968 pi->mc_reg_table_start = tmp;
1970 ret = amdgpu_ci_read_smc_sram_dword(adev,
1971 SMU7_FIRMWARE_HEADER_LOCATION +
1972 offsetof(SMU7_Firmware_Header, FanTable),
1973 &tmp, pi->sram_end);
1977 pi->fan_table_start = tmp;
1979 ret = amdgpu_ci_read_smc_sram_dword(adev,
1980 SMU7_FIRMWARE_HEADER_LOCATION +
1981 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1982 &tmp, pi->sram_end);
1986 pi->arb_table_start = tmp;
1991 static void ci_read_clock_registers(struct amdgpu_device *adev)
1993 struct ci_power_info *pi = ci_get_pi(adev);
1995 pi->clock_registers.cg_spll_func_cntl =
1996 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1997 pi->clock_registers.cg_spll_func_cntl_2 =
1998 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1999 pi->clock_registers.cg_spll_func_cntl_3 =
2000 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
2001 pi->clock_registers.cg_spll_func_cntl_4 =
2002 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
2003 pi->clock_registers.cg_spll_spread_spectrum =
2004 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2005 pi->clock_registers.cg_spll_spread_spectrum_2 =
2006 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
2007 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
2008 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
2009 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
2010 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
2011 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
2012 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
2013 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
2014 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
2015 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
2018 static void ci_init_sclk_t(struct amdgpu_device *adev)
2020 struct ci_power_info *pi = ci_get_pi(adev);
2022 pi->low_sclk_interrupt_t = 0;
2025 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2028 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2031 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2033 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2034 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2037 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2039 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2041 tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2043 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2047 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2050 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2057 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2061 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2065 for (i = 0; i < adev->usec_timeout; i++) {
2066 if (RREG32(mmSMC_RESP_0) == 1)
2075 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2078 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2080 return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
2083 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2086 struct ci_power_info *pi = ci_get_pi(adev);
2089 if (pi->caps_sclk_ds) {
2090 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2093 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2097 if (pi->caps_sclk_ds) {
2098 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2106 static void ci_program_display_gap(struct amdgpu_device *adev)
2108 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2109 u32 pre_vbi_time_in_us;
2110 u32 frame_time_in_us;
2111 u32 ref_clock = adev->clock.spll.reference_freq;
2112 u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2113 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2115 tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2116 if (adev->pm.dpm.new_active_crtc_count > 0)
2117 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2119 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2120 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2122 if (refresh_rate == 0)
2124 if (vblank_time == 0xffffffff)
2126 frame_time_in_us = 1000000 / refresh_rate;
2127 pre_vbi_time_in_us =
2128 frame_time_in_us - 200 - vblank_time;
2129 tmp = pre_vbi_time_in_us * (ref_clock / 100);
2131 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2132 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2133 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2136 ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2140 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2142 struct ci_power_info *pi = ci_get_pi(adev);
2146 if (pi->caps_sclk_ss_support) {
2147 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2148 tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2149 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2152 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2153 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2154 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2156 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2157 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2158 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2162 static void ci_program_sstp(struct amdgpu_device *adev)
2164 WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2165 ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2166 (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2169 static void ci_enable_display_gap(struct amdgpu_device *adev)
2171 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2173 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2174 CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2175 tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2176 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2178 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2181 static void ci_program_vc(struct amdgpu_device *adev)
2185 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2186 tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2187 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2189 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2190 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2191 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2192 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2193 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2194 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2195 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2196 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2199 static void ci_clear_vc(struct amdgpu_device *adev)
2203 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2204 tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2205 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2207 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2208 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2209 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2210 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2211 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2212 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2213 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2214 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2217 static int ci_upload_firmware(struct amdgpu_device *adev)
2221 if (amdgpu_ci_is_smc_running(adev)) {
2222 DRM_INFO("smc is running, no need to load smc firmware\n");
2226 for (i = 0; i < adev->usec_timeout; i++) {
2227 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2230 WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2232 amdgpu_ci_stop_smc_clock(adev);
2233 amdgpu_ci_reset_smc(adev);
2235 ret = amdgpu_ci_load_smc_ucode(adev, SMC_RAM_END);
2241 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2242 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2243 struct atom_voltage_table *voltage_table)
2247 if (voltage_dependency_table == NULL)
2250 voltage_table->mask_low = 0;
2251 voltage_table->phase_delay = 0;
2253 voltage_table->count = voltage_dependency_table->count;
2254 for (i = 0; i < voltage_table->count; i++) {
2255 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2256 voltage_table->entries[i].smio_low = 0;
2262 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2264 struct ci_power_info *pi = ci_get_pi(adev);
2267 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2268 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2269 VOLTAGE_OBJ_GPIO_LUT,
2270 &pi->vddc_voltage_table);
2273 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2274 ret = ci_get_svi2_voltage_table(adev,
2275 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2276 &pi->vddc_voltage_table);
2281 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2282 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2283 &pi->vddc_voltage_table);
2285 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2286 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2287 VOLTAGE_OBJ_GPIO_LUT,
2288 &pi->vddci_voltage_table);
2291 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2292 ret = ci_get_svi2_voltage_table(adev,
2293 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2294 &pi->vddci_voltage_table);
2299 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2300 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2301 &pi->vddci_voltage_table);
2303 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2304 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2305 VOLTAGE_OBJ_GPIO_LUT,
2306 &pi->mvdd_voltage_table);
2309 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2310 ret = ci_get_svi2_voltage_table(adev,
2311 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2312 &pi->mvdd_voltage_table);
2317 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2318 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2319 &pi->mvdd_voltage_table);
2324 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2325 struct atom_voltage_table_entry *voltage_table,
2326 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2330 ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2331 &smc_voltage_table->StdVoltageHiSidd,
2332 &smc_voltage_table->StdVoltageLoSidd);
2335 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2336 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2339 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2340 smc_voltage_table->StdVoltageHiSidd =
2341 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2342 smc_voltage_table->StdVoltageLoSidd =
2343 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2346 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2347 SMU7_Discrete_DpmTable *table)
2349 struct ci_power_info *pi = ci_get_pi(adev);
2352 table->VddcLevelCount = pi->vddc_voltage_table.count;
2353 for (count = 0; count < table->VddcLevelCount; count++) {
2354 ci_populate_smc_voltage_table(adev,
2355 &pi->vddc_voltage_table.entries[count],
2356 &table->VddcLevel[count]);
2358 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2359 table->VddcLevel[count].Smio |=
2360 pi->vddc_voltage_table.entries[count].smio_low;
2362 table->VddcLevel[count].Smio = 0;
2364 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2369 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2370 SMU7_Discrete_DpmTable *table)
2373 struct ci_power_info *pi = ci_get_pi(adev);
2375 table->VddciLevelCount = pi->vddci_voltage_table.count;
2376 for (count = 0; count < table->VddciLevelCount; count++) {
2377 ci_populate_smc_voltage_table(adev,
2378 &pi->vddci_voltage_table.entries[count],
2379 &table->VddciLevel[count]);
2381 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2382 table->VddciLevel[count].Smio |=
2383 pi->vddci_voltage_table.entries[count].smio_low;
2385 table->VddciLevel[count].Smio = 0;
2387 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2392 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2393 SMU7_Discrete_DpmTable *table)
2395 struct ci_power_info *pi = ci_get_pi(adev);
2398 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2399 for (count = 0; count < table->MvddLevelCount; count++) {
2400 ci_populate_smc_voltage_table(adev,
2401 &pi->mvdd_voltage_table.entries[count],
2402 &table->MvddLevel[count]);
2404 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2405 table->MvddLevel[count].Smio |=
2406 pi->mvdd_voltage_table.entries[count].smio_low;
2408 table->MvddLevel[count].Smio = 0;
2410 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2415 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2416 SMU7_Discrete_DpmTable *table)
2420 ret = ci_populate_smc_vddc_table(adev, table);
2424 ret = ci_populate_smc_vddci_table(adev, table);
2428 ret = ci_populate_smc_mvdd_table(adev, table);
2435 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2436 SMU7_Discrete_VoltageLevel *voltage)
2438 struct ci_power_info *pi = ci_get_pi(adev);
2441 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2442 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2443 if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2444 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2449 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2456 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2457 struct atom_voltage_table_entry *voltage_table,
2458 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2461 bool voltage_found = false;
2462 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2463 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2465 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2468 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2469 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2470 if (voltage_table->value ==
2471 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2472 voltage_found = true;
2473 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2476 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2477 *std_voltage_lo_sidd =
2478 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2479 *std_voltage_hi_sidd =
2480 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2485 if (!voltage_found) {
2486 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2487 if (voltage_table->value <=
2488 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2489 voltage_found = true;
2490 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2493 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2494 *std_voltage_lo_sidd =
2495 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2496 *std_voltage_hi_sidd =
2497 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2507 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2508 const struct amdgpu_phase_shedding_limits_table *limits,
2510 u32 *phase_shedding)
2514 *phase_shedding = 1;
2516 for (i = 0; i < limits->count; i++) {
2517 if (sclk < limits->entries[i].sclk) {
2518 *phase_shedding = i;
2524 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2525 const struct amdgpu_phase_shedding_limits_table *limits,
2527 u32 *phase_shedding)
2531 *phase_shedding = 1;
2533 for (i = 0; i < limits->count; i++) {
2534 if (mclk < limits->entries[i].mclk) {
2535 *phase_shedding = i;
2541 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2543 struct ci_power_info *pi = ci_get_pi(adev);
2547 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2548 &tmp, pi->sram_end);
2553 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2555 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2559 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2560 struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2561 u32 clock, u32 *voltage)
2565 if (allowed_clock_voltage_table->count == 0)
2568 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2569 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2570 *voltage = allowed_clock_voltage_table->entries[i].v;
2575 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2580 static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2584 u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2589 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2591 if (tmp >= min || i == 0)
2598 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2600 return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2603 static int ci_reset_to_default(struct amdgpu_device *adev)
2605 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2609 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2613 tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2615 if (tmp == MC_CG_ARB_FREQ_F0)
2618 return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2621 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2622 const u32 engine_clock,
2623 const u32 memory_clock,
2629 tmp = RREG32(mmMC_SEQ_MISC0);
2630 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2633 ((adev->pdev->device == 0x67B0) ||
2634 (adev->pdev->device == 0x67B1))) {
2635 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2636 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2637 *dram_timimg2 &= ~0x00ff0000;
2638 *dram_timimg2 |= tmp2 << 16;
2639 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2640 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2641 *dram_timimg2 &= ~0x00ff0000;
2642 *dram_timimg2 |= tmp2 << 16;
2647 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2650 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2656 amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2658 dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
2659 dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2660 burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2662 ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2664 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2665 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2666 arb_regs->McArbBurstTime = (u8)burst_time;
2671 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2673 struct ci_power_info *pi = ci_get_pi(adev);
2674 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2678 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2680 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2681 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2682 ret = ci_populate_memory_timing_parameters(adev,
2683 pi->dpm_table.sclk_table.dpm_levels[i].value,
2684 pi->dpm_table.mclk_table.dpm_levels[j].value,
2685 &arb_regs.entries[i][j]);
2692 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2693 pi->arb_table_start,
2695 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2701 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2703 struct ci_power_info *pi = ci_get_pi(adev);
2705 if (pi->need_update_smu7_dpm_table == 0)
2708 return ci_do_program_memory_timing_parameters(adev);
2711 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2712 struct amdgpu_ps *amdgpu_boot_state)
2714 struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2715 struct ci_power_info *pi = ci_get_pi(adev);
2718 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2719 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2720 boot_state->performance_levels[0].sclk) {
2721 pi->smc_state_table.GraphicsBootLevel = level;
2726 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2727 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2728 boot_state->performance_levels[0].mclk) {
2729 pi->smc_state_table.MemoryBootLevel = level;
2735 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2740 for (i = dpm_table->count; i > 0; i--) {
2741 mask_value = mask_value << 1;
2742 if (dpm_table->dpm_levels[i-1].enabled)
2745 mask_value &= 0xFFFFFFFE;
2751 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2752 SMU7_Discrete_DpmTable *table)
2754 struct ci_power_info *pi = ci_get_pi(adev);
2755 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2758 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2759 table->LinkLevel[i].PcieGenSpeed =
2760 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2761 table->LinkLevel[i].PcieLaneCount =
2762 amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2763 table->LinkLevel[i].EnabledForActivity = 1;
2764 table->LinkLevel[i].DownT = cpu_to_be32(5);
2765 table->LinkLevel[i].UpT = cpu_to_be32(30);
2768 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2769 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2770 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2773 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2774 SMU7_Discrete_DpmTable *table)
2777 struct atom_clock_dividers dividers;
2780 table->UvdLevelCount =
2781 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2783 for (count = 0; count < table->UvdLevelCount; count++) {
2784 table->UvdLevel[count].VclkFrequency =
2785 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2786 table->UvdLevel[count].DclkFrequency =
2787 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2788 table->UvdLevel[count].MinVddc =
2789 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2790 table->UvdLevel[count].MinVddcPhases = 1;
2792 ret = amdgpu_atombios_get_clock_dividers(adev,
2793 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2794 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2798 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2800 ret = amdgpu_atombios_get_clock_dividers(adev,
2801 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2802 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2806 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2808 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2809 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2810 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2816 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2817 SMU7_Discrete_DpmTable *table)
2820 struct atom_clock_dividers dividers;
2823 table->VceLevelCount =
2824 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2826 for (count = 0; count < table->VceLevelCount; count++) {
2827 table->VceLevel[count].Frequency =
2828 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2829 table->VceLevel[count].MinVoltage =
2830 (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2831 table->VceLevel[count].MinPhases = 1;
2833 ret = amdgpu_atombios_get_clock_dividers(adev,
2834 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2835 table->VceLevel[count].Frequency, false, ÷rs);
2839 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2841 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2842 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2849 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2850 SMU7_Discrete_DpmTable *table)
2853 struct atom_clock_dividers dividers;
2856 table->AcpLevelCount = (u8)
2857 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2859 for (count = 0; count < table->AcpLevelCount; count++) {
2860 table->AcpLevel[count].Frequency =
2861 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2862 table->AcpLevel[count].MinVoltage =
2863 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2864 table->AcpLevel[count].MinPhases = 1;
2866 ret = amdgpu_atombios_get_clock_dividers(adev,
2867 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2868 table->AcpLevel[count].Frequency, false, ÷rs);
2872 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2874 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2875 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2881 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2882 SMU7_Discrete_DpmTable *table)
2885 struct atom_clock_dividers dividers;
2888 table->SamuLevelCount =
2889 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2891 for (count = 0; count < table->SamuLevelCount; count++) {
2892 table->SamuLevel[count].Frequency =
2893 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2894 table->SamuLevel[count].MinVoltage =
2895 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2896 table->SamuLevel[count].MinPhases = 1;
2898 ret = amdgpu_atombios_get_clock_dividers(adev,
2899 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2900 table->SamuLevel[count].Frequency, false, ÷rs);
2904 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2906 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2907 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2913 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2915 SMU7_Discrete_MemoryLevel *mclk,
2919 struct ci_power_info *pi = ci_get_pi(adev);
2920 u32 dll_cntl = pi->clock_registers.dll_cntl;
2921 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2922 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2923 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2924 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2925 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2926 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2927 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2928 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2929 struct atom_mpll_param mpll_param;
2932 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2936 mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2937 mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2939 mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2940 MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2941 mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2942 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2943 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2945 mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2946 mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2948 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2949 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2950 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2951 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2952 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2955 if (pi->caps_mclk_ss_support) {
2956 struct amdgpu_atom_ss ss;
2959 u32 reference_clock = adev->clock.mpll.reference_freq;
2961 if (mpll_param.qdr == 1)
2962 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2964 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2966 tmp = (freq_nom / reference_clock);
2968 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2969 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2970 u32 clks = reference_clock * 5 / ss.rate;
2971 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2973 mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2974 mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2976 mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2977 mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2981 mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2982 mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2985 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2986 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2988 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2989 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2991 mclk->MclkFrequency = memory_clock;
2992 mclk->MpllFuncCntl = mpll_func_cntl;
2993 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2994 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2995 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2996 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2997 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2998 mclk->DllCntl = dll_cntl;
2999 mclk->MpllSs1 = mpll_ss1;
3000 mclk->MpllSs2 = mpll_ss2;
3005 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
3007 SMU7_Discrete_MemoryLevel *memory_level)
3009 struct ci_power_info *pi = ci_get_pi(adev);
3013 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
3014 ret = ci_get_dependency_volt_by_clk(adev,
3015 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3016 memory_clock, &memory_level->MinVddc);
3021 if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
3022 ret = ci_get_dependency_volt_by_clk(adev,
3023 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3024 memory_clock, &memory_level->MinVddci);
3029 if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3030 ret = ci_get_dependency_volt_by_clk(adev,
3031 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3032 memory_clock, &memory_level->MinMvdd);
3037 memory_level->MinVddcPhases = 1;
3039 if (pi->vddc_phase_shed_control)
3040 ci_populate_phase_value_based_on_mclk(adev,
3041 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3043 &memory_level->MinVddcPhases);
3045 memory_level->EnabledForActivity = 1;
3046 memory_level->EnabledForThrottle = 1;
3047 memory_level->UpH = 0;
3048 memory_level->DownH = 100;
3049 memory_level->VoltageDownH = 0;
3050 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3052 memory_level->StutterEnable = false;
3053 memory_level->StrobeEnable = false;
3054 memory_level->EdcReadEnable = false;
3055 memory_level->EdcWriteEnable = false;
3056 memory_level->RttEnable = false;
3058 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3060 if (pi->mclk_stutter_mode_threshold &&
3061 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3062 (!pi->uvd_enabled) &&
3063 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3064 (adev->pm.dpm.new_active_crtc_count <= 2))
3065 memory_level->StutterEnable = true;
3067 if (pi->mclk_strobe_mode_threshold &&
3068 (memory_clock <= pi->mclk_strobe_mode_threshold))
3069 memory_level->StrobeEnable = 1;
3071 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3072 memory_level->StrobeRatio =
3073 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3074 if (pi->mclk_edc_enable_threshold &&
3075 (memory_clock > pi->mclk_edc_enable_threshold))
3076 memory_level->EdcReadEnable = true;
3078 if (pi->mclk_edc_wr_enable_threshold &&
3079 (memory_clock > pi->mclk_edc_wr_enable_threshold))
3080 memory_level->EdcWriteEnable = true;
3082 if (memory_level->StrobeEnable) {
3083 if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3084 ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3085 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3087 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3089 dll_state_on = pi->dll_default_on;
3092 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3093 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3096 ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3100 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3101 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3102 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3103 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3105 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3106 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3107 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3108 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3109 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3110 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3111 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3112 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3113 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3114 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3115 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3120 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3121 SMU7_Discrete_DpmTable *table)
3123 struct ci_power_info *pi = ci_get_pi(adev);
3124 struct atom_clock_dividers dividers;
3125 SMU7_Discrete_VoltageLevel voltage_level;
3126 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3127 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3128 u32 dll_cntl = pi->clock_registers.dll_cntl;
3129 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3132 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3135 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3137 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3139 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3141 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3143 ret = amdgpu_atombios_get_clock_dividers(adev,
3144 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3145 table->ACPILevel.SclkFrequency, false, ÷rs);
3149 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3150 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3151 table->ACPILevel.DeepSleepDivId = 0;
3153 spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3154 spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3156 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3157 spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3159 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3160 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3161 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3162 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3163 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3164 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3165 table->ACPILevel.CcPwrDynRm = 0;
3166 table->ACPILevel.CcPwrDynRm1 = 0;
3168 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3169 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3170 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3171 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3172 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3173 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3174 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3175 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3176 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3177 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3178 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3180 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3181 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3183 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3185 table->MemoryACPILevel.MinVddci =
3186 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3188 table->MemoryACPILevel.MinVddci =
3189 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3192 if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3193 table->MemoryACPILevel.MinMvdd = 0;
3195 table->MemoryACPILevel.MinMvdd =
3196 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3198 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3199 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3200 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3201 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3203 dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3205 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3206 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3207 table->MemoryACPILevel.MpllAdFuncCntl =
3208 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3209 table->MemoryACPILevel.MpllDqFuncCntl =
3210 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3211 table->MemoryACPILevel.MpllFuncCntl =
3212 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3213 table->MemoryACPILevel.MpllFuncCntl_1 =
3214 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3215 table->MemoryACPILevel.MpllFuncCntl_2 =
3216 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3217 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3218 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3220 table->MemoryACPILevel.EnabledForThrottle = 0;
3221 table->MemoryACPILevel.EnabledForActivity = 0;
3222 table->MemoryACPILevel.UpH = 0;
3223 table->MemoryACPILevel.DownH = 100;
3224 table->MemoryACPILevel.VoltageDownH = 0;
3225 table->MemoryACPILevel.ActivityLevel =
3226 cpu_to_be16((u16)pi->mclk_activity_target);
3228 table->MemoryACPILevel.StutterEnable = false;
3229 table->MemoryACPILevel.StrobeEnable = false;
3230 table->MemoryACPILevel.EdcReadEnable = false;
3231 table->MemoryACPILevel.EdcWriteEnable = false;
3232 table->MemoryACPILevel.RttEnable = false;
3238 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3240 struct ci_power_info *pi = ci_get_pi(adev);
3241 struct ci_ulv_parm *ulv = &pi->ulv;
3243 if (ulv->supported) {
3245 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3248 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3255 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3256 SMU7_Discrete_Ulv *state)
3258 struct ci_power_info *pi = ci_get_pi(adev);
3259 u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3261 state->CcPwrDynRm = 0;
3262 state->CcPwrDynRm1 = 0;
3264 if (ulv_voltage == 0) {
3265 pi->ulv.supported = false;
3269 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3270 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3271 state->VddcOffset = 0;
3274 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3276 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3277 state->VddcOffsetVid = 0;
3279 state->VddcOffsetVid = (u8)
3280 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3281 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3283 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3285 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3286 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3287 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3292 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3294 SMU7_Discrete_GraphicsLevel *sclk)
3296 struct ci_power_info *pi = ci_get_pi(adev);
3297 struct atom_clock_dividers dividers;
3298 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3299 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3300 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3301 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3302 u32 reference_clock = adev->clock.spll.reference_freq;
3303 u32 reference_divider;
3307 ret = amdgpu_atombios_get_clock_dividers(adev,
3308 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3309 engine_clock, false, ÷rs);
3313 reference_divider = 1 + dividers.ref_div;
3314 fbdiv = dividers.fb_div & 0x3FFFFFF;
3316 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3317 spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3318 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3320 if (pi->caps_sclk_ss_support) {
3321 struct amdgpu_atom_ss ss;
3322 u32 vco_freq = engine_clock * dividers.post_div;
3324 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3325 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3326 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3327 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3329 cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3330 cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3331 cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3333 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3334 cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3338 sclk->SclkFrequency = engine_clock;
3339 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3340 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3341 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3342 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3343 sclk->SclkDid = (u8)dividers.post_divider;
3348 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3350 u16 sclk_activity_level_t,
3351 SMU7_Discrete_GraphicsLevel *graphic_level)
3353 struct ci_power_info *pi = ci_get_pi(adev);
3356 ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3360 ret = ci_get_dependency_volt_by_clk(adev,
3361 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3362 engine_clock, &graphic_level->MinVddc);
3366 graphic_level->SclkFrequency = engine_clock;
3368 graphic_level->Flags = 0;
3369 graphic_level->MinVddcPhases = 1;
3371 if (pi->vddc_phase_shed_control)
3372 ci_populate_phase_value_based_on_sclk(adev,
3373 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3375 &graphic_level->MinVddcPhases);
3377 graphic_level->ActivityLevel = sclk_activity_level_t;
3379 graphic_level->CcPwrDynRm = 0;
3380 graphic_level->CcPwrDynRm1 = 0;
3381 graphic_level->EnabledForThrottle = 1;
3382 graphic_level->UpH = 0;
3383 graphic_level->DownH = 0;
3384 graphic_level->VoltageDownH = 0;
3385 graphic_level->PowerThrottle = 0;
3387 if (pi->caps_sclk_ds)
3388 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
3389 CISLAND_MINIMUM_ENGINE_CLOCK);
3391 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3393 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3394 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3395 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3396 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3397 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3398 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3399 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3400 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3401 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3402 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3403 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3408 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3410 struct ci_power_info *pi = ci_get_pi(adev);
3411 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3412 u32 level_array_address = pi->dpm_table_start +
3413 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3414 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3415 SMU7_MAX_LEVELS_GRAPHICS;
3416 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3419 memset(levels, 0, level_array_size);
3421 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3422 ret = ci_populate_single_graphic_level(adev,
3423 dpm_table->sclk_table.dpm_levels[i].value,
3424 (u16)pi->activity_target[i],
3425 &pi->smc_state_table.GraphicsLevel[i]);
3429 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3430 if (i == (dpm_table->sclk_table.count - 1))
3431 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3432 PPSMC_DISPLAY_WATERMARK_HIGH;
3434 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3436 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3437 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3438 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3440 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3441 (u8 *)levels, level_array_size,
3449 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3450 SMU7_Discrete_Ulv *ulv_level)
3452 return ci_populate_ulv_level(adev, ulv_level);
3455 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3457 struct ci_power_info *pi = ci_get_pi(adev);
3458 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3459 u32 level_array_address = pi->dpm_table_start +
3460 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3461 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3462 SMU7_MAX_LEVELS_MEMORY;
3463 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3466 memset(levels, 0, level_array_size);
3468 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3469 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3471 ret = ci_populate_single_memory_level(adev,
3472 dpm_table->mclk_table.dpm_levels[i].value,
3473 &pi->smc_state_table.MemoryLevel[i]);
3478 if ((dpm_table->mclk_table.count >= 2) &&
3479 ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3480 pi->smc_state_table.MemoryLevel[1].MinVddc =
3481 pi->smc_state_table.MemoryLevel[0].MinVddc;
3482 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3483 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3486 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3488 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3489 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3490 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3492 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3493 PPSMC_DISPLAY_WATERMARK_HIGH;
3495 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3496 (u8 *)levels, level_array_size,
3504 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3505 struct ci_single_dpm_table* dpm_table,
3510 dpm_table->count = count;
3511 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3512 dpm_table->dpm_levels[i].enabled = false;
3515 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3516 u32 index, u32 pcie_gen, u32 pcie_lanes)
3518 dpm_table->dpm_levels[index].value = pcie_gen;
3519 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3520 dpm_table->dpm_levels[index].enabled = true;
3523 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3525 struct ci_power_info *pi = ci_get_pi(adev);
3527 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3530 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3531 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3532 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3533 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3534 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3535 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3538 ci_reset_single_dpm_table(adev,
3539 &pi->dpm_table.pcie_speed_table,
3540 SMU7_MAX_LEVELS_LINK);
3542 if (adev->asic_type == CHIP_BONAIRE)
3543 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3544 pi->pcie_gen_powersaving.min,
3545 pi->pcie_lane_powersaving.max);
3547 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3548 pi->pcie_gen_powersaving.min,
3549 pi->pcie_lane_powersaving.min);
3550 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3551 pi->pcie_gen_performance.min,
3552 pi->pcie_lane_performance.min);
3553 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3554 pi->pcie_gen_powersaving.min,
3555 pi->pcie_lane_powersaving.max);
3556 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3557 pi->pcie_gen_performance.min,
3558 pi->pcie_lane_performance.max);
3559 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3560 pi->pcie_gen_powersaving.max,
3561 pi->pcie_lane_powersaving.max);
3562 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3563 pi->pcie_gen_performance.max,
3564 pi->pcie_lane_performance.max);
3566 pi->dpm_table.pcie_speed_table.count = 6;
3571 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3573 struct ci_power_info *pi = ci_get_pi(adev);
3574 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3575 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3576 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3577 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3578 struct amdgpu_cac_leakage_table *std_voltage_table =
3579 &adev->pm.dpm.dyn_state.cac_leakage_table;
3582 if (allowed_sclk_vddc_table == NULL)
3584 if (allowed_sclk_vddc_table->count < 1)
3586 if (allowed_mclk_table == NULL)
3588 if (allowed_mclk_table->count < 1)
3591 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3593 ci_reset_single_dpm_table(adev,
3594 &pi->dpm_table.sclk_table,
3595 SMU7_MAX_LEVELS_GRAPHICS);
3596 ci_reset_single_dpm_table(adev,
3597 &pi->dpm_table.mclk_table,
3598 SMU7_MAX_LEVELS_MEMORY);
3599 ci_reset_single_dpm_table(adev,
3600 &pi->dpm_table.vddc_table,
3601 SMU7_MAX_LEVELS_VDDC);
3602 ci_reset_single_dpm_table(adev,
3603 &pi->dpm_table.vddci_table,
3604 SMU7_MAX_LEVELS_VDDCI);
3605 ci_reset_single_dpm_table(adev,
3606 &pi->dpm_table.mvdd_table,
3607 SMU7_MAX_LEVELS_MVDD);
3609 pi->dpm_table.sclk_table.count = 0;
3610 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3612 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3613 allowed_sclk_vddc_table->entries[i].clk)) {
3614 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3615 allowed_sclk_vddc_table->entries[i].clk;
3616 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3617 (i == 0) ? true : false;
3618 pi->dpm_table.sclk_table.count++;
3622 pi->dpm_table.mclk_table.count = 0;
3623 for (i = 0; i < allowed_mclk_table->count; i++) {
3625 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3626 allowed_mclk_table->entries[i].clk)) {
3627 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3628 allowed_mclk_table->entries[i].clk;
3629 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3630 (i == 0) ? true : false;
3631 pi->dpm_table.mclk_table.count++;
3635 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3636 pi->dpm_table.vddc_table.dpm_levels[i].value =
3637 allowed_sclk_vddc_table->entries[i].v;
3638 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3639 std_voltage_table->entries[i].leakage;
3640 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3642 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3644 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3645 if (allowed_mclk_table) {
3646 for (i = 0; i < allowed_mclk_table->count; i++) {
3647 pi->dpm_table.vddci_table.dpm_levels[i].value =
3648 allowed_mclk_table->entries[i].v;
3649 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3651 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3654 allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3655 if (allowed_mclk_table) {
3656 for (i = 0; i < allowed_mclk_table->count; i++) {
3657 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3658 allowed_mclk_table->entries[i].v;
3659 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3661 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3664 ci_setup_default_pcie_tables(adev);
3666 /* save a copy of the default DPM table */
3667 memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),
3668 sizeof(struct ci_dpm_table));
3673 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3674 u32 value, u32 *boot_level)
3679 for(i = 0; i < table->count; i++) {
3680 if (value == table->dpm_levels[i].value) {
3689 static void ci_save_default_power_profile(struct amdgpu_device *adev)
3691 struct ci_power_info *pi = ci_get_pi(adev);
3692 struct SMU7_Discrete_GraphicsLevel *levels =
3693 pi->smc_state_table.GraphicsLevel;
3694 uint32_t min_level = 0;
3696 pi->default_gfx_power_profile.activity_threshold =
3697 be16_to_cpu(levels[0].ActivityLevel);
3698 pi->default_gfx_power_profile.up_hyst = levels[0].UpH;
3699 pi->default_gfx_power_profile.down_hyst = levels[0].DownH;
3700 pi->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
3702 pi->default_compute_power_profile = pi->default_gfx_power_profile;
3703 pi->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
3705 /* Optimize compute power profile: Use only highest
3706 * 2 power levels (if more than 2 are available), Hysteresis:
3709 if (pi->smc_state_table.GraphicsDpmLevelCount > 2)
3710 min_level = pi->smc_state_table.GraphicsDpmLevelCount - 2;
3711 else if (pi->smc_state_table.GraphicsDpmLevelCount == 2)
3713 pi->default_compute_power_profile.min_sclk =
3714 be32_to_cpu(levels[min_level].SclkFrequency);
3716 pi->default_compute_power_profile.up_hyst = 0;
3717 pi->default_compute_power_profile.down_hyst = 5;
3719 pi->gfx_power_profile = pi->default_gfx_power_profile;
3720 pi->compute_power_profile = pi->default_compute_power_profile;
3723 static int ci_init_smc_table(struct amdgpu_device *adev)
3725 struct ci_power_info *pi = ci_get_pi(adev);
3726 struct ci_ulv_parm *ulv = &pi->ulv;
3727 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3728 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3731 ret = ci_setup_default_dpm_tables(adev);
3735 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3736 ci_populate_smc_voltage_tables(adev, table);
3738 ci_init_fps_limits(adev);
3740 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3741 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3743 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3744 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3746 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3747 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3749 if (ulv->supported) {
3750 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3753 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3756 ret = ci_populate_all_graphic_levels(adev);
3760 ret = ci_populate_all_memory_levels(adev);
3764 ci_populate_smc_link_level(adev, table);
3766 ret = ci_populate_smc_acpi_level(adev, table);
3770 ret = ci_populate_smc_vce_level(adev, table);
3774 ret = ci_populate_smc_acp_level(adev, table);
3778 ret = ci_populate_smc_samu_level(adev, table);
3782 ret = ci_do_program_memory_timing_parameters(adev);
3786 ret = ci_populate_smc_uvd_level(adev, table);
3790 table->UvdBootLevel = 0;
3791 table->VceBootLevel = 0;
3792 table->AcpBootLevel = 0;
3793 table->SamuBootLevel = 0;
3794 table->GraphicsBootLevel = 0;
3795 table->MemoryBootLevel = 0;
3797 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3798 pi->vbios_boot_state.sclk_bootup_value,
3799 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3801 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3802 pi->vbios_boot_state.mclk_bootup_value,
3803 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3805 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3806 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3807 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3809 ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3811 ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3815 table->UVDInterval = 1;
3816 table->VCEInterval = 1;
3817 table->ACPInterval = 1;
3818 table->SAMUInterval = 1;
3819 table->GraphicsVoltageChangeEnable = 1;
3820 table->GraphicsThermThrottleEnable = 1;
3821 table->GraphicsInterval = 1;
3822 table->VoltageInterval = 1;
3823 table->ThermalInterval = 1;
3824 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3825 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3826 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3827 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3828 table->MemoryVoltageChangeEnable = 1;
3829 table->MemoryInterval = 1;
3830 table->VoltageResponseTime = 0;
3831 table->VddcVddciDelta = 4000;
3832 table->PhaseResponseTime = 0;
3833 table->MemoryThermThrottleEnable = 1;
3834 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3835 table->PCIeGenInterval = 1;
3836 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3837 table->SVI2Enable = 1;
3839 table->SVI2Enable = 0;
3841 table->ThermGpio = 17;
3842 table->SclkStepSize = 0x4000;
3844 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3845 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3846 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3847 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3848 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3849 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3850 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3851 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3852 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3853 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3854 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3855 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3856 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3857 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3859 ret = amdgpu_ci_copy_bytes_to_smc(adev,
3860 pi->dpm_table_start +
3861 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3862 (u8 *)&table->SystemFlags,
3863 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3868 ci_save_default_power_profile(adev);
3873 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3874 struct ci_single_dpm_table *dpm_table,
3875 u32 low_limit, u32 high_limit)
3879 for (i = 0; i < dpm_table->count; i++) {
3880 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3881 (dpm_table->dpm_levels[i].value > high_limit))
3882 dpm_table->dpm_levels[i].enabled = false;
3884 dpm_table->dpm_levels[i].enabled = true;
3888 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3889 u32 speed_low, u32 lanes_low,
3890 u32 speed_high, u32 lanes_high)
3892 struct ci_power_info *pi = ci_get_pi(adev);
3893 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3896 for (i = 0; i < pcie_table->count; i++) {
3897 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3898 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3899 (pcie_table->dpm_levels[i].value > speed_high) ||
3900 (pcie_table->dpm_levels[i].param1 > lanes_high))
3901 pcie_table->dpm_levels[i].enabled = false;
3903 pcie_table->dpm_levels[i].enabled = true;
3906 for (i = 0; i < pcie_table->count; i++) {
3907 if (pcie_table->dpm_levels[i].enabled) {
3908 for (j = i + 1; j < pcie_table->count; j++) {
3909 if (pcie_table->dpm_levels[j].enabled) {
3910 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3911 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3912 pcie_table->dpm_levels[j].enabled = false;
3919 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3920 struct amdgpu_ps *amdgpu_state)
3922 struct ci_ps *state = ci_get_ps(amdgpu_state);
3923 struct ci_power_info *pi = ci_get_pi(adev);
3924 u32 high_limit_count;
3926 if (state->performance_level_count < 1)
3929 if (state->performance_level_count == 1)
3930 high_limit_count = 0;
3932 high_limit_count = 1;
3934 ci_trim_single_dpm_states(adev,
3935 &pi->dpm_table.sclk_table,
3936 state->performance_levels[0].sclk,
3937 state->performance_levels[high_limit_count].sclk);
3939 ci_trim_single_dpm_states(adev,
3940 &pi->dpm_table.mclk_table,
3941 state->performance_levels[0].mclk,
3942 state->performance_levels[high_limit_count].mclk);
3944 ci_trim_pcie_dpm_states(adev,
3945 state->performance_levels[0].pcie_gen,
3946 state->performance_levels[0].pcie_lane,
3947 state->performance_levels[high_limit_count].pcie_gen,
3948 state->performance_levels[high_limit_count].pcie_lane);
3953 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3955 struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3956 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3957 struct amdgpu_clock_voltage_dependency_table *vddc_table =
3958 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3959 u32 requested_voltage = 0;
3962 if (disp_voltage_table == NULL)
3964 if (!disp_voltage_table->count)
3967 for (i = 0; i < disp_voltage_table->count; i++) {
3968 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3969 requested_voltage = disp_voltage_table->entries[i].v;
3972 for (i = 0; i < vddc_table->count; i++) {
3973 if (requested_voltage <= vddc_table->entries[i].v) {
3974 requested_voltage = vddc_table->entries[i].v;
3975 return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3976 PPSMC_MSG_VddC_Request,
3977 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3985 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3987 struct ci_power_info *pi = ci_get_pi(adev);
3988 PPSMC_Result result;
3990 ci_apply_disp_minimum_voltage_request(adev);
3992 if (!pi->sclk_dpm_key_disabled) {
3993 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3994 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3995 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3996 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3997 if (result != PPSMC_Result_OK)
4002 if (!pi->mclk_dpm_key_disabled) {
4003 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4004 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4005 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4006 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4007 if (result != PPSMC_Result_OK)
4013 if (!pi->pcie_dpm_key_disabled) {
4014 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4015 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4016 PPSMC_MSG_PCIeDPM_SetEnabledMask,
4017 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4018 if (result != PPSMC_Result_OK)
4027 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
4028 struct amdgpu_ps *amdgpu_state)
4030 struct ci_power_info *pi = ci_get_pi(adev);
4031 struct ci_ps *state = ci_get_ps(amdgpu_state);
4032 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
4033 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4034 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
4035 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4038 pi->need_update_smu7_dpm_table = 0;
4040 for (i = 0; i < sclk_table->count; i++) {
4041 if (sclk == sclk_table->dpm_levels[i].value)
4045 if (i >= sclk_table->count) {
4046 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4048 /* XXX check display min clock requirements */
4049 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
4050 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4053 for (i = 0; i < mclk_table->count; i++) {
4054 if (mclk == mclk_table->dpm_levels[i].value)
4058 if (i >= mclk_table->count)
4059 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4061 if (adev->pm.dpm.current_active_crtc_count !=
4062 adev->pm.dpm.new_active_crtc_count)
4063 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4066 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4067 struct amdgpu_ps *amdgpu_state)
4069 struct ci_power_info *pi = ci_get_pi(adev);
4070 struct ci_ps *state = ci_get_ps(amdgpu_state);
4071 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4072 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4073 struct ci_dpm_table *dpm_table = &pi->dpm_table;
4076 if (!pi->need_update_smu7_dpm_table)
4079 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4080 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4082 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4083 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4085 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4086 ret = ci_populate_all_graphic_levels(adev);
4091 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4092 ret = ci_populate_all_memory_levels(adev);
4100 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4102 struct ci_power_info *pi = ci_get_pi(adev);
4103 const struct amdgpu_clock_and_voltage_limits *max_limits;
4106 if (adev->pm.dpm.ac_power)
4107 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4109 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4112 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4114 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4115 if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4116 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4118 if (!pi->caps_uvd_dpm)
4123 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4124 PPSMC_MSG_UVDDPM_SetEnabledMask,
4125 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4127 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4128 pi->uvd_enabled = true;
4129 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4130 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4131 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4132 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4135 if (pi->uvd_enabled) {
4136 pi->uvd_enabled = false;
4137 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4138 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4139 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4140 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4144 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4145 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4149 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4151 struct ci_power_info *pi = ci_get_pi(adev);
4152 const struct amdgpu_clock_and_voltage_limits *max_limits;
4155 if (adev->pm.dpm.ac_power)
4156 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4158 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4161 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4162 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4163 if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4164 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4166 if (!pi->caps_vce_dpm)
4171 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4172 PPSMC_MSG_VCEDPM_SetEnabledMask,
4173 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4176 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4177 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4182 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4184 struct ci_power_info *pi = ci_get_pi(adev);
4185 const struct amdgpu_clock_and_voltage_limits *max_limits;
4188 if (adev->pm.dpm.ac_power)
4189 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4191 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4194 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4195 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4196 if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4197 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4199 if (!pi->caps_samu_dpm)
4204 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4205 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4206 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4208 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4209 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4213 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4215 struct ci_power_info *pi = ci_get_pi(adev);
4216 const struct amdgpu_clock_and_voltage_limits *max_limits;
4219 if (adev->pm.dpm.ac_power)
4220 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4222 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4225 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4226 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4227 if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4228 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4230 if (!pi->caps_acp_dpm)
4235 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4236 PPSMC_MSG_ACPDPM_SetEnabledMask,
4237 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4240 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4241 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4246 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4248 struct ci_power_info *pi = ci_get_pi(adev);
4253 /* turn the clocks on when decoding */
4254 if (pi->caps_uvd_dpm ||
4255 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4256 pi->smc_state_table.UvdBootLevel = 0;
4258 pi->smc_state_table.UvdBootLevel =
4259 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4261 tmp = RREG32_SMC(ixDPM_TABLE_475);
4262 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4263 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4264 WREG32_SMC(ixDPM_TABLE_475, tmp);
4265 ret = ci_enable_uvd_dpm(adev, true);
4267 ret = ci_enable_uvd_dpm(adev, false);
4275 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4278 u32 min_evclk = 30000; /* ??? */
4279 struct amdgpu_vce_clock_voltage_dependency_table *table =
4280 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4282 for (i = 0; i < table->count; i++) {
4283 if (table->entries[i].evclk >= min_evclk)
4287 return table->count - 1;
4290 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4291 struct amdgpu_ps *amdgpu_new_state,
4292 struct amdgpu_ps *amdgpu_current_state)
4294 struct ci_power_info *pi = ci_get_pi(adev);
4298 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4299 if (amdgpu_new_state->evclk) {
4300 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4301 tmp = RREG32_SMC(ixDPM_TABLE_475);
4302 tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4303 tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4304 WREG32_SMC(ixDPM_TABLE_475, tmp);
4306 ret = ci_enable_vce_dpm(adev, true);
4308 ret = ci_enable_vce_dpm(adev, false);
4317 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4319 return ci_enable_samu_dpm(adev, gate);
4322 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4324 struct ci_power_info *pi = ci_get_pi(adev);
4328 pi->smc_state_table.AcpBootLevel = 0;
4330 tmp = RREG32_SMC(ixDPM_TABLE_475);
4331 tmp &= ~AcpBootLevel_MASK;
4332 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4333 WREG32_SMC(ixDPM_TABLE_475, tmp);
4336 return ci_enable_acp_dpm(adev, !gate);
4340 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4341 struct amdgpu_ps *amdgpu_state)
4343 struct ci_power_info *pi = ci_get_pi(adev);
4346 ret = ci_trim_dpm_states(adev, amdgpu_state);
4350 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4351 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4352 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4353 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4354 pi->last_mclk_dpm_enable_mask =
4355 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4356 if (pi->uvd_enabled) {
4357 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4358 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4360 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4361 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4366 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4371 while ((level_mask & (1 << level)) == 0)
4378 static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4379 enum amd_dpm_forced_level level)
4381 struct ci_power_info *pi = ci_get_pi(adev);
4385 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
4386 if ((!pi->pcie_dpm_key_disabled) &&
4387 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4389 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4393 ret = ci_dpm_force_state_pcie(adev, level);
4396 for (i = 0; i < adev->usec_timeout; i++) {
4397 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4398 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4399 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4406 if ((!pi->sclk_dpm_key_disabled) &&
4407 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4409 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4413 ret = ci_dpm_force_state_sclk(adev, levels);
4416 for (i = 0; i < adev->usec_timeout; i++) {
4417 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4418 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4419 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4426 if ((!pi->mclk_dpm_key_disabled) &&
4427 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4429 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4433 ret = ci_dpm_force_state_mclk(adev, levels);
4436 for (i = 0; i < adev->usec_timeout; i++) {
4437 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4438 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4439 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4446 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
4447 if ((!pi->sclk_dpm_key_disabled) &&
4448 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4449 levels = ci_get_lowest_enabled_level(adev,
4450 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4451 ret = ci_dpm_force_state_sclk(adev, levels);
4454 for (i = 0; i < adev->usec_timeout; i++) {
4455 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4456 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4457 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4463 if ((!pi->mclk_dpm_key_disabled) &&
4464 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4465 levels = ci_get_lowest_enabled_level(adev,
4466 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4467 ret = ci_dpm_force_state_mclk(adev, levels);
4470 for (i = 0; i < adev->usec_timeout; i++) {
4471 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4472 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4473 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4479 if ((!pi->pcie_dpm_key_disabled) &&
4480 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4481 levels = ci_get_lowest_enabled_level(adev,
4482 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4483 ret = ci_dpm_force_state_pcie(adev, levels);
4486 for (i = 0; i < adev->usec_timeout; i++) {
4487 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4488 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4489 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4495 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
4496 if (!pi->pcie_dpm_key_disabled) {
4497 PPSMC_Result smc_result;
4499 smc_result = amdgpu_ci_send_msg_to_smc(adev,
4500 PPSMC_MSG_PCIeDPM_UnForceLevel);
4501 if (smc_result != PPSMC_Result_OK)
4504 ret = ci_upload_dpm_level_enable_mask(adev);
4509 adev->pm.dpm.forced_level = level;
4514 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4515 struct ci_mc_reg_table *table)
4520 for (i = 0, j = table->last; i < table->last; i++) {
4521 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4523 switch(table->mc_reg_address[i].s1) {
4524 case mmMC_SEQ_MISC1:
4525 temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4526 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4527 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4528 for (k = 0; k < table->num_entries; k++) {
4529 table->mc_reg_table_entry[k].mc_data[j] =
4530 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4533 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4536 temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4537 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4538 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4539 for (k = 0; k < table->num_entries; k++) {
4540 table->mc_reg_table_entry[k].mc_data[j] =
4541 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4542 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4543 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4546 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4549 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4550 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4551 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4552 for (k = 0; k < table->num_entries; k++) {
4553 table->mc_reg_table_entry[k].mc_data[j] =
4554 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4557 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4561 case mmMC_SEQ_RESERVE_M:
4562 temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4563 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4564 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4565 for (k = 0; k < table->num_entries; k++) {
4566 table->mc_reg_table_entry[k].mc_data[j] =
4567 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4570 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4584 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4589 case mmMC_SEQ_RAS_TIMING:
4590 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4592 case mmMC_SEQ_DLL_STBY:
4593 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4595 case mmMC_SEQ_G5PDX_CMD0:
4596 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4598 case mmMC_SEQ_G5PDX_CMD1:
4599 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4601 case mmMC_SEQ_G5PDX_CTRL:
4602 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4604 case mmMC_SEQ_CAS_TIMING:
4605 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4607 case mmMC_SEQ_MISC_TIMING:
4608 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4610 case mmMC_SEQ_MISC_TIMING2:
4611 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4613 case mmMC_SEQ_PMG_DVS_CMD:
4614 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4616 case mmMC_SEQ_PMG_DVS_CTL:
4617 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4619 case mmMC_SEQ_RD_CTL_D0:
4620 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4622 case mmMC_SEQ_RD_CTL_D1:
4623 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4625 case mmMC_SEQ_WR_CTL_D0:
4626 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4628 case mmMC_SEQ_WR_CTL_D1:
4629 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4631 case mmMC_PMG_CMD_EMRS:
4632 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4634 case mmMC_PMG_CMD_MRS:
4635 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4637 case mmMC_PMG_CMD_MRS1:
4638 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4640 case mmMC_SEQ_PMG_TIMING:
4641 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4643 case mmMC_PMG_CMD_MRS2:
4644 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4646 case mmMC_SEQ_WR_CTL_2:
4647 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4657 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4661 for (i = 0; i < table->last; i++) {
4662 for (j = 1; j < table->num_entries; j++) {
4663 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4664 table->mc_reg_table_entry[j].mc_data[i]) {
4665 table->valid_flag |= 1 << i;
4672 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4677 for (i = 0; i < table->last; i++) {
4678 table->mc_reg_address[i].s0 =
4679 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4680 address : table->mc_reg_address[i].s1;
4684 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4685 struct ci_mc_reg_table *ci_table)
4689 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4691 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4694 for (i = 0; i < table->last; i++)
4695 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4697 ci_table->last = table->last;
4699 for (i = 0; i < table->num_entries; i++) {
4700 ci_table->mc_reg_table_entry[i].mclk_max =
4701 table->mc_reg_table_entry[i].mclk_max;
4702 for (j = 0; j < table->last; j++)
4703 ci_table->mc_reg_table_entry[i].mc_data[j] =
4704 table->mc_reg_table_entry[i].mc_data[j];
4706 ci_table->num_entries = table->num_entries;
4711 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4712 struct ci_mc_reg_table *table)
4718 tmp = RREG32(mmMC_SEQ_MISC0);
4719 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4722 ((adev->pdev->device == 0x67B0) ||
4723 (adev->pdev->device == 0x67B1))) {
4724 for (i = 0; i < table->last; i++) {
4725 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4727 switch (table->mc_reg_address[i].s1) {
4728 case mmMC_SEQ_MISC1:
4729 for (k = 0; k < table->num_entries; k++) {
4730 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4731 (table->mc_reg_table_entry[k].mclk_max == 137500))
4732 table->mc_reg_table_entry[k].mc_data[i] =
4733 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4737 case mmMC_SEQ_WR_CTL_D0:
4738 for (k = 0; k < table->num_entries; k++) {
4739 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4740 (table->mc_reg_table_entry[k].mclk_max == 137500))
4741 table->mc_reg_table_entry[k].mc_data[i] =
4742 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4746 case mmMC_SEQ_WR_CTL_D1:
4747 for (k = 0; k < table->num_entries; k++) {
4748 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4749 (table->mc_reg_table_entry[k].mclk_max == 137500))
4750 table->mc_reg_table_entry[k].mc_data[i] =
4751 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4755 case mmMC_SEQ_WR_CTL_2:
4756 for (k = 0; k < table->num_entries; k++) {
4757 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4758 (table->mc_reg_table_entry[k].mclk_max == 137500))
4759 table->mc_reg_table_entry[k].mc_data[i] = 0;
4762 case mmMC_SEQ_CAS_TIMING:
4763 for (k = 0; k < table->num_entries; k++) {
4764 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4765 table->mc_reg_table_entry[k].mc_data[i] =
4766 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4768 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4769 table->mc_reg_table_entry[k].mc_data[i] =
4770 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4774 case mmMC_SEQ_MISC_TIMING:
4775 for (k = 0; k < table->num_entries; k++) {
4776 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4777 table->mc_reg_table_entry[k].mc_data[i] =
4778 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4780 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4781 table->mc_reg_table_entry[k].mc_data[i] =
4782 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4791 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4792 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4793 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4794 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4795 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4801 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4803 struct ci_power_info *pi = ci_get_pi(adev);
4804 struct atom_mc_reg_table *table;
4805 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4806 u8 module_index = ci_get_memory_module_index(adev);
4809 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4813 WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4814 WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4815 WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4816 WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4817 WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4818 WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4819 WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4820 WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4821 WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4822 WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4823 WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4824 WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4825 WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4826 WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4827 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4828 WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4829 WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4830 WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4831 WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4832 WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4834 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4838 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4842 ci_set_s0_mc_reg_index(ci_table);
4844 ret = ci_register_patching_mc_seq(adev, ci_table);
4848 ret = ci_set_mc_special_registers(adev, ci_table);
4852 ci_set_valid_flag(ci_table);
4860 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4861 SMU7_Discrete_MCRegisters *mc_reg_table)
4863 struct ci_power_info *pi = ci_get_pi(adev);
4866 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4867 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4868 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4870 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4871 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4876 mc_reg_table->last = (u8)i;
4881 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4882 SMU7_Discrete_MCRegisterSet *data,
4883 u32 num_entries, u32 valid_flag)
4887 for (i = 0, j = 0; j < num_entries; j++) {
4888 if (valid_flag & (1 << j)) {
4889 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4895 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4896 const u32 memory_clock,
4897 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4899 struct ci_power_info *pi = ci_get_pi(adev);
4902 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4903 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4907 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4910 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4911 mc_reg_table_data, pi->mc_reg_table.last,
4912 pi->mc_reg_table.valid_flag);
4915 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4916 SMU7_Discrete_MCRegisters *mc_reg_table)
4918 struct ci_power_info *pi = ci_get_pi(adev);
4921 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4922 ci_convert_mc_reg_table_entry_to_smc(adev,
4923 pi->dpm_table.mclk_table.dpm_levels[i].value,
4924 &mc_reg_table->data[i]);
4927 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4929 struct ci_power_info *pi = ci_get_pi(adev);
4932 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4934 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4937 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4939 return amdgpu_ci_copy_bytes_to_smc(adev,
4940 pi->mc_reg_table_start,
4941 (u8 *)&pi->smc_mc_reg_table,
4942 sizeof(SMU7_Discrete_MCRegisters),
4946 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4948 struct ci_power_info *pi = ci_get_pi(adev);
4950 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4953 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4955 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4957 return amdgpu_ci_copy_bytes_to_smc(adev,
4958 pi->mc_reg_table_start +
4959 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4960 (u8 *)&pi->smc_mc_reg_table.data[0],
4961 sizeof(SMU7_Discrete_MCRegisterSet) *
4962 pi->dpm_table.mclk_table.count,
4966 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4968 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4970 tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4971 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4974 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4975 struct amdgpu_ps *amdgpu_state)
4977 struct ci_ps *state = ci_get_ps(amdgpu_state);
4979 u16 pcie_speed, max_speed = 0;
4981 for (i = 0; i < state->performance_level_count; i++) {
4982 pcie_speed = state->performance_levels[i].pcie_gen;
4983 if (max_speed < pcie_speed)
4984 max_speed = pcie_speed;
4990 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4994 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4995 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4996 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4998 return (u16)speed_cntl;
5001 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
5005 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
5006 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
5007 link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
5009 switch (link_width) {
5025 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
5026 struct amdgpu_ps *amdgpu_new_state,
5027 struct amdgpu_ps *amdgpu_current_state)
5029 struct ci_power_info *pi = ci_get_pi(adev);
5030 enum amdgpu_pcie_gen target_link_speed =
5031 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5032 enum amdgpu_pcie_gen current_link_speed;
5034 if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
5035 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
5037 current_link_speed = pi->force_pcie_gen;
5039 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5040 pi->pspp_notify_required = false;
5041 if (target_link_speed > current_link_speed) {
5042 switch (target_link_speed) {
5044 case AMDGPU_PCIE_GEN3:
5045 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5047 pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
5048 if (current_link_speed == AMDGPU_PCIE_GEN2)
5050 case AMDGPU_PCIE_GEN2:
5051 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5055 pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
5059 if (target_link_speed < current_link_speed)
5060 pi->pspp_notify_required = true;
5064 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5065 struct amdgpu_ps *amdgpu_new_state,
5066 struct amdgpu_ps *amdgpu_current_state)
5068 struct ci_power_info *pi = ci_get_pi(adev);
5069 enum amdgpu_pcie_gen target_link_speed =
5070 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5073 if (pi->pspp_notify_required) {
5074 if (target_link_speed == AMDGPU_PCIE_GEN3)
5075 request = PCIE_PERF_REQ_PECI_GEN3;
5076 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5077 request = PCIE_PERF_REQ_PECI_GEN2;
5079 request = PCIE_PERF_REQ_PECI_GEN1;
5081 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5082 (ci_get_current_pcie_speed(adev) > 0))
5086 amdgpu_acpi_pcie_performance_request(adev, request, false);
5091 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5093 struct ci_power_info *pi = ci_get_pi(adev);
5094 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5095 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5096 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5097 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5098 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5099 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5101 if (allowed_sclk_vddc_table == NULL)
5103 if (allowed_sclk_vddc_table->count < 1)
5105 if (allowed_mclk_vddc_table == NULL)
5107 if (allowed_mclk_vddc_table->count < 1)
5109 if (allowed_mclk_vddci_table == NULL)
5111 if (allowed_mclk_vddci_table->count < 1)
5114 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5115 pi->max_vddc_in_pp_table =
5116 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5118 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5119 pi->max_vddci_in_pp_table =
5120 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5122 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5123 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5124 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5125 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5126 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5127 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5128 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5129 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5134 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5136 struct ci_power_info *pi = ci_get_pi(adev);
5137 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5140 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5141 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5142 *vddc = leakage_table->actual_voltage[leakage_index];
5148 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5150 struct ci_power_info *pi = ci_get_pi(adev);
5151 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5154 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5155 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5156 *vddci = leakage_table->actual_voltage[leakage_index];
5162 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5163 struct amdgpu_clock_voltage_dependency_table *table)
5168 for (i = 0; i < table->count; i++)
5169 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5173 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5174 struct amdgpu_clock_voltage_dependency_table *table)
5179 for (i = 0; i < table->count; i++)
5180 ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5184 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5185 struct amdgpu_vce_clock_voltage_dependency_table *table)
5190 for (i = 0; i < table->count; i++)
5191 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5195 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5196 struct amdgpu_uvd_clock_voltage_dependency_table *table)
5201 for (i = 0; i < table->count; i++)
5202 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5206 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5207 struct amdgpu_phase_shedding_limits_table *table)
5212 for (i = 0; i < table->count; i++)
5213 ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5217 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5218 struct amdgpu_clock_and_voltage_limits *table)
5221 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5222 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5226 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5227 struct amdgpu_cac_leakage_table *table)
5232 for (i = 0; i < table->count; i++)
5233 ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5237 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5240 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5241 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5242 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5243 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5244 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5245 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5246 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5247 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5248 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5249 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5250 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5251 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5252 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5253 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5254 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5255 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5256 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5257 &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5258 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5259 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5260 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5261 &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5262 ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5263 &adev->pm.dpm.dyn_state.cac_leakage_table);
5267 static void ci_update_current_ps(struct amdgpu_device *adev,
5268 struct amdgpu_ps *rps)
5270 struct ci_ps *new_ps = ci_get_ps(rps);
5271 struct ci_power_info *pi = ci_get_pi(adev);
5273 pi->current_rps = *rps;
5274 pi->current_ps = *new_ps;
5275 pi->current_rps.ps_priv = &pi->current_ps;
5276 adev->pm.dpm.current_ps = &pi->current_rps;
5279 static void ci_update_requested_ps(struct amdgpu_device *adev,
5280 struct amdgpu_ps *rps)
5282 struct ci_ps *new_ps = ci_get_ps(rps);
5283 struct ci_power_info *pi = ci_get_pi(adev);
5285 pi->requested_rps = *rps;
5286 pi->requested_ps = *new_ps;
5287 pi->requested_rps.ps_priv = &pi->requested_ps;
5288 adev->pm.dpm.requested_ps = &pi->requested_rps;
5291 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5293 struct ci_power_info *pi = ci_get_pi(adev);
5294 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5295 struct amdgpu_ps *new_ps = &requested_ps;
5297 ci_update_requested_ps(adev, new_ps);
5299 ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5304 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5306 struct ci_power_info *pi = ci_get_pi(adev);
5307 struct amdgpu_ps *new_ps = &pi->requested_rps;
5309 ci_update_current_ps(adev, new_ps);
5313 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5315 ci_read_clock_registers(adev);
5316 ci_enable_acpi_power_management(adev);
5317 ci_init_sclk_t(adev);
5320 static int ci_dpm_enable(struct amdgpu_device *adev)
5322 struct ci_power_info *pi = ci_get_pi(adev);
5323 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5326 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5327 ci_enable_voltage_control(adev);
5328 ret = ci_construct_voltage_tables(adev);
5330 DRM_ERROR("ci_construct_voltage_tables failed\n");
5334 if (pi->caps_dynamic_ac_timing) {
5335 ret = ci_initialize_mc_reg_table(adev);
5337 pi->caps_dynamic_ac_timing = false;
5340 ci_enable_spread_spectrum(adev, true);
5341 if (pi->thermal_protection)
5342 ci_enable_thermal_protection(adev, true);
5343 ci_program_sstp(adev);
5344 ci_enable_display_gap(adev);
5345 ci_program_vc(adev);
5346 ret = ci_upload_firmware(adev);
5348 DRM_ERROR("ci_upload_firmware failed\n");
5351 ret = ci_process_firmware_header(adev);
5353 DRM_ERROR("ci_process_firmware_header failed\n");
5356 ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5358 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5361 ret = ci_init_smc_table(adev);
5363 DRM_ERROR("ci_init_smc_table failed\n");
5366 ret = ci_init_arb_table_index(adev);
5368 DRM_ERROR("ci_init_arb_table_index failed\n");
5371 if (pi->caps_dynamic_ac_timing) {
5372 ret = ci_populate_initial_mc_reg_table(adev);
5374 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5378 ret = ci_populate_pm_base(adev);
5380 DRM_ERROR("ci_populate_pm_base failed\n");
5383 ci_dpm_start_smc(adev);
5384 ci_enable_vr_hot_gpio_interrupt(adev);
5385 ret = ci_notify_smc_display_change(adev, false);
5387 DRM_ERROR("ci_notify_smc_display_change failed\n");
5390 ci_enable_sclk_control(adev, true);
5391 ret = ci_enable_ulv(adev, true);
5393 DRM_ERROR("ci_enable_ulv failed\n");
5396 ret = ci_enable_ds_master_switch(adev, true);
5398 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5401 ret = ci_start_dpm(adev);
5403 DRM_ERROR("ci_start_dpm failed\n");
5406 ret = ci_enable_didt(adev, true);
5408 DRM_ERROR("ci_enable_didt failed\n");
5411 ret = ci_enable_smc_cac(adev, true);
5413 DRM_ERROR("ci_enable_smc_cac failed\n");
5416 ret = ci_enable_power_containment(adev, true);
5418 DRM_ERROR("ci_enable_power_containment failed\n");
5422 ret = ci_power_control_set_level(adev);
5424 DRM_ERROR("ci_power_control_set_level failed\n");
5428 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5430 ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5432 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5436 ci_thermal_start_thermal_controller(adev);
5438 ci_update_current_ps(adev, boot_ps);
5443 static void ci_dpm_disable(struct amdgpu_device *adev)
5445 struct ci_power_info *pi = ci_get_pi(adev);
5446 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5448 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5449 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5450 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5451 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5453 ci_dpm_powergate_uvd(adev, true);
5455 if (!amdgpu_ci_is_smc_running(adev))
5458 ci_thermal_stop_thermal_controller(adev);
5460 if (pi->thermal_protection)
5461 ci_enable_thermal_protection(adev, false);
5462 ci_enable_power_containment(adev, false);
5463 ci_enable_smc_cac(adev, false);
5464 ci_enable_didt(adev, false);
5465 ci_enable_spread_spectrum(adev, false);
5466 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5468 ci_enable_ds_master_switch(adev, false);
5469 ci_enable_ulv(adev, false);
5471 ci_reset_to_default(adev);
5472 ci_dpm_stop_smc(adev);
5473 ci_force_switch_to_arb_f0(adev);
5474 ci_enable_thermal_based_sclk_dpm(adev, false);
5476 ci_update_current_ps(adev, boot_ps);
5479 static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5481 struct ci_power_info *pi = ci_get_pi(adev);
5482 struct amdgpu_ps *new_ps = &pi->requested_rps;
5483 struct amdgpu_ps *old_ps = &pi->current_rps;
5486 ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5487 if (pi->pcie_performance_request)
5488 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5489 ret = ci_freeze_sclk_mclk_dpm(adev);
5491 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5494 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5496 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5499 ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5501 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5505 ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5507 DRM_ERROR("ci_update_vce_dpm failed\n");
5511 ret = ci_update_sclk_t(adev);
5513 DRM_ERROR("ci_update_sclk_t failed\n");
5516 if (pi->caps_dynamic_ac_timing) {
5517 ret = ci_update_and_upload_mc_reg_table(adev);
5519 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5523 ret = ci_program_memory_timing_parameters(adev);
5525 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5528 ret = ci_unfreeze_sclk_mclk_dpm(adev);
5530 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5533 ret = ci_upload_dpm_level_enable_mask(adev);
5535 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5538 if (pi->pcie_performance_request)
5539 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5545 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5547 ci_set_boot_state(adev);
5551 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5553 ci_program_display_gap(adev);
5557 struct _ATOM_POWERPLAY_INFO info;
5558 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5559 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5560 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5561 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5562 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5565 union pplib_clock_info {
5566 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5567 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5568 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5569 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5570 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5571 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5574 union pplib_power_state {
5575 struct _ATOM_PPLIB_STATE v1;
5576 struct _ATOM_PPLIB_STATE_V2 v2;
5579 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5580 struct amdgpu_ps *rps,
5581 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5584 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5585 rps->class = le16_to_cpu(non_clock_info->usClassification);
5586 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5588 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5589 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5590 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5596 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5597 adev->pm.dpm.boot_ps = rps;
5598 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5599 adev->pm.dpm.uvd_ps = rps;
5602 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5603 struct amdgpu_ps *rps, int index,
5604 union pplib_clock_info *clock_info)
5606 struct ci_power_info *pi = ci_get_pi(adev);
5607 struct ci_ps *ps = ci_get_ps(rps);
5608 struct ci_pl *pl = &ps->performance_levels[index];
5610 ps->performance_level_count = index + 1;
5612 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5613 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5614 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5615 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5617 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5619 pi->vbios_boot_state.pcie_gen_bootup_value,
5620 clock_info->ci.ucPCIEGen);
5621 pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5622 pi->vbios_boot_state.pcie_lane_bootup_value,
5623 le16_to_cpu(clock_info->ci.usPCIELane));
5625 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5626 pi->acpi_pcie_gen = pl->pcie_gen;
5629 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5630 pi->ulv.supported = true;
5632 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5635 /* patch up boot state */
5636 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5637 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5638 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5639 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5640 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5643 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5644 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5645 pi->use_pcie_powersaving_levels = true;
5646 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5647 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5648 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5649 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5650 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5651 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5652 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5653 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5655 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5656 pi->use_pcie_performance_levels = true;
5657 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5658 pi->pcie_gen_performance.max = pl->pcie_gen;
5659 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5660 pi->pcie_gen_performance.min = pl->pcie_gen;
5661 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5662 pi->pcie_lane_performance.max = pl->pcie_lane;
5663 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5664 pi->pcie_lane_performance.min = pl->pcie_lane;
5671 static int ci_parse_power_table(struct amdgpu_device *adev)
5673 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5674 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5675 union pplib_power_state *power_state;
5676 int i, j, k, non_clock_array_index, clock_array_index;
5677 union pplib_clock_info *clock_info;
5678 struct _StateArray *state_array;
5679 struct _ClockInfoArray *clock_info_array;
5680 struct _NonClockInfoArray *non_clock_info_array;
5681 union power_info *power_info;
5682 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5685 u8 *power_state_offset;
5688 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5689 &frev, &crev, &data_offset))
5691 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5693 amdgpu_add_thermal_controller(adev);
5695 state_array = (struct _StateArray *)
5696 (mode_info->atom_context->bios + data_offset +
5697 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5698 clock_info_array = (struct _ClockInfoArray *)
5699 (mode_info->atom_context->bios + data_offset +
5700 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5701 non_clock_info_array = (struct _NonClockInfoArray *)
5702 (mode_info->atom_context->bios + data_offset +
5703 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5705 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5706 state_array->ucNumEntries, GFP_KERNEL);
5707 if (!adev->pm.dpm.ps)
5709 power_state_offset = (u8 *)state_array->states;
5710 for (i = 0; i < state_array->ucNumEntries; i++) {
5712 power_state = (union pplib_power_state *)power_state_offset;
5713 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5714 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5715 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5716 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5718 kfree(adev->pm.dpm.ps);
5721 adev->pm.dpm.ps[i].ps_priv = ps;
5722 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5724 non_clock_info_array->ucEntrySize);
5726 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5727 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5728 clock_array_index = idx[j];
5729 if (clock_array_index >= clock_info_array->ucNumEntries)
5731 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5733 clock_info = (union pplib_clock_info *)
5734 ((u8 *)&clock_info_array->clockInfo[0] +
5735 (clock_array_index * clock_info_array->ucEntrySize));
5736 ci_parse_pplib_clock_info(adev,
5737 &adev->pm.dpm.ps[i], k,
5741 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5743 adev->pm.dpm.num_ps = state_array->ucNumEntries;
5745 /* fill in the vce power states */
5746 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
5748 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5749 clock_info = (union pplib_clock_info *)
5750 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5751 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5752 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5753 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5754 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5755 adev->pm.dpm.vce_states[i].sclk = sclk;
5756 adev->pm.dpm.vce_states[i].mclk = mclk;
5762 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5763 struct ci_vbios_boot_state *boot_state)
5765 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5766 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5767 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5771 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5772 &frev, &crev, &data_offset)) {
5774 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5776 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5777 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5778 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5779 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5780 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5781 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5782 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5789 static void ci_dpm_fini(struct amdgpu_device *adev)
5793 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5794 kfree(adev->pm.dpm.ps[i].ps_priv);
5796 kfree(adev->pm.dpm.ps);
5797 kfree(adev->pm.dpm.priv);
5798 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5799 amdgpu_free_extended_power_table(adev);
5803 * ci_dpm_init_microcode - load ucode images from disk
5805 * @adev: amdgpu_device pointer
5807 * Use the firmware interface to load the ucode images into
5808 * the driver (not loaded into hw).
5809 * Returns 0 on success, error on failure.
5811 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5813 const char *chip_name;
5819 switch (adev->asic_type) {
5821 if ((adev->pdev->revision == 0x80) ||
5822 (adev->pdev->revision == 0x81) ||
5823 (adev->pdev->device == 0x665f))
5824 chip_name = "bonaire_k";
5826 chip_name = "bonaire";
5829 if (adev->pdev->revision == 0x80)
5830 chip_name = "hawaii_k";
5832 chip_name = "hawaii";
5840 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
5841 err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
5844 err = amdgpu_ucode_validate(adev->pm.fw);
5848 pr_err("cik_smc: Failed to load firmware \"%s\"\n", fw_name);
5849 release_firmware(adev->pm.fw);
5855 static int ci_dpm_init(struct amdgpu_device *adev)
5857 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5858 SMU7_Discrete_DpmTable *dpm_table;
5859 struct amdgpu_gpio_rec gpio;
5860 u16 data_offset, size;
5862 struct ci_power_info *pi;
5865 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5868 adev->pm.dpm.priv = pi;
5871 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5872 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5874 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5876 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5877 pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5878 pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5879 pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5881 pi->pcie_lane_performance.max = 0;
5882 pi->pcie_lane_performance.min = 16;
5883 pi->pcie_lane_powersaving.max = 0;
5884 pi->pcie_lane_powersaving.min = 16;
5886 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5892 ret = amdgpu_get_platform_caps(adev);
5898 ret = amdgpu_parse_extended_power_table(adev);
5904 ret = ci_parse_power_table(adev);
5910 pi->dll_default_on = false;
5911 pi->sram_end = SMC_RAM_END;
5913 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5914 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5915 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5916 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5917 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5918 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5919 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5920 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5922 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5924 pi->sclk_dpm_key_disabled = 0;
5925 pi->mclk_dpm_key_disabled = 0;
5926 pi->pcie_dpm_key_disabled = 0;
5927 pi->thermal_sclk_dpm_enabled = 0;
5929 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
5930 pi->caps_sclk_ds = true;
5932 pi->caps_sclk_ds = false;
5934 pi->mclk_strobe_mode_threshold = 40000;
5935 pi->mclk_stutter_mode_threshold = 40000;
5936 pi->mclk_edc_enable_threshold = 40000;
5937 pi->mclk_edc_wr_enable_threshold = 40000;
5939 ci_initialize_powertune_defaults(adev);
5941 pi->caps_fps = false;
5943 pi->caps_sclk_throttle_low_notification = false;
5945 pi->caps_uvd_dpm = true;
5946 pi->caps_vce_dpm = true;
5948 ci_get_leakage_voltages(adev);
5949 ci_patch_dependency_tables_with_leakage(adev);
5950 ci_set_private_data_variables_based_on_pptable(adev);
5952 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5953 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5954 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5958 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5959 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5960 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5961 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5962 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5963 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5964 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5965 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5966 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5968 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5969 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5970 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5972 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5973 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5974 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5975 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5977 if (adev->asic_type == CHIP_HAWAII) {
5978 pi->thermal_temp_setting.temperature_low = 94500;
5979 pi->thermal_temp_setting.temperature_high = 95000;
5980 pi->thermal_temp_setting.temperature_shutdown = 104000;
5982 pi->thermal_temp_setting.temperature_low = 99500;
5983 pi->thermal_temp_setting.temperature_high = 100000;
5984 pi->thermal_temp_setting.temperature_shutdown = 104000;
5987 pi->uvd_enabled = false;
5989 dpm_table = &pi->smc_state_table;
5991 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5993 dpm_table->VRHotGpio = gpio.shift;
5994 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5996 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5997 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
6000 gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
6002 dpm_table->AcDcGpio = gpio.shift;
6003 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
6005 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
6006 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
6009 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
6011 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
6013 switch (gpio.shift) {
6015 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
6016 tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
6019 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
6020 tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
6023 tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
6026 tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
6029 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
6032 DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift);
6035 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
6038 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6039 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6040 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6041 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
6042 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6043 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
6044 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6046 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
6047 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
6048 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6049 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
6050 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6052 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
6055 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
6056 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
6057 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6058 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
6059 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6061 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
6064 pi->vddc_phase_shed_control = true;
6066 #if defined(CONFIG_ACPI)
6067 pi->pcie_performance_request =
6068 amdgpu_acpi_is_pcie_performance_request_supported(adev);
6070 pi->pcie_performance_request = false;
6073 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6074 &frev, &crev, &data_offset)) {
6075 pi->caps_sclk_ss_support = true;
6076 pi->caps_mclk_ss_support = true;
6077 pi->dynamic_ss = true;
6079 pi->caps_sclk_ss_support = false;
6080 pi->caps_mclk_ss_support = false;
6081 pi->dynamic_ss = true;
6084 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6085 pi->thermal_protection = true;
6087 pi->thermal_protection = false;
6089 pi->caps_dynamic_ac_timing = true;
6091 pi->uvd_power_gated = true;
6093 /* make sure dc limits are valid */
6094 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6095 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6096 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6097 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6099 pi->fan_ctrl_is_in_default_mode = true;
6105 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6108 struct ci_power_info *pi = ci_get_pi(adev);
6109 struct amdgpu_ps *rps = &pi->current_rps;
6110 u32 sclk = ci_get_average_sclk_freq(adev);
6111 u32 mclk = ci_get_average_mclk_freq(adev);
6112 u32 activity_percent = 50;
6115 ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6119 activity_percent += 0x80;
6120 activity_percent >>= 8;
6121 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6124 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
6125 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6126 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
6128 seq_printf(m, "GPU load: %u %%\n", activity_percent);
6131 static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6132 struct amdgpu_ps *rps)
6134 struct ci_ps *ps = ci_get_ps(rps);
6138 amdgpu_dpm_print_class_info(rps->class, rps->class2);
6139 amdgpu_dpm_print_cap_info(rps->caps);
6140 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6141 for (i = 0; i < ps->performance_level_count; i++) {
6142 pl = &ps->performance_levels[i];
6143 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6144 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6146 amdgpu_dpm_print_ps_status(adev, rps);
6149 static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1,
6150 const struct ci_pl *ci_cpl2)
6152 return ((ci_cpl1->mclk == ci_cpl2->mclk) &&
6153 (ci_cpl1->sclk == ci_cpl2->sclk) &&
6154 (ci_cpl1->pcie_gen == ci_cpl2->pcie_gen) &&
6155 (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));
6158 static int ci_check_state_equal(struct amdgpu_device *adev,
6159 struct amdgpu_ps *cps,
6160 struct amdgpu_ps *rps,
6163 struct ci_ps *ci_cps;
6164 struct ci_ps *ci_rps;
6167 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
6170 ci_cps = ci_get_ps(cps);
6171 ci_rps = ci_get_ps(rps);
6173 if (ci_cps == NULL) {
6178 if (ci_cps->performance_level_count != ci_rps->performance_level_count) {
6184 for (i = 0; i < ci_cps->performance_level_count; i++) {
6185 if (!ci_are_power_levels_equal(&(ci_cps->performance_levels[i]),
6186 &(ci_rps->performance_levels[i]))) {
6192 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6193 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
6194 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
6199 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6201 struct ci_power_info *pi = ci_get_pi(adev);
6202 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6205 return requested_state->performance_levels[0].sclk;
6207 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6210 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6212 struct ci_power_info *pi = ci_get_pi(adev);
6213 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6216 return requested_state->performance_levels[0].mclk;
6218 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6221 /* get temperature in millidegrees */
6222 static int ci_dpm_get_temp(struct amdgpu_device *adev)
6225 int actual_temp = 0;
6227 temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6228 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6233 actual_temp = temp & 0x1ff;
6235 actual_temp = actual_temp * 1000;
6240 static int ci_set_temperature_range(struct amdgpu_device *adev)
6244 ret = ci_thermal_enable_alert(adev, false);
6247 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6248 CISLANDS_TEMP_RANGE_MAX);
6251 ret = ci_thermal_enable_alert(adev, true);
6257 static int ci_dpm_early_init(void *handle)
6259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6261 ci_dpm_set_dpm_funcs(adev);
6262 ci_dpm_set_irq_funcs(adev);
6267 static int ci_dpm_late_init(void *handle)
6270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6275 /* init the sysfs and debugfs files late */
6276 ret = amdgpu_pm_sysfs_init(adev);
6280 ret = ci_set_temperature_range(adev);
6287 static int ci_dpm_sw_init(void *handle)
6290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6292 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
6293 &adev->pm.dpm.thermal.irq);
6297 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
6298 &adev->pm.dpm.thermal.irq);
6302 /* default to balanced state */
6303 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6304 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6305 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
6306 adev->pm.default_sclk = adev->clock.default_sclk;
6307 adev->pm.default_mclk = adev->clock.default_mclk;
6308 adev->pm.current_sclk = adev->clock.default_sclk;
6309 adev->pm.current_mclk = adev->clock.default_mclk;
6310 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6312 ret = ci_dpm_init_microcode(adev);
6316 if (amdgpu_dpm == 0)
6319 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6320 mutex_lock(&adev->pm.mutex);
6321 ret = ci_dpm_init(adev);
6324 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6325 if (amdgpu_dpm == 1)
6326 amdgpu_pm_print_power_states(adev);
6327 mutex_unlock(&adev->pm.mutex);
6328 DRM_INFO("amdgpu: dpm initialized\n");
6334 mutex_unlock(&adev->pm.mutex);
6335 DRM_ERROR("amdgpu: dpm initialization failed\n");
6339 static int ci_dpm_sw_fini(void *handle)
6341 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6343 flush_work(&adev->pm.dpm.thermal.work);
6345 mutex_lock(&adev->pm.mutex);
6346 amdgpu_pm_sysfs_fini(adev);
6348 mutex_unlock(&adev->pm.mutex);
6350 release_firmware(adev->pm.fw);
6356 static int ci_dpm_hw_init(void *handle)
6360 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6363 ret = ci_upload_firmware(adev);
6365 DRM_ERROR("ci_upload_firmware failed\n");
6368 ci_dpm_start_smc(adev);
6372 mutex_lock(&adev->pm.mutex);
6373 ci_dpm_setup_asic(adev);
6374 ret = ci_dpm_enable(adev);
6376 adev->pm.dpm_enabled = false;
6378 adev->pm.dpm_enabled = true;
6379 mutex_unlock(&adev->pm.mutex);
6384 static int ci_dpm_hw_fini(void *handle)
6386 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6388 if (adev->pm.dpm_enabled) {
6389 mutex_lock(&adev->pm.mutex);
6390 ci_dpm_disable(adev);
6391 mutex_unlock(&adev->pm.mutex);
6393 ci_dpm_stop_smc(adev);
6399 static int ci_dpm_suspend(void *handle)
6401 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6403 if (adev->pm.dpm_enabled) {
6404 mutex_lock(&adev->pm.mutex);
6405 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
6406 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
6407 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
6408 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
6409 adev->pm.dpm.last_user_state = adev->pm.dpm.user_state;
6410 adev->pm.dpm.last_state = adev->pm.dpm.state;
6411 adev->pm.dpm.user_state = POWER_STATE_TYPE_INTERNAL_BOOT;
6412 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_BOOT;
6413 mutex_unlock(&adev->pm.mutex);
6414 amdgpu_pm_compute_clocks(adev);
6421 static int ci_dpm_resume(void *handle)
6424 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6426 if (adev->pm.dpm_enabled) {
6427 /* asic init will reset to the boot state */
6428 mutex_lock(&adev->pm.mutex);
6429 ci_dpm_setup_asic(adev);
6430 ret = ci_dpm_enable(adev);
6432 adev->pm.dpm_enabled = false;
6434 adev->pm.dpm_enabled = true;
6435 adev->pm.dpm.user_state = adev->pm.dpm.last_user_state;
6436 adev->pm.dpm.state = adev->pm.dpm.last_state;
6437 mutex_unlock(&adev->pm.mutex);
6438 if (adev->pm.dpm_enabled)
6439 amdgpu_pm_compute_clocks(adev);
6444 static bool ci_dpm_is_idle(void *handle)
6450 static int ci_dpm_wait_for_idle(void *handle)
6456 static int ci_dpm_soft_reset(void *handle)
6461 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6462 struct amdgpu_irq_src *source,
6464 enum amdgpu_interrupt_state state)
6469 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6471 case AMDGPU_IRQ_STATE_DISABLE:
6472 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6473 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6474 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6476 case AMDGPU_IRQ_STATE_ENABLE:
6477 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6478 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6479 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6486 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6488 case AMDGPU_IRQ_STATE_DISABLE:
6489 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6490 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6491 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6493 case AMDGPU_IRQ_STATE_ENABLE:
6494 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6495 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6496 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6509 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6510 struct amdgpu_irq_src *source,
6511 struct amdgpu_iv_entry *entry)
6513 bool queue_thermal = false;
6518 switch (entry->src_id) {
6519 case 230: /* thermal low to high */
6520 DRM_DEBUG("IH: thermal low to high\n");
6521 adev->pm.dpm.thermal.high_to_low = false;
6522 queue_thermal = true;
6524 case 231: /* thermal high to low */
6525 DRM_DEBUG("IH: thermal high to low\n");
6526 adev->pm.dpm.thermal.high_to_low = true;
6527 queue_thermal = true;
6534 schedule_work(&adev->pm.dpm.thermal.work);
6539 static int ci_dpm_set_clockgating_state(void *handle,
6540 enum amd_clockgating_state state)
6545 static int ci_dpm_set_powergating_state(void *handle,
6546 enum amd_powergating_state state)
6551 static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
6552 enum pp_clock_type type, char *buf)
6554 struct ci_power_info *pi = ci_get_pi(adev);
6555 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
6556 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
6557 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
6559 int i, now, size = 0;
6560 uint32_t clock, pcie_speed;
6564 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
6565 clock = RREG32(mmSMC_MSG_ARG_0);
6567 for (i = 0; i < sclk_table->count; i++) {
6568 if (clock > sclk_table->dpm_levels[i].value)
6574 for (i = 0; i < sclk_table->count; i++)
6575 size += sprintf(buf + size, "%d: %uMhz %s\n",
6576 i, sclk_table->dpm_levels[i].value / 100,
6577 (i == now) ? "*" : "");
6580 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
6581 clock = RREG32(mmSMC_MSG_ARG_0);
6583 for (i = 0; i < mclk_table->count; i++) {
6584 if (clock > mclk_table->dpm_levels[i].value)
6590 for (i = 0; i < mclk_table->count; i++)
6591 size += sprintf(buf + size, "%d: %uMhz %s\n",
6592 i, mclk_table->dpm_levels[i].value / 100,
6593 (i == now) ? "*" : "");
6596 pcie_speed = ci_get_current_pcie_speed(adev);
6597 for (i = 0; i < pcie_table->count; i++) {
6598 if (pcie_speed != pcie_table->dpm_levels[i].value)
6604 for (i = 0; i < pcie_table->count; i++)
6605 size += sprintf(buf + size, "%d: %s %s\n", i,
6606 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
6607 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6608 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6609 (i == now) ? "*" : "");
6618 static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
6619 enum pp_clock_type type, uint32_t mask)
6621 struct ci_power_info *pi = ci_get_pi(adev);
6623 if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |
6624 AMD_DPM_FORCED_LEVEL_LOW |
6625 AMD_DPM_FORCED_LEVEL_HIGH))
6630 if (!pi->sclk_dpm_key_disabled)
6631 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6632 PPSMC_MSG_SCLKDPM_SetEnabledMask,
6633 pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
6637 if (!pi->mclk_dpm_key_disabled)
6638 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6639 PPSMC_MSG_MCLKDPM_SetEnabledMask,
6640 pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
6645 uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
6651 if (!pi->pcie_dpm_key_disabled)
6652 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
6653 PPSMC_MSG_PCIeDPM_ForceLevel,
6664 static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
6666 struct ci_power_info *pi = ci_get_pi(adev);
6667 struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
6668 struct ci_single_dpm_table *golden_sclk_table =
6669 &(pi->golden_dpm_table.sclk_table);
6672 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
6673 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
6675 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6680 static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
6682 struct ci_power_info *pi = ci_get_pi(adev);
6683 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6684 struct ci_single_dpm_table *golden_sclk_table =
6685 &(pi->golden_dpm_table.sclk_table);
6690 ps->performance_levels[ps->performance_level_count - 1].sclk =
6691 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
6693 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6698 static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
6700 struct ci_power_info *pi = ci_get_pi(adev);
6701 struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
6702 struct ci_single_dpm_table *golden_mclk_table =
6703 &(pi->golden_dpm_table.mclk_table);
6706 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
6707 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
6709 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6714 static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
6716 struct ci_power_info *pi = ci_get_pi(adev);
6717 struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
6718 struct ci_single_dpm_table *golden_mclk_table =
6719 &(pi->golden_dpm_table.mclk_table);
6724 ps->performance_levels[ps->performance_level_count - 1].mclk =
6725 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
6727 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6732 static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev,
6733 struct amd_pp_profile *query)
6735 struct ci_power_info *pi = ci_get_pi(adev);
6740 if (query->type == AMD_PP_GFX_PROFILE)
6741 memcpy(query, &pi->gfx_power_profile,
6742 sizeof(struct amd_pp_profile));
6743 else if (query->type == AMD_PP_COMPUTE_PROFILE)
6744 memcpy(query, &pi->compute_power_profile,
6745 sizeof(struct amd_pp_profile));
6752 static int ci_populate_requested_graphic_levels(struct amdgpu_device *adev,
6753 struct amd_pp_profile *request)
6755 struct ci_power_info *pi = ci_get_pi(adev);
6756 struct ci_dpm_table *dpm_table = &(pi->dpm_table);
6757 struct SMU7_Discrete_GraphicsLevel *levels =
6758 pi->smc_state_table.GraphicsLevel;
6759 uint32_t array = pi->dpm_table_start +
6760 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
6761 uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
6762 SMU7_MAX_LEVELS_GRAPHICS;
6765 for (i = 0; i < dpm_table->sclk_table.count; i++) {
6766 levels[i].ActivityLevel =
6767 cpu_to_be16(request->activity_threshold);
6768 levels[i].EnabledForActivity = 1;
6769 levels[i].UpH = request->up_hyst;
6770 levels[i].DownH = request->down_hyst;
6773 return amdgpu_ci_copy_bytes_to_smc(adev, array, (uint8_t *)levels,
6774 array_size, pi->sram_end);
6777 static void ci_find_min_clock_masks(struct amdgpu_device *adev,
6778 uint32_t *sclk_mask, uint32_t *mclk_mask,
6779 uint32_t min_sclk, uint32_t min_mclk)
6781 struct ci_power_info *pi = ci_get_pi(adev);
6782 struct ci_dpm_table *dpm_table = &(pi->dpm_table);
6785 for (i = 0; i < dpm_table->sclk_table.count; i++) {
6786 if (dpm_table->sclk_table.dpm_levels[i].enabled &&
6787 dpm_table->sclk_table.dpm_levels[i].value >= min_sclk)
6788 *sclk_mask |= 1 << i;
6791 for (i = 0; i < dpm_table->mclk_table.count; i++) {
6792 if (dpm_table->mclk_table.dpm_levels[i].enabled &&
6793 dpm_table->mclk_table.dpm_levels[i].value >= min_mclk)
6794 *mclk_mask |= 1 << i;
6798 static int ci_set_power_profile_state(struct amdgpu_device *adev,
6799 struct amd_pp_profile *request)
6801 struct ci_power_info *pi = ci_get_pi(adev);
6802 int tmp_result, result = 0;
6803 uint32_t sclk_mask = 0, mclk_mask = 0;
6805 tmp_result = ci_freeze_sclk_mclk_dpm(adev);
6807 DRM_ERROR("Failed to freeze SCLK MCLK DPM!");
6808 result = tmp_result;
6811 tmp_result = ci_populate_requested_graphic_levels(adev,
6814 DRM_ERROR("Failed to populate requested graphic levels!");
6815 result = tmp_result;
6818 tmp_result = ci_unfreeze_sclk_mclk_dpm(adev);
6820 DRM_ERROR("Failed to unfreeze SCLK MCLK DPM!");
6821 result = tmp_result;
6824 ci_find_min_clock_masks(adev, &sclk_mask, &mclk_mask,
6825 request->min_sclk, request->min_mclk);
6828 if (!pi->sclk_dpm_key_disabled)
6829 amdgpu_ci_send_msg_to_smc_with_parameter(
6831 PPSMC_MSG_SCLKDPM_SetEnabledMask,
6832 pi->dpm_level_enable_mask.
6833 sclk_dpm_enable_mask &
6838 if (!pi->mclk_dpm_key_disabled)
6839 amdgpu_ci_send_msg_to_smc_with_parameter(
6841 PPSMC_MSG_MCLKDPM_SetEnabledMask,
6842 pi->dpm_level_enable_mask.
6843 mclk_dpm_enable_mask &
6851 static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev,
6852 struct amd_pp_profile *request)
6854 struct ci_power_info *pi = ci_get_pi(adev);
6857 if (!pi || !request)
6860 if (adev->pm.dpm.forced_level !=
6861 AMD_DPM_FORCED_LEVEL_AUTO)
6864 if (request->min_sclk ||
6865 request->min_mclk ||
6866 request->activity_threshold ||
6868 request->down_hyst) {
6869 if (request->type == AMD_PP_GFX_PROFILE)
6870 memcpy(&pi->gfx_power_profile, request,
6871 sizeof(struct amd_pp_profile));
6872 else if (request->type == AMD_PP_COMPUTE_PROFILE)
6873 memcpy(&pi->compute_power_profile, request,
6874 sizeof(struct amd_pp_profile));
6878 if (request->type == pi->current_power_profile)
6879 ret = ci_set_power_profile_state(
6883 /* set power profile if it exists */
6884 switch (request->type) {
6885 case AMD_PP_GFX_PROFILE:
6886 ret = ci_set_power_profile_state(
6888 &pi->gfx_power_profile);
6890 case AMD_PP_COMPUTE_PROFILE:
6891 ret = ci_set_power_profile_state(
6893 &pi->compute_power_profile);
6901 pi->current_power_profile = request->type;
6906 static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev,
6907 struct amd_pp_profile *request)
6909 struct ci_power_info *pi = ci_get_pi(adev);
6911 if (!pi || !request)
6914 if (request->type == AMD_PP_GFX_PROFILE) {
6915 pi->gfx_power_profile = pi->default_gfx_power_profile;
6916 return ci_dpm_set_power_profile_state(adev,
6917 &pi->gfx_power_profile);
6918 } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
6919 pi->compute_power_profile =
6920 pi->default_compute_power_profile;
6921 return ci_dpm_set_power_profile_state(adev,
6922 &pi->compute_power_profile);
6927 static int ci_dpm_switch_power_profile(struct amdgpu_device *adev,
6928 enum amd_pp_profile_type type)
6930 struct ci_power_info *pi = ci_get_pi(adev);
6931 struct amd_pp_profile request = {0};
6936 if (pi->current_power_profile != type) {
6937 request.type = type;
6938 return ci_dpm_set_power_profile_state(adev, &request);
6944 static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
6945 void *value, int *size)
6947 u32 activity_percent = 50;
6950 /* size must be at least 4 bytes for all sensors */
6955 case AMDGPU_PP_SENSOR_GFX_SCLK:
6956 *((uint32_t *)value) = ci_get_average_sclk_freq(adev);
6959 case AMDGPU_PP_SENSOR_GFX_MCLK:
6960 *((uint32_t *)value) = ci_get_average_mclk_freq(adev);
6963 case AMDGPU_PP_SENSOR_GPU_TEMP:
6964 *((uint32_t *)value) = ci_dpm_get_temp(adev);
6967 case AMDGPU_PP_SENSOR_GPU_LOAD:
6968 ret = ci_read_smc_soft_register(adev,
6969 offsetof(SMU7_SoftRegisters,
6973 activity_percent += 0x80;
6974 activity_percent >>= 8;
6976 activity_percent > 100 ? 100 : activity_percent;
6978 *((uint32_t *)value) = activity_percent;
6986 const struct amd_ip_funcs ci_dpm_ip_funcs = {
6988 .early_init = ci_dpm_early_init,
6989 .late_init = ci_dpm_late_init,
6990 .sw_init = ci_dpm_sw_init,
6991 .sw_fini = ci_dpm_sw_fini,
6992 .hw_init = ci_dpm_hw_init,
6993 .hw_fini = ci_dpm_hw_fini,
6994 .suspend = ci_dpm_suspend,
6995 .resume = ci_dpm_resume,
6996 .is_idle = ci_dpm_is_idle,
6997 .wait_for_idle = ci_dpm_wait_for_idle,
6998 .soft_reset = ci_dpm_soft_reset,
6999 .set_clockgating_state = ci_dpm_set_clockgating_state,
7000 .set_powergating_state = ci_dpm_set_powergating_state,
7003 static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
7004 .get_temperature = &ci_dpm_get_temp,
7005 .pre_set_power_state = &ci_dpm_pre_set_power_state,
7006 .set_power_state = &ci_dpm_set_power_state,
7007 .post_set_power_state = &ci_dpm_post_set_power_state,
7008 .display_configuration_changed = &ci_dpm_display_configuration_changed,
7009 .get_sclk = &ci_dpm_get_sclk,
7010 .get_mclk = &ci_dpm_get_mclk,
7011 .print_power_state = &ci_dpm_print_power_state,
7012 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
7013 .force_performance_level = &ci_dpm_force_performance_level,
7014 .vblank_too_short = &ci_dpm_vblank_too_short,
7015 .powergate_uvd = &ci_dpm_powergate_uvd,
7016 .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
7017 .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
7018 .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
7019 .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
7020 .print_clock_levels = ci_dpm_print_clock_levels,
7021 .force_clock_level = ci_dpm_force_clock_level,
7022 .get_sclk_od = ci_dpm_get_sclk_od,
7023 .set_sclk_od = ci_dpm_set_sclk_od,
7024 .get_mclk_od = ci_dpm_get_mclk_od,
7025 .set_mclk_od = ci_dpm_set_mclk_od,
7026 .check_state_equal = ci_check_state_equal,
7027 .get_vce_clock_state = amdgpu_get_vce_clock_state,
7028 .get_power_profile_state = ci_dpm_get_power_profile_state,
7029 .set_power_profile_state = ci_dpm_set_power_profile_state,
7030 .reset_power_profile_state = ci_dpm_reset_power_profile_state,
7031 .switch_power_profile = ci_dpm_switch_power_profile,
7032 .read_sensor = ci_dpm_read_sensor,
7035 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
7037 if (adev->pm.funcs == NULL)
7038 adev->pm.funcs = &ci_dpm_funcs;
7041 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
7042 .set = ci_dpm_set_interrupt_state,
7043 .process = ci_dpm_process_interrupt,
7046 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
7048 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
7049 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;