2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_pm.h"
28 #include "amdgpu_ucode.h"
30 #include "amdgpu_dpm.h"
34 #include <linux/seq_file.h>
36 #include "smu/smu_7_0_1_d.h"
37 #include "smu/smu_7_0_1_sh_mask.h"
39 #include "dce/dce_8_0_d.h"
40 #include "dce/dce_8_0_sh_mask.h"
42 #include "bif/bif_4_1_d.h"
43 #include "bif/bif_4_1_sh_mask.h"
45 #include "gca/gfx_7_2_d.h"
46 #include "gca/gfx_7_2_sh_mask.h"
48 #include "gmc/gmc_7_1_d.h"
49 #include "gmc/gmc_7_1_sh_mask.h"
53 #define MC_CG_ARB_FREQ_F0 0x0a
54 #define MC_CG_ARB_FREQ_F1 0x0b
55 #define MC_CG_ARB_FREQ_F2 0x0c
56 #define MC_CG_ARB_FREQ_F3 0x0d
58 #define SMC_RAM_END 0x40000
60 #define VOLTAGE_SCALE 4
61 #define VOLTAGE_VID_OFFSET_SCALE1 625
62 #define VOLTAGE_VID_OFFSET_SCALE2 100
64 static const struct ci_pt_defaults defaults_hawaii_xt =
66 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
67 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
68 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
71 static const struct ci_pt_defaults defaults_hawaii_pro =
73 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
74 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
75 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
78 static const struct ci_pt_defaults defaults_bonaire_xt =
80 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
81 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
82 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
85 static const struct ci_pt_defaults defaults_bonaire_pro =
87 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
88 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
89 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
92 static const struct ci_pt_defaults defaults_saturn_xt =
94 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
95 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
96 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
99 static const struct ci_pt_defaults defaults_saturn_pro =
101 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
102 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
103 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
106 static const struct ci_pt_config_reg didt_config_ci[] =
108 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
163 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
164 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
165 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
166 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
167 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
168 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
169 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
170 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
171 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
172 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
173 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
174 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
175 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
176 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
177 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
178 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
179 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
183 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
185 return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
188 #define MC_CG_ARB_FREQ_F0 0x0a
189 #define MC_CG_ARB_FREQ_F1 0x0b
190 #define MC_CG_ARB_FREQ_F2 0x0c
191 #define MC_CG_ARB_FREQ_F3 0x0d
193 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
194 u32 arb_freq_src, u32 arb_freq_dest)
196 u32 mc_arb_dram_timing;
197 u32 mc_arb_dram_timing2;
201 switch (arb_freq_src) {
202 case MC_CG_ARB_FREQ_F0:
203 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
204 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
205 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
206 MC_ARB_BURST_TIME__STATE0__SHIFT;
208 case MC_CG_ARB_FREQ_F1:
209 mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1);
210 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
211 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
212 MC_ARB_BURST_TIME__STATE1__SHIFT;
218 switch (arb_freq_dest) {
219 case MC_CG_ARB_FREQ_F0:
220 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
221 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
222 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
223 ~MC_ARB_BURST_TIME__STATE0_MASK);
225 case MC_CG_ARB_FREQ_F1:
226 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
227 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
228 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
229 ~MC_ARB_BURST_TIME__STATE1_MASK);
235 mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
236 WREG32(mmMC_CG_CONFIG, mc_cg_config);
237 WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
238 ~MC_ARB_CG__CG_ARB_REQ_MASK);
243 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
247 if (memory_clock < 10000)
249 else if (memory_clock >= 80000)
250 mc_para_index = 0x0f;
252 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
253 return mc_para_index;
256 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
261 if (memory_clock < 12500)
262 mc_para_index = 0x00;
263 else if (memory_clock > 47500)
264 mc_para_index = 0x0f;
266 mc_para_index = (u8)((memory_clock - 10000) / 2500);
268 if (memory_clock < 65000)
269 mc_para_index = 0x00;
270 else if (memory_clock > 135000)
271 mc_para_index = 0x0f;
273 mc_para_index = (u8)((memory_clock - 60000) / 5000);
275 return mc_para_index;
278 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
279 u32 max_voltage_steps,
280 struct atom_voltage_table *voltage_table)
282 unsigned int i, diff;
284 if (voltage_table->count <= max_voltage_steps)
287 diff = voltage_table->count - max_voltage_steps;
289 for (i = 0; i < max_voltage_steps; i++)
290 voltage_table->entries[i] = voltage_table->entries[i + diff];
292 voltage_table->count = max_voltage_steps;
295 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
296 struct atom_voltage_table_entry *voltage_table,
297 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
298 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
299 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
301 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
302 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
303 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
305 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
306 PPSMC_Msg msg, u32 parameter);
307 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
308 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
310 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
312 struct ci_power_info *pi = adev->pm.dpm.priv;
317 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
319 struct ci_ps *ps = rps->ps_priv;
324 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
326 struct ci_power_info *pi = ci_get_pi(adev);
328 switch (adev->pdev->device) {
336 pi->powertune_defaults = &defaults_bonaire_xt;
342 pi->powertune_defaults = &defaults_saturn_xt;
346 pi->powertune_defaults = &defaults_hawaii_xt;
350 pi->powertune_defaults = &defaults_hawaii_pro;
360 pi->powertune_defaults = &defaults_bonaire_xt;
364 pi->dte_tj_offset = 0;
366 pi->caps_power_containment = true;
367 pi->caps_cac = false;
368 pi->caps_sq_ramping = false;
369 pi->caps_db_ramping = false;
370 pi->caps_td_ramping = false;
371 pi->caps_tcp_ramping = false;
373 if (pi->caps_power_containment) {
375 if (adev->asic_type == CHIP_HAWAII)
376 pi->enable_bapm_feature = false;
378 pi->enable_bapm_feature = true;
379 pi->enable_tdc_limit_feature = true;
380 pi->enable_pkg_pwr_tracking_feature = true;
384 static u8 ci_convert_to_vid(u16 vddc)
386 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
389 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
391 struct ci_power_info *pi = ci_get_pi(adev);
392 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
393 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
394 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
397 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
399 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
401 if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
402 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
405 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
406 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
407 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
408 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
409 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
411 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
412 hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
418 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
420 struct ci_power_info *pi = ci_get_pi(adev);
421 u8 *vid = pi->smc_powertune_table.VddCVid;
424 if (pi->vddc_voltage_table.count > 8)
427 for (i = 0; i < pi->vddc_voltage_table.count; i++)
428 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
433 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
435 struct ci_power_info *pi = ci_get_pi(adev);
436 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
438 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
439 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
440 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
441 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
446 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
448 struct ci_power_info *pi = ci_get_pi(adev);
449 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
452 tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
453 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
454 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
455 pt_defaults->tdc_vddc_throttle_release_limit_perc;
456 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
461 static int ci_populate_dw8(struct amdgpu_device *adev)
463 struct ci_power_info *pi = ci_get_pi(adev);
464 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
467 ret = amdgpu_ci_read_smc_sram_dword(adev,
468 SMU7_FIRMWARE_HEADER_LOCATION +
469 offsetof(SMU7_Firmware_Header, PmFuseTable) +
470 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
471 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
476 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
481 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
483 struct ci_power_info *pi = ci_get_pi(adev);
485 if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
486 (adev->pm.dpm.fan.fan_output_sensitivity == 0))
487 adev->pm.dpm.fan.fan_output_sensitivity =
488 adev->pm.dpm.fan.default_fan_output_sensitivity;
490 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
491 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
496 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
498 struct ci_power_info *pi = ci_get_pi(adev);
499 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
500 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
503 min = max = hi_vid[0];
504 for (i = 0; i < 8; i++) {
505 if (0 != hi_vid[i]) {
512 if (0 != lo_vid[i]) {
520 if ((min == 0) || (max == 0))
522 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
523 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
528 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
530 struct ci_power_info *pi = ci_get_pi(adev);
531 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
532 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
533 struct amdgpu_cac_tdp_table *cac_tdp_table =
534 adev->pm.dpm.dyn_state.cac_tdp_table;
536 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
537 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
539 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
540 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
545 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
547 struct ci_power_info *pi = ci_get_pi(adev);
548 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
549 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
550 struct amdgpu_cac_tdp_table *cac_tdp_table =
551 adev->pm.dpm.dyn_state.cac_tdp_table;
552 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
557 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
558 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
560 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
561 dpm_table->GpuTjMax =
562 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
563 dpm_table->GpuTjHyst = 8;
565 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
568 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
569 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
571 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
572 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
575 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
576 def1 = pt_defaults->bapmti_r;
577 def2 = pt_defaults->bapmti_rc;
579 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
580 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
581 for (k = 0; k < SMU7_DTE_SINKS; k++) {
582 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
583 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
593 static int ci_populate_pm_base(struct amdgpu_device *adev)
595 struct ci_power_info *pi = ci_get_pi(adev);
596 u32 pm_fuse_table_offset;
599 if (pi->caps_power_containment) {
600 ret = amdgpu_ci_read_smc_sram_dword(adev,
601 SMU7_FIRMWARE_HEADER_LOCATION +
602 offsetof(SMU7_Firmware_Header, PmFuseTable),
603 &pm_fuse_table_offset, pi->sram_end);
606 ret = ci_populate_bapm_vddc_vid_sidd(adev);
609 ret = ci_populate_vddc_vid(adev);
612 ret = ci_populate_svi_load_line(adev);
615 ret = ci_populate_tdc_limit(adev);
618 ret = ci_populate_dw8(adev);
621 ret = ci_populate_fuzzy_fan(adev);
624 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
627 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
630 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
631 (u8 *)&pi->smc_powertune_table,
632 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
640 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
642 struct ci_power_info *pi = ci_get_pi(adev);
645 if (pi->caps_sq_ramping) {
646 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
648 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
650 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
651 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
654 if (pi->caps_db_ramping) {
655 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
657 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
659 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
660 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
663 if (pi->caps_td_ramping) {
664 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
666 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
668 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
669 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
672 if (pi->caps_tcp_ramping) {
673 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
675 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
677 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
678 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
682 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
683 const struct ci_pt_config_reg *cac_config_regs)
685 const struct ci_pt_config_reg *config_regs = cac_config_regs;
689 if (config_regs == NULL)
692 while (config_regs->offset != 0xFFFFFFFF) {
693 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
694 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
696 switch (config_regs->type) {
697 case CISLANDS_CONFIGREG_SMC_IND:
698 data = RREG32_SMC(config_regs->offset);
700 case CISLANDS_CONFIGREG_DIDT_IND:
701 data = RREG32_DIDT(config_regs->offset);
704 data = RREG32(config_regs->offset);
708 data &= ~config_regs->mask;
709 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
712 switch (config_regs->type) {
713 case CISLANDS_CONFIGREG_SMC_IND:
714 WREG32_SMC(config_regs->offset, data);
716 case CISLANDS_CONFIGREG_DIDT_IND:
717 WREG32_DIDT(config_regs->offset, data);
720 WREG32(config_regs->offset, data);
730 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
732 struct ci_power_info *pi = ci_get_pi(adev);
735 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
736 pi->caps_td_ramping || pi->caps_tcp_ramping) {
737 gfx_v7_0_enter_rlc_safe_mode(adev);
740 ret = ci_program_pt_config_registers(adev, didt_config_ci);
742 gfx_v7_0_exit_rlc_safe_mode(adev);
747 ci_do_enable_didt(adev, enable);
749 gfx_v7_0_exit_rlc_safe_mode(adev);
755 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
757 struct ci_power_info *pi = ci_get_pi(adev);
758 PPSMC_Result smc_result;
762 pi->power_containment_features = 0;
763 if (pi->caps_power_containment) {
764 if (pi->enable_bapm_feature) {
765 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
766 if (smc_result != PPSMC_Result_OK)
769 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
772 if (pi->enable_tdc_limit_feature) {
773 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
774 if (smc_result != PPSMC_Result_OK)
777 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
780 if (pi->enable_pkg_pwr_tracking_feature) {
781 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
782 if (smc_result != PPSMC_Result_OK) {
785 struct amdgpu_cac_tdp_table *cac_tdp_table =
786 adev->pm.dpm.dyn_state.cac_tdp_table;
787 u32 default_pwr_limit =
788 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
790 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
792 ci_set_power_limit(adev, default_pwr_limit);
797 if (pi->caps_power_containment && pi->power_containment_features) {
798 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
799 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
801 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
802 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
804 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
805 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
806 pi->power_containment_features = 0;
813 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
815 struct ci_power_info *pi = ci_get_pi(adev);
816 PPSMC_Result smc_result;
821 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
822 if (smc_result != PPSMC_Result_OK) {
824 pi->cac_enabled = false;
826 pi->cac_enabled = true;
828 } else if (pi->cac_enabled) {
829 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
830 pi->cac_enabled = false;
837 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
840 struct ci_power_info *pi = ci_get_pi(adev);
841 PPSMC_Result smc_result = PPSMC_Result_OK;
843 if (pi->thermal_sclk_dpm_enabled) {
845 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
847 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
850 if (smc_result == PPSMC_Result_OK)
856 static int ci_power_control_set_level(struct amdgpu_device *adev)
858 struct ci_power_info *pi = ci_get_pi(adev);
859 struct amdgpu_cac_tdp_table *cac_tdp_table =
860 adev->pm.dpm.dyn_state.cac_tdp_table;
864 bool adjust_polarity = false; /* ??? */
866 if (pi->caps_power_containment) {
867 adjust_percent = adjust_polarity ?
868 adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
869 target_tdp = ((100 + adjust_percent) *
870 (s32)cac_tdp_table->configurable_tdp) / 100;
872 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
878 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
880 struct ci_power_info *pi = ci_get_pi(adev);
882 if (pi->uvd_power_gated == gate)
885 pi->uvd_power_gated = gate;
887 ci_update_uvd_dpm(adev, gate);
890 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
892 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
893 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
895 /* disable mclk switching if the refresh is >120Hz, even if the
896 * blanking period would allow it
898 if (amdgpu_dpm_get_vrefresh(adev) > 120)
901 if (vblank_time < switch_limit)
908 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
909 struct amdgpu_ps *rps)
911 struct ci_ps *ps = ci_get_ps(rps);
912 struct ci_power_info *pi = ci_get_pi(adev);
913 struct amdgpu_clock_and_voltage_limits *max_limits;
914 bool disable_mclk_switching;
918 if (rps->vce_active) {
919 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
920 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
926 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
927 ci_dpm_vblank_too_short(adev))
928 disable_mclk_switching = true;
930 disable_mclk_switching = false;
932 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
933 pi->battery_state = true;
935 pi->battery_state = false;
937 if (adev->pm.dpm.ac_power)
938 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
940 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
942 if (adev->pm.dpm.ac_power == false) {
943 for (i = 0; i < ps->performance_level_count; i++) {
944 if (ps->performance_levels[i].mclk > max_limits->mclk)
945 ps->performance_levels[i].mclk = max_limits->mclk;
946 if (ps->performance_levels[i].sclk > max_limits->sclk)
947 ps->performance_levels[i].sclk = max_limits->sclk;
951 /* XXX validate the min clocks required for display */
953 if (disable_mclk_switching) {
954 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
955 sclk = ps->performance_levels[0].sclk;
957 mclk = ps->performance_levels[0].mclk;
958 sclk = ps->performance_levels[0].sclk;
961 if (rps->vce_active) {
962 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
963 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
964 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
965 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
968 ps->performance_levels[0].sclk = sclk;
969 ps->performance_levels[0].mclk = mclk;
971 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
972 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
974 if (disable_mclk_switching) {
975 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
976 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
978 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
979 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
983 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
984 int min_temp, int max_temp)
986 int low_temp = 0 * 1000;
987 int high_temp = 255 * 1000;
990 if (low_temp < min_temp)
992 if (high_temp > max_temp)
993 high_temp = max_temp;
994 if (high_temp < low_temp) {
995 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
999 tmp = RREG32_SMC(ixCG_THERMAL_INT);
1000 tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
1001 tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1002 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1003 WREG32_SMC(ixCG_THERMAL_INT, tmp);
1006 /* XXX: need to figure out how to handle this properly */
1007 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1008 tmp &= DIG_THERM_DPM_MASK;
1009 tmp |= DIG_THERM_DPM(high_temp / 1000);
1010 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1013 adev->pm.dpm.thermal.min_temp = low_temp;
1014 adev->pm.dpm.thermal.max_temp = high_temp;
1018 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1021 u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1022 PPSMC_Result result;
1025 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1026 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1027 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1028 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1029 if (result != PPSMC_Result_OK) {
1030 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1034 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1035 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1036 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1037 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1038 if (result != PPSMC_Result_OK) {
1039 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1047 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1049 struct ci_power_info *pi = ci_get_pi(adev);
1052 if (pi->fan_ctrl_is_in_default_mode) {
1053 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1054 >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1055 pi->fan_ctrl_default_mode = tmp;
1056 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1057 >> CG_FDO_CTRL2__TMIN__SHIFT;
1059 pi->fan_ctrl_is_in_default_mode = false;
1062 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1063 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1064 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1066 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1067 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1068 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1071 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1073 struct ci_power_info *pi = ci_get_pi(adev);
1074 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1076 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1077 u16 fdo_min, slope1, slope2;
1078 u32 reference_clock, tmp;
1082 if (!pi->fan_table_start) {
1083 adev->pm.dpm.fan.ucode_fan_control = false;
1087 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1088 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1091 adev->pm.dpm.fan.ucode_fan_control = false;
1095 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1096 do_div(tmp64, 10000);
1097 fdo_min = (u16)tmp64;
1099 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1100 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1102 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1103 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1105 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1106 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1108 fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1109 fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1110 fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1112 fan_table.Slope1 = cpu_to_be16(slope1);
1113 fan_table.Slope2 = cpu_to_be16(slope2);
1115 fan_table.FdoMin = cpu_to_be16(fdo_min);
1117 fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1119 fan_table.HystUp = cpu_to_be16(1);
1121 fan_table.HystSlope = cpu_to_be16(1);
1123 fan_table.TempRespLim = cpu_to_be16(5);
1125 reference_clock = amdgpu_asic_get_xclk(adev);
1127 fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1128 reference_clock) / 1600);
1130 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1132 tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1133 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1134 fan_table.TempSrc = (uint8_t)tmp;
1136 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1137 pi->fan_table_start,
1143 DRM_ERROR("Failed to load fan table to the SMC.");
1144 adev->pm.dpm.fan.ucode_fan_control = false;
1150 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1152 struct ci_power_info *pi = ci_get_pi(adev);
1155 if (pi->caps_od_fuzzy_fan_control_support) {
1156 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1157 PPSMC_StartFanControl,
1159 if (ret != PPSMC_Result_OK)
1161 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1162 PPSMC_MSG_SetFanPwmMax,
1163 adev->pm.dpm.fan.default_max_fan_pwm);
1164 if (ret != PPSMC_Result_OK)
1167 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1168 PPSMC_StartFanControl,
1170 if (ret != PPSMC_Result_OK)
1174 pi->fan_is_controlled_by_smc = true;
1179 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1182 struct ci_power_info *pi = ci_get_pi(adev);
1184 ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1185 if (ret == PPSMC_Result_OK) {
1186 pi->fan_is_controlled_by_smc = false;
1193 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1199 if (adev->pm.no_fan)
1202 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1203 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1204 duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1205 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1210 tmp64 = (u64)duty * 100;
1211 do_div(tmp64, duty100);
1212 *speed = (u32)tmp64;
1220 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1226 struct ci_power_info *pi = ci_get_pi(adev);
1228 if (adev->pm.no_fan)
1231 if (pi->fan_is_controlled_by_smc)
1237 duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1238 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1243 tmp64 = (u64)speed * duty100;
1247 tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1248 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1249 WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1254 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1257 /* stop auto-manage */
1258 if (adev->pm.dpm.fan.ucode_fan_control)
1259 ci_fan_ctrl_stop_smc_fan_control(adev);
1260 ci_fan_ctrl_set_static_mode(adev, mode);
1262 /* restart auto-manage */
1263 if (adev->pm.dpm.fan.ucode_fan_control)
1264 ci_thermal_start_smc_fan_control(adev);
1266 ci_fan_ctrl_set_default_mode(adev);
1270 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1272 struct ci_power_info *pi = ci_get_pi(adev);
1275 if (pi->fan_is_controlled_by_smc)
1278 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1279 return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
1283 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1287 u32 xclk = amdgpu_asic_get_xclk(adev);
1289 if (adev->pm.no_fan)
1292 if (adev->pm.fan_pulses_per_revolution == 0)
1295 tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1296 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1297 if (tach_period == 0)
1300 *speed = 60 * xclk * 10000 / tach_period;
1305 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1308 u32 tach_period, tmp;
1309 u32 xclk = amdgpu_asic_get_xclk(adev);
1311 if (adev->pm.no_fan)
1314 if (adev->pm.fan_pulses_per_revolution == 0)
1317 if ((speed < adev->pm.fan_min_rpm) ||
1318 (speed > adev->pm.fan_max_rpm))
1321 if (adev->pm.dpm.fan.ucode_fan_control)
1322 ci_fan_ctrl_stop_smc_fan_control(adev);
1324 tach_period = 60 * xclk * 10000 / (8 * speed);
1325 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1326 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1327 WREG32_SMC(CG_TACH_CTRL, tmp);
1329 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1335 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1337 struct ci_power_info *pi = ci_get_pi(adev);
1340 if (!pi->fan_ctrl_is_in_default_mode) {
1341 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1342 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1343 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1345 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1346 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1347 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1348 pi->fan_ctrl_is_in_default_mode = true;
1352 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1354 if (adev->pm.dpm.fan.ucode_fan_control) {
1355 ci_fan_ctrl_start_smc_fan_control(adev);
1356 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1360 static void ci_thermal_initialize(struct amdgpu_device *adev)
1364 if (adev->pm.fan_pulses_per_revolution) {
1365 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1366 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1367 << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1368 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1371 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1372 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1373 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1376 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1380 ci_thermal_initialize(adev);
1381 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1384 ret = ci_thermal_enable_alert(adev, true);
1387 if (adev->pm.dpm.fan.ucode_fan_control) {
1388 ret = ci_thermal_setup_fan_table(adev);
1391 ci_thermal_start_smc_fan_control(adev);
1397 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1399 if (!adev->pm.no_fan)
1400 ci_fan_ctrl_set_default_mode(adev);
1404 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1405 u16 reg_offset, u32 *value)
1407 struct ci_power_info *pi = ci_get_pi(adev);
1409 return amdgpu_ci_read_smc_sram_dword(adev,
1410 pi->soft_regs_start + reg_offset,
1411 value, pi->sram_end);
1415 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1416 u16 reg_offset, u32 value)
1418 struct ci_power_info *pi = ci_get_pi(adev);
1420 return amdgpu_ci_write_smc_sram_dword(adev,
1421 pi->soft_regs_start + reg_offset,
1422 value, pi->sram_end);
1425 static void ci_init_fps_limits(struct amdgpu_device *adev)
1427 struct ci_power_info *pi = ci_get_pi(adev);
1428 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1434 table->FpsHighT = cpu_to_be16(tmp);
1437 table->FpsLowT = cpu_to_be16(tmp);
1441 static int ci_update_sclk_t(struct amdgpu_device *adev)
1443 struct ci_power_info *pi = ci_get_pi(adev);
1445 u32 low_sclk_interrupt_t = 0;
1447 if (pi->caps_sclk_throttle_low_notification) {
1448 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1450 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1451 pi->dpm_table_start +
1452 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1453 (u8 *)&low_sclk_interrupt_t,
1454 sizeof(u32), pi->sram_end);
1461 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1463 struct ci_power_info *pi = ci_get_pi(adev);
1464 u16 leakage_id, virtual_voltage_id;
1468 pi->vddc_leakage.count = 0;
1469 pi->vddci_leakage.count = 0;
1471 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1472 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1473 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1474 if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1476 if (vddc != 0 && vddc != virtual_voltage_id) {
1477 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1478 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1479 pi->vddc_leakage.count++;
1482 } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1483 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1484 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1485 if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1488 if (vddc != 0 && vddc != virtual_voltage_id) {
1489 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1490 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1491 pi->vddc_leakage.count++;
1493 if (vddci != 0 && vddci != virtual_voltage_id) {
1494 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1495 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1496 pi->vddci_leakage.count++;
1503 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1505 struct ci_power_info *pi = ci_get_pi(adev);
1506 bool want_thermal_protection;
1507 enum amdgpu_dpm_event_src dpm_event_src;
1513 want_thermal_protection = false;
1515 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1516 want_thermal_protection = true;
1517 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1519 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1520 want_thermal_protection = true;
1521 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1523 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1524 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1525 want_thermal_protection = true;
1526 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1530 if (want_thermal_protection) {
1532 /* XXX: need to figure out how to handle this properly */
1533 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1534 tmp &= DPM_EVENT_SRC_MASK;
1535 tmp |= DPM_EVENT_SRC(dpm_event_src);
1536 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1539 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1540 if (pi->thermal_protection)
1541 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1543 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1544 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1546 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1547 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1548 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1552 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1553 enum amdgpu_dpm_auto_throttle_src source,
1556 struct ci_power_info *pi = ci_get_pi(adev);
1559 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1560 pi->active_auto_throttle_sources |= 1 << source;
1561 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1564 if (pi->active_auto_throttle_sources & (1 << source)) {
1565 pi->active_auto_throttle_sources &= ~(1 << source);
1566 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1571 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1573 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1574 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1577 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1579 struct ci_power_info *pi = ci_get_pi(adev);
1580 PPSMC_Result smc_result;
1582 if (!pi->need_update_smu7_dpm_table)
1585 if ((!pi->sclk_dpm_key_disabled) &&
1586 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1587 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1588 if (smc_result != PPSMC_Result_OK)
1592 if ((!pi->mclk_dpm_key_disabled) &&
1593 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1594 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1595 if (smc_result != PPSMC_Result_OK)
1599 pi->need_update_smu7_dpm_table = 0;
1603 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1605 struct ci_power_info *pi = ci_get_pi(adev);
1606 PPSMC_Result smc_result;
1609 if (!pi->sclk_dpm_key_disabled) {
1610 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1611 if (smc_result != PPSMC_Result_OK)
1615 if (!pi->mclk_dpm_key_disabled) {
1616 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1617 if (smc_result != PPSMC_Result_OK)
1620 WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1621 ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1623 WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1624 WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1625 WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1629 WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1630 WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1631 WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1634 if (!pi->sclk_dpm_key_disabled) {
1635 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1636 if (smc_result != PPSMC_Result_OK)
1640 if (!pi->mclk_dpm_key_disabled) {
1641 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1642 if (smc_result != PPSMC_Result_OK)
1650 static int ci_start_dpm(struct amdgpu_device *adev)
1652 struct ci_power_info *pi = ci_get_pi(adev);
1653 PPSMC_Result smc_result;
1657 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1658 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1659 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1661 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1662 tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1663 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1665 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1667 WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1669 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1670 if (smc_result != PPSMC_Result_OK)
1673 ret = ci_enable_sclk_mclk_dpm(adev, true);
1677 if (!pi->pcie_dpm_key_disabled) {
1678 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1679 if (smc_result != PPSMC_Result_OK)
1686 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1688 struct ci_power_info *pi = ci_get_pi(adev);
1689 PPSMC_Result smc_result;
1691 if (!pi->need_update_smu7_dpm_table)
1694 if ((!pi->sclk_dpm_key_disabled) &&
1695 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1696 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1697 if (smc_result != PPSMC_Result_OK)
1701 if ((!pi->mclk_dpm_key_disabled) &&
1702 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1703 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1704 if (smc_result != PPSMC_Result_OK)
1711 static int ci_stop_dpm(struct amdgpu_device *adev)
1713 struct ci_power_info *pi = ci_get_pi(adev);
1714 PPSMC_Result smc_result;
1718 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1719 tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1720 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1722 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1723 tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1724 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1726 if (!pi->pcie_dpm_key_disabled) {
1727 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1728 if (smc_result != PPSMC_Result_OK)
1732 ret = ci_enable_sclk_mclk_dpm(adev, false);
1736 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1737 if (smc_result != PPSMC_Result_OK)
1743 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1745 u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1748 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1750 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1751 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1755 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1758 struct ci_power_info *pi = ci_get_pi(adev);
1759 struct amdgpu_cac_tdp_table *cac_tdp_table =
1760 adev->pm.dpm.dyn_state.cac_tdp_table;
1764 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1766 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1768 ci_set_power_limit(adev, power_limit);
1770 if (pi->caps_automatic_dc_transition) {
1772 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1774 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1781 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1782 PPSMC_Msg msg, u32 parameter)
1784 WREG32(mmSMC_MSG_ARG_0, parameter);
1785 return amdgpu_ci_send_msg_to_smc(adev, msg);
1788 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1789 PPSMC_Msg msg, u32 *parameter)
1791 PPSMC_Result smc_result;
1793 smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1795 if ((smc_result == PPSMC_Result_OK) && parameter)
1796 *parameter = RREG32(mmSMC_MSG_ARG_0);
1801 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1803 struct ci_power_info *pi = ci_get_pi(adev);
1805 if (!pi->sclk_dpm_key_disabled) {
1806 PPSMC_Result smc_result =
1807 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1808 if (smc_result != PPSMC_Result_OK)
1815 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1817 struct ci_power_info *pi = ci_get_pi(adev);
1819 if (!pi->mclk_dpm_key_disabled) {
1820 PPSMC_Result smc_result =
1821 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1822 if (smc_result != PPSMC_Result_OK)
1829 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1831 struct ci_power_info *pi = ci_get_pi(adev);
1833 if (!pi->pcie_dpm_key_disabled) {
1834 PPSMC_Result smc_result =
1835 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1836 if (smc_result != PPSMC_Result_OK)
1843 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1845 struct ci_power_info *pi = ci_get_pi(adev);
1847 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1848 PPSMC_Result smc_result =
1849 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1850 if (smc_result != PPSMC_Result_OK)
1857 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1860 PPSMC_Result smc_result =
1861 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1862 if (smc_result != PPSMC_Result_OK)
1868 static int ci_set_boot_state(struct amdgpu_device *adev)
1870 return ci_enable_sclk_mclk_dpm(adev, false);
1874 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1877 PPSMC_Result smc_result =
1878 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1879 PPSMC_MSG_API_GetSclkFrequency,
1881 if (smc_result != PPSMC_Result_OK)
1887 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1890 PPSMC_Result smc_result =
1891 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1892 PPSMC_MSG_API_GetMclkFrequency,
1894 if (smc_result != PPSMC_Result_OK)
1900 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1904 amdgpu_ci_program_jump_on_start(adev);
1905 amdgpu_ci_start_smc_clock(adev);
1906 amdgpu_ci_start_smc(adev);
1907 for (i = 0; i < adev->usec_timeout; i++) {
1908 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1913 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1915 amdgpu_ci_reset_smc(adev);
1916 amdgpu_ci_stop_smc_clock(adev);
1919 static int ci_process_firmware_header(struct amdgpu_device *adev)
1921 struct ci_power_info *pi = ci_get_pi(adev);
1925 ret = amdgpu_ci_read_smc_sram_dword(adev,
1926 SMU7_FIRMWARE_HEADER_LOCATION +
1927 offsetof(SMU7_Firmware_Header, DpmTable),
1928 &tmp, pi->sram_end);
1932 pi->dpm_table_start = tmp;
1934 ret = amdgpu_ci_read_smc_sram_dword(adev,
1935 SMU7_FIRMWARE_HEADER_LOCATION +
1936 offsetof(SMU7_Firmware_Header, SoftRegisters),
1937 &tmp, pi->sram_end);
1941 pi->soft_regs_start = tmp;
1943 ret = amdgpu_ci_read_smc_sram_dword(adev,
1944 SMU7_FIRMWARE_HEADER_LOCATION +
1945 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1946 &tmp, pi->sram_end);
1950 pi->mc_reg_table_start = tmp;
1952 ret = amdgpu_ci_read_smc_sram_dword(adev,
1953 SMU7_FIRMWARE_HEADER_LOCATION +
1954 offsetof(SMU7_Firmware_Header, FanTable),
1955 &tmp, pi->sram_end);
1959 pi->fan_table_start = tmp;
1961 ret = amdgpu_ci_read_smc_sram_dword(adev,
1962 SMU7_FIRMWARE_HEADER_LOCATION +
1963 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1964 &tmp, pi->sram_end);
1968 pi->arb_table_start = tmp;
1973 static void ci_read_clock_registers(struct amdgpu_device *adev)
1975 struct ci_power_info *pi = ci_get_pi(adev);
1977 pi->clock_registers.cg_spll_func_cntl =
1978 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1979 pi->clock_registers.cg_spll_func_cntl_2 =
1980 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1981 pi->clock_registers.cg_spll_func_cntl_3 =
1982 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
1983 pi->clock_registers.cg_spll_func_cntl_4 =
1984 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
1985 pi->clock_registers.cg_spll_spread_spectrum =
1986 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
1987 pi->clock_registers.cg_spll_spread_spectrum_2 =
1988 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
1989 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
1990 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
1991 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
1992 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
1993 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
1994 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
1995 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
1996 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
1997 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
2000 static void ci_init_sclk_t(struct amdgpu_device *adev)
2002 struct ci_power_info *pi = ci_get_pi(adev);
2004 pi->low_sclk_interrupt_t = 0;
2007 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2010 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2013 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2015 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2016 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2019 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2021 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2023 tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2025 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2029 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2032 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2039 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2043 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2047 for (i = 0; i < adev->usec_timeout; i++) {
2048 if (RREG32(mmSMC_RESP_0) == 1)
2057 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2060 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2062 return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
2065 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2068 struct ci_power_info *pi = ci_get_pi(adev);
2071 if (pi->caps_sclk_ds) {
2072 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2075 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2079 if (pi->caps_sclk_ds) {
2080 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2088 static void ci_program_display_gap(struct amdgpu_device *adev)
2090 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2091 u32 pre_vbi_time_in_us;
2092 u32 frame_time_in_us;
2093 u32 ref_clock = adev->clock.spll.reference_freq;
2094 u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2095 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2097 tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2098 if (adev->pm.dpm.new_active_crtc_count > 0)
2099 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2101 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2102 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2104 if (refresh_rate == 0)
2106 if (vblank_time == 0xffffffff)
2108 frame_time_in_us = 1000000 / refresh_rate;
2109 pre_vbi_time_in_us =
2110 frame_time_in_us - 200 - vblank_time;
2111 tmp = pre_vbi_time_in_us * (ref_clock / 100);
2113 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2114 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2115 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2118 ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2122 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2124 struct ci_power_info *pi = ci_get_pi(adev);
2128 if (pi->caps_sclk_ss_support) {
2129 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2130 tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2131 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2134 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2135 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2136 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2138 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2139 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2140 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2144 static void ci_program_sstp(struct amdgpu_device *adev)
2146 WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2147 ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2148 (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2151 static void ci_enable_display_gap(struct amdgpu_device *adev)
2153 u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2155 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2156 CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2157 tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2158 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2160 WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2163 static void ci_program_vc(struct amdgpu_device *adev)
2167 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2168 tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2169 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2171 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2172 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2173 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2174 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2175 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2176 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2177 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2178 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2181 static void ci_clear_vc(struct amdgpu_device *adev)
2185 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2186 tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2187 WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2189 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2190 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2191 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2192 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2193 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2194 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2195 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2196 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2199 static int ci_upload_firmware(struct amdgpu_device *adev)
2201 struct ci_power_info *pi = ci_get_pi(adev);
2204 for (i = 0; i < adev->usec_timeout; i++) {
2205 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2208 WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2210 amdgpu_ci_stop_smc_clock(adev);
2211 amdgpu_ci_reset_smc(adev);
2213 ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end);
2219 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2220 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2221 struct atom_voltage_table *voltage_table)
2225 if (voltage_dependency_table == NULL)
2228 voltage_table->mask_low = 0;
2229 voltage_table->phase_delay = 0;
2231 voltage_table->count = voltage_dependency_table->count;
2232 for (i = 0; i < voltage_table->count; i++) {
2233 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2234 voltage_table->entries[i].smio_low = 0;
2240 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2242 struct ci_power_info *pi = ci_get_pi(adev);
2245 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2246 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2247 VOLTAGE_OBJ_GPIO_LUT,
2248 &pi->vddc_voltage_table);
2251 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2252 ret = ci_get_svi2_voltage_table(adev,
2253 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2254 &pi->vddc_voltage_table);
2259 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2260 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2261 &pi->vddc_voltage_table);
2263 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2264 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2265 VOLTAGE_OBJ_GPIO_LUT,
2266 &pi->vddci_voltage_table);
2269 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2270 ret = ci_get_svi2_voltage_table(adev,
2271 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2272 &pi->vddci_voltage_table);
2277 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2278 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2279 &pi->vddci_voltage_table);
2281 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2282 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2283 VOLTAGE_OBJ_GPIO_LUT,
2284 &pi->mvdd_voltage_table);
2287 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2288 ret = ci_get_svi2_voltage_table(adev,
2289 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2290 &pi->mvdd_voltage_table);
2295 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2296 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2297 &pi->mvdd_voltage_table);
2302 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2303 struct atom_voltage_table_entry *voltage_table,
2304 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2308 ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2309 &smc_voltage_table->StdVoltageHiSidd,
2310 &smc_voltage_table->StdVoltageLoSidd);
2313 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2314 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2317 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2318 smc_voltage_table->StdVoltageHiSidd =
2319 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2320 smc_voltage_table->StdVoltageLoSidd =
2321 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2324 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2325 SMU7_Discrete_DpmTable *table)
2327 struct ci_power_info *pi = ci_get_pi(adev);
2330 table->VddcLevelCount = pi->vddc_voltage_table.count;
2331 for (count = 0; count < table->VddcLevelCount; count++) {
2332 ci_populate_smc_voltage_table(adev,
2333 &pi->vddc_voltage_table.entries[count],
2334 &table->VddcLevel[count]);
2336 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2337 table->VddcLevel[count].Smio |=
2338 pi->vddc_voltage_table.entries[count].smio_low;
2340 table->VddcLevel[count].Smio = 0;
2342 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2347 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2348 SMU7_Discrete_DpmTable *table)
2351 struct ci_power_info *pi = ci_get_pi(adev);
2353 table->VddciLevelCount = pi->vddci_voltage_table.count;
2354 for (count = 0; count < table->VddciLevelCount; count++) {
2355 ci_populate_smc_voltage_table(adev,
2356 &pi->vddci_voltage_table.entries[count],
2357 &table->VddciLevel[count]);
2359 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2360 table->VddciLevel[count].Smio |=
2361 pi->vddci_voltage_table.entries[count].smio_low;
2363 table->VddciLevel[count].Smio = 0;
2365 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2370 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2371 SMU7_Discrete_DpmTable *table)
2373 struct ci_power_info *pi = ci_get_pi(adev);
2376 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2377 for (count = 0; count < table->MvddLevelCount; count++) {
2378 ci_populate_smc_voltage_table(adev,
2379 &pi->mvdd_voltage_table.entries[count],
2380 &table->MvddLevel[count]);
2382 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2383 table->MvddLevel[count].Smio |=
2384 pi->mvdd_voltage_table.entries[count].smio_low;
2386 table->MvddLevel[count].Smio = 0;
2388 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2393 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2394 SMU7_Discrete_DpmTable *table)
2398 ret = ci_populate_smc_vddc_table(adev, table);
2402 ret = ci_populate_smc_vddci_table(adev, table);
2406 ret = ci_populate_smc_mvdd_table(adev, table);
2413 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2414 SMU7_Discrete_VoltageLevel *voltage)
2416 struct ci_power_info *pi = ci_get_pi(adev);
2419 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2420 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2421 if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2422 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2427 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2434 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2435 struct atom_voltage_table_entry *voltage_table,
2436 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2439 bool voltage_found = false;
2440 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2441 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2443 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2446 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2447 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2448 if (voltage_table->value ==
2449 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2450 voltage_found = true;
2451 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2454 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2455 *std_voltage_lo_sidd =
2456 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2457 *std_voltage_hi_sidd =
2458 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2463 if (!voltage_found) {
2464 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2465 if (voltage_table->value <=
2466 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2467 voltage_found = true;
2468 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2471 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2472 *std_voltage_lo_sidd =
2473 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2474 *std_voltage_hi_sidd =
2475 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2485 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2486 const struct amdgpu_phase_shedding_limits_table *limits,
2488 u32 *phase_shedding)
2492 *phase_shedding = 1;
2494 for (i = 0; i < limits->count; i++) {
2495 if (sclk < limits->entries[i].sclk) {
2496 *phase_shedding = i;
2502 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2503 const struct amdgpu_phase_shedding_limits_table *limits,
2505 u32 *phase_shedding)
2509 *phase_shedding = 1;
2511 for (i = 0; i < limits->count; i++) {
2512 if (mclk < limits->entries[i].mclk) {
2513 *phase_shedding = i;
2519 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2521 struct ci_power_info *pi = ci_get_pi(adev);
2525 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2526 &tmp, pi->sram_end);
2531 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2533 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2537 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2538 struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2539 u32 clock, u32 *voltage)
2543 if (allowed_clock_voltage_table->count == 0)
2546 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2547 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2548 *voltage = allowed_clock_voltage_table->entries[i].v;
2553 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2558 static u8 ci_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2559 u32 sclk, u32 min_sclk_in_sr)
2563 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2564 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2569 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2570 tmp = sclk / (1 << i);
2571 if (tmp >= min || i == 0)
2578 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2580 return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2583 static int ci_reset_to_default(struct amdgpu_device *adev)
2585 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2589 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2593 tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2595 if (tmp == MC_CG_ARB_FREQ_F0)
2598 return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2601 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2602 const u32 engine_clock,
2603 const u32 memory_clock,
2609 tmp = RREG32(mmMC_SEQ_MISC0);
2610 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2613 ((adev->pdev->device == 0x67B0) ||
2614 (adev->pdev->device == 0x67B1))) {
2615 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2616 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2617 *dram_timimg2 &= ~0x00ff0000;
2618 *dram_timimg2 |= tmp2 << 16;
2619 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2620 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2621 *dram_timimg2 &= ~0x00ff0000;
2622 *dram_timimg2 |= tmp2 << 16;
2627 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2630 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2636 amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2638 dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
2639 dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2640 burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2642 ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2644 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2645 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2646 arb_regs->McArbBurstTime = (u8)burst_time;
2651 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2653 struct ci_power_info *pi = ci_get_pi(adev);
2654 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2658 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2660 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2661 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2662 ret = ci_populate_memory_timing_parameters(adev,
2663 pi->dpm_table.sclk_table.dpm_levels[i].value,
2664 pi->dpm_table.mclk_table.dpm_levels[j].value,
2665 &arb_regs.entries[i][j]);
2672 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2673 pi->arb_table_start,
2675 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2681 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2683 struct ci_power_info *pi = ci_get_pi(adev);
2685 if (pi->need_update_smu7_dpm_table == 0)
2688 return ci_do_program_memory_timing_parameters(adev);
2691 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2692 struct amdgpu_ps *amdgpu_boot_state)
2694 struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2695 struct ci_power_info *pi = ci_get_pi(adev);
2698 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2699 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2700 boot_state->performance_levels[0].sclk) {
2701 pi->smc_state_table.GraphicsBootLevel = level;
2706 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2707 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2708 boot_state->performance_levels[0].mclk) {
2709 pi->smc_state_table.MemoryBootLevel = level;
2715 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2720 for (i = dpm_table->count; i > 0; i--) {
2721 mask_value = mask_value << 1;
2722 if (dpm_table->dpm_levels[i-1].enabled)
2725 mask_value &= 0xFFFFFFFE;
2731 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2732 SMU7_Discrete_DpmTable *table)
2734 struct ci_power_info *pi = ci_get_pi(adev);
2735 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2738 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2739 table->LinkLevel[i].PcieGenSpeed =
2740 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2741 table->LinkLevel[i].PcieLaneCount =
2742 amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2743 table->LinkLevel[i].EnabledForActivity = 1;
2744 table->LinkLevel[i].DownT = cpu_to_be32(5);
2745 table->LinkLevel[i].UpT = cpu_to_be32(30);
2748 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2749 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2750 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2753 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2754 SMU7_Discrete_DpmTable *table)
2757 struct atom_clock_dividers dividers;
2760 table->UvdLevelCount =
2761 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2763 for (count = 0; count < table->UvdLevelCount; count++) {
2764 table->UvdLevel[count].VclkFrequency =
2765 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2766 table->UvdLevel[count].DclkFrequency =
2767 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2768 table->UvdLevel[count].MinVddc =
2769 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2770 table->UvdLevel[count].MinVddcPhases = 1;
2772 ret = amdgpu_atombios_get_clock_dividers(adev,
2773 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2774 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2778 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2780 ret = amdgpu_atombios_get_clock_dividers(adev,
2781 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2782 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2786 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2788 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2789 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2790 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2796 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2797 SMU7_Discrete_DpmTable *table)
2800 struct atom_clock_dividers dividers;
2803 table->VceLevelCount =
2804 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2806 for (count = 0; count < table->VceLevelCount; count++) {
2807 table->VceLevel[count].Frequency =
2808 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2809 table->VceLevel[count].MinVoltage =
2810 (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2811 table->VceLevel[count].MinPhases = 1;
2813 ret = amdgpu_atombios_get_clock_dividers(adev,
2814 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2815 table->VceLevel[count].Frequency, false, ÷rs);
2819 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2821 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2822 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2829 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2830 SMU7_Discrete_DpmTable *table)
2833 struct atom_clock_dividers dividers;
2836 table->AcpLevelCount = (u8)
2837 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2839 for (count = 0; count < table->AcpLevelCount; count++) {
2840 table->AcpLevel[count].Frequency =
2841 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2842 table->AcpLevel[count].MinVoltage =
2843 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2844 table->AcpLevel[count].MinPhases = 1;
2846 ret = amdgpu_atombios_get_clock_dividers(adev,
2847 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2848 table->AcpLevel[count].Frequency, false, ÷rs);
2852 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2854 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2855 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2861 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2862 SMU7_Discrete_DpmTable *table)
2865 struct atom_clock_dividers dividers;
2868 table->SamuLevelCount =
2869 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2871 for (count = 0; count < table->SamuLevelCount; count++) {
2872 table->SamuLevel[count].Frequency =
2873 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2874 table->SamuLevel[count].MinVoltage =
2875 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2876 table->SamuLevel[count].MinPhases = 1;
2878 ret = amdgpu_atombios_get_clock_dividers(adev,
2879 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2880 table->SamuLevel[count].Frequency, false, ÷rs);
2884 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2886 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2887 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2893 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2895 SMU7_Discrete_MemoryLevel *mclk,
2899 struct ci_power_info *pi = ci_get_pi(adev);
2900 u32 dll_cntl = pi->clock_registers.dll_cntl;
2901 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2902 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2903 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2904 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2905 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2906 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2907 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2908 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2909 struct atom_mpll_param mpll_param;
2912 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2916 mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2917 mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2919 mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2920 MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2921 mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2922 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2923 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2925 mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2926 mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2928 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2929 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2930 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2931 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2932 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2935 if (pi->caps_mclk_ss_support) {
2936 struct amdgpu_atom_ss ss;
2939 u32 reference_clock = adev->clock.mpll.reference_freq;
2941 if (mpll_param.qdr == 1)
2942 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2944 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2946 tmp = (freq_nom / reference_clock);
2948 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2949 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2950 u32 clks = reference_clock * 5 / ss.rate;
2951 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2953 mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2954 mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2956 mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2957 mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2961 mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2962 mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2965 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2966 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2968 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2969 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2971 mclk->MclkFrequency = memory_clock;
2972 mclk->MpllFuncCntl = mpll_func_cntl;
2973 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2974 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2975 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2976 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2977 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2978 mclk->DllCntl = dll_cntl;
2979 mclk->MpllSs1 = mpll_ss1;
2980 mclk->MpllSs2 = mpll_ss2;
2985 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
2987 SMU7_Discrete_MemoryLevel *memory_level)
2989 struct ci_power_info *pi = ci_get_pi(adev);
2993 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2994 ret = ci_get_dependency_volt_by_clk(adev,
2995 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2996 memory_clock, &memory_level->MinVddc);
3001 if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
3002 ret = ci_get_dependency_volt_by_clk(adev,
3003 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3004 memory_clock, &memory_level->MinVddci);
3009 if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3010 ret = ci_get_dependency_volt_by_clk(adev,
3011 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3012 memory_clock, &memory_level->MinMvdd);
3017 memory_level->MinVddcPhases = 1;
3019 if (pi->vddc_phase_shed_control)
3020 ci_populate_phase_value_based_on_mclk(adev,
3021 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3023 &memory_level->MinVddcPhases);
3025 memory_level->EnabledForThrottle = 1;
3026 memory_level->EnabledForActivity = 1;
3027 memory_level->UpH = 0;
3028 memory_level->DownH = 100;
3029 memory_level->VoltageDownH = 0;
3030 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3032 memory_level->StutterEnable = false;
3033 memory_level->StrobeEnable = false;
3034 memory_level->EdcReadEnable = false;
3035 memory_level->EdcWriteEnable = false;
3036 memory_level->RttEnable = false;
3038 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3040 if (pi->mclk_stutter_mode_threshold &&
3041 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3042 (pi->uvd_enabled == false) &&
3043 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3044 (adev->pm.dpm.new_active_crtc_count <= 2))
3045 memory_level->StutterEnable = true;
3047 if (pi->mclk_strobe_mode_threshold &&
3048 (memory_clock <= pi->mclk_strobe_mode_threshold))
3049 memory_level->StrobeEnable = 1;
3051 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3052 memory_level->StrobeRatio =
3053 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3054 if (pi->mclk_edc_enable_threshold &&
3055 (memory_clock > pi->mclk_edc_enable_threshold))
3056 memory_level->EdcReadEnable = true;
3058 if (pi->mclk_edc_wr_enable_threshold &&
3059 (memory_clock > pi->mclk_edc_wr_enable_threshold))
3060 memory_level->EdcWriteEnable = true;
3062 if (memory_level->StrobeEnable) {
3063 if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3064 ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3065 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3067 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3069 dll_state_on = pi->dll_default_on;
3072 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3073 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3076 ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3080 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3081 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3082 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3083 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3085 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3086 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3087 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3088 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3089 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3090 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3091 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3092 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3093 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3094 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3095 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3100 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3101 SMU7_Discrete_DpmTable *table)
3103 struct ci_power_info *pi = ci_get_pi(adev);
3104 struct atom_clock_dividers dividers;
3105 SMU7_Discrete_VoltageLevel voltage_level;
3106 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3107 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3108 u32 dll_cntl = pi->clock_registers.dll_cntl;
3109 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3112 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3115 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3117 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3119 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3121 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3123 ret = amdgpu_atombios_get_clock_dividers(adev,
3124 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3125 table->ACPILevel.SclkFrequency, false, ÷rs);
3129 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3130 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3131 table->ACPILevel.DeepSleepDivId = 0;
3133 spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3134 spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3136 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3137 spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3139 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3140 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3141 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3142 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3143 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3144 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3145 table->ACPILevel.CcPwrDynRm = 0;
3146 table->ACPILevel.CcPwrDynRm1 = 0;
3148 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3149 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3150 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3151 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3152 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3153 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3154 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3155 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3156 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3157 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3158 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3160 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3161 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3163 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3165 table->MemoryACPILevel.MinVddci =
3166 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3168 table->MemoryACPILevel.MinVddci =
3169 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3172 if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3173 table->MemoryACPILevel.MinMvdd = 0;
3175 table->MemoryACPILevel.MinMvdd =
3176 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3178 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3179 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3180 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3181 MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3183 dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3185 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3186 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3187 table->MemoryACPILevel.MpllAdFuncCntl =
3188 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3189 table->MemoryACPILevel.MpllDqFuncCntl =
3190 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3191 table->MemoryACPILevel.MpllFuncCntl =
3192 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3193 table->MemoryACPILevel.MpllFuncCntl_1 =
3194 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3195 table->MemoryACPILevel.MpllFuncCntl_2 =
3196 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3197 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3198 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3200 table->MemoryACPILevel.EnabledForThrottle = 0;
3201 table->MemoryACPILevel.EnabledForActivity = 0;
3202 table->MemoryACPILevel.UpH = 0;
3203 table->MemoryACPILevel.DownH = 100;
3204 table->MemoryACPILevel.VoltageDownH = 0;
3205 table->MemoryACPILevel.ActivityLevel =
3206 cpu_to_be16((u16)pi->mclk_activity_target);
3208 table->MemoryACPILevel.StutterEnable = false;
3209 table->MemoryACPILevel.StrobeEnable = false;
3210 table->MemoryACPILevel.EdcReadEnable = false;
3211 table->MemoryACPILevel.EdcWriteEnable = false;
3212 table->MemoryACPILevel.RttEnable = false;
3218 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3220 struct ci_power_info *pi = ci_get_pi(adev);
3221 struct ci_ulv_parm *ulv = &pi->ulv;
3223 if (ulv->supported) {
3225 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3228 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3235 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3236 SMU7_Discrete_Ulv *state)
3238 struct ci_power_info *pi = ci_get_pi(adev);
3239 u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3241 state->CcPwrDynRm = 0;
3242 state->CcPwrDynRm1 = 0;
3244 if (ulv_voltage == 0) {
3245 pi->ulv.supported = false;
3249 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3250 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3251 state->VddcOffset = 0;
3254 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3256 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3257 state->VddcOffsetVid = 0;
3259 state->VddcOffsetVid = (u8)
3260 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3261 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3263 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3265 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3266 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3267 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3272 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3274 SMU7_Discrete_GraphicsLevel *sclk)
3276 struct ci_power_info *pi = ci_get_pi(adev);
3277 struct atom_clock_dividers dividers;
3278 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3279 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3280 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3281 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3282 u32 reference_clock = adev->clock.spll.reference_freq;
3283 u32 reference_divider;
3287 ret = amdgpu_atombios_get_clock_dividers(adev,
3288 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3289 engine_clock, false, ÷rs);
3293 reference_divider = 1 + dividers.ref_div;
3294 fbdiv = dividers.fb_div & 0x3FFFFFF;
3296 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3297 spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3298 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3300 if (pi->caps_sclk_ss_support) {
3301 struct amdgpu_atom_ss ss;
3302 u32 vco_freq = engine_clock * dividers.post_div;
3304 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3305 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3306 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3307 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3309 cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3310 cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3311 cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3313 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3314 cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3318 sclk->SclkFrequency = engine_clock;
3319 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3320 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3321 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3322 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3323 sclk->SclkDid = (u8)dividers.post_divider;
3328 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3330 u16 sclk_activity_level_t,
3331 SMU7_Discrete_GraphicsLevel *graphic_level)
3333 struct ci_power_info *pi = ci_get_pi(adev);
3336 ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3340 ret = ci_get_dependency_volt_by_clk(adev,
3341 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3342 engine_clock, &graphic_level->MinVddc);
3346 graphic_level->SclkFrequency = engine_clock;
3348 graphic_level->Flags = 0;
3349 graphic_level->MinVddcPhases = 1;
3351 if (pi->vddc_phase_shed_control)
3352 ci_populate_phase_value_based_on_sclk(adev,
3353 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3355 &graphic_level->MinVddcPhases);
3357 graphic_level->ActivityLevel = sclk_activity_level_t;
3359 graphic_level->CcPwrDynRm = 0;
3360 graphic_level->CcPwrDynRm1 = 0;
3361 graphic_level->EnabledForThrottle = 1;
3362 graphic_level->UpH = 0;
3363 graphic_level->DownH = 0;
3364 graphic_level->VoltageDownH = 0;
3365 graphic_level->PowerThrottle = 0;
3367 if (pi->caps_sclk_ds)
3368 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(adev,
3370 CISLAND_MINIMUM_ENGINE_CLOCK);
3372 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3374 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3375 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3376 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3377 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3378 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3379 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3380 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3381 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3382 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3383 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3384 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3385 graphic_level->EnabledForActivity = 1;
3390 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3392 struct ci_power_info *pi = ci_get_pi(adev);
3393 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3394 u32 level_array_address = pi->dpm_table_start +
3395 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3396 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3397 SMU7_MAX_LEVELS_GRAPHICS;
3398 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3401 memset(levels, 0, level_array_size);
3403 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3404 ret = ci_populate_single_graphic_level(adev,
3405 dpm_table->sclk_table.dpm_levels[i].value,
3406 (u16)pi->activity_target[i],
3407 &pi->smc_state_table.GraphicsLevel[i]);
3411 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3412 if (i == (dpm_table->sclk_table.count - 1))
3413 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3414 PPSMC_DISPLAY_WATERMARK_HIGH;
3417 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3418 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3419 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3421 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3422 (u8 *)levels, level_array_size,
3430 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3431 SMU7_Discrete_Ulv *ulv_level)
3433 return ci_populate_ulv_level(adev, ulv_level);
3436 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3438 struct ci_power_info *pi = ci_get_pi(adev);
3439 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3440 u32 level_array_address = pi->dpm_table_start +
3441 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3442 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3443 SMU7_MAX_LEVELS_MEMORY;
3444 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3447 memset(levels, 0, level_array_size);
3449 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3450 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3452 ret = ci_populate_single_memory_level(adev,
3453 dpm_table->mclk_table.dpm_levels[i].value,
3454 &pi->smc_state_table.MemoryLevel[i]);
3459 if ((dpm_table->mclk_table.count >= 2) &&
3460 ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3461 pi->smc_state_table.MemoryLevel[1].MinVddc =
3462 pi->smc_state_table.MemoryLevel[0].MinVddc;
3463 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3464 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3467 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3469 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3470 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3471 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3473 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3474 PPSMC_DISPLAY_WATERMARK_HIGH;
3476 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3477 (u8 *)levels, level_array_size,
3485 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3486 struct ci_single_dpm_table* dpm_table,
3491 dpm_table->count = count;
3492 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3493 dpm_table->dpm_levels[i].enabled = false;
3496 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3497 u32 index, u32 pcie_gen, u32 pcie_lanes)
3499 dpm_table->dpm_levels[index].value = pcie_gen;
3500 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3501 dpm_table->dpm_levels[index].enabled = true;
3504 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3506 struct ci_power_info *pi = ci_get_pi(adev);
3508 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3511 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3512 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3513 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3514 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3515 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3516 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3519 ci_reset_single_dpm_table(adev,
3520 &pi->dpm_table.pcie_speed_table,
3521 SMU7_MAX_LEVELS_LINK);
3523 if (adev->asic_type == CHIP_BONAIRE)
3524 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3525 pi->pcie_gen_powersaving.min,
3526 pi->pcie_lane_powersaving.max);
3528 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3529 pi->pcie_gen_powersaving.min,
3530 pi->pcie_lane_powersaving.min);
3531 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3532 pi->pcie_gen_performance.min,
3533 pi->pcie_lane_performance.min);
3534 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3535 pi->pcie_gen_powersaving.min,
3536 pi->pcie_lane_powersaving.max);
3537 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3538 pi->pcie_gen_performance.min,
3539 pi->pcie_lane_performance.max);
3540 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3541 pi->pcie_gen_powersaving.max,
3542 pi->pcie_lane_powersaving.max);
3543 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3544 pi->pcie_gen_performance.max,
3545 pi->pcie_lane_performance.max);
3547 pi->dpm_table.pcie_speed_table.count = 6;
3552 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3554 struct ci_power_info *pi = ci_get_pi(adev);
3555 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3556 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3557 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3558 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3559 struct amdgpu_cac_leakage_table *std_voltage_table =
3560 &adev->pm.dpm.dyn_state.cac_leakage_table;
3563 if (allowed_sclk_vddc_table == NULL)
3565 if (allowed_sclk_vddc_table->count < 1)
3567 if (allowed_mclk_table == NULL)
3569 if (allowed_mclk_table->count < 1)
3572 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3574 ci_reset_single_dpm_table(adev,
3575 &pi->dpm_table.sclk_table,
3576 SMU7_MAX_LEVELS_GRAPHICS);
3577 ci_reset_single_dpm_table(adev,
3578 &pi->dpm_table.mclk_table,
3579 SMU7_MAX_LEVELS_MEMORY);
3580 ci_reset_single_dpm_table(adev,
3581 &pi->dpm_table.vddc_table,
3582 SMU7_MAX_LEVELS_VDDC);
3583 ci_reset_single_dpm_table(adev,
3584 &pi->dpm_table.vddci_table,
3585 SMU7_MAX_LEVELS_VDDCI);
3586 ci_reset_single_dpm_table(adev,
3587 &pi->dpm_table.mvdd_table,
3588 SMU7_MAX_LEVELS_MVDD);
3590 pi->dpm_table.sclk_table.count = 0;
3591 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3593 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3594 allowed_sclk_vddc_table->entries[i].clk)) {
3595 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3596 allowed_sclk_vddc_table->entries[i].clk;
3597 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3598 (i == 0) ? true : false;
3599 pi->dpm_table.sclk_table.count++;
3603 pi->dpm_table.mclk_table.count = 0;
3604 for (i = 0; i < allowed_mclk_table->count; i++) {
3606 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3607 allowed_mclk_table->entries[i].clk)) {
3608 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3609 allowed_mclk_table->entries[i].clk;
3610 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3611 (i == 0) ? true : false;
3612 pi->dpm_table.mclk_table.count++;
3616 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3617 pi->dpm_table.vddc_table.dpm_levels[i].value =
3618 allowed_sclk_vddc_table->entries[i].v;
3619 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3620 std_voltage_table->entries[i].leakage;
3621 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3623 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3625 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3626 if (allowed_mclk_table) {
3627 for (i = 0; i < allowed_mclk_table->count; i++) {
3628 pi->dpm_table.vddci_table.dpm_levels[i].value =
3629 allowed_mclk_table->entries[i].v;
3630 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3632 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3635 allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3636 if (allowed_mclk_table) {
3637 for (i = 0; i < allowed_mclk_table->count; i++) {
3638 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3639 allowed_mclk_table->entries[i].v;
3640 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3642 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3645 ci_setup_default_pcie_tables(adev);
3650 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3651 u32 value, u32 *boot_level)
3656 for(i = 0; i < table->count; i++) {
3657 if (value == table->dpm_levels[i].value) {
3666 static int ci_init_smc_table(struct amdgpu_device *adev)
3668 struct ci_power_info *pi = ci_get_pi(adev);
3669 struct ci_ulv_parm *ulv = &pi->ulv;
3670 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3671 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3674 ret = ci_setup_default_dpm_tables(adev);
3678 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3679 ci_populate_smc_voltage_tables(adev, table);
3681 ci_init_fps_limits(adev);
3683 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3684 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3686 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3687 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3689 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3690 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3692 if (ulv->supported) {
3693 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3696 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3699 ret = ci_populate_all_graphic_levels(adev);
3703 ret = ci_populate_all_memory_levels(adev);
3707 ci_populate_smc_link_level(adev, table);
3709 ret = ci_populate_smc_acpi_level(adev, table);
3713 ret = ci_populate_smc_vce_level(adev, table);
3717 ret = ci_populate_smc_acp_level(adev, table);
3721 ret = ci_populate_smc_samu_level(adev, table);
3725 ret = ci_do_program_memory_timing_parameters(adev);
3729 ret = ci_populate_smc_uvd_level(adev, table);
3733 table->UvdBootLevel = 0;
3734 table->VceBootLevel = 0;
3735 table->AcpBootLevel = 0;
3736 table->SamuBootLevel = 0;
3737 table->GraphicsBootLevel = 0;
3738 table->MemoryBootLevel = 0;
3740 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3741 pi->vbios_boot_state.sclk_bootup_value,
3742 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3744 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3745 pi->vbios_boot_state.mclk_bootup_value,
3746 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3748 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3749 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3750 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3752 ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3754 ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3758 table->UVDInterval = 1;
3759 table->VCEInterval = 1;
3760 table->ACPInterval = 1;
3761 table->SAMUInterval = 1;
3762 table->GraphicsVoltageChangeEnable = 1;
3763 table->GraphicsThermThrottleEnable = 1;
3764 table->GraphicsInterval = 1;
3765 table->VoltageInterval = 1;
3766 table->ThermalInterval = 1;
3767 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3768 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3769 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3770 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3771 table->MemoryVoltageChangeEnable = 1;
3772 table->MemoryInterval = 1;
3773 table->VoltageResponseTime = 0;
3774 table->VddcVddciDelta = 4000;
3775 table->PhaseResponseTime = 0;
3776 table->MemoryThermThrottleEnable = 1;
3777 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3778 table->PCIeGenInterval = 1;
3779 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3780 table->SVI2Enable = 1;
3782 table->SVI2Enable = 0;
3784 table->ThermGpio = 17;
3785 table->SclkStepSize = 0x4000;
3787 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3788 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3789 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3790 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3791 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3792 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3793 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3794 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3795 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3796 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3797 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3798 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3799 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3800 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3802 ret = amdgpu_ci_copy_bytes_to_smc(adev,
3803 pi->dpm_table_start +
3804 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3805 (u8 *)&table->SystemFlags,
3806 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3814 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3815 struct ci_single_dpm_table *dpm_table,
3816 u32 low_limit, u32 high_limit)
3820 for (i = 0; i < dpm_table->count; i++) {
3821 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3822 (dpm_table->dpm_levels[i].value > high_limit))
3823 dpm_table->dpm_levels[i].enabled = false;
3825 dpm_table->dpm_levels[i].enabled = true;
3829 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3830 u32 speed_low, u32 lanes_low,
3831 u32 speed_high, u32 lanes_high)
3833 struct ci_power_info *pi = ci_get_pi(adev);
3834 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3837 for (i = 0; i < pcie_table->count; i++) {
3838 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3839 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3840 (pcie_table->dpm_levels[i].value > speed_high) ||
3841 (pcie_table->dpm_levels[i].param1 > lanes_high))
3842 pcie_table->dpm_levels[i].enabled = false;
3844 pcie_table->dpm_levels[i].enabled = true;
3847 for (i = 0; i < pcie_table->count; i++) {
3848 if (pcie_table->dpm_levels[i].enabled) {
3849 for (j = i + 1; j < pcie_table->count; j++) {
3850 if (pcie_table->dpm_levels[j].enabled) {
3851 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3852 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3853 pcie_table->dpm_levels[j].enabled = false;
3860 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3861 struct amdgpu_ps *amdgpu_state)
3863 struct ci_ps *state = ci_get_ps(amdgpu_state);
3864 struct ci_power_info *pi = ci_get_pi(adev);
3865 u32 high_limit_count;
3867 if (state->performance_level_count < 1)
3870 if (state->performance_level_count == 1)
3871 high_limit_count = 0;
3873 high_limit_count = 1;
3875 ci_trim_single_dpm_states(adev,
3876 &pi->dpm_table.sclk_table,
3877 state->performance_levels[0].sclk,
3878 state->performance_levels[high_limit_count].sclk);
3880 ci_trim_single_dpm_states(adev,
3881 &pi->dpm_table.mclk_table,
3882 state->performance_levels[0].mclk,
3883 state->performance_levels[high_limit_count].mclk);
3885 ci_trim_pcie_dpm_states(adev,
3886 state->performance_levels[0].pcie_gen,
3887 state->performance_levels[0].pcie_lane,
3888 state->performance_levels[high_limit_count].pcie_gen,
3889 state->performance_levels[high_limit_count].pcie_lane);
3894 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3896 struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3897 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3898 struct amdgpu_clock_voltage_dependency_table *vddc_table =
3899 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3900 u32 requested_voltage = 0;
3903 if (disp_voltage_table == NULL)
3905 if (!disp_voltage_table->count)
3908 for (i = 0; i < disp_voltage_table->count; i++) {
3909 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3910 requested_voltage = disp_voltage_table->entries[i].v;
3913 for (i = 0; i < vddc_table->count; i++) {
3914 if (requested_voltage <= vddc_table->entries[i].v) {
3915 requested_voltage = vddc_table->entries[i].v;
3916 return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3917 PPSMC_MSG_VddC_Request,
3918 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3926 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3928 struct ci_power_info *pi = ci_get_pi(adev);
3929 PPSMC_Result result;
3931 ci_apply_disp_minimum_voltage_request(adev);
3933 if (!pi->sclk_dpm_key_disabled) {
3934 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3935 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3936 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3937 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3938 if (result != PPSMC_Result_OK)
3943 if (!pi->mclk_dpm_key_disabled) {
3944 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3945 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3946 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3947 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3948 if (result != PPSMC_Result_OK)
3954 if (!pi->pcie_dpm_key_disabled) {
3955 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3956 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3957 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3958 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3959 if (result != PPSMC_Result_OK)
3968 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
3969 struct amdgpu_ps *amdgpu_state)
3971 struct ci_power_info *pi = ci_get_pi(adev);
3972 struct ci_ps *state = ci_get_ps(amdgpu_state);
3973 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3974 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3975 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3976 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3979 pi->need_update_smu7_dpm_table = 0;
3981 for (i = 0; i < sclk_table->count; i++) {
3982 if (sclk == sclk_table->dpm_levels[i].value)
3986 if (i >= sclk_table->count) {
3987 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3989 /* XXX check display min clock requirements */
3990 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3991 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3994 for (i = 0; i < mclk_table->count; i++) {
3995 if (mclk == mclk_table->dpm_levels[i].value)
3999 if (i >= mclk_table->count)
4000 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4002 if (adev->pm.dpm.current_active_crtc_count !=
4003 adev->pm.dpm.new_active_crtc_count)
4004 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4007 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4008 struct amdgpu_ps *amdgpu_state)
4010 struct ci_power_info *pi = ci_get_pi(adev);
4011 struct ci_ps *state = ci_get_ps(amdgpu_state);
4012 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4013 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4014 struct ci_dpm_table *dpm_table = &pi->dpm_table;
4017 if (!pi->need_update_smu7_dpm_table)
4020 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4021 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4023 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4024 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4026 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4027 ret = ci_populate_all_graphic_levels(adev);
4032 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4033 ret = ci_populate_all_memory_levels(adev);
4041 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4043 struct ci_power_info *pi = ci_get_pi(adev);
4044 const struct amdgpu_clock_and_voltage_limits *max_limits;
4047 if (adev->pm.dpm.ac_power)
4048 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4050 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4053 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4055 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4056 if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4057 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4059 if (!pi->caps_uvd_dpm)
4064 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4065 PPSMC_MSG_UVDDPM_SetEnabledMask,
4066 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4068 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4069 pi->uvd_enabled = true;
4070 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4071 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4072 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4073 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4076 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4077 pi->uvd_enabled = false;
4078 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4079 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4080 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4081 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4085 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4086 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4090 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4092 struct ci_power_info *pi = ci_get_pi(adev);
4093 const struct amdgpu_clock_and_voltage_limits *max_limits;
4096 if (adev->pm.dpm.ac_power)
4097 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4099 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4102 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4103 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4104 if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4105 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4107 if (!pi->caps_vce_dpm)
4112 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4113 PPSMC_MSG_VCEDPM_SetEnabledMask,
4114 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4117 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4118 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4123 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4125 struct ci_power_info *pi = ci_get_pi(adev);
4126 const struct amdgpu_clock_and_voltage_limits *max_limits;
4129 if (adev->pm.dpm.ac_power)
4130 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4132 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4135 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4136 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4137 if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4138 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4140 if (!pi->caps_samu_dpm)
4145 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4146 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4147 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4149 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4150 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4154 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4156 struct ci_power_info *pi = ci_get_pi(adev);
4157 const struct amdgpu_clock_and_voltage_limits *max_limits;
4160 if (adev->pm.dpm.ac_power)
4161 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4163 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4166 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4167 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4168 if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4169 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4171 if (!pi->caps_acp_dpm)
4176 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4177 PPSMC_MSG_ACPDPM_SetEnabledMask,
4178 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4181 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4182 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4187 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4189 struct ci_power_info *pi = ci_get_pi(adev);
4193 if (pi->caps_uvd_dpm ||
4194 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4195 pi->smc_state_table.UvdBootLevel = 0;
4197 pi->smc_state_table.UvdBootLevel =
4198 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4200 tmp = RREG32_SMC(ixDPM_TABLE_475);
4201 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4202 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4203 WREG32_SMC(ixDPM_TABLE_475, tmp);
4206 return ci_enable_uvd_dpm(adev, !gate);
4209 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4212 u32 min_evclk = 30000; /* ??? */
4213 struct amdgpu_vce_clock_voltage_dependency_table *table =
4214 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4216 for (i = 0; i < table->count; i++) {
4217 if (table->entries[i].evclk >= min_evclk)
4221 return table->count - 1;
4224 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4225 struct amdgpu_ps *amdgpu_new_state,
4226 struct amdgpu_ps *amdgpu_current_state)
4228 struct ci_power_info *pi = ci_get_pi(adev);
4232 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4233 if (amdgpu_new_state->evclk) {
4234 /* turn the clocks on when encoding */
4235 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4236 AMD_CG_STATE_UNGATE);
4240 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4241 tmp = RREG32_SMC(ixDPM_TABLE_475);
4242 tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4243 tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4244 WREG32_SMC(ixDPM_TABLE_475, tmp);
4246 ret = ci_enable_vce_dpm(adev, true);
4248 /* turn the clocks off when not encoding */
4249 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4254 ret = ci_enable_vce_dpm(adev, false);
4261 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4263 return ci_enable_samu_dpm(adev, gate);
4266 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4268 struct ci_power_info *pi = ci_get_pi(adev);
4272 pi->smc_state_table.AcpBootLevel = 0;
4274 tmp = RREG32_SMC(ixDPM_TABLE_475);
4275 tmp &= ~AcpBootLevel_MASK;
4276 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4277 WREG32_SMC(ixDPM_TABLE_475, tmp);
4280 return ci_enable_acp_dpm(adev, !gate);
4284 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4285 struct amdgpu_ps *amdgpu_state)
4287 struct ci_power_info *pi = ci_get_pi(adev);
4290 ret = ci_trim_dpm_states(adev, amdgpu_state);
4294 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4295 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4296 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4297 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4298 pi->last_mclk_dpm_enable_mask =
4299 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4300 if (pi->uvd_enabled) {
4301 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4302 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4304 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4305 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4310 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4315 while ((level_mask & (1 << level)) == 0)
4322 static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4323 enum amdgpu_dpm_forced_level level)
4325 struct ci_power_info *pi = ci_get_pi(adev);
4329 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
4330 if ((!pi->pcie_dpm_key_disabled) &&
4331 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4333 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4337 ret = ci_dpm_force_state_pcie(adev, level);
4340 for (i = 0; i < adev->usec_timeout; i++) {
4341 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4342 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4343 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4350 if ((!pi->sclk_dpm_key_disabled) &&
4351 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4353 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4357 ret = ci_dpm_force_state_sclk(adev, levels);
4360 for (i = 0; i < adev->usec_timeout; i++) {
4361 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4362 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4363 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4370 if ((!pi->mclk_dpm_key_disabled) &&
4371 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4373 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4377 ret = ci_dpm_force_state_mclk(adev, levels);
4380 for (i = 0; i < adev->usec_timeout; i++) {
4381 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4382 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4383 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4390 if ((!pi->pcie_dpm_key_disabled) &&
4391 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4393 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4397 ret = ci_dpm_force_state_pcie(adev, level);
4400 for (i = 0; i < adev->usec_timeout; i++) {
4401 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4402 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4403 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4410 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
4411 if ((!pi->sclk_dpm_key_disabled) &&
4412 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4413 levels = ci_get_lowest_enabled_level(adev,
4414 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4415 ret = ci_dpm_force_state_sclk(adev, levels);
4418 for (i = 0; i < adev->usec_timeout; i++) {
4419 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4420 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4421 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4427 if ((!pi->mclk_dpm_key_disabled) &&
4428 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4429 levels = ci_get_lowest_enabled_level(adev,
4430 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4431 ret = ci_dpm_force_state_mclk(adev, levels);
4434 for (i = 0; i < adev->usec_timeout; i++) {
4435 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4436 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4437 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4443 if ((!pi->pcie_dpm_key_disabled) &&
4444 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4445 levels = ci_get_lowest_enabled_level(adev,
4446 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4447 ret = ci_dpm_force_state_pcie(adev, levels);
4450 for (i = 0; i < adev->usec_timeout; i++) {
4451 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4452 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4453 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4459 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
4460 if (!pi->pcie_dpm_key_disabled) {
4461 PPSMC_Result smc_result;
4463 smc_result = amdgpu_ci_send_msg_to_smc(adev,
4464 PPSMC_MSG_PCIeDPM_UnForceLevel);
4465 if (smc_result != PPSMC_Result_OK)
4468 ret = ci_upload_dpm_level_enable_mask(adev);
4473 adev->pm.dpm.forced_level = level;
4478 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4479 struct ci_mc_reg_table *table)
4484 for (i = 0, j = table->last; i < table->last; i++) {
4485 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4487 switch(table->mc_reg_address[i].s1) {
4488 case mmMC_SEQ_MISC1:
4489 temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4490 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4491 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4492 for (k = 0; k < table->num_entries; k++) {
4493 table->mc_reg_table_entry[k].mc_data[j] =
4494 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4497 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4500 temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4501 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4502 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4503 for (k = 0; k < table->num_entries; k++) {
4504 table->mc_reg_table_entry[k].mc_data[j] =
4505 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4506 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4507 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4510 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4513 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4514 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4515 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4516 for (k = 0; k < table->num_entries; k++) {
4517 table->mc_reg_table_entry[k].mc_data[j] =
4518 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4521 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4525 case mmMC_SEQ_RESERVE_M:
4526 temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4527 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4528 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4529 for (k = 0; k < table->num_entries; k++) {
4530 table->mc_reg_table_entry[k].mc_data[j] =
4531 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4534 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4548 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4553 case mmMC_SEQ_RAS_TIMING:
4554 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4556 case mmMC_SEQ_DLL_STBY:
4557 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4559 case mmMC_SEQ_G5PDX_CMD0:
4560 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4562 case mmMC_SEQ_G5PDX_CMD1:
4563 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4565 case mmMC_SEQ_G5PDX_CTRL:
4566 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4568 case mmMC_SEQ_CAS_TIMING:
4569 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4571 case mmMC_SEQ_MISC_TIMING:
4572 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4574 case mmMC_SEQ_MISC_TIMING2:
4575 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4577 case mmMC_SEQ_PMG_DVS_CMD:
4578 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4580 case mmMC_SEQ_PMG_DVS_CTL:
4581 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4583 case mmMC_SEQ_RD_CTL_D0:
4584 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4586 case mmMC_SEQ_RD_CTL_D1:
4587 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4589 case mmMC_SEQ_WR_CTL_D0:
4590 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4592 case mmMC_SEQ_WR_CTL_D1:
4593 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4595 case mmMC_PMG_CMD_EMRS:
4596 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4598 case mmMC_PMG_CMD_MRS:
4599 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4601 case mmMC_PMG_CMD_MRS1:
4602 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4604 case mmMC_SEQ_PMG_TIMING:
4605 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4607 case mmMC_PMG_CMD_MRS2:
4608 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4610 case mmMC_SEQ_WR_CTL_2:
4611 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4621 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4625 for (i = 0; i < table->last; i++) {
4626 for (j = 1; j < table->num_entries; j++) {
4627 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4628 table->mc_reg_table_entry[j].mc_data[i]) {
4629 table->valid_flag |= 1 << i;
4636 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4641 for (i = 0; i < table->last; i++) {
4642 table->mc_reg_address[i].s0 =
4643 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4644 address : table->mc_reg_address[i].s1;
4648 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4649 struct ci_mc_reg_table *ci_table)
4653 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4655 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4658 for (i = 0; i < table->last; i++)
4659 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4661 ci_table->last = table->last;
4663 for (i = 0; i < table->num_entries; i++) {
4664 ci_table->mc_reg_table_entry[i].mclk_max =
4665 table->mc_reg_table_entry[i].mclk_max;
4666 for (j = 0; j < table->last; j++)
4667 ci_table->mc_reg_table_entry[i].mc_data[j] =
4668 table->mc_reg_table_entry[i].mc_data[j];
4670 ci_table->num_entries = table->num_entries;
4675 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4676 struct ci_mc_reg_table *table)
4682 tmp = RREG32(mmMC_SEQ_MISC0);
4683 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4686 ((adev->pdev->device == 0x67B0) ||
4687 (adev->pdev->device == 0x67B1))) {
4688 for (i = 0; i < table->last; i++) {
4689 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4691 switch (table->mc_reg_address[i].s1) {
4692 case mmMC_SEQ_MISC1:
4693 for (k = 0; k < table->num_entries; k++) {
4694 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4695 (table->mc_reg_table_entry[k].mclk_max == 137500))
4696 table->mc_reg_table_entry[k].mc_data[i] =
4697 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4701 case mmMC_SEQ_WR_CTL_D0:
4702 for (k = 0; k < table->num_entries; k++) {
4703 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4704 (table->mc_reg_table_entry[k].mclk_max == 137500))
4705 table->mc_reg_table_entry[k].mc_data[i] =
4706 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4710 case mmMC_SEQ_WR_CTL_D1:
4711 for (k = 0; k < table->num_entries; k++) {
4712 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4713 (table->mc_reg_table_entry[k].mclk_max == 137500))
4714 table->mc_reg_table_entry[k].mc_data[i] =
4715 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4719 case mmMC_SEQ_WR_CTL_2:
4720 for (k = 0; k < table->num_entries; k++) {
4721 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4722 (table->mc_reg_table_entry[k].mclk_max == 137500))
4723 table->mc_reg_table_entry[k].mc_data[i] = 0;
4726 case mmMC_SEQ_CAS_TIMING:
4727 for (k = 0; k < table->num_entries; k++) {
4728 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4729 table->mc_reg_table_entry[k].mc_data[i] =
4730 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4732 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4733 table->mc_reg_table_entry[k].mc_data[i] =
4734 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4738 case mmMC_SEQ_MISC_TIMING:
4739 for (k = 0; k < table->num_entries; k++) {
4740 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4741 table->mc_reg_table_entry[k].mc_data[i] =
4742 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4744 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4745 table->mc_reg_table_entry[k].mc_data[i] =
4746 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4755 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4756 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4757 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4758 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4759 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4765 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4767 struct ci_power_info *pi = ci_get_pi(adev);
4768 struct atom_mc_reg_table *table;
4769 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4770 u8 module_index = ci_get_memory_module_index(adev);
4773 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4777 WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4778 WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4779 WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4780 WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4781 WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4782 WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4783 WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4784 WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4785 WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4786 WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4787 WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4788 WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4789 WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4790 WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4791 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4792 WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4793 WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4794 WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4795 WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4796 WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4798 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4802 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4806 ci_set_s0_mc_reg_index(ci_table);
4808 ret = ci_register_patching_mc_seq(adev, ci_table);
4812 ret = ci_set_mc_special_registers(adev, ci_table);
4816 ci_set_valid_flag(ci_table);
4824 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4825 SMU7_Discrete_MCRegisters *mc_reg_table)
4827 struct ci_power_info *pi = ci_get_pi(adev);
4830 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4831 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4832 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4834 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4835 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4840 mc_reg_table->last = (u8)i;
4845 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4846 SMU7_Discrete_MCRegisterSet *data,
4847 u32 num_entries, u32 valid_flag)
4851 for (i = 0, j = 0; j < num_entries; j++) {
4852 if (valid_flag & (1 << j)) {
4853 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4859 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4860 const u32 memory_clock,
4861 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4863 struct ci_power_info *pi = ci_get_pi(adev);
4866 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4867 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4871 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4874 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4875 mc_reg_table_data, pi->mc_reg_table.last,
4876 pi->mc_reg_table.valid_flag);
4879 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4880 SMU7_Discrete_MCRegisters *mc_reg_table)
4882 struct ci_power_info *pi = ci_get_pi(adev);
4885 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4886 ci_convert_mc_reg_table_entry_to_smc(adev,
4887 pi->dpm_table.mclk_table.dpm_levels[i].value,
4888 &mc_reg_table->data[i]);
4891 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4893 struct ci_power_info *pi = ci_get_pi(adev);
4896 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4898 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4901 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4903 return amdgpu_ci_copy_bytes_to_smc(adev,
4904 pi->mc_reg_table_start,
4905 (u8 *)&pi->smc_mc_reg_table,
4906 sizeof(SMU7_Discrete_MCRegisters),
4910 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4912 struct ci_power_info *pi = ci_get_pi(adev);
4914 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4917 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4919 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4921 return amdgpu_ci_copy_bytes_to_smc(adev,
4922 pi->mc_reg_table_start +
4923 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4924 (u8 *)&pi->smc_mc_reg_table.data[0],
4925 sizeof(SMU7_Discrete_MCRegisterSet) *
4926 pi->dpm_table.mclk_table.count,
4930 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4932 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4934 tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4935 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4938 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4939 struct amdgpu_ps *amdgpu_state)
4941 struct ci_ps *state = ci_get_ps(amdgpu_state);
4943 u16 pcie_speed, max_speed = 0;
4945 for (i = 0; i < state->performance_level_count; i++) {
4946 pcie_speed = state->performance_levels[i].pcie_gen;
4947 if (max_speed < pcie_speed)
4948 max_speed = pcie_speed;
4954 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4958 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4959 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4960 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4962 return (u16)speed_cntl;
4965 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
4969 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
4970 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
4971 link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4973 switch (link_width) {
4989 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
4990 struct amdgpu_ps *amdgpu_new_state,
4991 struct amdgpu_ps *amdgpu_current_state)
4993 struct ci_power_info *pi = ci_get_pi(adev);
4994 enum amdgpu_pcie_gen target_link_speed =
4995 ci_get_maximum_link_speed(adev, amdgpu_new_state);
4996 enum amdgpu_pcie_gen current_link_speed;
4998 if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
4999 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
5001 current_link_speed = pi->force_pcie_gen;
5003 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5004 pi->pspp_notify_required = false;
5005 if (target_link_speed > current_link_speed) {
5006 switch (target_link_speed) {
5008 case AMDGPU_PCIE_GEN3:
5009 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5011 pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
5012 if (current_link_speed == AMDGPU_PCIE_GEN2)
5014 case AMDGPU_PCIE_GEN2:
5015 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5019 pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
5023 if (target_link_speed < current_link_speed)
5024 pi->pspp_notify_required = true;
5028 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5029 struct amdgpu_ps *amdgpu_new_state,
5030 struct amdgpu_ps *amdgpu_current_state)
5032 struct ci_power_info *pi = ci_get_pi(adev);
5033 enum amdgpu_pcie_gen target_link_speed =
5034 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5037 if (pi->pspp_notify_required) {
5038 if (target_link_speed == AMDGPU_PCIE_GEN3)
5039 request = PCIE_PERF_REQ_PECI_GEN3;
5040 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5041 request = PCIE_PERF_REQ_PECI_GEN2;
5043 request = PCIE_PERF_REQ_PECI_GEN1;
5045 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5046 (ci_get_current_pcie_speed(adev) > 0))
5050 amdgpu_acpi_pcie_performance_request(adev, request, false);
5055 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5057 struct ci_power_info *pi = ci_get_pi(adev);
5058 struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5059 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5060 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5061 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5062 struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5063 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5065 if (allowed_sclk_vddc_table == NULL)
5067 if (allowed_sclk_vddc_table->count < 1)
5069 if (allowed_mclk_vddc_table == NULL)
5071 if (allowed_mclk_vddc_table->count < 1)
5073 if (allowed_mclk_vddci_table == NULL)
5075 if (allowed_mclk_vddci_table->count < 1)
5078 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5079 pi->max_vddc_in_pp_table =
5080 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5082 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5083 pi->max_vddci_in_pp_table =
5084 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5086 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5087 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5088 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5089 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5090 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5091 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5092 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5093 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5098 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5100 struct ci_power_info *pi = ci_get_pi(adev);
5101 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5104 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5105 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5106 *vddc = leakage_table->actual_voltage[leakage_index];
5112 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5114 struct ci_power_info *pi = ci_get_pi(adev);
5115 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5118 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5119 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5120 *vddci = leakage_table->actual_voltage[leakage_index];
5126 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5127 struct amdgpu_clock_voltage_dependency_table *table)
5132 for (i = 0; i < table->count; i++)
5133 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5137 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5138 struct amdgpu_clock_voltage_dependency_table *table)
5143 for (i = 0; i < table->count; i++)
5144 ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5148 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5149 struct amdgpu_vce_clock_voltage_dependency_table *table)
5154 for (i = 0; i < table->count; i++)
5155 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5159 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5160 struct amdgpu_uvd_clock_voltage_dependency_table *table)
5165 for (i = 0; i < table->count; i++)
5166 ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5170 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5171 struct amdgpu_phase_shedding_limits_table *table)
5176 for (i = 0; i < table->count; i++)
5177 ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5181 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5182 struct amdgpu_clock_and_voltage_limits *table)
5185 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5186 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5190 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5191 struct amdgpu_cac_leakage_table *table)
5196 for (i = 0; i < table->count; i++)
5197 ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5201 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5204 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5205 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5206 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5207 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5208 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5209 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5210 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5211 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5212 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5213 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5214 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5215 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5216 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5217 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5218 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5219 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5220 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5221 &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5222 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5223 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5224 ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5225 &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5226 ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5227 &adev->pm.dpm.dyn_state.cac_leakage_table);
5231 static void ci_update_current_ps(struct amdgpu_device *adev,
5232 struct amdgpu_ps *rps)
5234 struct ci_ps *new_ps = ci_get_ps(rps);
5235 struct ci_power_info *pi = ci_get_pi(adev);
5237 pi->current_rps = *rps;
5238 pi->current_ps = *new_ps;
5239 pi->current_rps.ps_priv = &pi->current_ps;
5242 static void ci_update_requested_ps(struct amdgpu_device *adev,
5243 struct amdgpu_ps *rps)
5245 struct ci_ps *new_ps = ci_get_ps(rps);
5246 struct ci_power_info *pi = ci_get_pi(adev);
5248 pi->requested_rps = *rps;
5249 pi->requested_ps = *new_ps;
5250 pi->requested_rps.ps_priv = &pi->requested_ps;
5253 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5255 struct ci_power_info *pi = ci_get_pi(adev);
5256 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5257 struct amdgpu_ps *new_ps = &requested_ps;
5259 ci_update_requested_ps(adev, new_ps);
5261 ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5266 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5268 struct ci_power_info *pi = ci_get_pi(adev);
5269 struct amdgpu_ps *new_ps = &pi->requested_rps;
5271 ci_update_current_ps(adev, new_ps);
5275 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5277 ci_read_clock_registers(adev);
5278 ci_enable_acpi_power_management(adev);
5279 ci_init_sclk_t(adev);
5282 static int ci_dpm_enable(struct amdgpu_device *adev)
5284 struct ci_power_info *pi = ci_get_pi(adev);
5285 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5288 if (amdgpu_ci_is_smc_running(adev))
5290 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5291 ci_enable_voltage_control(adev);
5292 ret = ci_construct_voltage_tables(adev);
5294 DRM_ERROR("ci_construct_voltage_tables failed\n");
5298 if (pi->caps_dynamic_ac_timing) {
5299 ret = ci_initialize_mc_reg_table(adev);
5301 pi->caps_dynamic_ac_timing = false;
5304 ci_enable_spread_spectrum(adev, true);
5305 if (pi->thermal_protection)
5306 ci_enable_thermal_protection(adev, true);
5307 ci_program_sstp(adev);
5308 ci_enable_display_gap(adev);
5309 ci_program_vc(adev);
5310 ret = ci_upload_firmware(adev);
5312 DRM_ERROR("ci_upload_firmware failed\n");
5315 ret = ci_process_firmware_header(adev);
5317 DRM_ERROR("ci_process_firmware_header failed\n");
5320 ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5322 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5325 ret = ci_init_smc_table(adev);
5327 DRM_ERROR("ci_init_smc_table failed\n");
5330 ret = ci_init_arb_table_index(adev);
5332 DRM_ERROR("ci_init_arb_table_index failed\n");
5335 if (pi->caps_dynamic_ac_timing) {
5336 ret = ci_populate_initial_mc_reg_table(adev);
5338 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5342 ret = ci_populate_pm_base(adev);
5344 DRM_ERROR("ci_populate_pm_base failed\n");
5347 ci_dpm_start_smc(adev);
5348 ci_enable_vr_hot_gpio_interrupt(adev);
5349 ret = ci_notify_smc_display_change(adev, false);
5351 DRM_ERROR("ci_notify_smc_display_change failed\n");
5354 ci_enable_sclk_control(adev, true);
5355 ret = ci_enable_ulv(adev, true);
5357 DRM_ERROR("ci_enable_ulv failed\n");
5360 ret = ci_enable_ds_master_switch(adev, true);
5362 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5365 ret = ci_start_dpm(adev);
5367 DRM_ERROR("ci_start_dpm failed\n");
5370 ret = ci_enable_didt(adev, true);
5372 DRM_ERROR("ci_enable_didt failed\n");
5375 ret = ci_enable_smc_cac(adev, true);
5377 DRM_ERROR("ci_enable_smc_cac failed\n");
5380 ret = ci_enable_power_containment(adev, true);
5382 DRM_ERROR("ci_enable_power_containment failed\n");
5386 ret = ci_power_control_set_level(adev);
5388 DRM_ERROR("ci_power_control_set_level failed\n");
5392 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5394 ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5396 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5400 ci_thermal_start_thermal_controller(adev);
5402 ci_update_current_ps(adev, boot_ps);
5404 if (adev->irq.installed &&
5405 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
5407 PPSMC_Result result;
5409 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
5410 CISLANDS_TEMP_RANGE_MAX);
5412 DRM_ERROR("ci_thermal_set_temperature_range failed\n");
5415 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
5416 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5417 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
5418 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5421 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
5423 if (result != PPSMC_Result_OK)
5424 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5431 static void ci_dpm_disable(struct amdgpu_device *adev)
5433 struct ci_power_info *pi = ci_get_pi(adev);
5434 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5436 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5437 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5438 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5439 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5441 ci_dpm_powergate_uvd(adev, false);
5443 if (!amdgpu_ci_is_smc_running(adev))
5446 ci_thermal_stop_thermal_controller(adev);
5448 if (pi->thermal_protection)
5449 ci_enable_thermal_protection(adev, false);
5450 ci_enable_power_containment(adev, false);
5451 ci_enable_smc_cac(adev, false);
5452 ci_enable_didt(adev, false);
5453 ci_enable_spread_spectrum(adev, false);
5454 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5456 ci_enable_ds_master_switch(adev, false);
5457 ci_enable_ulv(adev, false);
5459 ci_reset_to_default(adev);
5460 ci_dpm_stop_smc(adev);
5461 ci_force_switch_to_arb_f0(adev);
5462 ci_enable_thermal_based_sclk_dpm(adev, false);
5464 ci_update_current_ps(adev, boot_ps);
5467 static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5469 struct ci_power_info *pi = ci_get_pi(adev);
5470 struct amdgpu_ps *new_ps = &pi->requested_rps;
5471 struct amdgpu_ps *old_ps = &pi->current_rps;
5474 ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5475 if (pi->pcie_performance_request)
5476 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5477 ret = ci_freeze_sclk_mclk_dpm(adev);
5479 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5482 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5484 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5487 ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5489 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5493 ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5495 DRM_ERROR("ci_update_vce_dpm failed\n");
5499 ret = ci_update_sclk_t(adev);
5501 DRM_ERROR("ci_update_sclk_t failed\n");
5504 if (pi->caps_dynamic_ac_timing) {
5505 ret = ci_update_and_upload_mc_reg_table(adev);
5507 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5511 ret = ci_program_memory_timing_parameters(adev);
5513 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5516 ret = ci_unfreeze_sclk_mclk_dpm(adev);
5518 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5521 ret = ci_upload_dpm_level_enable_mask(adev);
5523 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5526 if (pi->pcie_performance_request)
5527 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5533 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5535 ci_set_boot_state(adev);
5539 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5541 ci_program_display_gap(adev);
5545 struct _ATOM_POWERPLAY_INFO info;
5546 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5547 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5548 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5549 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5550 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5553 union pplib_clock_info {
5554 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5555 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5556 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5557 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5558 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5559 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5562 union pplib_power_state {
5563 struct _ATOM_PPLIB_STATE v1;
5564 struct _ATOM_PPLIB_STATE_V2 v2;
5567 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5568 struct amdgpu_ps *rps,
5569 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5572 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5573 rps->class = le16_to_cpu(non_clock_info->usClassification);
5574 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5576 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5577 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5578 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5584 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5585 adev->pm.dpm.boot_ps = rps;
5586 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5587 adev->pm.dpm.uvd_ps = rps;
5590 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5591 struct amdgpu_ps *rps, int index,
5592 union pplib_clock_info *clock_info)
5594 struct ci_power_info *pi = ci_get_pi(adev);
5595 struct ci_ps *ps = ci_get_ps(rps);
5596 struct ci_pl *pl = &ps->performance_levels[index];
5598 ps->performance_level_count = index + 1;
5600 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5601 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5602 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5603 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5605 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5607 pi->vbios_boot_state.pcie_gen_bootup_value,
5608 clock_info->ci.ucPCIEGen);
5609 pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5610 pi->vbios_boot_state.pcie_lane_bootup_value,
5611 le16_to_cpu(clock_info->ci.usPCIELane));
5613 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5614 pi->acpi_pcie_gen = pl->pcie_gen;
5617 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5618 pi->ulv.supported = true;
5620 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5623 /* patch up boot state */
5624 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5625 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5626 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5627 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5628 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5631 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5632 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5633 pi->use_pcie_powersaving_levels = true;
5634 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5635 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5636 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5637 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5638 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5639 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5640 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5641 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5643 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5644 pi->use_pcie_performance_levels = true;
5645 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5646 pi->pcie_gen_performance.max = pl->pcie_gen;
5647 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5648 pi->pcie_gen_performance.min = pl->pcie_gen;
5649 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5650 pi->pcie_lane_performance.max = pl->pcie_lane;
5651 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5652 pi->pcie_lane_performance.min = pl->pcie_lane;
5659 static int ci_parse_power_table(struct amdgpu_device *adev)
5661 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5662 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5663 union pplib_power_state *power_state;
5664 int i, j, k, non_clock_array_index, clock_array_index;
5665 union pplib_clock_info *clock_info;
5666 struct _StateArray *state_array;
5667 struct _ClockInfoArray *clock_info_array;
5668 struct _NonClockInfoArray *non_clock_info_array;
5669 union power_info *power_info;
5670 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5673 u8 *power_state_offset;
5676 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5677 &frev, &crev, &data_offset))
5679 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5681 amdgpu_add_thermal_controller(adev);
5683 state_array = (struct _StateArray *)
5684 (mode_info->atom_context->bios + data_offset +
5685 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5686 clock_info_array = (struct _ClockInfoArray *)
5687 (mode_info->atom_context->bios + data_offset +
5688 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5689 non_clock_info_array = (struct _NonClockInfoArray *)
5690 (mode_info->atom_context->bios + data_offset +
5691 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5693 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5694 state_array->ucNumEntries, GFP_KERNEL);
5695 if (!adev->pm.dpm.ps)
5697 power_state_offset = (u8 *)state_array->states;
5698 for (i = 0; i < state_array->ucNumEntries; i++) {
5700 power_state = (union pplib_power_state *)power_state_offset;
5701 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5702 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5703 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5704 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5706 kfree(adev->pm.dpm.ps);
5709 adev->pm.dpm.ps[i].ps_priv = ps;
5710 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5712 non_clock_info_array->ucEntrySize);
5714 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5715 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5716 clock_array_index = idx[j];
5717 if (clock_array_index >= clock_info_array->ucNumEntries)
5719 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5721 clock_info = (union pplib_clock_info *)
5722 ((u8 *)&clock_info_array->clockInfo[0] +
5723 (clock_array_index * clock_info_array->ucEntrySize));
5724 ci_parse_pplib_clock_info(adev,
5725 &adev->pm.dpm.ps[i], k,
5729 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5731 adev->pm.dpm.num_ps = state_array->ucNumEntries;
5733 /* fill in the vce power states */
5734 for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
5736 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5737 clock_info = (union pplib_clock_info *)
5738 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5739 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5740 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5741 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5742 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5743 adev->pm.dpm.vce_states[i].sclk = sclk;
5744 adev->pm.dpm.vce_states[i].mclk = mclk;
5750 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5751 struct ci_vbios_boot_state *boot_state)
5753 struct amdgpu_mode_info *mode_info = &adev->mode_info;
5754 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5755 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5759 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5760 &frev, &crev, &data_offset)) {
5762 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5764 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5765 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5766 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5767 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5768 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5769 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5770 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5777 static void ci_dpm_fini(struct amdgpu_device *adev)
5781 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5782 kfree(adev->pm.dpm.ps[i].ps_priv);
5784 kfree(adev->pm.dpm.ps);
5785 kfree(adev->pm.dpm.priv);
5786 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5787 amdgpu_free_extended_power_table(adev);
5791 * ci_dpm_init_microcode - load ucode images from disk
5793 * @adev: amdgpu_device pointer
5795 * Use the firmware interface to load the ucode images into
5796 * the driver (not loaded into hw).
5797 * Returns 0 on success, error on failure.
5799 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5801 const char *chip_name;
5807 switch (adev->asic_type) {
5809 chip_name = "bonaire";
5812 chip_name = "hawaii";
5819 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
5820 err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
5823 err = amdgpu_ucode_validate(adev->pm.fw);
5828 "cik_smc: Failed to load firmware \"%s\"\n",
5830 release_firmware(adev->pm.fw);
5836 static int ci_dpm_init(struct amdgpu_device *adev)
5838 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5839 SMU7_Discrete_DpmTable *dpm_table;
5840 struct amdgpu_gpio_rec gpio;
5841 u16 data_offset, size;
5843 struct ci_power_info *pi;
5847 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5850 adev->pm.dpm.priv = pi;
5852 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
5854 pi->sys_pcie_mask = 0;
5856 pi->sys_pcie_mask = mask;
5857 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5859 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5860 pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5861 pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5862 pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5864 pi->pcie_lane_performance.max = 0;
5865 pi->pcie_lane_performance.min = 16;
5866 pi->pcie_lane_powersaving.max = 0;
5867 pi->pcie_lane_powersaving.min = 16;
5869 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5875 ret = amdgpu_get_platform_caps(adev);
5881 ret = amdgpu_parse_extended_power_table(adev);
5887 ret = ci_parse_power_table(adev);
5893 pi->dll_default_on = false;
5894 pi->sram_end = SMC_RAM_END;
5896 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5897 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5898 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5899 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5900 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5901 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5902 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5903 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5905 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5907 pi->sclk_dpm_key_disabled = 0;
5908 pi->mclk_dpm_key_disabled = 0;
5909 pi->pcie_dpm_key_disabled = 0;
5910 pi->thermal_sclk_dpm_enabled = 0;
5912 pi->caps_sclk_ds = true;
5914 pi->mclk_strobe_mode_threshold = 40000;
5915 pi->mclk_stutter_mode_threshold = 40000;
5916 pi->mclk_edc_enable_threshold = 40000;
5917 pi->mclk_edc_wr_enable_threshold = 40000;
5919 ci_initialize_powertune_defaults(adev);
5921 pi->caps_fps = false;
5923 pi->caps_sclk_throttle_low_notification = false;
5925 pi->caps_uvd_dpm = true;
5926 pi->caps_vce_dpm = true;
5928 ci_get_leakage_voltages(adev);
5929 ci_patch_dependency_tables_with_leakage(adev);
5930 ci_set_private_data_variables_based_on_pptable(adev);
5932 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5933 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5934 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5938 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5939 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5940 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5941 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5942 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5943 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5944 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5945 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5946 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5948 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5949 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5950 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5952 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5953 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5954 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5955 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5957 if (adev->asic_type == CHIP_HAWAII) {
5958 pi->thermal_temp_setting.temperature_low = 94500;
5959 pi->thermal_temp_setting.temperature_high = 95000;
5960 pi->thermal_temp_setting.temperature_shutdown = 104000;
5962 pi->thermal_temp_setting.temperature_low = 99500;
5963 pi->thermal_temp_setting.temperature_high = 100000;
5964 pi->thermal_temp_setting.temperature_shutdown = 104000;
5967 pi->uvd_enabled = false;
5969 dpm_table = &pi->smc_state_table;
5971 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5973 dpm_table->VRHotGpio = gpio.shift;
5974 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5976 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5977 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5980 gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
5982 dpm_table->AcDcGpio = gpio.shift;
5983 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5985 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5986 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5989 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
5991 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
5993 switch (gpio.shift) {
5995 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5996 tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5999 tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
6000 tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
6003 tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
6006 tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
6009 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
6012 DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
6015 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
6018 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6019 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6020 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
6021 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
6022 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6023 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
6024 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6026 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
6027 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
6028 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6029 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
6030 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6032 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
6035 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
6036 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
6037 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
6038 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
6039 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
6041 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
6044 pi->vddc_phase_shed_control = true;
6046 #if defined(CONFIG_ACPI)
6047 pi->pcie_performance_request =
6048 amdgpu_acpi_is_pcie_performance_request_supported(adev);
6050 pi->pcie_performance_request = false;
6053 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6054 &frev, &crev, &data_offset)) {
6055 pi->caps_sclk_ss_support = true;
6056 pi->caps_mclk_ss_support = true;
6057 pi->dynamic_ss = true;
6059 pi->caps_sclk_ss_support = false;
6060 pi->caps_mclk_ss_support = false;
6061 pi->dynamic_ss = true;
6064 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6065 pi->thermal_protection = true;
6067 pi->thermal_protection = false;
6069 pi->caps_dynamic_ac_timing = true;
6071 pi->uvd_power_gated = false;
6073 /* make sure dc limits are valid */
6074 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6075 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6076 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6077 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6079 pi->fan_ctrl_is_in_default_mode = true;
6085 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6088 struct ci_power_info *pi = ci_get_pi(adev);
6089 struct amdgpu_ps *rps = &pi->current_rps;
6090 u32 sclk = ci_get_average_sclk_freq(adev);
6091 u32 mclk = ci_get_average_mclk_freq(adev);
6093 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
6094 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6095 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
6099 static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6100 struct amdgpu_ps *rps)
6102 struct ci_ps *ps = ci_get_ps(rps);
6106 amdgpu_dpm_print_class_info(rps->class, rps->class2);
6107 amdgpu_dpm_print_cap_info(rps->caps);
6108 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6109 for (i = 0; i < ps->performance_level_count; i++) {
6110 pl = &ps->performance_levels[i];
6111 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6112 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6114 amdgpu_dpm_print_ps_status(adev, rps);
6117 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6119 struct ci_power_info *pi = ci_get_pi(adev);
6120 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6123 return requested_state->performance_levels[0].sclk;
6125 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6128 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6130 struct ci_power_info *pi = ci_get_pi(adev);
6131 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6134 return requested_state->performance_levels[0].mclk;
6136 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6139 /* get temperature in millidegrees */
6140 static int ci_dpm_get_temp(struct amdgpu_device *adev)
6143 int actual_temp = 0;
6145 temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6146 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6151 actual_temp = temp & 0x1ff;
6153 actual_temp = actual_temp * 1000;
6158 static int ci_set_temperature_range(struct amdgpu_device *adev)
6162 ret = ci_thermal_enable_alert(adev, false);
6165 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6166 CISLANDS_TEMP_RANGE_MAX);
6169 ret = ci_thermal_enable_alert(adev, true);
6175 static int ci_dpm_early_init(void *handle)
6177 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6179 ci_dpm_set_dpm_funcs(adev);
6180 ci_dpm_set_irq_funcs(adev);
6185 static int ci_dpm_late_init(void *handle)
6188 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6193 /* init the sysfs and debugfs files late */
6194 ret = amdgpu_pm_sysfs_init(adev);
6198 ret = ci_set_temperature_range(adev);
6202 ci_dpm_powergate_uvd(adev, true);
6207 static int ci_dpm_sw_init(void *handle)
6210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6212 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
6216 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
6220 /* default to balanced state */
6221 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6222 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6223 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
6224 adev->pm.default_sclk = adev->clock.default_sclk;
6225 adev->pm.default_mclk = adev->clock.default_mclk;
6226 adev->pm.current_sclk = adev->clock.default_sclk;
6227 adev->pm.current_mclk = adev->clock.default_mclk;
6228 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6230 if (amdgpu_dpm == 0)
6233 ret = ci_dpm_init_microcode(adev);
6237 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6238 mutex_lock(&adev->pm.mutex);
6239 ret = ci_dpm_init(adev);
6242 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6243 if (amdgpu_dpm == 1)
6244 amdgpu_pm_print_power_states(adev);
6245 mutex_unlock(&adev->pm.mutex);
6246 DRM_INFO("amdgpu: dpm initialized\n");
6252 mutex_unlock(&adev->pm.mutex);
6253 DRM_ERROR("amdgpu: dpm initialization failed\n");
6257 static int ci_dpm_sw_fini(void *handle)
6259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6261 mutex_lock(&adev->pm.mutex);
6262 amdgpu_pm_sysfs_fini(adev);
6264 mutex_unlock(&adev->pm.mutex);
6269 static int ci_dpm_hw_init(void *handle)
6273 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6278 mutex_lock(&adev->pm.mutex);
6279 ci_dpm_setup_asic(adev);
6280 ret = ci_dpm_enable(adev);
6282 adev->pm.dpm_enabled = false;
6284 adev->pm.dpm_enabled = true;
6285 mutex_unlock(&adev->pm.mutex);
6290 static int ci_dpm_hw_fini(void *handle)
6292 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6294 if (adev->pm.dpm_enabled) {
6295 mutex_lock(&adev->pm.mutex);
6296 ci_dpm_disable(adev);
6297 mutex_unlock(&adev->pm.mutex);
6303 static int ci_dpm_suspend(void *handle)
6305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6307 if (adev->pm.dpm_enabled) {
6308 mutex_lock(&adev->pm.mutex);
6310 ci_dpm_disable(adev);
6311 /* reset the power state */
6312 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6313 mutex_unlock(&adev->pm.mutex);
6318 static int ci_dpm_resume(void *handle)
6321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6323 if (adev->pm.dpm_enabled) {
6324 /* asic init will reset to the boot state */
6325 mutex_lock(&adev->pm.mutex);
6326 ci_dpm_setup_asic(adev);
6327 ret = ci_dpm_enable(adev);
6329 adev->pm.dpm_enabled = false;
6331 adev->pm.dpm_enabled = true;
6332 mutex_unlock(&adev->pm.mutex);
6333 if (adev->pm.dpm_enabled)
6334 amdgpu_pm_compute_clocks(adev);
6339 static bool ci_dpm_is_idle(void *handle)
6345 static int ci_dpm_wait_for_idle(void *handle)
6351 static void ci_dpm_print_status(void *handle)
6353 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6355 dev_info(adev->dev, "CIK DPM registers\n");
6356 dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n",
6357 RREG32(mmBIOS_SCRATCH_4));
6358 dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n",
6359 RREG32(mmMC_ARB_DRAM_TIMING));
6360 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n",
6361 RREG32(mmMC_ARB_DRAM_TIMING2));
6362 dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n",
6363 RREG32(mmMC_ARB_BURST_TIME));
6364 dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n",
6365 RREG32(mmMC_ARB_DRAM_TIMING_1));
6366 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n",
6367 RREG32(mmMC_ARB_DRAM_TIMING2_1));
6368 dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n",
6369 RREG32(mmMC_CG_CONFIG));
6370 dev_info(adev->dev, " MC_ARB_CG=0x%08X\n",
6371 RREG32(mmMC_ARB_CG));
6372 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
6373 RREG32_DIDT(ixDIDT_SQ_CTRL0));
6374 dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n",
6375 RREG32_DIDT(ixDIDT_DB_CTRL0));
6376 dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n",
6377 RREG32_DIDT(ixDIDT_TD_CTRL0));
6378 dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n",
6379 RREG32_DIDT(ixDIDT_TCP_CTRL0));
6380 dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n",
6381 RREG32_SMC(ixCG_THERMAL_INT));
6382 dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n",
6383 RREG32_SMC(ixCG_THERMAL_CTRL));
6384 dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n",
6385 RREG32_SMC(ixGENERAL_PWRMGT));
6386 dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n",
6387 RREG32(mmMC_SEQ_CNTL_3));
6388 dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n",
6389 RREG32_SMC(ixLCAC_MC0_CNTL));
6390 dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n",
6391 RREG32_SMC(ixLCAC_MC1_CNTL));
6392 dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n",
6393 RREG32_SMC(ixLCAC_CPL_CNTL));
6394 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n",
6395 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
6396 dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n",
6397 RREG32(mmBIF_LNCNT_RESET));
6398 dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n",
6399 RREG32_SMC(ixFIRMWARE_FLAGS));
6400 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n",
6401 RREG32_SMC(ixCG_SPLL_FUNC_CNTL));
6402 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n",
6403 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));
6404 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n",
6405 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));
6406 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n",
6407 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));
6408 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",
6409 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));
6410 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",
6411 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));
6412 dev_info(adev->dev, " DLL_CNTL=0x%08X\n",
6413 RREG32(mmDLL_CNTL));
6414 dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n",
6415 RREG32(mmMCLK_PWRMGT_CNTL));
6416 dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n",
6417 RREG32(mmMPLL_AD_FUNC_CNTL));
6418 dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n",
6419 RREG32(mmMPLL_DQ_FUNC_CNTL));
6420 dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n",
6421 RREG32(mmMPLL_FUNC_CNTL));
6422 dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n",
6423 RREG32(mmMPLL_FUNC_CNTL_1));
6424 dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n",
6425 RREG32(mmMPLL_FUNC_CNTL_2));
6426 dev_info(adev->dev, " MPLL_SS1=0x%08X\n",
6427 RREG32(mmMPLL_SS1));
6428 dev_info(adev->dev, " MPLL_SS2=0x%08X\n",
6429 RREG32(mmMPLL_SS2));
6430 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n",
6431 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));
6432 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n",
6433 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));
6434 dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n",
6435 RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));
6436 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n",
6437 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
6438 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n",
6439 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));
6440 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n",
6441 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));
6442 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n",
6443 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));
6444 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n",
6445 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));
6446 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n",
6447 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));
6448 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n",
6449 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));
6450 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n",
6451 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));
6452 dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n",
6453 RREG32_SMC(ixRCU_UC_EVENTS));
6454 dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n",
6455 RREG32_SMC(ixDPM_TABLE_475));
6456 dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n",
6457 RREG32(mmMC_SEQ_RAS_TIMING_LP));
6458 dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n",
6459 RREG32(mmMC_SEQ_RAS_TIMING));
6460 dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n",
6461 RREG32(mmMC_SEQ_CAS_TIMING_LP));
6462 dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n",
6463 RREG32(mmMC_SEQ_CAS_TIMING));
6464 dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n",
6465 RREG32(mmMC_SEQ_DLL_STBY_LP));
6466 dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n",
6467 RREG32(mmMC_SEQ_DLL_STBY));
6468 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",
6469 RREG32(mmMC_SEQ_G5PDX_CMD0_LP));
6470 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n",
6471 RREG32(mmMC_SEQ_G5PDX_CMD0));
6472 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",
6473 RREG32(mmMC_SEQ_G5PDX_CMD1_LP));
6474 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n",
6475 RREG32(mmMC_SEQ_G5PDX_CMD1));
6476 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",
6477 RREG32(mmMC_SEQ_G5PDX_CTRL_LP));
6478 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n",
6479 RREG32(mmMC_SEQ_G5PDX_CTRL));
6480 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",
6481 RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));
6482 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n",
6483 RREG32(mmMC_SEQ_PMG_DVS_CMD));
6484 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",
6485 RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));
6486 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n",
6487 RREG32(mmMC_SEQ_PMG_DVS_CTL));
6488 dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n",
6489 RREG32(mmMC_SEQ_MISC_TIMING_LP));
6490 dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n",
6491 RREG32(mmMC_SEQ_MISC_TIMING));
6492 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n",
6493 RREG32(mmMC_SEQ_MISC_TIMING2_LP));
6494 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n",
6495 RREG32(mmMC_SEQ_MISC_TIMING2));
6496 dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",
6497 RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));
6498 dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n",
6499 RREG32(mmMC_PMG_CMD_EMRS));
6500 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",
6501 RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));
6502 dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n",
6503 RREG32(mmMC_PMG_CMD_MRS));
6504 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",
6505 RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));
6506 dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n",
6507 RREG32(mmMC_PMG_CMD_MRS1));
6508 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n",
6509 RREG32(mmMC_SEQ_WR_CTL_D0_LP));
6510 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n",
6511 RREG32(mmMC_SEQ_WR_CTL_D0));
6512 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n",
6513 RREG32(mmMC_SEQ_WR_CTL_D1_LP));
6514 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n",
6515 RREG32(mmMC_SEQ_WR_CTL_D1));
6516 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n",
6517 RREG32(mmMC_SEQ_RD_CTL_D0_LP));
6518 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n",
6519 RREG32(mmMC_SEQ_RD_CTL_D0));
6520 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n",
6521 RREG32(mmMC_SEQ_RD_CTL_D1_LP));
6522 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n",
6523 RREG32(mmMC_SEQ_RD_CTL_D1));
6524 dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n",
6525 RREG32(mmMC_SEQ_PMG_TIMING_LP));
6526 dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n",
6527 RREG32(mmMC_SEQ_PMG_TIMING));
6528 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",
6529 RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));
6530 dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n",
6531 RREG32(mmMC_PMG_CMD_MRS2));
6532 dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n",
6533 RREG32(mmMC_SEQ_WR_CTL_2_LP));
6534 dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n",
6535 RREG32(mmMC_SEQ_WR_CTL_2));
6536 dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n",
6537 RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));
6538 dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",
6539 RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));
6540 dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n",
6541 RREG32(mmSMC_IND_INDEX_0));
6542 dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n",
6543 RREG32(mmSMC_IND_DATA_0));
6544 dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n",
6545 RREG32(mmSMC_IND_ACCESS_CNTL));
6546 dev_info(adev->dev, " SMC_RESP_0=0x%08X\n",
6547 RREG32(mmSMC_RESP_0));
6548 dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n",
6549 RREG32(mmSMC_MESSAGE_0));
6550 dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n",
6551 RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));
6552 dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",
6553 RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));
6554 dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n",
6555 RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));
6556 dev_info(adev->dev, " SMC_PC_C=0x%08X\n",
6557 RREG32_SMC(ixSMC_PC_C));
6560 static int ci_dpm_soft_reset(void *handle)
6565 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6566 struct amdgpu_irq_src *source,
6568 enum amdgpu_interrupt_state state)
6573 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6575 case AMDGPU_IRQ_STATE_DISABLE:
6576 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6577 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6578 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6580 case AMDGPU_IRQ_STATE_ENABLE:
6581 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6582 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6583 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6590 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6592 case AMDGPU_IRQ_STATE_DISABLE:
6593 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6594 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6595 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6597 case AMDGPU_IRQ_STATE_ENABLE:
6598 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6599 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6600 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6613 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6614 struct amdgpu_irq_src *source,
6615 struct amdgpu_iv_entry *entry)
6617 bool queue_thermal = false;
6622 switch (entry->src_id) {
6623 case 230: /* thermal low to high */
6624 DRM_DEBUG("IH: thermal low to high\n");
6625 adev->pm.dpm.thermal.high_to_low = false;
6626 queue_thermal = true;
6628 case 231: /* thermal high to low */
6629 DRM_DEBUG("IH: thermal high to low\n");
6630 adev->pm.dpm.thermal.high_to_low = true;
6631 queue_thermal = true;
6638 schedule_work(&adev->pm.dpm.thermal.work);
6643 static int ci_dpm_set_clockgating_state(void *handle,
6644 enum amd_clockgating_state state)
6649 static int ci_dpm_set_powergating_state(void *handle,
6650 enum amd_powergating_state state)
6655 const struct amd_ip_funcs ci_dpm_ip_funcs = {
6656 .early_init = ci_dpm_early_init,
6657 .late_init = ci_dpm_late_init,
6658 .sw_init = ci_dpm_sw_init,
6659 .sw_fini = ci_dpm_sw_fini,
6660 .hw_init = ci_dpm_hw_init,
6661 .hw_fini = ci_dpm_hw_fini,
6662 .suspend = ci_dpm_suspend,
6663 .resume = ci_dpm_resume,
6664 .is_idle = ci_dpm_is_idle,
6665 .wait_for_idle = ci_dpm_wait_for_idle,
6666 .soft_reset = ci_dpm_soft_reset,
6667 .print_status = ci_dpm_print_status,
6668 .set_clockgating_state = ci_dpm_set_clockgating_state,
6669 .set_powergating_state = ci_dpm_set_powergating_state,
6672 static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
6673 .get_temperature = &ci_dpm_get_temp,
6674 .pre_set_power_state = &ci_dpm_pre_set_power_state,
6675 .set_power_state = &ci_dpm_set_power_state,
6676 .post_set_power_state = &ci_dpm_post_set_power_state,
6677 .display_configuration_changed = &ci_dpm_display_configuration_changed,
6678 .get_sclk = &ci_dpm_get_sclk,
6679 .get_mclk = &ci_dpm_get_mclk,
6680 .print_power_state = &ci_dpm_print_power_state,
6681 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
6682 .force_performance_level = &ci_dpm_force_performance_level,
6683 .vblank_too_short = &ci_dpm_vblank_too_short,
6684 .powergate_uvd = &ci_dpm_powergate_uvd,
6685 .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
6686 .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
6687 .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
6688 .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
6691 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
6693 if (adev->pm.funcs == NULL)
6694 adev->pm.funcs = &ci_dpm_funcs;
6697 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
6698 .set = ci_dpm_set_interrupt_state,
6699 .process = ci_dpm_process_interrupt,
6702 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6704 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6705 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;