2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vce.h"
38 /* 1 second timeout */
39 #define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000)
42 #ifdef CONFIG_DRM_AMDGPU_CIK
43 #define FIRMWARE_BONAIRE "/*(DEBLOBBED)*/"
44 #define FIRMWARE_KABINI "/*(DEBLOBBED)*/"
45 #define FIRMWARE_KAVERI "/*(DEBLOBBED)*/"
46 #define FIRMWARE_HAWAII "/*(DEBLOBBED)*/"
47 #define FIRMWARE_MULLINS "/*(DEBLOBBED)*/"
49 #define FIRMWARE_TONGA "/*(DEBLOBBED)*/"
50 #define FIRMWARE_CARRIZO "/*(DEBLOBBED)*/"
51 #define FIRMWARE_FIJI "/*(DEBLOBBED)*/"
52 #define FIRMWARE_STONEY "/*(DEBLOBBED)*/"
53 #define FIRMWARE_POLARIS10 "/*(DEBLOBBED)*/"
54 #define FIRMWARE_POLARIS11 "/*(DEBLOBBED)*/"
55 #define FIRMWARE_POLARIS12 "/*(DEBLOBBED)*/"
56 #define FIRMWARE_VEGAM "/*(DEBLOBBED)*/"
58 #define FIRMWARE_VEGA10 "/*(DEBLOBBED)*/"
59 #define FIRMWARE_VEGA12 "/*(DEBLOBBED)*/"
60 #define FIRMWARE_VEGA20 "/*(DEBLOBBED)*/"
62 #ifdef CONFIG_DRM_AMDGPU_CIK
67 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
70 * amdgpu_vce_init - allocate memory, load vce firmware
72 * @adev: amdgpu_device pointer
74 * First step to get VCE online, allocate memory and load the firmware
76 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
79 const struct common_firmware_header *hdr;
80 unsigned ucode_version, version_major, version_minor, binary_id;
83 switch (adev->asic_type) {
84 #ifdef CONFIG_DRM_AMDGPU_CIK
86 fw_name = FIRMWARE_BONAIRE;
89 fw_name = FIRMWARE_KAVERI;
92 fw_name = FIRMWARE_KABINI;
95 fw_name = FIRMWARE_HAWAII;
98 fw_name = FIRMWARE_MULLINS;
102 fw_name = FIRMWARE_TONGA;
105 fw_name = FIRMWARE_CARRIZO;
108 fw_name = FIRMWARE_FIJI;
111 fw_name = FIRMWARE_STONEY;
114 fw_name = FIRMWARE_POLARIS10;
117 fw_name = FIRMWARE_POLARIS11;
120 fw_name = FIRMWARE_POLARIS12;
123 fw_name = FIRMWARE_VEGAM;
126 fw_name = FIRMWARE_VEGA10;
129 fw_name = FIRMWARE_VEGA12;
132 fw_name = FIRMWARE_VEGA20;
139 r = reject_firmware(&adev->vce.fw, fw_name, adev->dev);
141 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
146 r = amdgpu_ucode_validate(adev->vce.fw);
148 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
150 release_firmware(adev->vce.fw);
155 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
157 ucode_version = le32_to_cpu(hdr->ucode_version);
158 version_major = (ucode_version >> 20) & 0xfff;
159 version_minor = (ucode_version >> 8) & 0xfff;
160 binary_id = ucode_version & 0xff;
161 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
162 version_major, version_minor, binary_id);
163 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
166 r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
167 AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
168 &adev->vce.gpu_addr, &adev->vce.cpu_addr);
170 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
174 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
175 atomic_set(&adev->vce.handles[i], 0);
176 adev->vce.filp[i] = NULL;
179 INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
180 mutex_init(&adev->vce.idle_mutex);
186 * amdgpu_vce_fini - free memory
188 * @adev: amdgpu_device pointer
190 * Last step on VCE teardown, free firmware memory
192 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
196 if (adev->vce.vcpu_bo == NULL)
199 drm_sched_entity_destroy(&adev->vce.entity);
201 amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
202 (void **)&adev->vce.cpu_addr);
204 for (i = 0; i < adev->vce.num_rings; i++)
205 amdgpu_ring_fini(&adev->vce.ring[i]);
207 release_firmware(adev->vce.fw);
208 mutex_destroy(&adev->vce.idle_mutex);
214 * amdgpu_vce_entity_init - init entity
216 * @adev: amdgpu_device pointer
219 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
221 struct amdgpu_ring *ring;
222 struct drm_sched_rq *rq;
225 ring = &adev->vce.ring[0];
226 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
227 r = drm_sched_entity_init(&adev->vce.entity, &rq, 1, NULL);
229 DRM_ERROR("Failed setting up VCE run queue.\n");
237 * amdgpu_vce_suspend - unpin VCE fw memory
239 * @adev: amdgpu_device pointer
242 int amdgpu_vce_suspend(struct amdgpu_device *adev)
246 cancel_delayed_work_sync(&adev->vce.idle_work);
248 if (adev->vce.vcpu_bo == NULL)
251 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
252 if (atomic_read(&adev->vce.handles[i]))
255 if (i == AMDGPU_MAX_VCE_HANDLES)
258 /* TODO: suspending running encoding sessions isn't supported */
263 * amdgpu_vce_resume - pin VCE fw memory
265 * @adev: amdgpu_device pointer
268 int amdgpu_vce_resume(struct amdgpu_device *adev)
271 const struct common_firmware_header *hdr;
275 if (adev->vce.vcpu_bo == NULL)
278 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
280 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
284 r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
286 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
287 dev_err(adev->dev, "(%d) VCE map failed\n", r);
291 hdr = (const struct common_firmware_header *)adev->vce.fw->data;
292 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
293 memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
294 adev->vce.fw->size - offset);
296 amdgpu_bo_kunmap(adev->vce.vcpu_bo);
298 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
304 * amdgpu_vce_idle_work_handler - power off VCE
306 * @work: pointer to work structure
308 * power of VCE when it's not used any more
310 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
312 struct amdgpu_device *adev =
313 container_of(work, struct amdgpu_device, vce.idle_work.work);
314 unsigned i, count = 0;
316 for (i = 0; i < adev->vce.num_rings; i++)
317 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
320 if (adev->pm.dpm_enabled) {
321 amdgpu_dpm_enable_vce(adev, false);
323 amdgpu_asic_set_vce_clocks(adev, 0, 0);
324 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
326 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
330 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
335 * amdgpu_vce_ring_begin_use - power up VCE
339 * Make sure VCE is powerd up when we want to use it
341 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
343 struct amdgpu_device *adev = ring->adev;
346 if (amdgpu_sriov_vf(adev))
349 mutex_lock(&adev->vce.idle_mutex);
350 set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
352 if (adev->pm.dpm_enabled) {
353 amdgpu_dpm_enable_vce(adev, true);
355 amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
356 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
357 AMD_CG_STATE_UNGATE);
358 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
359 AMD_PG_STATE_UNGATE);
363 mutex_unlock(&adev->vce.idle_mutex);
367 * amdgpu_vce_ring_end_use - power VCE down
371 * Schedule work to power VCE down again
373 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
375 if (!amdgpu_sriov_vf(ring->adev))
376 schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
380 * amdgpu_vce_free_handles - free still open VCE handles
382 * @adev: amdgpu_device pointer
383 * @filp: drm file pointer
385 * Close all VCE handles still open by this file pointer
387 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
389 struct amdgpu_ring *ring = &adev->vce.ring[0];
391 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
392 uint32_t handle = atomic_read(&adev->vce.handles[i]);
394 if (!handle || adev->vce.filp[i] != filp)
397 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
399 DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
401 adev->vce.filp[i] = NULL;
402 atomic_set(&adev->vce.handles[i], 0);
407 * amdgpu_vce_get_create_msg - generate a VCE create msg
409 * @adev: amdgpu_device pointer
410 * @ring: ring we should submit the msg to
411 * @handle: VCE session handle to use
412 * @fence: optional fence to return
414 * Open up a stream for HW test
416 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
417 struct dma_fence **fence)
419 const unsigned ib_size_dw = 1024;
420 struct amdgpu_job *job;
421 struct amdgpu_ib *ib;
422 struct dma_fence *f = NULL;
426 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
432 dummy = ib->gpu_addr + 1024;
434 /* stitch together an VCE create msg */
436 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
437 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
438 ib->ptr[ib->length_dw++] = handle;
440 if ((ring->adev->vce.fw_version >> 24) >= 52)
441 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
443 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
444 ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
445 ib->ptr[ib->length_dw++] = 0x00000000;
446 ib->ptr[ib->length_dw++] = 0x00000042;
447 ib->ptr[ib->length_dw++] = 0x0000000a;
448 ib->ptr[ib->length_dw++] = 0x00000001;
449 ib->ptr[ib->length_dw++] = 0x00000080;
450 ib->ptr[ib->length_dw++] = 0x00000060;
451 ib->ptr[ib->length_dw++] = 0x00000100;
452 ib->ptr[ib->length_dw++] = 0x00000100;
453 ib->ptr[ib->length_dw++] = 0x0000000c;
454 ib->ptr[ib->length_dw++] = 0x00000000;
455 if ((ring->adev->vce.fw_version >> 24) >= 52) {
456 ib->ptr[ib->length_dw++] = 0x00000000;
457 ib->ptr[ib->length_dw++] = 0x00000000;
458 ib->ptr[ib->length_dw++] = 0x00000000;
459 ib->ptr[ib->length_dw++] = 0x00000000;
462 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
463 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
464 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
465 ib->ptr[ib->length_dw++] = dummy;
466 ib->ptr[ib->length_dw++] = 0x00000001;
468 for (i = ib->length_dw; i < ib_size_dw; ++i)
471 r = amdgpu_job_submit_direct(job, ring, &f);
476 *fence = dma_fence_get(f);
481 amdgpu_job_free(job);
486 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
488 * @adev: amdgpu_device pointer
489 * @ring: ring we should submit the msg to
490 * @handle: VCE session handle to use
491 * @fence: optional fence to return
493 * Close up a stream for HW test or if userspace failed to do so
495 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
496 bool direct, struct dma_fence **fence)
498 const unsigned ib_size_dw = 1024;
499 struct amdgpu_job *job;
500 struct amdgpu_ib *ib;
501 struct dma_fence *f = NULL;
504 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
510 /* stitch together an VCE destroy msg */
512 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
513 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
514 ib->ptr[ib->length_dw++] = handle;
516 ib->ptr[ib->length_dw++] = 0x00000020; /* len */
517 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
518 ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
519 ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
520 ib->ptr[ib->length_dw++] = 0x00000000;
521 ib->ptr[ib->length_dw++] = 0x00000000;
522 ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
523 ib->ptr[ib->length_dw++] = 0x00000000;
525 ib->ptr[ib->length_dw++] = 0x00000008; /* len */
526 ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
528 for (i = ib->length_dw; i < ib_size_dw; ++i)
532 r = amdgpu_job_submit_direct(job, ring, &f);
534 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
535 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
540 *fence = dma_fence_get(f);
545 amdgpu_job_free(job);
550 * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
553 * @lo: address of lower dword
554 * @hi: address of higher dword
555 * @size: minimum size
556 * @index: bs/fb index
558 * Make sure that no BO cross a 4GB boundary.
560 static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
561 int lo, int hi, unsigned size, int32_t index)
563 int64_t offset = ((uint64_t)size) * ((int64_t)index);
564 struct ttm_operation_ctx ctx = { false, false };
565 struct amdgpu_bo_va_mapping *mapping;
566 unsigned i, fpfn, lpfn;
567 struct amdgpu_bo *bo;
571 addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
572 ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
575 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
576 lpfn = 0x100000000ULL >> PAGE_SHIFT;
579 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
582 r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
584 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
585 addr, lo, hi, size, index);
589 for (i = 0; i < bo->placement.num_placement; ++i) {
590 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
591 bo->placements[i].lpfn = bo->placements[i].lpfn ?
592 min(bo->placements[i].lpfn, lpfn) : lpfn;
594 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
599 * amdgpu_vce_cs_reloc - command submission relocation
602 * @lo: address of lower dword
603 * @hi: address of higher dword
604 * @size: minimum size
606 * Patch relocation inside command stream with real buffer address
608 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
609 int lo, int hi, unsigned size, uint32_t index)
611 struct amdgpu_bo_va_mapping *mapping;
612 struct amdgpu_bo *bo;
616 if (index == 0xffffffff)
619 addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
620 ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
621 addr += ((uint64_t)size) * ((uint64_t)index);
623 r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
625 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
626 addr, lo, hi, size, index);
630 if ((addr + (uint64_t)size) >
631 (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
632 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
637 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
638 addr += amdgpu_bo_gpu_offset(bo);
639 addr -= ((uint64_t)size) * ((uint64_t)index);
641 amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
642 amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
648 * amdgpu_vce_validate_handle - validate stream handle
651 * @handle: handle to validate
652 * @allocated: allocated a new handle?
654 * Validates the handle and return the found session index or -EINVAL
655 * we we don't have another free session index.
657 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
658 uint32_t handle, uint32_t *allocated)
662 /* validate the handle */
663 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
664 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
665 if (p->adev->vce.filp[i] != p->filp) {
666 DRM_ERROR("VCE handle collision detected!\n");
673 /* handle not found try to alloc a new one */
674 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
675 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
676 p->adev->vce.filp[i] = p->filp;
677 p->adev->vce.img_size[i] = 0;
678 *allocated |= 1 << i;
683 DRM_ERROR("No more free VCE handles!\n");
688 * amdgpu_vce_cs_parse - parse and validate the command stream
693 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
695 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
696 unsigned fb_idx = 0, bs_idx = 0;
697 int session_idx = -1;
698 uint32_t destroyed = 0;
699 uint32_t created = 0;
700 uint32_t allocated = 0;
701 uint32_t tmp, handle = 0;
702 uint32_t *size = &tmp;
707 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
709 for (idx = 0; idx < ib->length_dw;) {
710 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
711 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
713 if ((len < 8) || (len & 3)) {
714 DRM_ERROR("invalid VCE command length (%d)!\n", len);
720 case 0x00000002: /* task info */
721 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
722 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
725 case 0x03000001: /* encode */
726 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
731 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
737 case 0x05000001: /* context buffer */
738 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
744 case 0x05000004: /* video bitstream buffer */
745 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
746 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
752 case 0x05000005: /* feedback buffer */
753 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
759 case 0x0500000d: /* MV buffer */
760 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
765 r = amdgpu_vce_validate_bo(p, ib_idx, idx + 8,
775 for (idx = 0; idx < ib->length_dw;) {
776 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
777 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
780 case 0x00000001: /* session */
781 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
782 session_idx = amdgpu_vce_validate_handle(p, handle,
784 if (session_idx < 0) {
788 size = &p->adev->vce.img_size[session_idx];
791 case 0x00000002: /* task info */
792 fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
793 bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
796 case 0x01000001: /* create */
797 created |= 1 << session_idx;
798 if (destroyed & (1 << session_idx)) {
799 destroyed &= ~(1 << session_idx);
800 allocated |= 1 << session_idx;
802 } else if (!(allocated & (1 << session_idx))) {
803 DRM_ERROR("Handle already in use!\n");
808 *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
809 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
813 case 0x04000001: /* config extension */
814 case 0x04000002: /* pic control */
815 case 0x04000005: /* rate control */
816 case 0x04000007: /* motion estimation */
817 case 0x04000008: /* rdo */
818 case 0x04000009: /* vui */
819 case 0x05000002: /* auxiliary buffer */
820 case 0x05000009: /* clock table */
823 case 0x0500000c: /* hw config */
824 switch (p->adev->asic_type) {
825 #ifdef CONFIG_DRM_AMDGPU_CIK
837 case 0x03000001: /* encode */
838 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
843 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
849 case 0x02000001: /* destroy */
850 destroyed |= 1 << session_idx;
853 case 0x05000001: /* context buffer */
854 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
860 case 0x05000004: /* video bitstream buffer */
861 tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
862 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
868 case 0x05000005: /* feedback buffer */
869 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
875 case 0x0500000d: /* MV buffer */
876 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3,
881 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 8,
882 idx + 7, *size / 12, 0);
888 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
893 if (session_idx == -1) {
894 DRM_ERROR("no session command at start of IB\n");
902 if (allocated & ~created) {
903 DRM_ERROR("New session without create command!\n");
909 /* No error, free all destroyed handle slots */
912 /* Error during parsing, free all allocated handle slots */
916 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
918 atomic_set(&p->adev->vce.handles[i], 0);
924 * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
929 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
931 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
932 int session_idx = -1;
933 uint32_t destroyed = 0;
934 uint32_t created = 0;
935 uint32_t allocated = 0;
936 uint32_t tmp, handle = 0;
937 int i, r = 0, idx = 0;
939 while (idx < ib->length_dw) {
940 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
941 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
943 if ((len < 8) || (len & 3)) {
944 DRM_ERROR("invalid VCE command length (%d)!\n", len);
950 case 0x00000001: /* session */
951 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
952 session_idx = amdgpu_vce_validate_handle(p, handle,
954 if (session_idx < 0) {
960 case 0x01000001: /* create */
961 created |= 1 << session_idx;
962 if (destroyed & (1 << session_idx)) {
963 destroyed &= ~(1 << session_idx);
964 allocated |= 1 << session_idx;
966 } else if (!(allocated & (1 << session_idx))) {
967 DRM_ERROR("Handle already in use!\n");
974 case 0x02000001: /* destroy */
975 destroyed |= 1 << session_idx;
982 if (session_idx == -1) {
983 DRM_ERROR("no session command at start of IB\n");
991 if (allocated & ~created) {
992 DRM_ERROR("New session without create command!\n");
998 /* No error, free all destroyed handle slots */
1000 amdgpu_ib_free(p->adev, ib, NULL);
1002 /* Error during parsing, free all allocated handle slots */
1006 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
1008 atomic_set(&p->adev->vce.handles[i], 0);
1014 * amdgpu_vce_ring_emit_ib - execute indirect buffer
1016 * @ring: engine to use
1017 * @ib: the IB to execute
1020 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
1021 unsigned vmid, bool ctx_switch)
1023 amdgpu_ring_write(ring, VCE_CMD_IB);
1024 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1025 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1026 amdgpu_ring_write(ring, ib->length_dw);
1030 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1032 * @ring: engine to use
1036 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1039 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1041 amdgpu_ring_write(ring, VCE_CMD_FENCE);
1042 amdgpu_ring_write(ring, addr);
1043 amdgpu_ring_write(ring, upper_32_bits(addr));
1044 amdgpu_ring_write(ring, seq);
1045 amdgpu_ring_write(ring, VCE_CMD_TRAP);
1046 amdgpu_ring_write(ring, VCE_CMD_END);
1050 * amdgpu_vce_ring_test_ring - test if VCE ring is working
1052 * @ring: the engine to test on
1055 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1057 struct amdgpu_device *adev = ring->adev;
1060 int r, timeout = adev->usec_timeout;
1062 /* skip ring test for sriov*/
1063 if (amdgpu_sriov_vf(adev))
1066 r = amdgpu_ring_alloc(ring, 16);
1068 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
1073 rptr = amdgpu_ring_get_rptr(ring);
1075 amdgpu_ring_write(ring, VCE_CMD_END);
1076 amdgpu_ring_commit(ring);
1078 for (i = 0; i < timeout; i++) {
1079 if (amdgpu_ring_get_rptr(ring) != rptr)
1085 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
1088 DRM_ERROR("amdgpu: ring %d test failed\n",
1097 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1099 * @ring: the engine to test on
1102 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1104 struct dma_fence *fence = NULL;
1107 /* skip vce ring1/2 ib test for now, since it's not reliable */
1108 if (ring != &ring->adev->vce.ring[0])
1111 r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1113 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1117 r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1119 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1123 r = dma_fence_wait_timeout(fence, false, timeout);
1125 DRM_ERROR("amdgpu: IB test timed out.\n");
1128 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1130 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1134 dma_fence_put(fence);