2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
40 #include "uvd/uvd_4_2_d.h"
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
45 /* Firmware versions for VI */
46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE "/*(DEBLOBBED)*/"
57 #define FIRMWARE_KABINI "/*(DEBLOBBED)*/"
58 #define FIRMWARE_KAVERI "/*(DEBLOBBED)*/"
59 #define FIRMWARE_HAWAII "/*(DEBLOBBED)*/"
60 #define FIRMWARE_MULLINS "/*(DEBLOBBED)*/"
62 #define FIRMWARE_TONGA "/*(DEBLOBBED)*/"
63 #define FIRMWARE_CARRIZO "/*(DEBLOBBED)*/"
64 #define FIRMWARE_FIJI "/*(DEBLOBBED)*/"
65 #define FIRMWARE_STONEY "/*(DEBLOBBED)*/"
66 #define FIRMWARE_POLARIS10 "/*(DEBLOBBED)*/"
67 #define FIRMWARE_POLARIS11 "/*(DEBLOBBED)*/"
68 #define FIRMWARE_POLARIS12 "/*(DEBLOBBED)*/"
69 #define FIRMWARE_VEGAM "/*(DEBLOBBED)*/"
71 #define FIRMWARE_VEGA10 "/*(DEBLOBBED)*/"
72 #define FIRMWARE_VEGA12 "/*(DEBLOBBED)*/"
73 #define FIRMWARE_VEGA20 "/*(DEBLOBBED)*/"
75 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */
76 #define UVD_GPCOM_VCPU_CMD 0x03c3
77 #define UVD_GPCOM_VCPU_DATA0 0x03c4
78 #define UVD_GPCOM_VCPU_DATA1 0x03c5
79 #define UVD_NO_OP 0x03ff
80 #define UVD_BASE_SI 0x3800
83 * amdgpu_uvd_cs_ctx - Command submission parser context
85 * Used for emulating virtual memory support on UVD 4.2.
87 struct amdgpu_uvd_cs_ctx {
88 struct amdgpu_cs_parser *parser;
90 unsigned data0, data1;
94 /* does the IB has a msg command */
97 /* minimum buffer sizes */
101 #ifdef CONFIG_DRM_AMDGPU_CIK
106 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
108 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
110 unsigned long bo_size;
112 const struct common_firmware_header *hdr;
116 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
118 switch (adev->asic_type) {
119 #ifdef CONFIG_DRM_AMDGPU_CIK
121 fw_name = FIRMWARE_BONAIRE;
124 fw_name = FIRMWARE_KABINI;
127 fw_name = FIRMWARE_KAVERI;
130 fw_name = FIRMWARE_HAWAII;
133 fw_name = FIRMWARE_MULLINS;
137 fw_name = FIRMWARE_TONGA;
140 fw_name = FIRMWARE_FIJI;
143 fw_name = FIRMWARE_CARRIZO;
146 fw_name = FIRMWARE_STONEY;
149 fw_name = FIRMWARE_POLARIS10;
152 fw_name = FIRMWARE_POLARIS11;
155 fw_name = FIRMWARE_POLARIS12;
158 fw_name = FIRMWARE_VEGA10;
161 fw_name = FIRMWARE_VEGA12;
164 fw_name = FIRMWARE_VEGAM;
167 fw_name = FIRMWARE_VEGA20;
173 r = reject_firmware(&adev->uvd.fw, fw_name, adev->dev);
175 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
180 r = amdgpu_ucode_validate(adev->uvd.fw);
182 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
184 release_firmware(adev->uvd.fw);
189 /* Set the default UVD handles that the firmware can handle */
190 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
192 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
193 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
195 if (adev->asic_type < CHIP_VEGA20) {
196 unsigned version_major, version_minor;
198 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
199 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
200 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
201 version_major, version_minor, family_id);
204 * Limit the number of UVD handles depending on microcode major
205 * and minor versions. The firmware version which has 40 UVD
206 * instances support is 1.80. So all subsequent versions should
207 * also have the same support.
209 if ((version_major > 0x01) ||
210 ((version_major == 0x01) && (version_minor >= 0x50)))
211 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
213 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
216 if ((adev->asic_type == CHIP_POLARIS10 ||
217 adev->asic_type == CHIP_POLARIS11) &&
218 (adev->uvd.fw_version < FW_1_66_16))
219 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n",
220 version_major, version_minor);
222 unsigned int enc_major, enc_minor, dec_minor;
224 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
225 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
226 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
227 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n",
228 enc_major, enc_minor, dec_minor, family_id);
230 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
232 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
235 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
236 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
237 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
238 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
240 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
241 if (adev->uvd.harvest_config & (1 << j))
243 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
244 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
245 &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
247 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
252 for (i = 0; i < adev->uvd.max_handles; ++i) {
253 atomic_set(&adev->uvd.handles[i], 0);
254 adev->uvd.filp[i] = NULL;
257 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
258 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
259 adev->uvd.address_64_bit = true;
261 switch (adev->asic_type) {
263 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
266 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
269 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
272 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
275 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
281 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
285 drm_sched_entity_destroy(&adev->uvd.entity);
287 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
288 if (adev->uvd.harvest_config & (1 << j))
290 kvfree(adev->uvd.inst[j].saved_bo);
292 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
293 &adev->uvd.inst[j].gpu_addr,
294 (void **)&adev->uvd.inst[j].cpu_addr);
296 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
298 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
299 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
301 release_firmware(adev->uvd.fw);
307 * amdgpu_uvd_entity_init - init entity
309 * @adev: amdgpu_device pointer
312 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
314 struct amdgpu_ring *ring;
315 struct drm_sched_rq *rq;
318 ring = &adev->uvd.inst[0].ring;
319 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
320 r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);
322 DRM_ERROR("Failed setting up UVD kernel entity.\n");
329 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
335 cancel_delayed_work_sync(&adev->uvd.idle_work);
337 /* only valid for physical mode */
338 if (adev->asic_type < CHIP_POLARIS10) {
339 for (i = 0; i < adev->uvd.max_handles; ++i)
340 if (atomic_read(&adev->uvd.handles[i]))
343 if (i == adev->uvd.max_handles)
347 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
348 if (adev->uvd.harvest_config & (1 << j))
350 if (adev->uvd.inst[j].vcpu_bo == NULL)
353 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
354 ptr = adev->uvd.inst[j].cpu_addr;
356 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
357 if (!adev->uvd.inst[j].saved_bo)
360 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
365 int amdgpu_uvd_resume(struct amdgpu_device *adev)
371 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
372 if (adev->uvd.harvest_config & (1 << i))
374 if (adev->uvd.inst[i].vcpu_bo == NULL)
377 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
378 ptr = adev->uvd.inst[i].cpu_addr;
380 if (adev->uvd.inst[i].saved_bo != NULL) {
381 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
382 kvfree(adev->uvd.inst[i].saved_bo);
383 adev->uvd.inst[i].saved_bo = NULL;
385 const struct common_firmware_header *hdr;
388 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
389 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
390 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
391 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
392 le32_to_cpu(hdr->ucode_size_bytes));
393 size -= le32_to_cpu(hdr->ucode_size_bytes);
394 ptr += le32_to_cpu(hdr->ucode_size_bytes);
396 memset_io(ptr, 0, size);
397 /* to restore uvd fence seq */
398 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
404 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
406 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
409 for (i = 0; i < adev->uvd.max_handles; ++i) {
410 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
412 if (handle != 0 && adev->uvd.filp[i] == filp) {
413 struct dma_fence *fence;
415 r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
418 DRM_ERROR("Error destroying UVD %d!\n", r);
422 dma_fence_wait(fence, false);
423 dma_fence_put(fence);
425 adev->uvd.filp[i] = NULL;
426 atomic_set(&adev->uvd.handles[i], 0);
431 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
434 for (i = 0; i < abo->placement.num_placement; ++i) {
435 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
436 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
440 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
445 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
446 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
447 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
453 * amdgpu_uvd_cs_pass1 - first parsing round
455 * @ctx: UVD parser context
457 * Make sure UVD message and feedback buffers are in VRAM and
458 * nobody is violating an 256MB boundary.
460 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
462 struct ttm_operation_ctx tctx = { false, false };
463 struct amdgpu_bo_va_mapping *mapping;
464 struct amdgpu_bo *bo;
466 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
469 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
471 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
475 if (!ctx->parser->adev->uvd.address_64_bit) {
476 /* check if it's a message or feedback command */
477 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
478 if (cmd == 0x0 || cmd == 0x3) {
479 /* yes, force it into VRAM */
480 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
481 amdgpu_bo_placement_from_domain(bo, domain);
483 amdgpu_uvd_force_into_uvd_segment(bo);
485 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
492 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
494 * @msg: pointer to message structure
495 * @buf_sizes: returned buffer sizes
497 * Peek into the decode message and calculate the necessary buffer sizes.
499 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
500 unsigned buf_sizes[])
502 unsigned stream_type = msg[4];
503 unsigned width = msg[6];
504 unsigned height = msg[7];
505 unsigned dpb_size = msg[9];
506 unsigned pitch = msg[28];
507 unsigned level = msg[57];
509 unsigned width_in_mb = width / 16;
510 unsigned height_in_mb = ALIGN(height / 16, 2);
511 unsigned fs_in_mb = width_in_mb * height_in_mb;
513 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
514 unsigned min_ctx_size = ~0;
516 image_size = width * height;
517 image_size += image_size / 2;
518 image_size = ALIGN(image_size, 1024);
520 switch (stream_type) {
524 num_dpb_buffer = 8100 / fs_in_mb;
527 num_dpb_buffer = 18000 / fs_in_mb;
530 num_dpb_buffer = 20480 / fs_in_mb;
533 num_dpb_buffer = 32768 / fs_in_mb;
536 num_dpb_buffer = 34816 / fs_in_mb;
539 num_dpb_buffer = 110400 / fs_in_mb;
542 num_dpb_buffer = 184320 / fs_in_mb;
545 num_dpb_buffer = 184320 / fs_in_mb;
549 if (num_dpb_buffer > 17)
552 /* reference picture buffer */
553 min_dpb_size = image_size * num_dpb_buffer;
555 /* macroblock context buffer */
556 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
558 /* IT surface buffer */
559 min_dpb_size += width_in_mb * height_in_mb * 32;
564 /* reference picture buffer */
565 min_dpb_size = image_size * 3;
568 min_dpb_size += width_in_mb * height_in_mb * 128;
570 /* IT surface buffer */
571 min_dpb_size += width_in_mb * 64;
573 /* DB surface buffer */
574 min_dpb_size += width_in_mb * 128;
577 tmp = max(width_in_mb, height_in_mb);
578 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
583 /* reference picture buffer */
584 min_dpb_size = image_size * 3;
589 /* reference picture buffer */
590 min_dpb_size = image_size * 3;
593 min_dpb_size += width_in_mb * height_in_mb * 64;
595 /* IT surface buffer */
596 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
599 case 7: /* H264 Perf */
602 num_dpb_buffer = 8100 / fs_in_mb;
605 num_dpb_buffer = 18000 / fs_in_mb;
608 num_dpb_buffer = 20480 / fs_in_mb;
611 num_dpb_buffer = 32768 / fs_in_mb;
614 num_dpb_buffer = 34816 / fs_in_mb;
617 num_dpb_buffer = 110400 / fs_in_mb;
620 num_dpb_buffer = 184320 / fs_in_mb;
623 num_dpb_buffer = 184320 / fs_in_mb;
627 if (num_dpb_buffer > 17)
630 /* reference picture buffer */
631 min_dpb_size = image_size * num_dpb_buffer;
633 if (!adev->uvd.use_ctx_buf){
634 /* macroblock context buffer */
636 width_in_mb * height_in_mb * num_dpb_buffer * 192;
638 /* IT surface buffer */
639 min_dpb_size += width_in_mb * height_in_mb * 32;
641 /* macroblock context buffer */
643 width_in_mb * height_in_mb * num_dpb_buffer * 192;
652 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
653 image_size = ALIGN(image_size, 256);
655 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
656 min_dpb_size = image_size * num_dpb_buffer;
657 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
658 * 16 * num_dpb_buffer + 52 * 1024;
662 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
667 DRM_ERROR("Invalid UVD decoding target pitch!\n");
671 if (dpb_size < min_dpb_size) {
672 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
673 dpb_size, min_dpb_size);
677 buf_sizes[0x1] = dpb_size;
678 buf_sizes[0x2] = image_size;
679 buf_sizes[0x4] = min_ctx_size;
684 * amdgpu_uvd_cs_msg - handle UVD message
686 * @ctx: UVD parser context
687 * @bo: buffer object containing the message
688 * @offset: offset into the buffer object
690 * Peek into the UVD message and extract the session id.
691 * Make sure that we don't open up to many sessions.
693 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
694 struct amdgpu_bo *bo, unsigned offset)
696 struct amdgpu_device *adev = ctx->parser->adev;
697 int32_t *msg, msg_type, handle;
703 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
707 r = amdgpu_bo_kmap(bo, &ptr);
709 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
719 DRM_ERROR("Invalid UVD handle!\n");
725 /* it's a create msg, calc image size (width * height) */
726 amdgpu_bo_kunmap(bo);
728 /* try to alloc a new handle */
729 for (i = 0; i < adev->uvd.max_handles; ++i) {
730 if (atomic_read(&adev->uvd.handles[i]) == handle) {
731 DRM_ERROR(")Handle 0x%x already in use!\n",
736 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
737 adev->uvd.filp[i] = ctx->parser->filp;
742 DRM_ERROR("No more free UVD handles!\n");
746 /* it's a decode msg, calc buffer sizes */
747 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
748 amdgpu_bo_kunmap(bo);
752 /* validate the handle */
753 for (i = 0; i < adev->uvd.max_handles; ++i) {
754 if (atomic_read(&adev->uvd.handles[i]) == handle) {
755 if (adev->uvd.filp[i] != ctx->parser->filp) {
756 DRM_ERROR("UVD handle collision detected!\n");
763 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
767 /* it's a destroy msg, free the handle */
768 for (i = 0; i < adev->uvd.max_handles; ++i)
769 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
770 amdgpu_bo_kunmap(bo);
774 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
782 * amdgpu_uvd_cs_pass2 - second parsing round
784 * @ctx: UVD parser context
786 * Patch buffer addresses, make sure buffer sizes are correct.
788 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
790 struct amdgpu_bo_va_mapping *mapping;
791 struct amdgpu_bo *bo;
794 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
797 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
799 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
803 start = amdgpu_bo_gpu_offset(bo);
805 end = (mapping->last + 1 - mapping->start);
806 end = end * AMDGPU_GPU_PAGE_SIZE + start;
808 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
811 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
812 lower_32_bits(start));
813 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
814 upper_32_bits(start));
816 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
818 if ((end - start) < ctx->buf_sizes[cmd]) {
819 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
820 (unsigned)(end - start),
821 ctx->buf_sizes[cmd]);
825 } else if (cmd == 0x206) {
826 if ((end - start) < ctx->buf_sizes[4]) {
827 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
828 (unsigned)(end - start),
832 } else if ((cmd != 0x100) && (cmd != 0x204)) {
833 DRM_ERROR("invalid UVD command %X!\n", cmd);
837 if (!ctx->parser->adev->uvd.address_64_bit) {
838 if ((start >> 28) != ((end - 1) >> 28)) {
839 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
844 if ((cmd == 0 || cmd == 0x3) &&
845 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
846 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
853 ctx->has_msg_cmd = true;
854 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
857 } else if (!ctx->has_msg_cmd) {
858 DRM_ERROR("Message needed before other commands are send!\n");
866 * amdgpu_uvd_cs_reg - parse register writes
868 * @ctx: UVD parser context
869 * @cb: callback function
871 * Parse the register writes, call cb on each complete command.
873 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
874 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
876 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
880 for (i = 0; i <= ctx->count; ++i) {
881 unsigned reg = ctx->reg + i;
883 if (ctx->idx >= ib->length_dw) {
884 DRM_ERROR("Register command after end of CS!\n");
889 case mmUVD_GPCOM_VCPU_DATA0:
890 ctx->data0 = ctx->idx;
892 case mmUVD_GPCOM_VCPU_DATA1:
893 ctx->data1 = ctx->idx;
895 case mmUVD_GPCOM_VCPU_CMD:
900 case mmUVD_ENGINE_CNTL:
904 DRM_ERROR("Invalid reg 0x%X!\n", reg);
913 * amdgpu_uvd_cs_packets - parse UVD packets
915 * @ctx: UVD parser context
916 * @cb: callback function
918 * Parse the command stream packets.
920 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
921 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
923 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
926 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
927 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
928 unsigned type = CP_PACKET_GET_TYPE(cmd);
931 ctx->reg = CP_PACKET0_GET_REG(cmd);
932 ctx->count = CP_PACKET_GET_COUNT(cmd);
933 r = amdgpu_uvd_cs_reg(ctx, cb);
941 DRM_ERROR("Unknown packet type %d !\n", type);
949 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
951 * @parser: Command submission parser context
953 * Parse the command stream, patch in addresses as necessary.
955 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
957 struct amdgpu_uvd_cs_ctx ctx = {};
958 unsigned buf_sizes[] = {
960 [0x00000001] = 0xFFFFFFFF,
961 [0x00000002] = 0xFFFFFFFF,
963 [0x00000004] = 0xFFFFFFFF,
965 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
968 parser->job->vm = NULL;
969 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
971 if (ib->length_dw % 16) {
972 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
978 ctx.buf_sizes = buf_sizes;
981 /* first round only required on chips without UVD 64 bit address support */
982 if (!parser->adev->uvd.address_64_bit) {
983 /* first round, make sure the buffers are actually in the UVD segment */
984 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
989 /* second round, patch buffer addresses into the command stream */
990 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
994 if (!ctx.has_msg_cmd) {
995 DRM_ERROR("UVD-IBs need a msg command!\n");
1002 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1003 bool direct, struct dma_fence **fence)
1005 struct amdgpu_device *adev = ring->adev;
1006 struct dma_fence *f = NULL;
1007 struct amdgpu_job *job;
1008 struct amdgpu_ib *ib;
1013 unsigned offset_idx = 0;
1014 unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1016 amdgpu_bo_kunmap(bo);
1017 amdgpu_bo_unpin(bo);
1019 if (!ring->adev->uvd.address_64_bit) {
1020 struct ttm_operation_ctx ctx = { true, false };
1022 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
1023 amdgpu_uvd_force_into_uvd_segment(bo);
1024 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1029 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
1033 if (adev->asic_type >= CHIP_VEGA10) {
1034 offset_idx = 1 + ring->me;
1035 offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1036 offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1039 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1040 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1041 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1042 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1045 addr = amdgpu_bo_gpu_offset(bo);
1046 ib->ptr[0] = data[0];
1048 ib->ptr[2] = data[1];
1049 ib->ptr[3] = addr >> 32;
1050 ib->ptr[4] = data[2];
1052 for (i = 6; i < 16; i += 2) {
1053 ib->ptr[i] = data[3];
1059 r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
1061 msecs_to_jiffies(10));
1067 r = amdgpu_job_submit_direct(job, ring, &f);
1071 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
1072 AMDGPU_FENCE_OWNER_UNDEFINED, false);
1076 r = amdgpu_job_submit(job, &adev->uvd.entity,
1077 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1082 amdgpu_bo_fence(bo, f, false);
1083 amdgpu_bo_unreserve(bo);
1084 amdgpu_bo_unref(&bo);
1087 *fence = dma_fence_get(f);
1093 amdgpu_job_free(job);
1096 amdgpu_bo_unreserve(bo);
1097 amdgpu_bo_unref(&bo);
1101 /* multiple fence commands without any stream commands in between can
1102 crash the vcpu so just try to emmit a dummy create/destroy msg to
1104 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1105 struct dma_fence **fence)
1107 struct amdgpu_device *adev = ring->adev;
1108 struct amdgpu_bo *bo = NULL;
1112 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1113 AMDGPU_GEM_DOMAIN_VRAM,
1114 &bo, NULL, (void **)&msg);
1118 /* stitch together an UVD create msg */
1119 msg[0] = cpu_to_le32(0x00000de4);
1120 msg[1] = cpu_to_le32(0x00000000);
1121 msg[2] = cpu_to_le32(handle);
1122 msg[3] = cpu_to_le32(0x00000000);
1123 msg[4] = cpu_to_le32(0x00000000);
1124 msg[5] = cpu_to_le32(0x00000000);
1125 msg[6] = cpu_to_le32(0x00000000);
1126 msg[7] = cpu_to_le32(0x00000780);
1127 msg[8] = cpu_to_le32(0x00000440);
1128 msg[9] = cpu_to_le32(0x00000000);
1129 msg[10] = cpu_to_le32(0x01b37000);
1130 for (i = 11; i < 1024; ++i)
1131 msg[i] = cpu_to_le32(0x0);
1133 return amdgpu_uvd_send_msg(ring, bo, true, fence);
1136 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1137 bool direct, struct dma_fence **fence)
1139 struct amdgpu_device *adev = ring->adev;
1140 struct amdgpu_bo *bo = NULL;
1144 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1145 AMDGPU_GEM_DOMAIN_VRAM,
1146 &bo, NULL, (void **)&msg);
1150 /* stitch together an UVD destroy msg */
1151 msg[0] = cpu_to_le32(0x00000de4);
1152 msg[1] = cpu_to_le32(0x00000002);
1153 msg[2] = cpu_to_le32(handle);
1154 msg[3] = cpu_to_le32(0x00000000);
1155 for (i = 4; i < 1024; ++i)
1156 msg[i] = cpu_to_le32(0x0);
1158 return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1161 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1163 struct amdgpu_device *adev =
1164 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1165 unsigned fences = 0, i, j;
1167 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1168 if (adev->uvd.harvest_config & (1 << i))
1170 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1171 for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1172 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1177 if (adev->pm.dpm_enabled) {
1178 amdgpu_dpm_enable_uvd(adev, false);
1180 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1181 /* shutdown the UVD block */
1182 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1184 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1188 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1192 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1194 struct amdgpu_device *adev = ring->adev;
1197 if (amdgpu_sriov_vf(adev))
1200 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1202 if (adev->pm.dpm_enabled) {
1203 amdgpu_dpm_enable_uvd(adev, true);
1205 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1206 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1207 AMD_CG_STATE_UNGATE);
1208 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1209 AMD_PG_STATE_UNGATE);
1214 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1216 if (!amdgpu_sriov_vf(ring->adev))
1217 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1221 * amdgpu_uvd_ring_test_ib - test ib execution
1223 * @ring: amdgpu_ring pointer
1225 * Test if we can successfully execute an IB
1227 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1229 struct dma_fence *fence;
1231 uint32_t ip_instance = ring->me;
1233 r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1235 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ip_instance, r);
1239 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1241 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ip_instance, r);
1245 r = dma_fence_wait_timeout(fence, false, timeout);
1247 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ip_instance);
1250 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ip_instance, r);
1252 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ip_instance, ring->idx);
1256 dma_fence_put(fence);
1263 * amdgpu_uvd_used_handles - returns used UVD handles
1265 * @adev: amdgpu_device pointer
1267 * Returns the number of UVD handles in use
1269 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1272 uint32_t used_handles = 0;
1274 for (i = 0; i < adev->uvd.max_handles; ++i) {
1276 * Handles can be freed in any order, and not
1277 * necessarily linear. So we need to count
1278 * all non-zero handles.
1280 if (atomic_read(&adev->uvd.handles[i]))
1284 return used_handles;