drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT_MS     1000
  44
  45 /* Firmware Names */
  46 #ifdef CONFIG_DRM_AMDGPU_CIK
  47 #define FIRMWARE_BONAIRE        "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_KABINI         "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_KAVERI         "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_HAWAII         "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_MULLINS        "/*(DEBLOBBED)*/"
  52 #endif
  53 #define FIRMWARE_TONGA          "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_CARRIZO        "/*(DEBLOBBED)*/"
  55 #define FIRMWARE_FIJI           "/*(DEBLOBBED)*/"
  56 #define FIRMWARE_STONEY         "/*(DEBLOBBED)*/"
  57
  58 /**
  59  * amdgpu_uvd_cs_ctx - Command submission parser context
  60  *
  61  * Used for emulating virtual memory support on UVD 4.2.
  62  */
  63 struct amdgpu_uvd_cs_ctx {
  64         struct amdgpu_cs_parser *parser;
  65         unsigned reg, count;
  66         unsigned data0, data1;
  67         unsigned idx;
  68         unsigned ib_idx;
  69
  70         /* does the IB has a msg command */
  71         bool has_msg_cmd;
  72
  73         /* minimum buffer sizes */
  74         unsigned *buf_sizes;
  75 };
  76
  77 #ifdef CONFIG_DRM_AMDGPU_CIK
  78 /*(DEBLOBBED)*/
  79 #endif
  80 /*(DEBLOBBED)*/
  81
  82 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
  83 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
  84
  85 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
  86 {
  87         unsigned long bo_size;
  88         const char *fw_name;
  89         const struct common_firmware_header *hdr;
  90         unsigned version_major, version_minor, family_id;
  91         int i, r;
  92
  93         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
  94
  95         switch (adev->asic_type) {
  96 #ifdef CONFIG_DRM_AMDGPU_CIK
  97         case CHIP_BONAIRE:
  98                 fw_name = FIRMWARE_BONAIRE;
  99                 break;
 100         case CHIP_KABINI:
 101                 fw_name = FIRMWARE_KABINI;
 102                 break;
 103         case CHIP_KAVERI:
 104                 fw_name = FIRMWARE_KAVERI;
 105                 break;
 106         case CHIP_HAWAII:
 107                 fw_name = FIRMWARE_HAWAII;
 108                 break;
 109         case CHIP_MULLINS:
 110                 fw_name = FIRMWARE_MULLINS;
 111                 break;
 112 #endif
 113         case CHIP_TONGA:
 114                 fw_name = FIRMWARE_TONGA;
 115                 break;
 116         case CHIP_FIJI:
 117                 fw_name = FIRMWARE_FIJI;
 118                 break;
 119         case CHIP_CARRIZO:
 120                 fw_name = FIRMWARE_CARRIZO;
 121                 break;
 122         case CHIP_STONEY:
 123                 fw_name = FIRMWARE_STONEY;
 124                 break;
 125         default:
 126                 return -EINVAL;
 127         }
 128
 129         r = reject_firmware(&adev->uvd.fw, fw_name, adev->dev);
 130         if (r) {
 131                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 132                         fw_name);
 133                 return r;
 134         }
 135
 136         r = amdgpu_ucode_validate(adev->uvd.fw);
 137         if (r) {
 138                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 139                         fw_name);
 140                 release_firmware(adev->uvd.fw);
 141                 adev->uvd.fw = NULL;
 142                 return r;
 143         }
 144
 145         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 146         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 147         version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 148         version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 149         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 150                 version_major, version_minor, family_id);
 151
 152         adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
 153                                 (family_id << 8));
 154
 155         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 156                  +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
 157         r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
 158                              AMDGPU_GEM_DOMAIN_VRAM,
 159                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 160                              NULL, NULL, &adev->uvd.vcpu_bo);
 161         if (r) {
 162                 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 163                 return r;
 164         }
 165
 166         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 167         if (r) {
 168                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 169                 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
 170                 return r;
 171         }
 172
 173         r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 174                           &adev->uvd.gpu_addr);
 175         if (r) {
 176                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 177                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 178                 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
 179                 return r;
 180         }
 181
 182         r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
 183         if (r) {
 184                 dev_err(adev->dev, "(%d) UVD map failed\n", r);
 185                 return r;
 186         }
 187
 188         amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 189
 190         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 191                 atomic_set(&adev->uvd.handles[i], 0);
 192                 adev->uvd.filp[i] = NULL;
 193         }
 194
 195         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 196         if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 197                 adev->uvd.address_64_bit = true;
 198
 199         return 0;
 200 }
 201
 202 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 203 {
 204         int r;
 205
 206         if (adev->uvd.vcpu_bo == NULL)
 207                 return 0;
 208
 209         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 210         if (!r) {
 211                 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
 212                 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
 213                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 214         }
 215
 216         amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 217
 218         amdgpu_ring_fini(&adev->uvd.ring);
 219
 220         release_firmware(adev->uvd.fw);
 221
 222         return 0;
 223 }
 224
 225 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 226 {
 227         struct amdgpu_ring *ring = &adev->uvd.ring;
 228         int i, r;
 229
 230         if (adev->uvd.vcpu_bo == NULL)
 231                 return 0;
 232
 233         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 234                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 235                 if (handle != 0) {
 236                         struct fence *fence;
 237
 238                         amdgpu_uvd_note_usage(adev);
 239
 240                         r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
 241                         if (r) {
 242                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 243                                 continue;
 244                         }
 245
 246                         fence_wait(fence, false);
 247                         fence_put(fence);
 248
 249                         adev->uvd.filp[i] = NULL;
 250                         atomic_set(&adev->uvd.handles[i], 0);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 258 {
 259         unsigned size;
 260         void *ptr;
 261         const struct common_firmware_header *hdr;
 262         unsigned offset;
 263
 264         if (adev->uvd.vcpu_bo == NULL)
 265                 return -EINVAL;
 266
 267         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 268         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 269         memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
 270                 (adev->uvd.fw->size) - offset);
 271
 272         cancel_delayed_work_sync(&adev->uvd.idle_work);
 273
 274         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 275         size -= le32_to_cpu(hdr->ucode_size_bytes);
 276         ptr = adev->uvd.cpu_addr;
 277         ptr += le32_to_cpu(hdr->ucode_size_bytes);
 278
 279         memset(ptr, 0, size);
 280
 281         return 0;
 282 }
 283
 284 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 285 {
 286         struct amdgpu_ring *ring = &adev->uvd.ring;
 287         int i, r;
 288
 289         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 290                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 291                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 292                         struct fence *fence;
 293
 294                         amdgpu_uvd_note_usage(adev);
 295
 296                         r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
 297                         if (r) {
 298                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 299                                 continue;
 300                         }
 301
 302                         fence_wait(fence, false);
 303                         fence_put(fence);
 304
 305                         adev->uvd.filp[i] = NULL;
 306                         atomic_set(&adev->uvd.handles[i], 0);
 307                 }
 308         }
 309 }
 310
 311 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
 312 {
 313         int i;
 314         for (i = 0; i < rbo->placement.num_placement; ++i) {
 315                 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 316                 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 317         }
 318 }
 319
 320 /**
 321  * amdgpu_uvd_cs_pass1 - first parsing round
 322  *
 323  * @ctx: UVD parser context
 324  *
 325  * Make sure UVD message and feedback buffers are in VRAM and
 326  * nobody is violating an 256MB boundary.
 327  */
 328 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 329 {
 330         struct amdgpu_bo_va_mapping *mapping;
 331         struct amdgpu_bo *bo;
 332         uint32_t cmd, lo, hi;
 333         uint64_t addr;
 334         int r = 0;
 335
 336         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 337         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 338         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 339
 340         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 341         if (mapping == NULL) {
 342                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 343                 return -EINVAL;
 344         }
 345
 346         if (!ctx->parser->adev->uvd.address_64_bit) {
 347                 /* check if it's a message or feedback command */
 348                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 349                 if (cmd == 0x0 || cmd == 0x3) {
 350                         /* yes, force it into VRAM */
 351                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 352                         amdgpu_ttm_placement_from_domain(bo, domain);
 353                 }
 354                 amdgpu_uvd_force_into_uvd_segment(bo);
 355
 356                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 357         }
 358
 359         return r;
 360 }
 361
 362 /**
 363  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 364  *
 365  * @msg: pointer to message structure
 366  * @buf_sizes: returned buffer sizes
 367  *
 368  * Peek into the decode message and calculate the necessary buffer sizes.
 369  */
 370 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 371 {
 372         unsigned stream_type = msg[4];
 373         unsigned width = msg[6];
 374         unsigned height = msg[7];
 375         unsigned dpb_size = msg[9];
 376         unsigned pitch = msg[28];
 377         unsigned level = msg[57];
 378
 379         unsigned width_in_mb = width / 16;
 380         unsigned height_in_mb = ALIGN(height / 16, 2);
 381         unsigned fs_in_mb = width_in_mb * height_in_mb;
 382
 383         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 384         unsigned min_ctx_size = 0;
 385
 386         image_size = width * height;
 387         image_size += image_size / 2;
 388         image_size = ALIGN(image_size, 1024);
 389
 390         switch (stream_type) {
 391         case 0: /* H264 */
 392         case 7: /* H264 Perf */
 393                 switch(level) {
 394                 case 30:
 395                         num_dpb_buffer = 8100 / fs_in_mb;
 396                         break;
 397                 case 31:
 398                         num_dpb_buffer = 18000 / fs_in_mb;
 399                         break;
 400                 case 32:
 401                         num_dpb_buffer = 20480 / fs_in_mb;
 402                         break;
 403                 case 41:
 404                         num_dpb_buffer = 32768 / fs_in_mb;
 405                         break;
 406                 case 42:
 407                         num_dpb_buffer = 34816 / fs_in_mb;
 408                         break;
 409                 case 50:
 410                         num_dpb_buffer = 110400 / fs_in_mb;
 411                         break;
 412                 case 51:
 413                         num_dpb_buffer = 184320 / fs_in_mb;
 414                         break;
 415                 default:
 416                         num_dpb_buffer = 184320 / fs_in_mb;
 417                         break;
 418                 }
 419                 num_dpb_buffer++;
 420                 if (num_dpb_buffer > 17)
 421                         num_dpb_buffer = 17;
 422
 423                 /* reference picture buffer */
 424                 min_dpb_size = image_size * num_dpb_buffer;
 425
 426                 /* macroblock context buffer */
 427                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 428
 429                 /* IT surface buffer */
 430                 min_dpb_size += width_in_mb * height_in_mb * 32;
 431                 break;
 432
 433         case 1: /* VC1 */
 434
 435                 /* reference picture buffer */
 436                 min_dpb_size = image_size * 3;
 437
 438                 /* CONTEXT_BUFFER */
 439                 min_dpb_size += width_in_mb * height_in_mb * 128;
 440
 441                 /* IT surface buffer */
 442                 min_dpb_size += width_in_mb * 64;
 443
 444                 /* DB surface buffer */
 445                 min_dpb_size += width_in_mb * 128;
 446
 447                 /* BP */
 448                 tmp = max(width_in_mb, height_in_mb);
 449                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 450                 break;
 451
 452         case 3: /* MPEG2 */
 453
 454                 /* reference picture buffer */
 455                 min_dpb_size = image_size * 3;
 456                 break;
 457
 458         case 4: /* MPEG4 */
 459
 460                 /* reference picture buffer */
 461                 min_dpb_size = image_size * 3;
 462
 463                 /* CM */
 464                 min_dpb_size += width_in_mb * height_in_mb * 64;
 465
 466                 /* IT surface buffer */
 467                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 468                 break;
 469
 470         case 16: /* H265 */
 471                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 472                 image_size = ALIGN(image_size, 256);
 473
 474                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 475                 min_dpb_size = image_size * num_dpb_buffer;
 476                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 477                                            * 16 * num_dpb_buffer + 52 * 1024;
 478                 break;
 479
 480         default:
 481                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 482                 return -EINVAL;
 483         }
 484
 485         if (width > pitch) {
 486                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 487                 return -EINVAL;
 488         }
 489
 490         if (dpb_size < min_dpb_size) {
 491                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 492                           dpb_size, min_dpb_size);
 493                 return -EINVAL;
 494         }
 495
 496         buf_sizes[0x1] = dpb_size;
 497         buf_sizes[0x2] = image_size;
 498         buf_sizes[0x4] = min_ctx_size;
 499         return 0;
 500 }
 501
 502 /**
 503  * amdgpu_uvd_cs_msg - handle UVD message
 504  *
 505  * @ctx: UVD parser context
 506  * @bo: buffer object containing the message
 507  * @offset: offset into the buffer object
 508  *
 509  * Peek into the UVD message and extract the session id.
 510  * Make sure that we don't open up to many sessions.
 511  */
 512 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 513                              struct amdgpu_bo *bo, unsigned offset)
 514 {
 515         struct amdgpu_device *adev = ctx->parser->adev;
 516         int32_t *msg, msg_type, handle;
 517         void *ptr;
 518         long r;
 519         int i;
 520
 521         if (offset & 0x3F) {
 522                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 523                 return -EINVAL;
 524         }
 525
 526         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
 527                                                 MAX_SCHEDULE_TIMEOUT);
 528         if (r < 0) {
 529                 DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
 530                 return r;
 531         }
 532
 533         r = amdgpu_bo_kmap(bo, &ptr);
 534         if (r) {
 535                 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
 536                 return r;
 537         }
 538
 539         msg = ptr + offset;
 540
 541         msg_type = msg[1];
 542         handle = msg[2];
 543
 544         if (handle == 0) {
 545                 DRM_ERROR("Invalid UVD handle!\n");
 546                 return -EINVAL;
 547         }
 548
 549         switch (msg_type) {
 550         case 0:
 551                 /* it's a create msg, calc image size (width * height) */
 552                 amdgpu_bo_kunmap(bo);
 553
 554                 /* try to alloc a new handle */
 555                 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 556                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 557                                 DRM_ERROR("Handle 0x%x already in use!\n", handle);
 558                                 return -EINVAL;
 559                         }
 560
 561                         if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 562                                 adev->uvd.filp[i] = ctx->parser->filp;
 563                                 return 0;
 564                         }
 565                 }
 566
 567                 DRM_ERROR("No more free UVD handles!\n");
 568                 return -EINVAL;
 569
 570         case 1:
 571                 /* it's a decode msg, calc buffer sizes */
 572                 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
 573                 amdgpu_bo_kunmap(bo);
 574                 if (r)
 575                         return r;
 576
 577                 /* validate the handle */
 578                 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 579                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 580                                 if (adev->uvd.filp[i] != ctx->parser->filp) {
 581                                         DRM_ERROR("UVD handle collision detected!\n");
 582                                         return -EINVAL;
 583                                 }
 584                                 return 0;
 585                         }
 586                 }
 587
 588                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 589                 return -ENOENT;
 590
 591         case 2:
 592                 /* it's a destroy msg, free the handle */
 593                 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
 594                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 595                 amdgpu_bo_kunmap(bo);
 596                 return 0;
 597
 598         default:
 599                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 600                 return -EINVAL;
 601         }
 602         BUG();
 603         return -EINVAL;
 604 }
 605
 606 /**
 607  * amdgpu_uvd_cs_pass2 - second parsing round
 608  *
 609  * @ctx: UVD parser context
 610  *
 611  * Patch buffer addresses, make sure buffer sizes are correct.
 612  */
 613 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 614 {
 615         struct amdgpu_bo_va_mapping *mapping;
 616         struct amdgpu_bo *bo;
 617         struct amdgpu_ib *ib;
 618         uint32_t cmd, lo, hi;
 619         uint64_t start, end;
 620         uint64_t addr;
 621         int r;
 622
 623         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 624         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 625         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 626
 627         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 628         if (mapping == NULL)
 629                 return -EINVAL;
 630
 631         start = amdgpu_bo_gpu_offset(bo);
 632
 633         end = (mapping->it.last + 1 - mapping->it.start);
 634         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 635
 636         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 637         start += addr;
 638
 639         ib = &ctx->parser->ibs[ctx->ib_idx];
 640         ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
 641         ib->ptr[ctx->data1] = start >> 32;
 642
 643         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 644         if (cmd < 0x4) {
 645                 if ((end - start) < ctx->buf_sizes[cmd]) {
 646                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 647                                   (unsigned)(end - start),
 648                                   ctx->buf_sizes[cmd]);
 649                         return -EINVAL;
 650                 }
 651
 652         } else if (cmd == 0x206) {
 653                 if ((end - start) < ctx->buf_sizes[4]) {
 654                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 655                                           (unsigned)(end - start),
 656                                           ctx->buf_sizes[4]);
 657                         return -EINVAL;
 658                 }
 659         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 660                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 661                 return -EINVAL;
 662         }
 663
 664         if (!ctx->parser->adev->uvd.address_64_bit) {
 665                 if ((start >> 28) != ((end - 1) >> 28)) {
 666                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 667                                   start, end);
 668                         return -EINVAL;
 669                 }
 670
 671                 if ((cmd == 0 || cmd == 0x3) &&
 672                     (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
 673                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 674                                   start, end);
 675                         return -EINVAL;
 676                 }
 677         }
 678
 679         if (cmd == 0) {
 680                 ctx->has_msg_cmd = true;
 681                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 682                 if (r)
 683                         return r;
 684         } else if (!ctx->has_msg_cmd) {
 685                 DRM_ERROR("Message needed before other commands are send!\n");
 686                 return -EINVAL;
 687         }
 688
 689         return 0;
 690 }
 691
 692 /**
 693  * amdgpu_uvd_cs_reg - parse register writes
 694  *
 695  * @ctx: UVD parser context
 696  * @cb: callback function
 697  *
 698  * Parse the register writes, call cb on each complete command.
 699  */
 700 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 701                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 702 {
 703         struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
 704         int i, r;
 705
 706         ctx->idx++;
 707         for (i = 0; i <= ctx->count; ++i) {
 708                 unsigned reg = ctx->reg + i;
 709
 710                 if (ctx->idx >= ib->length_dw) {
 711                         DRM_ERROR("Register command after end of CS!\n");
 712                         return -EINVAL;
 713                 }
 714
 715                 switch (reg) {
 716                 case mmUVD_GPCOM_VCPU_DATA0:
 717                         ctx->data0 = ctx->idx;
 718                         break;
 719                 case mmUVD_GPCOM_VCPU_DATA1:
 720                         ctx->data1 = ctx->idx;
 721                         break;
 722                 case mmUVD_GPCOM_VCPU_CMD:
 723                         r = cb(ctx);
 724                         if (r)
 725                                 return r;
 726                         break;
 727                 case mmUVD_ENGINE_CNTL:
 728                         break;
 729                 default:
 730                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 731                         return -EINVAL;
 732                 }
 733                 ctx->idx++;
 734         }
 735         return 0;
 736 }
 737
 738 /**
 739  * amdgpu_uvd_cs_packets - parse UVD packets
 740  *
 741  * @ctx: UVD parser context
 742  * @cb: callback function
 743  *
 744  * Parse the command stream packets.
 745  */
 746 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 747                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 748 {
 749         struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
 750         int r;
 751
 752         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 753                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 754                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 755                 switch (type) {
 756                 case PACKET_TYPE0:
 757                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 758                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 759                         r = amdgpu_uvd_cs_reg(ctx, cb);
 760                         if (r)
 761                                 return r;
 762                         break;
 763                 case PACKET_TYPE2:
 764                         ++ctx->idx;
 765                         break;
 766                 default:
 767                         DRM_ERROR("Unknown packet type %d !\n", type);
 768                         return -EINVAL;
 769                 }
 770         }
 771         return 0;
 772 }
 773
 774 /**
 775  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 776  *
 777  * @parser: Command submission parser context
 778  *
 779  * Parse the command stream, patch in addresses as necessary.
 780  */
 781 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 782 {
 783         struct amdgpu_uvd_cs_ctx ctx = {};
 784         unsigned buf_sizes[] = {
 785                 [0x00000000]    =       2048,
 786                 [0x00000001]    =       0xFFFFFFFF,
 787                 [0x00000002]    =       0xFFFFFFFF,
 788                 [0x00000003]    =       2048,
 789                 [0x00000004]    =       0xFFFFFFFF,
 790         };
 791         struct amdgpu_ib *ib = &parser->ibs[ib_idx];
 792         int r;
 793
 794         if (ib->length_dw % 16) {
 795                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 796                           ib->length_dw);
 797                 return -EINVAL;
 798         }
 799
 800         ctx.parser = parser;
 801         ctx.buf_sizes = buf_sizes;
 802         ctx.ib_idx = ib_idx;
 803
 804         /* first round, make sure the buffers are actually in the UVD segment */
 805         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 806         if (r)
 807                 return r;
 808
 809         /* second round, patch buffer addresses into the command stream */
 810         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 811         if (r)
 812                 return r;
 813
 814         if (!ctx.has_msg_cmd) {
 815                 DRM_ERROR("UVD-IBs need a msg command!\n");
 816                 return -EINVAL;
 817         }
 818
 819         amdgpu_uvd_note_usage(ctx.parser->adev);
 820
 821         return 0;
 822 }
 823
 824 static int amdgpu_uvd_free_job(
 825         struct amdgpu_job *job)
 826 {
 827         amdgpu_ib_free(job->adev, job->ibs);
 828         kfree(job->ibs);
 829         return 0;
 830 }
 831
 832 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
 833                                struct amdgpu_bo *bo,
 834                                struct fence **fence)
 835 {
 836         struct ttm_validate_buffer tv;
 837         struct ww_acquire_ctx ticket;
 838         struct list_head head;
 839         struct amdgpu_ib *ib = NULL;
 840         struct fence *f = NULL;
 841         struct amdgpu_device *adev = ring->adev;
 842         uint64_t addr;
 843         int i, r;
 844
 845         memset(&tv, 0, sizeof(tv));
 846         tv.bo = &bo->tbo;
 847
 848         INIT_LIST_HEAD(&head);
 849         list_add(&tv.head, &head);
 850
 851         r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
 852         if (r)
 853                 return r;
 854
 855         if (!bo->adev->uvd.address_64_bit) {
 856                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
 857                 amdgpu_uvd_force_into_uvd_segment(bo);
 858         }
 859
 860         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 861         if (r)
 862                 goto err;
 863         ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
 864         if (!ib) {
 865                 r = -ENOMEM;
 866                 goto err;
 867         }
 868         r = amdgpu_ib_get(ring, NULL, 64, ib);
 869         if (r)
 870                 goto err1;
 871
 872         addr = amdgpu_bo_gpu_offset(bo);
 873         ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
 874         ib->ptr[1] = addr;
 875         ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
 876         ib->ptr[3] = addr >> 32;
 877         ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
 878         ib->ptr[5] = 0;
 879         for (i = 6; i < 16; ++i)
 880                 ib->ptr[i] = PACKET2(0);
 881         ib->length_dw = 16;
 882
 883         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
 884                                                  &amdgpu_uvd_free_job,
 885                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 886                                                  &f);
 887         if (r)
 888                 goto err2;
 889
 890         ttm_eu_fence_buffer_objects(&ticket, &head, f);
 891
 892         if (fence)
 893                 *fence = fence_get(f);
 894         amdgpu_bo_unref(&bo);
 895         fence_put(f);
 896         if (amdgpu_enable_scheduler)
 897                 return 0;
 898
 899         amdgpu_ib_free(ring->adev, ib);
 900         kfree(ib);
 901         return 0;
 902 err2:
 903         amdgpu_ib_free(ring->adev, ib);
 904 err1:
 905         kfree(ib);
 906 err:
 907         ttm_eu_backoff_reservation(&ticket, &head);
 908         return r;
 909 }
 910
 911 /* multiple fence commands without any stream commands in between can
 912    crash the vcpu so just try to emmit a dummy create/destroy msg to
 913    avoid this */
 914 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 915                               struct fence **fence)
 916 {
 917         struct amdgpu_device *adev = ring->adev;
 918         struct amdgpu_bo *bo;
 919         uint32_t *msg;
 920         int r, i;
 921
 922         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
 923                              AMDGPU_GEM_DOMAIN_VRAM,
 924                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 925                              NULL, NULL, &bo);
 926         if (r)
 927                 return r;
 928
 929         r = amdgpu_bo_reserve(bo, false);
 930         if (r) {
 931                 amdgpu_bo_unref(&bo);
 932                 return r;
 933         }
 934
 935         r = amdgpu_bo_kmap(bo, (void **)&msg);
 936         if (r) {
 937                 amdgpu_bo_unreserve(bo);
 938                 amdgpu_bo_unref(&bo);
 939                 return r;
 940         }
 941
 942         /* stitch together an UVD create msg */
 943         msg[0] = cpu_to_le32(0x00000de4);
 944         msg[1] = cpu_to_le32(0x00000000);
 945         msg[2] = cpu_to_le32(handle);
 946         msg[3] = cpu_to_le32(0x00000000);
 947         msg[4] = cpu_to_le32(0x00000000);
 948         msg[5] = cpu_to_le32(0x00000000);
 949         msg[6] = cpu_to_le32(0x00000000);
 950         msg[7] = cpu_to_le32(0x00000780);
 951         msg[8] = cpu_to_le32(0x00000440);
 952         msg[9] = cpu_to_le32(0x00000000);
 953         msg[10] = cpu_to_le32(0x01b37000);
 954         for (i = 11; i < 1024; ++i)
 955                 msg[i] = cpu_to_le32(0x0);
 956
 957         amdgpu_bo_kunmap(bo);
 958         amdgpu_bo_unreserve(bo);
 959
 960         return amdgpu_uvd_send_msg(ring, bo, fence);
 961 }
 962
 963 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 964                                struct fence **fence)
 965 {
 966         struct amdgpu_device *adev = ring->adev;
 967         struct amdgpu_bo *bo;
 968         uint32_t *msg;
 969         int r, i;
 970
 971         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
 972                              AMDGPU_GEM_DOMAIN_VRAM,
 973                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 974                              NULL, NULL, &bo);
 975         if (r)
 976                 return r;
 977
 978         r = amdgpu_bo_reserve(bo, false);
 979         if (r) {
 980                 amdgpu_bo_unref(&bo);
 981                 return r;
 982         }
 983
 984         r = amdgpu_bo_kmap(bo, (void **)&msg);
 985         if (r) {
 986                 amdgpu_bo_unreserve(bo);
 987                 amdgpu_bo_unref(&bo);
 988                 return r;
 989         }
 990
 991         /* stitch together an UVD destroy msg */
 992         msg[0] = cpu_to_le32(0x00000de4);
 993         msg[1] = cpu_to_le32(0x00000002);
 994         msg[2] = cpu_to_le32(handle);
 995         msg[3] = cpu_to_le32(0x00000000);
 996         for (i = 4; i < 1024; ++i)
 997                 msg[i] = cpu_to_le32(0x0);
 998
 999         amdgpu_bo_kunmap(bo);
1000         amdgpu_bo_unreserve(bo);
1001
1002         return amdgpu_uvd_send_msg(ring, bo, fence);
1003 }
1004
1005 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1006 {
1007         struct amdgpu_device *adev =
1008                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1009         unsigned i, fences, handles = 0;
1010
1011         fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1012
1013         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
1014                 if (atomic_read(&adev->uvd.handles[i]))
1015                         ++handles;
1016
1017         if (fences == 0 && handles == 0) {
1018                 if (adev->pm.dpm_enabled) {
1019                         amdgpu_dpm_enable_uvd(adev, false);
1020                 } else {
1021                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1022                 }
1023         } else {
1024                 schedule_delayed_work(&adev->uvd.idle_work,
1025                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1026         }
1027 }
1028
1029 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1030 {
1031         bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1032         set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1033                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1034
1035         if (set_clocks) {
1036                 if (adev->pm.dpm_enabled) {
1037                         amdgpu_dpm_enable_uvd(adev, true);
1038                 } else {
1039                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1040                 }
1041         }
1042 }