2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
40 #include "uvd/uvd_4_2_d.h"
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
45 /* Firmware versions for VI */
46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE "/*(DEBLOBBED)*/"
57 #define FIRMWARE_KABINI "/*(DEBLOBBED)*/"
58 #define FIRMWARE_KAVERI "/*(DEBLOBBED)*/"
59 #define FIRMWARE_HAWAII "/*(DEBLOBBED)*/"
60 #define FIRMWARE_MULLINS "/*(DEBLOBBED)*/"
62 #define FIRMWARE_TONGA "/*(DEBLOBBED)*/"
63 #define FIRMWARE_CARRIZO "/*(DEBLOBBED)*/"
64 #define FIRMWARE_FIJI "/*(DEBLOBBED)*/"
65 #define FIRMWARE_STONEY "/*(DEBLOBBED)*/"
66 #define FIRMWARE_POLARIS10 "/*(DEBLOBBED)*/"
67 #define FIRMWARE_POLARIS11 "/*(DEBLOBBED)*/"
70 * amdgpu_uvd_cs_ctx - Command submission parser context
72 * Used for emulating virtual memory support on UVD 4.2.
74 struct amdgpu_uvd_cs_ctx {
75 struct amdgpu_cs_parser *parser;
77 unsigned data0, data1;
81 /* does the IB has a msg command */
84 /* minimum buffer sizes */
88 #ifdef CONFIG_DRM_AMDGPU_CIK
93 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
95 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
97 struct amdgpu_ring *ring;
98 struct amd_sched_rq *rq;
99 unsigned long bo_size;
101 const struct common_firmware_header *hdr;
102 unsigned version_major, version_minor, family_id;
105 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
107 switch (adev->asic_type) {
108 #ifdef CONFIG_DRM_AMDGPU_CIK
110 fw_name = FIRMWARE_BONAIRE;
113 fw_name = FIRMWARE_KABINI;
116 fw_name = FIRMWARE_KAVERI;
119 fw_name = FIRMWARE_HAWAII;
122 fw_name = FIRMWARE_MULLINS;
126 fw_name = FIRMWARE_TONGA;
129 fw_name = FIRMWARE_FIJI;
132 fw_name = FIRMWARE_CARRIZO;
135 fw_name = FIRMWARE_STONEY;
138 fw_name = FIRMWARE_POLARIS10;
141 fw_name = FIRMWARE_POLARIS11;
147 r = reject_firmware(&adev->uvd.fw, fw_name, adev->dev);
149 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
154 r = amdgpu_ucode_validate(adev->uvd.fw);
156 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
158 release_firmware(adev->uvd.fw);
163 /* Set the default UVD handles that the firmware can handle */
164 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
166 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
167 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
168 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
169 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
170 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
171 version_major, version_minor, family_id);
174 * Limit the number of UVD handles depending on microcode major
175 * and minor versions. The firmware version which has 40 UVD
176 * instances support is 1.80. So all subsequent versions should
177 * also have the same support.
179 if ((version_major > 0x01) ||
180 ((version_major == 0x01) && (version_minor >= 0x50)))
181 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
183 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
186 if ((adev->asic_type == CHIP_POLARIS10 ||
187 adev->asic_type == CHIP_POLARIS11) &&
188 (adev->uvd.fw_version < FW_1_66_16))
189 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
190 version_major, version_minor);
192 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
193 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
194 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
195 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
196 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
197 &adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
199 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
203 ring = &adev->uvd.ring;
204 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
205 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
206 rq, amdgpu_sched_jobs);
208 DRM_ERROR("Failed setting up UVD run queue.\n");
212 for (i = 0; i < adev->uvd.max_handles; ++i) {
213 atomic_set(&adev->uvd.handles[i], 0);
214 adev->uvd.filp[i] = NULL;
217 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
218 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
219 adev->uvd.address_64_bit = true;
221 switch (adev->asic_type) {
223 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
226 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
229 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
232 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
235 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
241 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
243 kfree(adev->uvd.saved_bo);
245 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
247 amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo,
249 (void **)&adev->uvd.cpu_addr);
251 amdgpu_ring_fini(&adev->uvd.ring);
253 release_firmware(adev->uvd.fw);
258 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
264 if (adev->uvd.vcpu_bo == NULL)
267 /* only valid for physical mode */
268 if (adev->asic_type < CHIP_POLARIS10) {
269 for (i = 0; i < adev->uvd.max_handles; ++i)
270 if (atomic_read(&adev->uvd.handles[i]))
273 if (i == adev->uvd.max_handles)
277 cancel_delayed_work_sync(&adev->uvd.idle_work);
279 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
280 ptr = adev->uvd.cpu_addr;
282 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
283 if (!adev->uvd.saved_bo)
286 memcpy_fromio(adev->uvd.saved_bo, ptr, size);
291 int amdgpu_uvd_resume(struct amdgpu_device *adev)
296 if (adev->uvd.vcpu_bo == NULL)
299 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
300 ptr = adev->uvd.cpu_addr;
302 if (adev->uvd.saved_bo != NULL) {
303 memcpy_toio(ptr, adev->uvd.saved_bo, size);
304 kfree(adev->uvd.saved_bo);
305 adev->uvd.saved_bo = NULL;
307 const struct common_firmware_header *hdr;
310 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
311 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
312 memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset,
313 le32_to_cpu(hdr->ucode_size_bytes));
314 size -= le32_to_cpu(hdr->ucode_size_bytes);
315 ptr += le32_to_cpu(hdr->ucode_size_bytes);
316 memset_io(ptr, 0, size);
322 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
324 struct amdgpu_ring *ring = &adev->uvd.ring;
327 for (i = 0; i < adev->uvd.max_handles; ++i) {
328 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
329 if (handle != 0 && adev->uvd.filp[i] == filp) {
332 r = amdgpu_uvd_get_destroy_msg(ring, handle,
335 DRM_ERROR("Error destroying UVD (%d)!\n", r);
339 fence_wait(fence, false);
342 adev->uvd.filp[i] = NULL;
343 atomic_set(&adev->uvd.handles[i], 0);
348 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
351 for (i = 0; i < abo->placement.num_placement; ++i) {
352 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
353 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
358 * amdgpu_uvd_cs_pass1 - first parsing round
360 * @ctx: UVD parser context
362 * Make sure UVD message and feedback buffers are in VRAM and
363 * nobody is violating an 256MB boundary.
365 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
367 struct amdgpu_bo_va_mapping *mapping;
368 struct amdgpu_bo *bo;
369 uint32_t cmd, lo, hi;
373 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
374 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
375 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
377 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
378 if (mapping == NULL) {
379 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
383 if (!ctx->parser->adev->uvd.address_64_bit) {
384 /* check if it's a message or feedback command */
385 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
386 if (cmd == 0x0 || cmd == 0x3) {
387 /* yes, force it into VRAM */
388 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
389 amdgpu_ttm_placement_from_domain(bo, domain);
391 amdgpu_uvd_force_into_uvd_segment(bo);
393 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
400 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
402 * @msg: pointer to message structure
403 * @buf_sizes: returned buffer sizes
405 * Peek into the decode message and calculate the necessary buffer sizes.
407 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
408 unsigned buf_sizes[])
410 unsigned stream_type = msg[4];
411 unsigned width = msg[6];
412 unsigned height = msg[7];
413 unsigned dpb_size = msg[9];
414 unsigned pitch = msg[28];
415 unsigned level = msg[57];
417 unsigned width_in_mb = width / 16;
418 unsigned height_in_mb = ALIGN(height / 16, 2);
419 unsigned fs_in_mb = width_in_mb * height_in_mb;
421 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
422 unsigned min_ctx_size = ~0;
424 image_size = width * height;
425 image_size += image_size / 2;
426 image_size = ALIGN(image_size, 1024);
428 switch (stream_type) {
432 num_dpb_buffer = 8100 / fs_in_mb;
435 num_dpb_buffer = 18000 / fs_in_mb;
438 num_dpb_buffer = 20480 / fs_in_mb;
441 num_dpb_buffer = 32768 / fs_in_mb;
444 num_dpb_buffer = 34816 / fs_in_mb;
447 num_dpb_buffer = 110400 / fs_in_mb;
450 num_dpb_buffer = 184320 / fs_in_mb;
453 num_dpb_buffer = 184320 / fs_in_mb;
457 if (num_dpb_buffer > 17)
460 /* reference picture buffer */
461 min_dpb_size = image_size * num_dpb_buffer;
463 /* macroblock context buffer */
464 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
466 /* IT surface buffer */
467 min_dpb_size += width_in_mb * height_in_mb * 32;
472 /* reference picture buffer */
473 min_dpb_size = image_size * 3;
476 min_dpb_size += width_in_mb * height_in_mb * 128;
478 /* IT surface buffer */
479 min_dpb_size += width_in_mb * 64;
481 /* DB surface buffer */
482 min_dpb_size += width_in_mb * 128;
485 tmp = max(width_in_mb, height_in_mb);
486 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
491 /* reference picture buffer */
492 min_dpb_size = image_size * 3;
497 /* reference picture buffer */
498 min_dpb_size = image_size * 3;
501 min_dpb_size += width_in_mb * height_in_mb * 64;
503 /* IT surface buffer */
504 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
507 case 7: /* H264 Perf */
510 num_dpb_buffer = 8100 / fs_in_mb;
513 num_dpb_buffer = 18000 / fs_in_mb;
516 num_dpb_buffer = 20480 / fs_in_mb;
519 num_dpb_buffer = 32768 / fs_in_mb;
522 num_dpb_buffer = 34816 / fs_in_mb;
525 num_dpb_buffer = 110400 / fs_in_mb;
528 num_dpb_buffer = 184320 / fs_in_mb;
531 num_dpb_buffer = 184320 / fs_in_mb;
535 if (num_dpb_buffer > 17)
538 /* reference picture buffer */
539 min_dpb_size = image_size * num_dpb_buffer;
541 if (!adev->uvd.use_ctx_buf){
542 /* macroblock context buffer */
544 width_in_mb * height_in_mb * num_dpb_buffer * 192;
546 /* IT surface buffer */
547 min_dpb_size += width_in_mb * height_in_mb * 32;
549 /* macroblock context buffer */
551 width_in_mb * height_in_mb * num_dpb_buffer * 192;
556 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
557 image_size = ALIGN(image_size, 256);
559 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
560 min_dpb_size = image_size * num_dpb_buffer;
561 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
562 * 16 * num_dpb_buffer + 52 * 1024;
566 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
571 DRM_ERROR("Invalid UVD decoding target pitch!\n");
575 if (dpb_size < min_dpb_size) {
576 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
577 dpb_size, min_dpb_size);
581 buf_sizes[0x1] = dpb_size;
582 buf_sizes[0x2] = image_size;
583 buf_sizes[0x4] = min_ctx_size;
588 * amdgpu_uvd_cs_msg - handle UVD message
590 * @ctx: UVD parser context
591 * @bo: buffer object containing the message
592 * @offset: offset into the buffer object
594 * Peek into the UVD message and extract the session id.
595 * Make sure that we don't open up to many sessions.
597 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
598 struct amdgpu_bo *bo, unsigned offset)
600 struct amdgpu_device *adev = ctx->parser->adev;
601 int32_t *msg, msg_type, handle;
607 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
611 r = amdgpu_bo_kmap(bo, &ptr);
613 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
623 DRM_ERROR("Invalid UVD handle!\n");
629 /* it's a create msg, calc image size (width * height) */
630 amdgpu_bo_kunmap(bo);
632 /* try to alloc a new handle */
633 for (i = 0; i < adev->uvd.max_handles; ++i) {
634 if (atomic_read(&adev->uvd.handles[i]) == handle) {
635 DRM_ERROR("Handle 0x%x already in use!\n", handle);
639 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
640 adev->uvd.filp[i] = ctx->parser->filp;
645 DRM_ERROR("No more free UVD handles!\n");
649 /* it's a decode msg, calc buffer sizes */
650 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
651 amdgpu_bo_kunmap(bo);
655 /* validate the handle */
656 for (i = 0; i < adev->uvd.max_handles; ++i) {
657 if (atomic_read(&adev->uvd.handles[i]) == handle) {
658 if (adev->uvd.filp[i] != ctx->parser->filp) {
659 DRM_ERROR("UVD handle collision detected!\n");
666 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
670 /* it's a destroy msg, free the handle */
671 for (i = 0; i < adev->uvd.max_handles; ++i)
672 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
673 amdgpu_bo_kunmap(bo);
677 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
685 * amdgpu_uvd_cs_pass2 - second parsing round
687 * @ctx: UVD parser context
689 * Patch buffer addresses, make sure buffer sizes are correct.
691 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
693 struct amdgpu_bo_va_mapping *mapping;
694 struct amdgpu_bo *bo;
695 uint32_t cmd, lo, hi;
700 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
701 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
702 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
704 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
708 start = amdgpu_bo_gpu_offset(bo);
710 end = (mapping->it.last + 1 - mapping->it.start);
711 end = end * AMDGPU_GPU_PAGE_SIZE + start;
713 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
716 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
717 lower_32_bits(start));
718 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
719 upper_32_bits(start));
721 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
723 if ((end - start) < ctx->buf_sizes[cmd]) {
724 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
725 (unsigned)(end - start),
726 ctx->buf_sizes[cmd]);
730 } else if (cmd == 0x206) {
731 if ((end - start) < ctx->buf_sizes[4]) {
732 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
733 (unsigned)(end - start),
737 } else if ((cmd != 0x100) && (cmd != 0x204)) {
738 DRM_ERROR("invalid UVD command %X!\n", cmd);
742 if (!ctx->parser->adev->uvd.address_64_bit) {
743 if ((start >> 28) != ((end - 1) >> 28)) {
744 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
749 if ((cmd == 0 || cmd == 0x3) &&
750 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
751 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
758 ctx->has_msg_cmd = true;
759 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
762 } else if (!ctx->has_msg_cmd) {
763 DRM_ERROR("Message needed before other commands are send!\n");
771 * amdgpu_uvd_cs_reg - parse register writes
773 * @ctx: UVD parser context
774 * @cb: callback function
776 * Parse the register writes, call cb on each complete command.
778 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
779 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
781 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
785 for (i = 0; i <= ctx->count; ++i) {
786 unsigned reg = ctx->reg + i;
788 if (ctx->idx >= ib->length_dw) {
789 DRM_ERROR("Register command after end of CS!\n");
794 case mmUVD_GPCOM_VCPU_DATA0:
795 ctx->data0 = ctx->idx;
797 case mmUVD_GPCOM_VCPU_DATA1:
798 ctx->data1 = ctx->idx;
800 case mmUVD_GPCOM_VCPU_CMD:
805 case mmUVD_ENGINE_CNTL:
809 DRM_ERROR("Invalid reg 0x%X!\n", reg);
818 * amdgpu_uvd_cs_packets - parse UVD packets
820 * @ctx: UVD parser context
821 * @cb: callback function
823 * Parse the command stream packets.
825 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
826 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
828 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
831 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
832 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
833 unsigned type = CP_PACKET_GET_TYPE(cmd);
836 ctx->reg = CP_PACKET0_GET_REG(cmd);
837 ctx->count = CP_PACKET_GET_COUNT(cmd);
838 r = amdgpu_uvd_cs_reg(ctx, cb);
846 DRM_ERROR("Unknown packet type %d !\n", type);
854 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
856 * @parser: Command submission parser context
858 * Parse the command stream, patch in addresses as necessary.
860 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
862 struct amdgpu_uvd_cs_ctx ctx = {};
863 unsigned buf_sizes[] = {
865 [0x00000001] = 0xFFFFFFFF,
866 [0x00000002] = 0xFFFFFFFF,
868 [0x00000004] = 0xFFFFFFFF,
870 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
873 if (ib->length_dw % 16) {
874 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
879 r = amdgpu_cs_sysvm_access_required(parser);
884 ctx.buf_sizes = buf_sizes;
887 /* first round, make sure the buffers are actually in the UVD segment */
888 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
892 /* second round, patch buffer addresses into the command stream */
893 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
897 if (!ctx.has_msg_cmd) {
898 DRM_ERROR("UVD-IBs need a msg command!\n");
905 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
906 bool direct, struct fence **fence)
908 struct ttm_validate_buffer tv;
909 struct ww_acquire_ctx ticket;
910 struct list_head head;
911 struct amdgpu_job *job;
912 struct amdgpu_ib *ib;
913 struct fence *f = NULL;
914 struct amdgpu_device *adev = ring->adev;
918 memset(&tv, 0, sizeof(tv));
921 INIT_LIST_HEAD(&head);
922 list_add(&tv.head, &head);
924 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
928 if (!bo->adev->uvd.address_64_bit) {
929 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
930 amdgpu_uvd_force_into_uvd_segment(bo);
933 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
937 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
942 addr = amdgpu_bo_gpu_offset(bo);
943 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
945 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
946 ib->ptr[3] = addr >> 32;
947 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
949 for (i = 6; i < 16; i += 2) {
950 ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0);
956 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
957 job->fence = fence_get(f);
961 amdgpu_job_free(job);
963 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
964 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
969 ttm_eu_fence_buffer_objects(&ticket, &head, f);
972 *fence = fence_get(f);
973 amdgpu_bo_unref(&bo);
979 amdgpu_job_free(job);
982 ttm_eu_backoff_reservation(&ticket, &head);
986 /* multiple fence commands without any stream commands in between can
987 crash the vcpu so just try to emmit a dummy create/destroy msg to
989 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
990 struct fence **fence)
992 struct amdgpu_device *adev = ring->adev;
993 struct amdgpu_bo *bo;
997 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
998 AMDGPU_GEM_DOMAIN_VRAM,
999 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1004 r = amdgpu_bo_reserve(bo, false);
1006 amdgpu_bo_unref(&bo);
1010 r = amdgpu_bo_kmap(bo, (void **)&msg);
1012 amdgpu_bo_unreserve(bo);
1013 amdgpu_bo_unref(&bo);
1017 /* stitch together an UVD create msg */
1018 msg[0] = cpu_to_le32(0x00000de4);
1019 msg[1] = cpu_to_le32(0x00000000);
1020 msg[2] = cpu_to_le32(handle);
1021 msg[3] = cpu_to_le32(0x00000000);
1022 msg[4] = cpu_to_le32(0x00000000);
1023 msg[5] = cpu_to_le32(0x00000000);
1024 msg[6] = cpu_to_le32(0x00000000);
1025 msg[7] = cpu_to_le32(0x00000780);
1026 msg[8] = cpu_to_le32(0x00000440);
1027 msg[9] = cpu_to_le32(0x00000000);
1028 msg[10] = cpu_to_le32(0x01b37000);
1029 for (i = 11; i < 1024; ++i)
1030 msg[i] = cpu_to_le32(0x0);
1032 amdgpu_bo_kunmap(bo);
1033 amdgpu_bo_unreserve(bo);
1035 return amdgpu_uvd_send_msg(ring, bo, true, fence);
1038 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1039 bool direct, struct fence **fence)
1041 struct amdgpu_device *adev = ring->adev;
1042 struct amdgpu_bo *bo;
1046 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
1047 AMDGPU_GEM_DOMAIN_VRAM,
1048 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1053 r = amdgpu_bo_reserve(bo, false);
1055 amdgpu_bo_unref(&bo);
1059 r = amdgpu_bo_kmap(bo, (void **)&msg);
1061 amdgpu_bo_unreserve(bo);
1062 amdgpu_bo_unref(&bo);
1066 /* stitch together an UVD destroy msg */
1067 msg[0] = cpu_to_le32(0x00000de4);
1068 msg[1] = cpu_to_le32(0x00000002);
1069 msg[2] = cpu_to_le32(handle);
1070 msg[3] = cpu_to_le32(0x00000000);
1071 for (i = 4; i < 1024; ++i)
1072 msg[i] = cpu_to_le32(0x0);
1074 amdgpu_bo_kunmap(bo);
1075 amdgpu_bo_unreserve(bo);
1077 return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1080 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1082 struct amdgpu_device *adev =
1083 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1084 unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1087 if (adev->pm.dpm_enabled) {
1088 amdgpu_dpm_enable_uvd(adev, false);
1090 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1093 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1097 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1099 struct amdgpu_device *adev = ring->adev;
1100 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1103 if (adev->pm.dpm_enabled) {
1104 amdgpu_dpm_enable_uvd(adev, true);
1106 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1111 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1113 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1117 * amdgpu_uvd_ring_test_ib - test ib execution
1119 * @ring: amdgpu_ring pointer
1121 * Test if we can successfully execute an IB
1123 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1125 struct fence *fence;
1128 r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1130 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
1134 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1136 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
1140 r = fence_wait_timeout(fence, false, timeout);
1142 DRM_ERROR("amdgpu: IB test timed out.\n");
1145 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1147 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);