2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <drm/ttm/ttm_bo_api.h>
33 #include <drm/ttm/ttm_bo_driver.h>
34 #include <drm/ttm/ttm_placement.h>
35 #include <drm/ttm/ttm_module.h>
36 #include <drm/ttm/ttm_page_alloc.h>
38 #include <drm/amdgpu_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
46 #include "amdgpu_trace.h"
47 #include "bif/bif_4_1_d.h"
49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
51 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
52 struct ttm_mem_reg *mem, unsigned num_pages,
53 uint64_t offset, unsigned window,
54 struct amdgpu_ring *ring,
57 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
58 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
63 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
65 return ttm_mem_global_init(ref->object);
68 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
70 ttm_mem_global_release(ref->object);
73 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
75 struct drm_global_reference *global_ref;
76 struct amdgpu_ring *ring;
77 struct amd_sched_rq *rq;
80 adev->mman.mem_global_referenced = false;
81 global_ref = &adev->mman.mem_global_ref;
82 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
83 global_ref->size = sizeof(struct ttm_mem_global);
84 global_ref->init = &amdgpu_ttm_mem_global_init;
85 global_ref->release = &amdgpu_ttm_mem_global_release;
86 r = drm_global_item_ref(global_ref);
88 DRM_ERROR("Failed setting up TTM memory accounting "
93 adev->mman.bo_global_ref.mem_glob =
94 adev->mman.mem_global_ref.object;
95 global_ref = &adev->mman.bo_global_ref.ref;
96 global_ref->global_type = DRM_GLOBAL_TTM_BO;
97 global_ref->size = sizeof(struct ttm_bo_global);
98 global_ref->init = &ttm_bo_global_init;
99 global_ref->release = &ttm_bo_global_release;
100 r = drm_global_item_ref(global_ref);
102 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
106 mutex_init(&adev->mman.gtt_window_lock);
108 ring = adev->mman.buffer_funcs_ring;
109 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
110 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
111 rq, amdgpu_sched_jobs);
113 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
117 adev->mman.mem_global_referenced = true;
122 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
124 drm_global_item_unref(&adev->mman.mem_global_ref);
129 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
131 if (adev->mman.mem_global_referenced) {
132 amd_sched_entity_fini(adev->mman.entity.sched,
134 mutex_destroy(&adev->mman.gtt_window_lock);
135 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
136 drm_global_item_unref(&adev->mman.mem_global_ref);
137 adev->mman.mem_global_referenced = false;
141 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
146 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
147 struct ttm_mem_type_manager *man)
149 struct amdgpu_device *adev;
151 adev = amdgpu_ttm_adev(bdev);
156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
157 man->available_caching = TTM_PL_MASK_CACHING;
158 man->default_caching = TTM_PL_FLAG_CACHED;
161 man->func = &amdgpu_gtt_mgr_func;
162 man->gpu_offset = adev->mc.gart_start;
163 man->available_caching = TTM_PL_MASK_CACHING;
164 man->default_caching = TTM_PL_FLAG_CACHED;
165 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
168 /* "On-card" video ram */
169 man->func = &amdgpu_vram_mgr_func;
170 man->gpu_offset = adev->mc.vram_start;
171 man->flags = TTM_MEMTYPE_FLAG_FIXED |
172 TTM_MEMTYPE_FLAG_MAPPABLE;
173 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
174 man->default_caching = TTM_PL_FLAG_WC;
179 /* On-chip GDS memory*/
180 man->func = &ttm_bo_manager_func;
182 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
183 man->available_caching = TTM_PL_FLAG_UNCACHED;
184 man->default_caching = TTM_PL_FLAG_UNCACHED;
187 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
193 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
194 struct ttm_placement *placement)
196 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
197 struct amdgpu_bo *abo;
198 static const struct ttm_place placements = {
201 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
204 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
205 placement->placement = &placements;
206 placement->busy_placement = &placements;
207 placement->num_placement = 1;
208 placement->num_busy_placement = 1;
211 abo = container_of(bo, struct amdgpu_bo, tbo);
212 switch (bo->mem.mem_type) {
214 if (adev->mman.buffer_funcs &&
215 adev->mman.buffer_funcs_ring &&
216 adev->mman.buffer_funcs_ring->ready == false) {
217 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
218 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
219 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
220 unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
221 struct drm_mm_node *node = bo->mem.mm_node;
222 unsigned long pages_left;
224 for (pages_left = bo->mem.num_pages;
226 pages_left -= node->size, node++) {
227 if (node->start < fpfn)
234 /* Try evicting to the CPU inaccessible part of VRAM
235 * first, but only set GTT as busy placement, so this
236 * BO will be evicted to GTT rather than causing other
237 * BOs to be evicted from VRAM
239 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
240 AMDGPU_GEM_DOMAIN_GTT);
241 abo->placements[0].fpfn = fpfn;
242 abo->placements[0].lpfn = 0;
243 abo->placement.busy_placement = &abo->placements[1];
244 abo->placement.num_busy_placement = 1;
247 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
252 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
254 *placement = abo->placement;
257 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
259 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
261 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
263 return drm_vma_node_verify_access(&abo->gem_base.vma_node,
267 static void amdgpu_move_null(struct ttm_buffer_object *bo,
268 struct ttm_mem_reg *new_mem)
270 struct ttm_mem_reg *old_mem = &bo->mem;
272 BUG_ON(old_mem->mm_node != NULL);
274 new_mem->mm_node = NULL;
277 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
278 struct drm_mm_node *mm_node,
279 struct ttm_mem_reg *mem)
283 if (mem->mem_type != TTM_PL_TT ||
284 amdgpu_gtt_mgr_is_allocated(mem)) {
285 addr = mm_node->start << PAGE_SHIFT;
286 addr += bo->bdev->man[mem->mem_type].gpu_offset;
291 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
292 bool evict, bool no_wait_gpu,
293 struct ttm_mem_reg *new_mem,
294 struct ttm_mem_reg *old_mem)
296 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
297 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
299 struct drm_mm_node *old_mm, *new_mm;
300 uint64_t old_start, old_size, new_start, new_size;
301 unsigned long num_pages;
302 struct dma_fence *fence = NULL;
305 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
308 DRM_ERROR("Trying to move memory with ring turned off.\n");
312 old_mm = old_mem->mm_node;
313 old_size = old_mm->size;
314 old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
316 new_mm = new_mem->mm_node;
317 new_size = new_mm->size;
318 new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
320 num_pages = new_mem->num_pages;
321 mutex_lock(&adev->mman.gtt_window_lock);
323 unsigned long cur_pages = min(min(old_size, new_size),
324 (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
325 uint64_t from = old_start, to = new_start;
326 struct dma_fence *next;
328 if (old_mem->mem_type == TTM_PL_TT &&
329 !amdgpu_gtt_mgr_is_allocated(old_mem)) {
330 r = amdgpu_map_buffer(bo, old_mem, cur_pages,
331 old_start, 0, ring, &from);
336 if (new_mem->mem_type == TTM_PL_TT &&
337 !amdgpu_gtt_mgr_is_allocated(new_mem)) {
338 r = amdgpu_map_buffer(bo, new_mem, cur_pages,
339 new_start, 1, ring, &to);
344 r = amdgpu_copy_buffer(ring, from, to,
345 cur_pages * PAGE_SIZE,
346 bo->resv, &next, false, true);
350 dma_fence_put(fence);
353 num_pages -= cur_pages;
357 old_size -= cur_pages;
359 old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
360 old_size = old_mm->size;
362 old_start += cur_pages * PAGE_SIZE;
365 new_size -= cur_pages;
367 new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
368 new_size = new_mm->size;
370 new_start += cur_pages * PAGE_SIZE;
373 mutex_unlock(&adev->mman.gtt_window_lock);
375 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
376 dma_fence_put(fence);
380 mutex_unlock(&adev->mman.gtt_window_lock);
383 dma_fence_wait(fence, false);
384 dma_fence_put(fence);
388 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
389 bool evict, bool interruptible,
391 struct ttm_mem_reg *new_mem)
393 struct amdgpu_device *adev;
394 struct ttm_mem_reg *old_mem = &bo->mem;
395 struct ttm_mem_reg tmp_mem;
396 struct ttm_place placements;
397 struct ttm_placement placement;
400 adev = amdgpu_ttm_adev(bo->bdev);
402 tmp_mem.mm_node = NULL;
403 placement.num_placement = 1;
404 placement.placement = &placements;
405 placement.num_busy_placement = 1;
406 placement.busy_placement = &placements;
409 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
410 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
411 interruptible, no_wait_gpu);
416 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
421 r = ttm_tt_bind(bo->ttm, &tmp_mem);
425 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
429 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
431 ttm_bo_mem_put(bo, &tmp_mem);
435 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
436 bool evict, bool interruptible,
438 struct ttm_mem_reg *new_mem)
440 struct amdgpu_device *adev;
441 struct ttm_mem_reg *old_mem = &bo->mem;
442 struct ttm_mem_reg tmp_mem;
443 struct ttm_placement placement;
444 struct ttm_place placements;
447 adev = amdgpu_ttm_adev(bo->bdev);
449 tmp_mem.mm_node = NULL;
450 placement.num_placement = 1;
451 placement.placement = &placements;
452 placement.num_busy_placement = 1;
453 placement.busy_placement = &placements;
456 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
457 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
458 interruptible, no_wait_gpu);
462 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
466 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
471 ttm_bo_mem_put(bo, &tmp_mem);
475 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
476 bool evict, bool interruptible,
478 struct ttm_mem_reg *new_mem)
480 struct amdgpu_device *adev;
481 struct amdgpu_bo *abo;
482 struct ttm_mem_reg *old_mem = &bo->mem;
485 /* Can't move a pinned BO */
486 abo = container_of(bo, struct amdgpu_bo, tbo);
487 if (WARN_ON_ONCE(abo->pin_count > 0))
490 adev = amdgpu_ttm_adev(bo->bdev);
492 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
493 amdgpu_move_null(bo, new_mem);
496 if ((old_mem->mem_type == TTM_PL_TT &&
497 new_mem->mem_type == TTM_PL_SYSTEM) ||
498 (old_mem->mem_type == TTM_PL_SYSTEM &&
499 new_mem->mem_type == TTM_PL_TT)) {
501 amdgpu_move_null(bo, new_mem);
504 if (adev->mman.buffer_funcs == NULL ||
505 adev->mman.buffer_funcs_ring == NULL ||
506 !adev->mman.buffer_funcs_ring->ready) {
511 if (old_mem->mem_type == TTM_PL_VRAM &&
512 new_mem->mem_type == TTM_PL_SYSTEM) {
513 r = amdgpu_move_vram_ram(bo, evict, interruptible,
514 no_wait_gpu, new_mem);
515 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
516 new_mem->mem_type == TTM_PL_VRAM) {
517 r = amdgpu_move_ram_vram(bo, evict, interruptible,
518 no_wait_gpu, new_mem);
520 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
525 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
531 if (bo->type == ttm_bo_type_device &&
532 new_mem->mem_type == TTM_PL_VRAM &&
533 old_mem->mem_type != TTM_PL_VRAM) {
534 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
535 * accesses the BO after it's moved.
537 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
540 /* update statistics */
541 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
545 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
547 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
548 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
550 mem->bus.addr = NULL;
552 mem->bus.size = mem->num_pages << PAGE_SHIFT;
554 mem->bus.is_iomem = false;
555 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
557 switch (mem->mem_type) {
564 mem->bus.offset = mem->start << PAGE_SHIFT;
565 /* check if it's visible */
566 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
568 mem->bus.base = adev->mc.aper_base;
569 mem->bus.is_iomem = true;
577 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
581 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
582 unsigned long page_offset)
584 struct drm_mm_node *mm = bo->mem.mm_node;
585 uint64_t size = mm->size;
586 uint64_t offset = page_offset;
588 page_offset = do_div(offset, size);
590 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
594 * TTM backend functions.
596 struct amdgpu_ttm_gup_task_list {
597 struct list_head list;
598 struct task_struct *task;
601 struct amdgpu_ttm_tt {
602 struct ttm_dma_tt ttm;
603 struct amdgpu_device *adev;
606 struct mm_struct *usermm;
608 spinlock_t guptasklock;
609 struct list_head guptasks;
610 atomic_t mmu_invalidations;
611 struct list_head list;
614 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
616 struct amdgpu_ttm_tt *gtt = (void *)ttm;
617 unsigned int flags = 0;
621 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
624 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
625 /* check that we only use anonymous memory
626 to prevent problems with writeback */
627 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
628 struct vm_area_struct *vma;
630 vma = find_vma(gtt->usermm, gtt->userptr);
631 if (!vma || vma->vm_file || vma->vm_end < end)
636 unsigned num_pages = ttm->num_pages - pinned;
637 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
638 struct page **p = pages + pinned;
639 struct amdgpu_ttm_gup_task_list guptask;
641 guptask.task = current;
642 spin_lock(>t->guptasklock);
643 list_add(&guptask.list, >t->guptasks);
644 spin_unlock(>t->guptasklock);
646 r = get_user_pages(userptr, num_pages, flags, p, NULL);
648 spin_lock(>t->guptasklock);
649 list_del(&guptask.list);
650 spin_unlock(>t->guptasklock);
657 } while (pinned < ttm->num_pages);
662 release_pages(pages, pinned, 0);
666 static void amdgpu_trace_dma_map(struct ttm_tt *ttm)
668 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
669 struct amdgpu_ttm_tt *gtt = (void *)ttm;
672 if (unlikely(trace_amdgpu_ttm_tt_populate_enabled())) {
673 for (i = 0; i < ttm->num_pages; i++) {
674 trace_amdgpu_ttm_tt_populate(
676 gtt->ttm.dma_address[i],
677 page_to_phys(ttm->pages[i]));
682 static void amdgpu_trace_dma_unmap(struct ttm_tt *ttm)
684 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
685 struct amdgpu_ttm_tt *gtt = (void *)ttm;
688 if (unlikely(trace_amdgpu_ttm_tt_unpopulate_enabled())) {
689 for (i = 0; i < ttm->num_pages; i++) {
690 trace_amdgpu_ttm_tt_unpopulate(
692 gtt->ttm.dma_address[i],
693 page_to_phys(ttm->pages[i]));
698 /* prepare the sg table with the user pages */
699 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
701 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
702 struct amdgpu_ttm_tt *gtt = (void *)ttm;
706 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
707 enum dma_data_direction direction = write ?
708 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
710 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
711 ttm->num_pages << PAGE_SHIFT,
717 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
718 if (nents != ttm->sg->nents)
721 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
722 gtt->ttm.dma_address, ttm->num_pages);
724 amdgpu_trace_dma_map(ttm);
734 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
736 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
737 struct amdgpu_ttm_tt *gtt = (void *)ttm;
738 struct sg_page_iter sg_iter;
740 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
741 enum dma_data_direction direction = write ?
742 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
744 /* double check that we don't free the table twice */
745 if (!ttm->sg || !ttm->sg->sgl)
748 /* free the sg table and pages again */
749 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
751 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
752 struct page *page = sg_page_iter_page(&sg_iter);
753 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
754 set_page_dirty(page);
756 mark_page_accessed(page);
760 amdgpu_trace_dma_unmap(ttm);
762 sg_free_table(ttm->sg);
765 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
766 struct ttm_mem_reg *bo_mem)
768 struct amdgpu_ttm_tt *gtt = (void*)ttm;
773 r = amdgpu_ttm_tt_pin_userptr(ttm);
775 DRM_ERROR("failed to pin userptr\n");
779 if (!ttm->num_pages) {
780 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
781 ttm->num_pages, bo_mem, ttm);
784 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
785 bo_mem->mem_type == AMDGPU_PL_GWS ||
786 bo_mem->mem_type == AMDGPU_PL_OA)
789 if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
792 spin_lock(>t->adev->gtt_list_lock);
793 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
794 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
795 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
796 ttm->pages, gtt->ttm.dma_address, flags);
799 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
800 ttm->num_pages, gtt->offset);
801 goto error_gart_bind;
804 list_add_tail(>t->list, >t->adev->gtt_list);
806 spin_unlock(>t->adev->gtt_list_lock);
810 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
812 struct amdgpu_ttm_tt *gtt = (void *)ttm;
814 return gtt && !list_empty(>t->list);
817 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
819 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
820 struct ttm_tt *ttm = bo->ttm;
821 struct ttm_mem_reg tmp;
823 struct ttm_placement placement;
824 struct ttm_place placements;
827 if (!ttm || amdgpu_ttm_is_bound(ttm))
832 placement.num_placement = 1;
833 placement.placement = &placements;
834 placement.num_busy_placement = 1;
835 placement.busy_placement = &placements;
837 placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
838 placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
840 r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
844 r = ttm_bo_move_ttm(bo, true, false, &tmp);
846 ttm_bo_mem_put(bo, &tmp);
848 bo->offset = (bo->mem.start << PAGE_SHIFT) +
849 bo->bdev->man[bo->mem.mem_type].gpu_offset;
854 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
856 struct amdgpu_ttm_tt *gtt, *tmp;
857 struct ttm_mem_reg bo_mem;
861 bo_mem.mem_type = TTM_PL_TT;
862 spin_lock(&adev->gtt_list_lock);
863 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
864 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem);
865 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
866 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
869 spin_unlock(&adev->gtt_list_lock);
870 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
871 gtt->ttm.ttm.num_pages, gtt->offset);
875 spin_unlock(&adev->gtt_list_lock);
879 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
881 struct amdgpu_ttm_tt *gtt = (void *)ttm;
885 amdgpu_ttm_tt_unpin_userptr(ttm);
887 if (!amdgpu_ttm_is_bound(ttm))
890 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
891 spin_lock(>t->adev->gtt_list_lock);
892 r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
894 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
895 gtt->ttm.ttm.num_pages, gtt->offset);
898 list_del_init(>t->list);
900 spin_unlock(>t->adev->gtt_list_lock);
904 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
906 struct amdgpu_ttm_tt *gtt = (void *)ttm;
908 ttm_dma_tt_fini(>t->ttm);
912 static struct ttm_backend_func amdgpu_backend_func = {
913 .bind = &amdgpu_ttm_backend_bind,
914 .unbind = &amdgpu_ttm_backend_unbind,
915 .destroy = &amdgpu_ttm_backend_destroy,
918 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
919 unsigned long size, uint32_t page_flags,
920 struct page *dummy_read_page)
922 struct amdgpu_device *adev;
923 struct amdgpu_ttm_tt *gtt;
925 adev = amdgpu_ttm_adev(bdev);
927 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
931 gtt->ttm.ttm.func = &amdgpu_backend_func;
933 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
937 INIT_LIST_HEAD(>t->list);
938 return >t->ttm.ttm;
941 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
943 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
944 struct amdgpu_ttm_tt *gtt = (void *)ttm;
947 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
949 if (ttm->state != tt_unpopulated)
952 if (gtt && gtt->userptr) {
953 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
957 ttm->page_flags |= TTM_PAGE_FLAG_SG;
958 ttm->state = tt_unbound;
962 if (slave && ttm->sg) {
963 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
964 gtt->ttm.dma_address, ttm->num_pages);
965 ttm->state = tt_unbound;
970 #ifdef CONFIG_SWIOTLB
971 if (swiotlb_nr_tbl()) {
972 r = ttm_dma_populate(>t->ttm, adev->dev);
977 r = ttm_pool_populate(ttm);
982 for (i = 0; i < ttm->num_pages; i++) {
983 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
985 PCI_DMA_BIDIRECTIONAL);
986 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
988 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
989 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
990 gtt->ttm.dma_address[i] = 0;
992 ttm_pool_unpopulate(ttm);
1000 amdgpu_trace_dma_map(ttm);
1004 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1006 struct amdgpu_device *adev;
1007 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1009 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1011 if (gtt && gtt->userptr) {
1014 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1021 adev = amdgpu_ttm_adev(ttm->bdev);
1023 amdgpu_trace_dma_unmap(ttm);
1025 #ifdef CONFIG_SWIOTLB
1026 if (swiotlb_nr_tbl()) {
1027 ttm_dma_unpopulate(>t->ttm, adev->dev);
1032 for (i = 0; i < ttm->num_pages; i++) {
1033 if (gtt->ttm.dma_address[i]) {
1034 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
1035 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1039 ttm_pool_unpopulate(ttm);
1042 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1045 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1050 gtt->userptr = addr;
1051 gtt->usermm = current->mm;
1052 gtt->userflags = flags;
1053 spin_lock_init(>t->guptasklock);
1054 INIT_LIST_HEAD(>t->guptasks);
1055 atomic_set(>t->mmu_invalidations, 0);
1060 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1062 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1070 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1073 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1074 struct amdgpu_ttm_gup_task_list *entry;
1077 if (gtt == NULL || !gtt->userptr)
1080 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1081 if (gtt->userptr > end || gtt->userptr + size <= start)
1084 spin_lock(>t->guptasklock);
1085 list_for_each_entry(entry, >t->guptasks, list) {
1086 if (entry->task == current) {
1087 spin_unlock(>t->guptasklock);
1091 spin_unlock(>t->guptasklock);
1093 atomic_inc(>t->mmu_invalidations);
1098 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1099 int *last_invalidated)
1101 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1102 int prev_invalidated = *last_invalidated;
1104 *last_invalidated = atomic_read(>t->mmu_invalidations);
1105 return prev_invalidated != *last_invalidated;
1108 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1110 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1115 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1118 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1119 struct ttm_mem_reg *mem)
1123 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1124 flags |= AMDGPU_PTE_VALID;
1126 if (mem && mem->mem_type == TTM_PL_TT) {
1127 flags |= AMDGPU_PTE_SYSTEM;
1129 if (ttm->caching_state == tt_cached)
1130 flags |= AMDGPU_PTE_SNOOPED;
1133 flags |= adev->gart.gart_pte_flags;
1134 flags |= AMDGPU_PTE_READABLE;
1136 if (!amdgpu_ttm_tt_is_readonly(ttm))
1137 flags |= AMDGPU_PTE_WRITEABLE;
1142 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1143 const struct ttm_place *place)
1145 unsigned long num_pages = bo->mem.num_pages;
1146 struct drm_mm_node *node = bo->mem.mm_node;
1148 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1149 return ttm_bo_eviction_valuable(bo, place);
1151 switch (bo->mem.mem_type) {
1156 /* Check each drm MM node individually */
1158 if (place->fpfn < (node->start + node->size) &&
1159 !(place->lpfn && place->lpfn <= node->start))
1162 num_pages -= node->size;
1171 return ttm_bo_eviction_valuable(bo, place);
1174 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1175 unsigned long offset,
1176 void *buf, int len, int write)
1178 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
1179 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1180 struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
1184 unsigned long flags;
1186 if (bo->mem.mem_type != TTM_PL_VRAM)
1189 while (offset >= (nodes->size << PAGE_SHIFT)) {
1190 offset -= nodes->size << PAGE_SHIFT;
1193 pos = (nodes->start << PAGE_SHIFT) + offset;
1195 while (len && pos < adev->mc.mc_vram_size) {
1196 uint64_t aligned_pos = pos & ~(uint64_t)3;
1197 uint32_t bytes = 4 - (pos & 3);
1198 uint32_t shift = (pos & 3) * 8;
1199 uint32_t mask = 0xffffffff << shift;
1202 mask &= 0xffffffff >> (bytes - len) * 8;
1206 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1207 WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1208 WREG32(mmMM_INDEX_HI, aligned_pos >> 31);
1209 if (!write || mask != 0xffffffff)
1210 value = RREG32(mmMM_DATA);
1213 value |= (*(uint32_t *)buf << shift) & mask;
1214 WREG32(mmMM_DATA, value);
1216 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1218 value = (value & mask) >> shift;
1219 memcpy(buf, &value, bytes);
1223 buf = (uint8_t *)buf + bytes;
1226 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1228 pos = (nodes->start << PAGE_SHIFT);
1235 static struct ttm_bo_driver amdgpu_bo_driver = {
1236 .ttm_tt_create = &amdgpu_ttm_tt_create,
1237 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1238 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1239 .invalidate_caches = &amdgpu_invalidate_caches,
1240 .init_mem_type = &amdgpu_init_mem_type,
1241 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1242 .evict_flags = &amdgpu_evict_flags,
1243 .move = &amdgpu_bo_move,
1244 .verify_access = &amdgpu_verify_access,
1245 .move_notify = &amdgpu_bo_move_notify,
1246 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1247 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1248 .io_mem_free = &amdgpu_ttm_io_mem_free,
1249 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1250 .access_memory = &amdgpu_ttm_access_memory
1253 int amdgpu_ttm_init(struct amdgpu_device *adev)
1259 r = amdgpu_ttm_global_init(adev);
1263 /* No others user of address space so set it to 0 */
1264 r = ttm_bo_device_init(&adev->mman.bdev,
1265 adev->mman.bo_global_ref.ref.object,
1267 adev->ddev->anon_inode->i_mapping,
1268 DRM_FILE_PAGE_OFFSET,
1271 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1274 adev->mman.initialized = true;
1275 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1276 adev->mc.real_vram_size >> PAGE_SHIFT);
1278 DRM_ERROR("Failed initializing VRAM heap.\n");
1282 /* Reduce size of CPU-visible VRAM if requested */
1283 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1284 if (amdgpu_vis_vram_limit > 0 &&
1285 vis_vram_limit <= adev->mc.visible_vram_size)
1286 adev->mc.visible_vram_size = vis_vram_limit;
1288 /* Change the size here instead of the init above so only lpfn is affected */
1289 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1291 r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
1292 AMDGPU_GEM_DOMAIN_VRAM,
1293 &adev->stolen_vga_memory,
1297 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1298 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1300 if (amdgpu_gtt_size == -1)
1301 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1302 adev->mc.mc_vram_size);
1304 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1305 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1307 DRM_ERROR("Failed initializing GTT heap.\n");
1310 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1311 (unsigned)(gtt_size / (1024 * 1024)));
1313 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1314 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1315 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1316 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1317 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1318 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1319 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1320 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1321 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1323 if (adev->gds.mem.total_size) {
1324 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1325 adev->gds.mem.total_size >> PAGE_SHIFT);
1327 DRM_ERROR("Failed initializing GDS heap.\n");
1333 if (adev->gds.gws.total_size) {
1334 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1335 adev->gds.gws.total_size >> PAGE_SHIFT);
1337 DRM_ERROR("Failed initializing gws heap.\n");
1343 if (adev->gds.oa.total_size) {
1344 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1345 adev->gds.oa.total_size >> PAGE_SHIFT);
1347 DRM_ERROR("Failed initializing oa heap.\n");
1352 r = amdgpu_ttm_debugfs_init(adev);
1354 DRM_ERROR("Failed to init debugfs\n");
1360 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1364 if (!adev->mman.initialized)
1366 amdgpu_ttm_debugfs_fini(adev);
1367 if (adev->stolen_vga_memory) {
1368 r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
1370 amdgpu_bo_unpin(adev->stolen_vga_memory);
1371 amdgpu_bo_unreserve(adev->stolen_vga_memory);
1373 amdgpu_bo_unref(&adev->stolen_vga_memory);
1375 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1376 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1377 if (adev->gds.mem.total_size)
1378 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1379 if (adev->gds.gws.total_size)
1380 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1381 if (adev->gds.oa.total_size)
1382 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1383 ttm_bo_device_release(&adev->mman.bdev);
1384 amdgpu_gart_fini(adev);
1385 amdgpu_ttm_global_fini(adev);
1386 adev->mman.initialized = false;
1387 DRM_INFO("amdgpu: ttm finalized\n");
1390 /* this should only be called at bootup or when userspace
1392 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1394 struct ttm_mem_type_manager *man;
1396 if (!adev->mman.initialized)
1399 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1400 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1401 man->size = size >> PAGE_SHIFT;
1404 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1406 struct drm_file *file_priv;
1407 struct amdgpu_device *adev;
1409 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1412 file_priv = filp->private_data;
1413 adev = file_priv->minor->dev->dev_private;
1417 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1420 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1421 struct ttm_mem_reg *mem, unsigned num_pages,
1422 uint64_t offset, unsigned window,
1423 struct amdgpu_ring *ring,
1426 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1427 struct amdgpu_device *adev = ring->adev;
1428 struct ttm_tt *ttm = bo->ttm;
1429 struct amdgpu_job *job;
1430 unsigned num_dw, num_bytes;
1431 dma_addr_t *dma_address;
1432 struct dma_fence *fence;
1433 uint64_t src_addr, dst_addr;
1437 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1438 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1440 *addr = adev->mc.gart_start;
1441 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1442 AMDGPU_GPU_PAGE_SIZE;
1444 num_dw = adev->mman.buffer_funcs->copy_num_dw;
1445 while (num_dw & 0x7)
1448 num_bytes = num_pages * 8;
1450 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1454 src_addr = num_dw * 4;
1455 src_addr += job->ibs[0].gpu_addr;
1457 dst_addr = adev->gart.table_addr;
1458 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1459 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1460 dst_addr, num_bytes);
1462 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1463 WARN_ON(job->ibs[0].length_dw > num_dw);
1465 dma_address = >t->ttm.dma_address[offset >> PAGE_SHIFT];
1466 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1467 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1468 &job->ibs[0].ptr[num_dw]);
1472 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1473 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1477 dma_fence_put(fence);
1482 amdgpu_job_free(job);
1486 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1487 uint64_t dst_offset, uint32_t byte_count,
1488 struct reservation_object *resv,
1489 struct dma_fence **fence, bool direct_submit,
1490 bool vm_needs_flush)
1492 struct amdgpu_device *adev = ring->adev;
1493 struct amdgpu_job *job;
1496 unsigned num_loops, num_dw;
1500 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1501 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1502 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1504 /* for IB padding */
1505 while (num_dw & 0x7)
1508 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1512 job->vm_needs_flush = vm_needs_flush;
1514 r = amdgpu_sync_resv(adev, &job->sync, resv,
1515 AMDGPU_FENCE_OWNER_UNDEFINED);
1517 DRM_ERROR("sync failed (%d).\n", r);
1522 for (i = 0; i < num_loops; i++) {
1523 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1525 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1526 dst_offset, cur_size_in_bytes);
1528 src_offset += cur_size_in_bytes;
1529 dst_offset += cur_size_in_bytes;
1530 byte_count -= cur_size_in_bytes;
1533 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1534 WARN_ON(job->ibs[0].length_dw > num_dw);
1535 if (direct_submit) {
1536 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1538 job->fence = dma_fence_get(*fence);
1540 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1541 amdgpu_job_free(job);
1543 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1544 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1552 amdgpu_job_free(job);
1556 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1558 struct reservation_object *resv,
1559 struct dma_fence **fence)
1561 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1562 /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/
1563 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1564 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1566 struct drm_mm_node *mm_node;
1567 unsigned long num_pages;
1568 unsigned int num_loops, num_dw;
1570 struct amdgpu_job *job;
1574 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1578 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1579 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1584 num_pages = bo->tbo.num_pages;
1585 mm_node = bo->tbo.mem.mm_node;
1588 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1590 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1591 num_pages -= mm_node->size;
1595 /* 10 double words for each SDMA_OP_PTEPDE cmd */
1596 num_dw = num_loops * 10;
1598 /* for IB padding */
1601 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1606 r = amdgpu_sync_resv(adev, &job->sync, resv,
1607 AMDGPU_FENCE_OWNER_UNDEFINED);
1609 DRM_ERROR("sync failed (%d).\n", r);
1614 num_pages = bo->tbo.num_pages;
1615 mm_node = bo->tbo.mem.mm_node;
1618 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1621 WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
1623 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1624 while (byte_count) {
1625 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1627 amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
1629 cur_size_in_bytes >> 3, 0,
1632 dst_addr += cur_size_in_bytes;
1633 byte_count -= cur_size_in_bytes;
1636 num_pages -= mm_node->size;
1640 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1641 WARN_ON(job->ibs[0].length_dw > num_dw);
1642 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1643 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1650 amdgpu_job_free(job);
1654 #if defined(CONFIG_DEBUG_FS)
1656 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1658 struct drm_info_node *node = (struct drm_info_node *)m->private;
1659 unsigned ttm_pl = *(int *)node->info_ent->data;
1660 struct drm_device *dev = node->minor->dev;
1661 struct amdgpu_device *adev = dev->dev_private;
1662 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1663 struct drm_printer p = drm_seq_file_printer(m);
1665 man->func->debug(man, &p);
1669 static int ttm_pl_vram = TTM_PL_VRAM;
1670 static int ttm_pl_tt = TTM_PL_TT;
1672 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1673 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1674 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1675 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1676 #ifdef CONFIG_SWIOTLB
1677 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1681 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1682 size_t size, loff_t *pos)
1684 struct amdgpu_device *adev = file_inode(f)->i_private;
1688 if (size & 0x3 || *pos & 0x3)
1691 if (*pos >= adev->mc.mc_vram_size)
1695 unsigned long flags;
1698 if (*pos >= adev->mc.mc_vram_size)
1701 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1702 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1703 WREG32(mmMM_INDEX_HI, *pos >> 31);
1704 value = RREG32(mmMM_DATA);
1705 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1707 r = put_user(value, (uint32_t *)buf);
1720 static const struct file_operations amdgpu_ttm_vram_fops = {
1721 .owner = THIS_MODULE,
1722 .read = amdgpu_ttm_vram_read,
1723 .llseek = default_llseek
1726 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1728 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1729 size_t size, loff_t *pos)
1731 struct amdgpu_device *adev = file_inode(f)->i_private;
1736 loff_t p = *pos / PAGE_SIZE;
1737 unsigned off = *pos & ~PAGE_MASK;
1738 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1742 if (p >= adev->gart.num_cpu_pages)
1745 page = adev->gart.pages[p];
1750 r = copy_to_user(buf, ptr, cur_size);
1751 kunmap(adev->gart.pages[p]);
1753 r = clear_user(buf, cur_size);
1767 static const struct file_operations amdgpu_ttm_gtt_fops = {
1768 .owner = THIS_MODULE,
1769 .read = amdgpu_ttm_gtt_read,
1770 .llseek = default_llseek
1777 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1779 #if defined(CONFIG_DEBUG_FS)
1782 struct drm_minor *minor = adev->ddev->primary;
1783 struct dentry *ent, *root = minor->debugfs_root;
1785 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1786 adev, &amdgpu_ttm_vram_fops);
1788 return PTR_ERR(ent);
1789 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1790 adev->mman.vram = ent;
1792 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1793 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1794 adev, &amdgpu_ttm_gtt_fops);
1796 return PTR_ERR(ent);
1797 i_size_write(ent->d_inode, adev->mc.gart_size);
1798 adev->mman.gtt = ent;
1801 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1803 #ifdef CONFIG_SWIOTLB
1804 if (!swiotlb_nr_tbl())
1808 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1815 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1817 #if defined(CONFIG_DEBUG_FS)
1819 debugfs_remove(adev->mman.vram);
1820 adev->mman.vram = NULL;
1822 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1823 debugfs_remove(adev->mman.gtt);
1824 adev->mman.gtt = NULL;