2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
37 #include <ttm/ttm_memory.h>
39 #include <drm/amdgpu_drm.h>
40 #include <linux/seq_file.h>
41 #include <linux/slab.h>
42 #include <linux/swiotlb.h>
43 #include <linux/swap.h>
44 #include <linux/pagemap.h>
45 #include <linux/debugfs.h>
47 #include "bif/bif_4_1_d.h"
49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
51 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
52 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
54 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
56 struct amdgpu_mman *mman;
57 struct amdgpu_device *adev;
59 mman = container_of(bdev, struct amdgpu_mman, bdev);
60 adev = container_of(mman, struct amdgpu_device, mman);
68 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
70 return ttm_mem_global_init(ref->object);
73 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
75 ttm_mem_global_release(ref->object);
78 int amdgpu_ttm_global_init(struct amdgpu_device *adev)
80 struct drm_global_reference *global_ref;
81 struct amdgpu_ring *ring;
82 struct amd_sched_rq *rq;
85 adev->mman.mem_global_referenced = false;
86 global_ref = &adev->mman.mem_global_ref;
87 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
88 global_ref->size = sizeof(struct ttm_mem_global);
89 global_ref->init = &amdgpu_ttm_mem_global_init;
90 global_ref->release = &amdgpu_ttm_mem_global_release;
91 r = drm_global_item_ref(global_ref);
93 DRM_ERROR("Failed setting up TTM memory accounting "
98 adev->mman.bo_global_ref.mem_glob =
99 adev->mman.mem_global_ref.object;
100 global_ref = &adev->mman.bo_global_ref.ref;
101 global_ref->global_type = DRM_GLOBAL_TTM_BO;
102 global_ref->size = sizeof(struct ttm_bo_global);
103 global_ref->init = &ttm_bo_global_init;
104 global_ref->release = &ttm_bo_global_release;
105 r = drm_global_item_ref(global_ref);
107 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
111 ring = adev->mman.buffer_funcs_ring;
112 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
113 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
114 rq, amdgpu_sched_jobs);
116 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
120 adev->mman.mem_global_referenced = true;
125 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
127 drm_global_item_unref(&adev->mman.mem_global_ref);
132 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
134 if (adev->mman.mem_global_referenced) {
135 amd_sched_entity_fini(adev->mman.entity.sched,
137 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
138 drm_global_item_unref(&adev->mman.mem_global_ref);
139 adev->mman.mem_global_referenced = false;
143 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
148 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
149 struct ttm_mem_type_manager *man)
151 struct amdgpu_device *adev;
153 adev = amdgpu_get_adev(bdev);
158 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
159 man->available_caching = TTM_PL_MASK_CACHING;
160 man->default_caching = TTM_PL_FLAG_CACHED;
163 man->func = &amdgpu_gtt_mgr_func;
164 man->gpu_offset = adev->mc.gtt_start;
165 man->available_caching = TTM_PL_MASK_CACHING;
166 man->default_caching = TTM_PL_FLAG_CACHED;
167 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
170 /* "On-card" video ram */
171 man->func = &ttm_bo_manager_func;
172 man->gpu_offset = adev->mc.vram_start;
173 man->flags = TTM_MEMTYPE_FLAG_FIXED |
174 TTM_MEMTYPE_FLAG_MAPPABLE;
175 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
176 man->default_caching = TTM_PL_FLAG_WC;
181 /* On-chip GDS memory*/
182 man->func = &ttm_bo_manager_func;
184 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
185 man->available_caching = TTM_PL_FLAG_UNCACHED;
186 man->default_caching = TTM_PL_FLAG_UNCACHED;
189 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
195 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
196 struct ttm_placement *placement)
198 struct amdgpu_bo *abo;
199 static struct ttm_place placements = {
202 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
206 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
207 placement->placement = &placements;
208 placement->busy_placement = &placements;
209 placement->num_placement = 1;
210 placement->num_busy_placement = 1;
213 abo = container_of(bo, struct amdgpu_bo, tbo);
214 switch (bo->mem.mem_type) {
216 if (abo->adev->mman.buffer_funcs_ring->ready == false) {
217 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
219 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
220 for (i = 0; i < abo->placement.num_placement; ++i) {
221 if (!(abo->placements[i].flags &
225 if (abo->placements[i].lpfn)
228 /* set an upper limit to force directly
229 * allocating address space for the BO.
231 abo->placements[i].lpfn =
232 abo->adev->mc.gtt_size >> PAGE_SHIFT;
238 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
240 *placement = abo->placement;
243 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
245 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
247 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
249 return drm_vma_node_verify_access(&abo->gem_base.vma_node,
253 static void amdgpu_move_null(struct ttm_buffer_object *bo,
254 struct ttm_mem_reg *new_mem)
256 struct ttm_mem_reg *old_mem = &bo->mem;
258 BUG_ON(old_mem->mm_node != NULL);
260 new_mem->mm_node = NULL;
263 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
264 bool evict, bool no_wait_gpu,
265 struct ttm_mem_reg *new_mem,
266 struct ttm_mem_reg *old_mem)
268 struct amdgpu_device *adev;
269 struct amdgpu_ring *ring;
270 uint64_t old_start, new_start;
274 adev = amdgpu_get_adev(bo->bdev);
275 ring = adev->mman.buffer_funcs_ring;
277 switch (old_mem->mem_type) {
279 r = amdgpu_ttm_bind(bo, old_mem);
284 old_start = (u64)old_mem->start << PAGE_SHIFT;
285 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
288 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
291 switch (new_mem->mem_type) {
293 r = amdgpu_ttm_bind(bo, new_mem);
298 new_start = (u64)new_mem->start << PAGE_SHIFT;
299 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
302 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
306 DRM_ERROR("Trying to move memory with ring turned off.\n");
310 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
312 r = amdgpu_copy_buffer(ring, old_start, new_start,
313 new_mem->num_pages * PAGE_SIZE, /* bytes */
314 bo->resv, &fence, false);
318 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
323 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
324 bool evict, bool interruptible,
326 struct ttm_mem_reg *new_mem)
328 struct amdgpu_device *adev;
329 struct ttm_mem_reg *old_mem = &bo->mem;
330 struct ttm_mem_reg tmp_mem;
331 struct ttm_place placements;
332 struct ttm_placement placement;
335 adev = amdgpu_get_adev(bo->bdev);
337 tmp_mem.mm_node = NULL;
338 placement.num_placement = 1;
339 placement.placement = &placements;
340 placement.num_busy_placement = 1;
341 placement.busy_placement = &placements;
343 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
344 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
345 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
346 interruptible, no_wait_gpu);
351 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
356 r = ttm_tt_bind(bo->ttm, &tmp_mem);
360 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
364 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
366 ttm_bo_mem_put(bo, &tmp_mem);
370 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
371 bool evict, bool interruptible,
373 struct ttm_mem_reg *new_mem)
375 struct amdgpu_device *adev;
376 struct ttm_mem_reg *old_mem = &bo->mem;
377 struct ttm_mem_reg tmp_mem;
378 struct ttm_placement placement;
379 struct ttm_place placements;
382 adev = amdgpu_get_adev(bo->bdev);
384 tmp_mem.mm_node = NULL;
385 placement.num_placement = 1;
386 placement.placement = &placements;
387 placement.num_busy_placement = 1;
388 placement.busy_placement = &placements;
390 placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
391 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
392 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
393 interruptible, no_wait_gpu);
397 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
401 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
406 ttm_bo_mem_put(bo, &tmp_mem);
410 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
411 bool evict, bool interruptible,
413 struct ttm_mem_reg *new_mem)
415 struct amdgpu_device *adev;
416 struct amdgpu_bo *abo;
417 struct ttm_mem_reg *old_mem = &bo->mem;
420 /* Can't move a pinned BO */
421 abo = container_of(bo, struct amdgpu_bo, tbo);
422 if (WARN_ON_ONCE(abo->pin_count > 0))
425 adev = amdgpu_get_adev(bo->bdev);
427 /* remember the eviction */
429 atomic64_inc(&adev->num_evictions);
431 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
432 amdgpu_move_null(bo, new_mem);
435 if ((old_mem->mem_type == TTM_PL_TT &&
436 new_mem->mem_type == TTM_PL_SYSTEM) ||
437 (old_mem->mem_type == TTM_PL_SYSTEM &&
438 new_mem->mem_type == TTM_PL_TT)) {
440 amdgpu_move_null(bo, new_mem);
443 if (adev->mman.buffer_funcs == NULL ||
444 adev->mman.buffer_funcs_ring == NULL ||
445 !adev->mman.buffer_funcs_ring->ready) {
450 if (old_mem->mem_type == TTM_PL_VRAM &&
451 new_mem->mem_type == TTM_PL_SYSTEM) {
452 r = amdgpu_move_vram_ram(bo, evict, interruptible,
453 no_wait_gpu, new_mem);
454 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
455 new_mem->mem_type == TTM_PL_VRAM) {
456 r = amdgpu_move_ram_vram(bo, evict, interruptible,
457 no_wait_gpu, new_mem);
459 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
464 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
470 /* update statistics */
471 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
475 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
477 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
478 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
480 mem->bus.addr = NULL;
482 mem->bus.size = mem->num_pages << PAGE_SHIFT;
484 mem->bus.is_iomem = false;
485 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
487 switch (mem->mem_type) {
494 if (mem->start == AMDGPU_BO_INVALID_OFFSET)
497 mem->bus.offset = mem->start << PAGE_SHIFT;
498 /* check if it's visible */
499 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
501 mem->bus.base = adev->mc.aper_base;
502 mem->bus.is_iomem = true;
505 * Alpha: use bus.addr to hold the ioremap() return,
506 * so we can modify bus.base below.
508 if (mem->placement & TTM_PL_FLAG_WC)
510 ioremap_wc(mem->bus.base + mem->bus.offset,
514 ioremap_nocache(mem->bus.base + mem->bus.offset,
518 * Alpha: Use just the bus offset plus
519 * the hose/domain memory base for bus.base.
520 * It then can be used to build PTEs for VRAM
521 * access, as done in ttm_bo_vm_fault().
523 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
524 adev->ddev->hose->dense_mem_base;
533 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
538 * TTM backend functions.
540 struct amdgpu_ttm_gup_task_list {
541 struct list_head list;
542 struct task_struct *task;
545 struct amdgpu_ttm_tt {
546 struct ttm_dma_tt ttm;
547 struct amdgpu_device *adev;
550 struct mm_struct *usermm;
552 spinlock_t guptasklock;
553 struct list_head guptasks;
554 atomic_t mmu_invalidations;
555 struct list_head list;
558 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
560 struct amdgpu_ttm_tt *gtt = (void *)ttm;
561 unsigned int flags = 0;
565 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
568 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
569 /* check that we only use anonymous memory
570 to prevent problems with writeback */
571 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
572 struct vm_area_struct *vma;
574 vma = find_vma(gtt->usermm, gtt->userptr);
575 if (!vma || vma->vm_file || vma->vm_end < end)
580 unsigned num_pages = ttm->num_pages - pinned;
581 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
582 struct page **p = pages + pinned;
583 struct amdgpu_ttm_gup_task_list guptask;
585 guptask.task = current;
586 spin_lock(>t->guptasklock);
587 list_add(&guptask.list, >t->guptasks);
588 spin_unlock(>t->guptasklock);
590 r = get_user_pages(userptr, num_pages, flags, p, NULL);
592 spin_lock(>t->guptasklock);
593 list_del(&guptask.list);
594 spin_unlock(>t->guptasklock);
601 } while (pinned < ttm->num_pages);
606 release_pages(pages, pinned, 0);
610 /* prepare the sg table with the user pages */
611 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
613 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
614 struct amdgpu_ttm_tt *gtt = (void *)ttm;
618 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
619 enum dma_data_direction direction = write ?
620 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
622 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
623 ttm->num_pages << PAGE_SHIFT,
629 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
630 if (nents != ttm->sg->nents)
633 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
634 gtt->ttm.dma_address, ttm->num_pages);
644 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
646 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
647 struct amdgpu_ttm_tt *gtt = (void *)ttm;
648 struct sg_page_iter sg_iter;
650 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
651 enum dma_data_direction direction = write ?
652 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
654 /* double check that we don't free the table twice */
655 if (!ttm->sg || !ttm->sg->sgl)
658 /* free the sg table and pages again */
659 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
661 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
662 struct page *page = sg_page_iter_page(&sg_iter);
663 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
664 set_page_dirty(page);
666 mark_page_accessed(page);
670 sg_free_table(ttm->sg);
673 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
674 struct ttm_mem_reg *bo_mem)
676 struct amdgpu_ttm_tt *gtt = (void*)ttm;
680 r = amdgpu_ttm_tt_pin_userptr(ttm);
682 DRM_ERROR("failed to pin userptr\n");
686 if (!ttm->num_pages) {
687 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
688 ttm->num_pages, bo_mem, ttm);
691 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
692 bo_mem->mem_type == AMDGPU_PL_GWS ||
693 bo_mem->mem_type == AMDGPU_PL_OA)
699 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
701 struct amdgpu_ttm_tt *gtt = (void *)ttm;
703 return gtt && !list_empty(>t->list);
706 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
708 struct ttm_tt *ttm = bo->ttm;
709 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
713 if (!ttm || amdgpu_ttm_is_bound(ttm))
716 r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
719 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
723 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
724 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
725 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
726 ttm->pages, gtt->ttm.dma_address, flags);
729 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
730 ttm->num_pages, gtt->offset);
733 spin_lock(>t->adev->gtt_list_lock);
734 list_add_tail(>t->list, >t->adev->gtt_list);
735 spin_unlock(>t->adev->gtt_list_lock);
739 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
741 struct amdgpu_ttm_tt *gtt, *tmp;
742 struct ttm_mem_reg bo_mem;
746 bo_mem.mem_type = TTM_PL_TT;
747 spin_lock(&adev->gtt_list_lock);
748 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
749 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem);
750 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
751 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
754 spin_unlock(&adev->gtt_list_lock);
755 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
756 gtt->ttm.ttm.num_pages, gtt->offset);
760 spin_unlock(&adev->gtt_list_lock);
764 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
766 struct amdgpu_ttm_tt *gtt = (void *)ttm;
769 amdgpu_ttm_tt_unpin_userptr(ttm);
771 if (!amdgpu_ttm_is_bound(ttm))
774 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
775 if (gtt->adev->gart.ready)
776 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
778 spin_lock(>t->adev->gtt_list_lock);
779 list_del_init(>t->list);
780 spin_unlock(>t->adev->gtt_list_lock);
785 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
787 struct amdgpu_ttm_tt *gtt = (void *)ttm;
789 ttm_dma_tt_fini(>t->ttm);
793 static struct ttm_backend_func amdgpu_backend_func = {
794 .bind = &amdgpu_ttm_backend_bind,
795 .unbind = &amdgpu_ttm_backend_unbind,
796 .destroy = &amdgpu_ttm_backend_destroy,
799 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
800 unsigned long size, uint32_t page_flags,
801 struct page *dummy_read_page)
803 struct amdgpu_device *adev;
804 struct amdgpu_ttm_tt *gtt;
806 adev = amdgpu_get_adev(bdev);
808 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
812 gtt->ttm.ttm.func = &amdgpu_backend_func;
814 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
818 INIT_LIST_HEAD(>t->list);
819 return >t->ttm.ttm;
822 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
824 struct amdgpu_device *adev;
825 struct amdgpu_ttm_tt *gtt = (void *)ttm;
828 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
830 if (ttm->state != tt_unpopulated)
833 if (gtt && gtt->userptr) {
834 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
838 ttm->page_flags |= TTM_PAGE_FLAG_SG;
839 ttm->state = tt_unbound;
843 if (slave && ttm->sg) {
844 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
845 gtt->ttm.dma_address, ttm->num_pages);
846 ttm->state = tt_unbound;
850 adev = amdgpu_get_adev(ttm->bdev);
852 #ifdef CONFIG_SWIOTLB
853 if (swiotlb_nr_tbl()) {
854 return ttm_dma_populate(>t->ttm, adev->dev);
858 r = ttm_pool_populate(ttm);
863 for (i = 0; i < ttm->num_pages; i++) {
864 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
866 PCI_DMA_BIDIRECTIONAL);
867 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
869 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
870 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
871 gtt->ttm.dma_address[i] = 0;
873 ttm_pool_unpopulate(ttm);
880 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
882 struct amdgpu_device *adev;
883 struct amdgpu_ttm_tt *gtt = (void *)ttm;
885 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
887 if (gtt && gtt->userptr) {
890 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
897 adev = amdgpu_get_adev(ttm->bdev);
899 #ifdef CONFIG_SWIOTLB
900 if (swiotlb_nr_tbl()) {
901 ttm_dma_unpopulate(>t->ttm, adev->dev);
906 for (i = 0; i < ttm->num_pages; i++) {
907 if (gtt->ttm.dma_address[i]) {
908 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
909 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
913 ttm_pool_unpopulate(ttm);
916 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
919 struct amdgpu_ttm_tt *gtt = (void *)ttm;
925 gtt->usermm = current->mm;
926 gtt->userflags = flags;
927 spin_lock_init(>t->guptasklock);
928 INIT_LIST_HEAD(>t->guptasks);
929 atomic_set(>t->mmu_invalidations, 0);
934 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
936 struct amdgpu_ttm_tt *gtt = (void *)ttm;
944 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
947 struct amdgpu_ttm_tt *gtt = (void *)ttm;
948 struct amdgpu_ttm_gup_task_list *entry;
951 if (gtt == NULL || !gtt->userptr)
954 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
955 if (gtt->userptr > end || gtt->userptr + size <= start)
958 spin_lock(>t->guptasklock);
959 list_for_each_entry(entry, >t->guptasks, list) {
960 if (entry->task == current) {
961 spin_unlock(>t->guptasklock);
965 spin_unlock(>t->guptasklock);
967 atomic_inc(>t->mmu_invalidations);
972 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
973 int *last_invalidated)
975 struct amdgpu_ttm_tt *gtt = (void *)ttm;
976 int prev_invalidated = *last_invalidated;
978 *last_invalidated = atomic_read(>t->mmu_invalidations);
979 return prev_invalidated != *last_invalidated;
982 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
984 struct amdgpu_ttm_tt *gtt = (void *)ttm;
989 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
992 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
993 struct ttm_mem_reg *mem)
997 if (mem && mem->mem_type != TTM_PL_SYSTEM)
998 flags |= AMDGPU_PTE_VALID;
1000 if (mem && mem->mem_type == TTM_PL_TT) {
1001 flags |= AMDGPU_PTE_SYSTEM;
1003 if (ttm->caching_state == tt_cached)
1004 flags |= AMDGPU_PTE_SNOOPED;
1007 if (adev->asic_type >= CHIP_TONGA)
1008 flags |= AMDGPU_PTE_EXECUTABLE;
1010 flags |= AMDGPU_PTE_READABLE;
1012 if (!amdgpu_ttm_tt_is_readonly(ttm))
1013 flags |= AMDGPU_PTE_WRITEABLE;
1018 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1020 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1023 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1024 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1026 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1027 if (&tbo->lru == lru->lru[j])
1028 lru->lru[j] = tbo->lru.prev;
1030 if (&tbo->swap == lru->swap_lru)
1031 lru->swap_lru = tbo->swap.prev;
1035 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1037 struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1038 unsigned log2_size = min(ilog2(tbo->num_pages),
1039 AMDGPU_TTM_LRU_SIZE - 1);
1041 return &adev->mman.log2_size[log2_size];
1044 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1046 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1047 struct list_head *res = lru->lru[tbo->mem.mem_type];
1049 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1050 while ((++lru)->lru[tbo->mem.mem_type] == res)
1051 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1056 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1058 struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1059 struct list_head *res = lru->swap_lru;
1061 lru->swap_lru = &tbo->swap;
1062 while ((++lru)->swap_lru == res)
1063 lru->swap_lru = &tbo->swap;
1068 static struct ttm_bo_driver amdgpu_bo_driver = {
1069 .ttm_tt_create = &amdgpu_ttm_tt_create,
1070 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1071 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1072 .invalidate_caches = &amdgpu_invalidate_caches,
1073 .init_mem_type = &amdgpu_init_mem_type,
1074 .evict_flags = &amdgpu_evict_flags,
1075 .move = &amdgpu_bo_move,
1076 .verify_access = &amdgpu_verify_access,
1077 .move_notify = &amdgpu_bo_move_notify,
1078 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1079 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1080 .io_mem_free = &amdgpu_ttm_io_mem_free,
1081 .lru_removal = &amdgpu_ttm_lru_removal,
1082 .lru_tail = &amdgpu_ttm_lru_tail,
1083 .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
1086 int amdgpu_ttm_init(struct amdgpu_device *adev)
1091 /* No others user of address space so set it to 0 */
1092 r = ttm_bo_device_init(&adev->mman.bdev,
1093 adev->mman.bo_global_ref.ref.object,
1095 adev->ddev->anon_inode->i_mapping,
1096 DRM_FILE_PAGE_OFFSET,
1099 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1103 for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1104 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1106 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1107 lru->lru[j] = &adev->mman.bdev.man[j].lru;
1108 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1111 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1112 adev->mman.guard.lru[j] = NULL;
1113 adev->mman.guard.swap_lru = NULL;
1115 adev->mman.initialized = true;
1116 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1117 adev->mc.real_vram_size >> PAGE_SHIFT);
1119 DRM_ERROR("Failed initializing VRAM heap.\n");
1122 /* Change the size here instead of the init above so only lpfn is affected */
1123 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1125 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1126 AMDGPU_GEM_DOMAIN_VRAM,
1127 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1128 NULL, NULL, &adev->stollen_vga_memory);
1132 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1135 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1136 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1138 amdgpu_bo_unref(&adev->stollen_vga_memory);
1141 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1142 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1143 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1144 adev->mc.gtt_size >> PAGE_SHIFT);
1146 DRM_ERROR("Failed initializing GTT heap.\n");
1149 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1150 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1152 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1153 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1154 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1155 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1156 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1157 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1158 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1159 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1160 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1162 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1163 adev->gds.mem.total_size >> PAGE_SHIFT);
1165 DRM_ERROR("Failed initializing GDS heap.\n");
1170 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1171 adev->gds.gws.total_size >> PAGE_SHIFT);
1173 DRM_ERROR("Failed initializing gws heap.\n");
1178 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1179 adev->gds.oa.total_size >> PAGE_SHIFT);
1181 DRM_ERROR("Failed initializing oa heap.\n");
1185 r = amdgpu_ttm_debugfs_init(adev);
1187 DRM_ERROR("Failed to init debugfs\n");
1193 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1197 if (!adev->mman.initialized)
1199 amdgpu_ttm_debugfs_fini(adev);
1200 if (adev->stollen_vga_memory) {
1201 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1203 amdgpu_bo_unpin(adev->stollen_vga_memory);
1204 amdgpu_bo_unreserve(adev->stollen_vga_memory);
1206 amdgpu_bo_unref(&adev->stollen_vga_memory);
1208 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1209 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1210 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1211 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1212 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1213 ttm_bo_device_release(&adev->mman.bdev);
1214 amdgpu_gart_fini(adev);
1215 amdgpu_ttm_global_fini(adev);
1216 adev->mman.initialized = false;
1217 DRM_INFO("amdgpu: ttm finalized\n");
1220 /* this should only be called at bootup or when userspace
1222 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1224 struct ttm_mem_type_manager *man;
1226 if (!adev->mman.initialized)
1229 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1230 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1231 man->size = size >> PAGE_SHIFT;
1234 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1236 struct drm_file *file_priv;
1237 struct amdgpu_device *adev;
1239 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1242 file_priv = filp->private_data;
1243 adev = file_priv->minor->dev->dev_private;
1247 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1250 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1251 uint64_t src_offset,
1252 uint64_t dst_offset,
1253 uint32_t byte_count,
1254 struct reservation_object *resv,
1255 struct fence **fence, bool direct_submit)
1257 struct amdgpu_device *adev = ring->adev;
1258 struct amdgpu_job *job;
1261 unsigned num_loops, num_dw;
1265 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1266 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1267 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1269 /* for IB padding */
1270 while (num_dw & 0x7)
1273 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1278 r = amdgpu_sync_resv(adev, &job->sync, resv,
1279 AMDGPU_FENCE_OWNER_UNDEFINED);
1281 DRM_ERROR("sync failed (%d).\n", r);
1286 for (i = 0; i < num_loops; i++) {
1287 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1289 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1290 dst_offset, cur_size_in_bytes);
1292 src_offset += cur_size_in_bytes;
1293 dst_offset += cur_size_in_bytes;
1294 byte_count -= cur_size_in_bytes;
1297 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1298 WARN_ON(job->ibs[0].length_dw > num_dw);
1299 if (direct_submit) {
1300 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1302 job->fence = fence_get(*fence);
1304 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1305 amdgpu_job_free(job);
1307 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1308 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1316 amdgpu_job_free(job);
1320 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1322 struct reservation_object *resv,
1323 struct fence **fence)
1325 struct amdgpu_device *adev = bo->adev;
1326 struct amdgpu_job *job;
1327 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1329 uint32_t max_bytes, byte_count;
1330 uint64_t dst_offset;
1331 unsigned int num_loops, num_dw;
1335 byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1336 max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1337 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1338 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1340 /* for IB padding */
1341 while (num_dw & 0x7)
1344 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1349 r = amdgpu_sync_resv(adev, &job->sync, resv,
1350 AMDGPU_FENCE_OWNER_UNDEFINED);
1352 DRM_ERROR("sync failed (%d).\n", r);
1357 dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1358 for (i = 0; i < num_loops; i++) {
1359 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1361 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1362 dst_offset, cur_size_in_bytes);
1364 dst_offset += cur_size_in_bytes;
1365 byte_count -= cur_size_in_bytes;
1368 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1369 WARN_ON(job->ibs[0].length_dw > num_dw);
1370 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1371 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1378 amdgpu_job_free(job);
1382 #if defined(CONFIG_DEBUG_FS)
1384 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1386 struct drm_info_node *node = (struct drm_info_node *)m->private;
1387 unsigned ttm_pl = *(int *)node->info_ent->data;
1388 struct drm_device *dev = node->minor->dev;
1389 struct amdgpu_device *adev = dev->dev_private;
1390 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1392 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1394 spin_lock(&glob->lru_lock);
1395 ret = drm_mm_dump_table(m, mm);
1396 spin_unlock(&glob->lru_lock);
1397 if (ttm_pl == TTM_PL_VRAM)
1398 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1399 adev->mman.bdev.man[ttm_pl].size,
1400 (u64)atomic64_read(&adev->vram_usage) >> 20,
1401 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1405 static int ttm_pl_vram = TTM_PL_VRAM;
1406 static int ttm_pl_tt = TTM_PL_TT;
1408 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1409 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1410 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1411 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1412 #ifdef CONFIG_SWIOTLB
1413 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1417 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1418 size_t size, loff_t *pos)
1420 struct amdgpu_device *adev = f->f_inode->i_private;
1424 if (size & 0x3 || *pos & 0x3)
1427 if (*pos >= adev->mc.mc_vram_size)
1431 unsigned long flags;
1434 if (*pos >= adev->mc.mc_vram_size)
1437 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1438 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1439 WREG32(mmMM_INDEX_HI, *pos >> 31);
1440 value = RREG32(mmMM_DATA);
1441 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1443 r = put_user(value, (uint32_t *)buf);
1456 static const struct file_operations amdgpu_ttm_vram_fops = {
1457 .owner = THIS_MODULE,
1458 .read = amdgpu_ttm_vram_read,
1459 .llseek = default_llseek
1462 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1464 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1465 size_t size, loff_t *pos)
1467 struct amdgpu_device *adev = f->f_inode->i_private;
1472 loff_t p = *pos / PAGE_SIZE;
1473 unsigned off = *pos & ~PAGE_MASK;
1474 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1478 if (p >= adev->gart.num_cpu_pages)
1481 page = adev->gart.pages[p];
1486 r = copy_to_user(buf, ptr, cur_size);
1487 kunmap(adev->gart.pages[p]);
1489 r = clear_user(buf, cur_size);
1503 static const struct file_operations amdgpu_ttm_gtt_fops = {
1504 .owner = THIS_MODULE,
1505 .read = amdgpu_ttm_gtt_read,
1506 .llseek = default_llseek
1513 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1515 #if defined(CONFIG_DEBUG_FS)
1518 struct drm_minor *minor = adev->ddev->primary;
1519 struct dentry *ent, *root = minor->debugfs_root;
1521 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1522 adev, &amdgpu_ttm_vram_fops);
1524 return PTR_ERR(ent);
1525 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1526 adev->mman.vram = ent;
1528 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1529 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1530 adev, &amdgpu_ttm_gtt_fops);
1532 return PTR_ERR(ent);
1533 i_size_write(ent->d_inode, adev->mc.gtt_size);
1534 adev->mman.gtt = ent;
1537 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1539 #ifdef CONFIG_SWIOTLB
1540 if (!swiotlb_nr_tbl())
1544 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1551 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1553 #if defined(CONFIG_DEBUG_FS)
1555 debugfs_remove(adev->mman.vram);
1556 adev->mman.vram = NULL;
1558 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1559 debugfs_remove(adev->mman.gtt);
1560 adev->mman.gtt = NULL;
1566 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1568 return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);