drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34
  35 static void psp_set_funcs(struct amdgpu_device *adev);
  36
  37 static int psp_early_init(void *handle)
  38 {
  39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  40         struct psp_context *psp = &adev->psp;
  41
  42         psp_set_funcs(adev);
  43
  44         switch (adev->asic_type) {
  45         case CHIP_VEGA10:
  46                 psp->init_microcode = psp_v3_1_init_microcode;
  47                 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  48                 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  49                 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  50                 psp->ring_init = psp_v3_1_ring_init;
  51                 psp->ring_create = psp_v3_1_ring_create;
  52                 psp->ring_destroy = psp_v3_1_ring_destroy;
  53                 psp->cmd_submit = psp_v3_1_cmd_submit;
  54                 psp->compare_sram_data = psp_v3_1_compare_sram_data;
  55                 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  56                 break;
  57         case CHIP_RAVEN:
  58 #if 0
  59                 psp->init_microcode = psp_v10_0_init_microcode;
  60 #endif
  61                 psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
  62                 psp->ring_init = psp_v10_0_ring_init;
  63                 psp->ring_create = psp_v10_0_ring_create;
  64                 psp->ring_destroy = psp_v10_0_ring_destroy;
  65                 psp->cmd_submit = psp_v10_0_cmd_submit;
  66                 psp->compare_sram_data = psp_v10_0_compare_sram_data;
  67                 break;
  68         default:
  69                 return -EINVAL;
  70         }
  71
  72         psp->adev = adev;
  73
  74         return 0;
  75 }
  76
  77 static int psp_sw_init(void *handle)
  78 {
  79         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  80         struct psp_context *psp = &adev->psp;
  81         int ret;
  82
  83         ret = psp_init_microcode(psp);
  84         if (ret) {
  85                 DRM_ERROR("Failed to load psp firmware!\n");
  86                 return ret;
  87         }
  88
  89         return 0;
  90 }
  91
  92 static int psp_sw_fini(void *handle)
  93 {
  94         return 0;
  95 }
  96
  97 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  98                  uint32_t reg_val, uint32_t mask, bool check_changed)
  99 {
 100         uint32_t val;
 101         int i;
 102         struct amdgpu_device *adev = psp->adev;
 103
 104         for (i = 0; i < adev->usec_timeout; i++) {
 105                 val = RREG32(reg_index);
 106                 if (check_changed) {
 107                         if (val != reg_val)
 108                                 return 0;
 109                 } else {
 110                         if ((val & mask) == reg_val)
 111                                 return 0;
 112                 }
 113                 udelay(1);
 114         }
 115
 116         return -ETIME;
 117 }
 118
 119 static int
 120 psp_cmd_submit_buf(struct psp_context *psp,
 121                    struct amdgpu_firmware_info *ucode,
 122                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 123                    int index)
 124 {
 125         int ret;
 126
 127         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 128
 129         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 130
 131         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 132                              fence_mc_addr, index);
 133
 134         while (*((unsigned int *)psp->fence_buf) != index) {
 135                 msleep(1);
 136         }
 137
 138         if (ucode) {
 139                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 140                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 141         }
 142
 143         return ret;
 144 }
 145
 146 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 147                                  uint64_t tmr_mc, uint32_t size)
 148 {
 149         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 150         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 151         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 152         cmd->cmd.cmd_setup_tmr.buf_size = size;
 153 }
 154
 155 /* Set up Trusted Memory Region */
 156 static int psp_tmr_init(struct psp_context *psp)
 157 {
 158         int ret;
 159
 160         /*
 161          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 162          * physical).
 163          *
 164          * Note: this memory need be reserved till the driver
 165          * uninitializes.
 166          */
 167         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 168                                       AMDGPU_GEM_DOMAIN_VRAM,
 169                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 170
 171         return ret;
 172 }
 173
 174 static int psp_tmr_load(struct psp_context *psp)
 175 {
 176         int ret;
 177         struct psp_gfx_cmd_resp *cmd;
 178
 179         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 180         if (!cmd)
 181                 return -ENOMEM;
 182
 183         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 184
 185         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 186                                  psp->fence_buf_mc_addr, 1);
 187         if (ret)
 188                 goto failed;
 189
 190         kfree(cmd);
 191
 192         return 0;
 193
 194 failed:
 195         kfree(cmd);
 196         return ret;
 197 }
 198
 199 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 200                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 201                                  uint32_t size, uint32_t shared_size)
 202 {
 203         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 204         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 205         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 206         cmd->cmd.cmd_load_ta.app_len = size;
 207
 208         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 209         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 210         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 211 }
 212
 213 static int psp_asd_init(struct psp_context *psp)
 214 {
 215         int ret;
 216
 217         /*
 218          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 219          * physical) for shared ASD <-> Driver
 220          */
 221         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 222                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 223                                       &psp->asd_shared_bo,
 224                                       &psp->asd_shared_mc_addr,
 225                                       &psp->asd_shared_buf);
 226
 227         return ret;
 228 }
 229
 230 static int psp_asd_load(struct psp_context *psp)
 231 {
 232         int ret;
 233         struct psp_gfx_cmd_resp *cmd;
 234
 235         /* If PSP version doesn't match ASD version, asd loading will be failed.
 236          * add workaround to bypass it for sriov now.
 237          * TODO: add version check to make it common
 238          */
 239         if (amdgpu_sriov_vf(psp->adev))
 240                 return 0;
 241
 242         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 243         if (!cmd)
 244                 return -ENOMEM;
 245
 246         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 247         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 248
 249         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 250                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 251
 252         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 253                                  psp->fence_buf_mc_addr, 2);
 254
 255         kfree(cmd);
 256
 257         return ret;
 258 }
 259
 260 static int psp_hw_start(struct psp_context *psp)
 261 {
 262         int ret;
 263
 264         ret = psp_bootloader_load_sysdrv(psp);
 265         if (ret)
 266                 return ret;
 267
 268         ret = psp_bootloader_load_sos(psp);
 269         if (ret)
 270                 return ret;
 271
 272         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 273         if (ret)
 274                 return ret;
 275
 276         ret = psp_tmr_load(psp);
 277         if (ret)
 278                 return ret;
 279
 280         ret = psp_asd_load(psp);
 281         if (ret)
 282                 return ret;
 283
 284         return 0;
 285 }
 286
 287 static int psp_np_fw_load(struct psp_context *psp)
 288 {
 289         int i, ret;
 290         struct amdgpu_firmware_info *ucode;
 291         struct amdgpu_device* adev = psp->adev;
 292
 293         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 294                 ucode = &adev->firmware.ucode[i];
 295                 if (!ucode->fw)
 296                         continue;
 297
 298                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 299                     psp_smu_reload_quirk(psp))
 300                         continue;
 301                 if (amdgpu_sriov_vf(adev) &&
 302                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 303                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 304                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 305                         /*skip ucode loading in SRIOV VF */
 306                         continue;
 307
 308                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 309                 if (ret)
 310                         return ret;
 311
 312                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 313                                          psp->fence_buf_mc_addr, i + 3);
 314                 if (ret)
 315                         return ret;
 316
 317 #if 0
 318                 /* check if firmware loaded sucessfully */
 319                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 320                         return -EINVAL;
 321 #endif
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int psp_load_fw(struct amdgpu_device *adev)
 328 {
 329         int ret;
 330         struct psp_context *psp = &adev->psp;
 331
 332         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 333         if (!psp->cmd)
 334                 return -ENOMEM;
 335
 336         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 337                                       AMDGPU_GEM_DOMAIN_GTT,
 338                                       &psp->fw_pri_bo,
 339                                       &psp->fw_pri_mc_addr,
 340                                       &psp->fw_pri_buf);
 341         if (ret)
 342                 goto failed;
 343
 344         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 345                                       AMDGPU_GEM_DOMAIN_VRAM,
 346                                       &psp->fence_buf_bo,
 347                                       &psp->fence_buf_mc_addr,
 348                                       &psp->fence_buf);
 349         if (ret)
 350                 goto failed_mem2;
 351
 352         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 353                                       AMDGPU_GEM_DOMAIN_VRAM,
 354                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 355                                       (void **)&psp->cmd_buf_mem);
 356         if (ret)
 357                 goto failed_mem1;
 358
 359         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 360
 361         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 362         if (ret)
 363                 goto failed_mem;
 364
 365         ret = psp_tmr_init(psp);
 366         if (ret)
 367                 goto failed_mem;
 368
 369         ret = psp_asd_init(psp);
 370         if (ret)
 371                 goto failed_mem;
 372
 373         ret = psp_hw_start(psp);
 374         if (ret)
 375                 goto failed_mem;
 376
 377         ret = psp_np_fw_load(psp);
 378         if (ret)
 379                 goto failed_mem;
 380
 381         return 0;
 382
 383 failed_mem:
 384         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 385                               &psp->cmd_buf_mc_addr,
 386                               (void **)&psp->cmd_buf_mem);
 387 failed_mem1:
 388         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 389                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 390 failed_mem2:
 391         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 392                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 393 failed:
 394         kfree(psp->cmd);
 395         psp->cmd = NULL;
 396         return ret;
 397 }
 398
 399 static int psp_hw_init(void *handle)
 400 {
 401         int ret;
 402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 403
 404
 405         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 406                 return 0;
 407
 408         mutex_lock(&adev->firmware.mutex);
 409         /*
 410          * This sequence is just used on hw_init only once, no need on
 411          * resume.
 412          */
 413         ret = amdgpu_ucode_init_bo(adev);
 414         if (ret)
 415                 goto failed;
 416
 417         ret = psp_load_fw(adev);
 418         if (ret) {
 419                 DRM_ERROR("PSP firmware loading failed\n");
 420                 goto failed;
 421         }
 422
 423         mutex_unlock(&adev->firmware.mutex);
 424         return 0;
 425
 426 failed:
 427         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 428         mutex_unlock(&adev->firmware.mutex);
 429         return -EINVAL;
 430 }
 431
 432 static int psp_hw_fini(void *handle)
 433 {
 434         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 435         struct psp_context *psp = &adev->psp;
 436
 437         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 438                 return 0;
 439
 440         amdgpu_ucode_fini_bo(adev);
 441
 442         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 443
 444         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 445         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 446                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 447         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 448                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 449         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 450                               &psp->asd_shared_buf);
 451         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 452                               (void **)&psp->cmd_buf_mem);
 453
 454         kfree(psp->cmd);
 455         psp->cmd = NULL;
 456
 457         return 0;
 458 }
 459
 460 static int psp_suspend(void *handle)
 461 {
 462         return 0;
 463 }
 464
 465 static int psp_resume(void *handle)
 466 {
 467         int ret;
 468         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 469         struct psp_context *psp = &adev->psp;
 470
 471         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 472                 return 0;
 473
 474         DRM_INFO("PSP is resuming...\n");
 475
 476         mutex_lock(&adev->firmware.mutex);
 477
 478         ret = psp_hw_start(psp);
 479         if (ret)
 480                 goto failed;
 481
 482         ret = psp_np_fw_load(psp);
 483         if (ret)
 484                 goto failed;
 485
 486         mutex_unlock(&adev->firmware.mutex);
 487
 488         return 0;
 489
 490 failed:
 491         DRM_ERROR("PSP resume failed\n");
 492         mutex_unlock(&adev->firmware.mutex);
 493         return ret;
 494 }
 495
 496 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 497                                         enum AMDGPU_UCODE_ID ucode_type)
 498 {
 499         struct amdgpu_firmware_info *ucode = NULL;
 500
 501         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 502                 DRM_INFO("firmware is not loaded by PSP\n");
 503                 return true;
 504         }
 505
 506         if (!adev->firmware.fw_size)
 507                 return false;
 508
 509         ucode = &adev->firmware.ucode[ucode_type];
 510         if (!ucode->fw || !ucode->ucode_size)
 511                 return false;
 512
 513         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 514 }
 515
 516 static int psp_set_clockgating_state(void *handle,
 517                                      enum amd_clockgating_state state)
 518 {
 519         return 0;
 520 }
 521
 522 static int psp_set_powergating_state(void *handle,
 523                                      enum amd_powergating_state state)
 524 {
 525         return 0;
 526 }
 527
 528 const struct amd_ip_funcs psp_ip_funcs = {
 529         .name = "psp",
 530         .early_init = psp_early_init,
 531         .late_init = NULL,
 532         .sw_init = psp_sw_init,
 533         .sw_fini = psp_sw_fini,
 534         .hw_init = psp_hw_init,
 535         .hw_fini = psp_hw_fini,
 536         .suspend = psp_suspend,
 537         .resume = psp_resume,
 538         .is_idle = NULL,
 539         .wait_for_idle = NULL,
 540         .soft_reset = NULL,
 541         .set_clockgating_state = psp_set_clockgating_state,
 542         .set_powergating_state = psp_set_powergating_state,
 543 };
 544
 545 static const struct amdgpu_psp_funcs psp_funcs = {
 546         .check_fw_loading_status = psp_check_fw_loading_status,
 547 };
 548
 549 static void psp_set_funcs(struct amdgpu_device *adev)
 550 {
 551         if (NULL == adev->firmware.funcs)
 552                 adev->firmware.funcs = &psp_funcs;
 553 }
 554
 555 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 556 {
 557         .type = AMD_IP_BLOCK_TYPE_PSP,
 558         .major = 3,
 559         .minor = 1,
 560         .rev = 0,
 561         .funcs = &psp_ip_funcs,
 562 };
 563
 564 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 565 {
 566         .type = AMD_IP_BLOCK_TYPE_PSP,
 567         .major = 10,
 568         .minor = 0,
 569         .rev = 0,
 570         .funcs = &psp_ip_funcs,
 571 };