drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  41 {
  42         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  43         struct amdgpu_bo *bo;
  44
  45         bo = container_of(tbo, struct amdgpu_bo, tbo);
  46
  47         amdgpu_bo_kunmap(bo);
  48
  49         if (bo->gem_base.import_attach)
  50                 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
  51         drm_gem_object_release(&bo->gem_base);
  52         amdgpu_bo_unref(&bo->parent);
  53         if (!list_empty(&bo->shadow_list)) {
  54                 mutex_lock(&adev->shadow_list_lock);
  55                 list_del_init(&bo->shadow_list);
  56                 mutex_unlock(&adev->shadow_list_lock);
  57         }
  58         kfree(bo->metadata);
  59         kfree(bo);
  60 }
  61
  62 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  63 {
  64         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  65                 return true;
  66         return false;
  67 }
  68
  69 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
  70                                       struct ttm_placement *placement,
  71                                       struct ttm_place *places,
  72                                       u32 domain, u64 flags)
  73 {
  74         u32 c = 0;
  75
  76         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  77                 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
  78
  79                 places[c].fpfn = 0;
  80                 places[c].lpfn = 0;
  81                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  82                         TTM_PL_FLAG_VRAM;
  83
  84                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
  85                         places[c].lpfn = visible_pfn;
  86                 else
  87                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
  88
  89                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
  90                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
  91                 c++;
  92         }
  93
  94         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
  95                 places[c].fpfn = 0;
  96                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
  97                         places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT;
  98                 else
  99                         places[c].lpfn = 0;
 100                 places[c].flags = TTM_PL_FLAG_TT;
 101                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 102                         places[c].flags |= TTM_PL_FLAG_WC |
 103                                 TTM_PL_FLAG_UNCACHED;
 104                 else
 105                         places[c].flags |= TTM_PL_FLAG_CACHED;
 106                 c++;
 107         }
 108
 109         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 110                 places[c].fpfn = 0;
 111                 places[c].lpfn = 0;
 112                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 113                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 114                         places[c].flags |= TTM_PL_FLAG_WC |
 115                                 TTM_PL_FLAG_UNCACHED;
 116                 else
 117                         places[c].flags |= TTM_PL_FLAG_CACHED;
 118                 c++;
 119         }
 120
 121         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 122                 places[c].fpfn = 0;
 123                 places[c].lpfn = 0;
 124                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 125                 c++;
 126         }
 127
 128         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 129                 places[c].fpfn = 0;
 130                 places[c].lpfn = 0;
 131                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 132                 c++;
 133         }
 134
 135         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 136                 places[c].fpfn = 0;
 137                 places[c].lpfn = 0;
 138                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 139                 c++;
 140         }
 141
 142         if (!c) {
 143                 places[c].fpfn = 0;
 144                 places[c].lpfn = 0;
 145                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 146                 c++;
 147         }
 148
 149         placement->num_placement = c;
 150         placement->placement = places;
 151
 152         placement->num_busy_placement = c;
 153         placement->busy_placement = places;
 154 }
 155
 156 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
 157 {
 158         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 159
 160         amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements,
 161                                   domain, abo->flags);
 162 }
 163
 164 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
 165                                         struct ttm_placement *placement)
 166 {
 167         BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
 168
 169         memcpy(bo->placements, placement->placement,
 170                placement->num_placement * sizeof(struct ttm_place));
 171         bo->placement.num_placement = placement->num_placement;
 172         bo->placement.num_busy_placement = placement->num_busy_placement;
 173         bo->placement.placement = bo->placements;
 174         bo->placement.busy_placement = bo->placements;
 175 }
 176
 177 /**
 178  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 179  *
 180  * @adev: amdgpu device object
 181  * @size: size for the new BO
 182  * @align: alignment for the new BO
 183  * @domain: where to place it
 184  * @bo_ptr: resulting BO
 185  * @gpu_addr: GPU addr of the pinned BO
 186  * @cpu_addr: optional CPU address mapping
 187  *
 188  * Allocates and pins a BO for kernel internal use, and returns it still
 189  * reserved.
 190  *
 191  * Returns 0 on success, negative error code otherwise.
 192  */
 193 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 194                               unsigned long size, int align,
 195                               u32 domain, struct amdgpu_bo **bo_ptr,
 196                               u64 *gpu_addr, void **cpu_addr)
 197 {
 198         bool free = false;
 199         int r;
 200
 201         if (!*bo_ptr) {
 202                 r = amdgpu_bo_create(adev, size, align, true, domain,
 203                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 204                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 205                                      NULL, NULL, 0, bo_ptr);
 206                 if (r) {
 207                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 208                                 r);
 209                         return r;
 210                 }
 211                 free = true;
 212         }
 213
 214         r = amdgpu_bo_reserve(*bo_ptr, false);
 215         if (r) {
 216                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 217                 goto error_free;
 218         }
 219
 220         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 221         if (r) {
 222                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 223                 goto error_unreserve;
 224         }
 225
 226         if (cpu_addr) {
 227                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 228                 if (r) {
 229                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 230                         goto error_unreserve;
 231                 }
 232         }
 233
 234         return 0;
 235
 236 error_unreserve:
 237         amdgpu_bo_unreserve(*bo_ptr);
 238
 239 error_free:
 240         if (free)
 241                 amdgpu_bo_unref(bo_ptr);
 242
 243         return r;
 244 }
 245
 246 /**
 247  * amdgpu_bo_create_kernel - create BO for kernel use
 248  *
 249  * @adev: amdgpu device object
 250  * @size: size for the new BO
 251  * @align: alignment for the new BO
 252  * @domain: where to place it
 253  * @bo_ptr: resulting BO
 254  * @gpu_addr: GPU addr of the pinned BO
 255  * @cpu_addr: optional CPU address mapping
 256  *
 257  * Allocates and pins a BO for kernel internal use.
 258  *
 259  * Returns 0 on success, negative error code otherwise.
 260  */
 261 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 262                             unsigned long size, int align,
 263                             u32 domain, struct amdgpu_bo **bo_ptr,
 264                             u64 *gpu_addr, void **cpu_addr)
 265 {
 266         int r;
 267
 268         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 269                                       gpu_addr, cpu_addr);
 270
 271         if (r)
 272                 return r;
 273
 274         amdgpu_bo_unreserve(*bo_ptr);
 275
 276         return 0;
 277 }
 278
 279 /**
 280  * amdgpu_bo_free_kernel - free BO for kernel use
 281  *
 282  * @bo: amdgpu BO to free
 283  *
 284  * unmaps and unpin a BO for kernel internal use.
 285  */
 286 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 287                            void **cpu_addr)
 288 {
 289         if (*bo == NULL)
 290                 return;
 291
 292         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 293                 if (cpu_addr)
 294                         amdgpu_bo_kunmap(*bo);
 295
 296                 amdgpu_bo_unpin(*bo);
 297                 amdgpu_bo_unreserve(*bo);
 298         }
 299         amdgpu_bo_unref(bo);
 300
 301         if (gpu_addr)
 302                 *gpu_addr = 0;
 303
 304         if (cpu_addr)
 305                 *cpu_addr = NULL;
 306 }
 307
 308 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 309                                 unsigned long size, int byte_align,
 310                                 bool kernel, u32 domain, u64 flags,
 311                                 struct sg_table *sg,
 312                                 struct ttm_placement *placement,
 313                                 struct reservation_object *resv,
 314                                 uint64_t init_value,
 315                                 struct amdgpu_bo **bo_ptr)
 316 {
 317         struct amdgpu_bo *bo;
 318         enum ttm_bo_type type;
 319         unsigned long page_align;
 320         u64 initial_bytes_moved, bytes_moved;
 321         size_t acc_size;
 322         int r;
 323
 324         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 325         size = ALIGN(size, PAGE_SIZE);
 326
 327         if (kernel) {
 328                 type = ttm_bo_type_kernel;
 329         } else if (sg) {
 330                 type = ttm_bo_type_sg;
 331         } else {
 332                 type = ttm_bo_type_device;
 333         }
 334         *bo_ptr = NULL;
 335
 336         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 337                                        sizeof(struct amdgpu_bo));
 338
 339         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 340         if (bo == NULL)
 341                 return -ENOMEM;
 342         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 343         if (unlikely(r)) {
 344                 kfree(bo);
 345                 return r;
 346         }
 347         INIT_LIST_HEAD(&bo->shadow_list);
 348         INIT_LIST_HEAD(&bo->va);
 349         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 350                                          AMDGPU_GEM_DOMAIN_GTT |
 351                                          AMDGPU_GEM_DOMAIN_CPU |
 352                                          AMDGPU_GEM_DOMAIN_GDS |
 353                                          AMDGPU_GEM_DOMAIN_GWS |
 354                                          AMDGPU_GEM_DOMAIN_OA);
 355         bo->allowed_domains = bo->preferred_domains;
 356         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 357                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 358
 359         bo->flags = flags;
 360
 361 #ifdef CONFIG_X86_32
 362         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 363          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 364          */
 365         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 366 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 367         /* Don't try to enable write-combining when it can't work, or things
 368          * may be slow
 369          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 370          */
 371
 372 #ifndef CONFIG_COMPILE_TEST
 373 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 374          thanks to write-combining
 375 #endif
 376
 377         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 378                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 379                               "better performance thanks to write-combining\n");
 380         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 381 #else
 382         /* For architectures that don't support WC memory,
 383          * mask out the WC flag from the BO
 384          */
 385         if (!drm_arch_can_wc_memory())
 386                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 387 #endif
 388
 389         amdgpu_fill_placement_to_bo(bo, placement);
 390         /* Kernel allocation are uninterruptible */
 391
 392         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 393         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 394                                  &bo->placement, page_align, !kernel, NULL,
 395                                  acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 396         if (unlikely(r != 0))
 397                 return r;
 398
 399         bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 400                       initial_bytes_moved;
 401         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 402             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 403             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 404                 amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved);
 405         else
 406                 amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0);
 407
 408         if (kernel)
 409                 bo->tbo.priority = 1;
 410
 411         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 412             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 413                 struct dma_fence *fence;
 414
 415                 r = amdgpu_fill_buffer(bo, init_value, bo->tbo.resv, &fence);
 416                 if (unlikely(r))
 417                         goto fail_unreserve;
 418
 419                 amdgpu_bo_fence(bo, fence, false);
 420                 dma_fence_put(bo->tbo.moving);
 421                 bo->tbo.moving = dma_fence_get(fence);
 422                 dma_fence_put(fence);
 423         }
 424         if (!resv)
 425                 amdgpu_bo_unreserve(bo);
 426         *bo_ptr = bo;
 427
 428         trace_amdgpu_bo_create(bo);
 429
 430         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 431         if (type == ttm_bo_type_device)
 432                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 433
 434         return 0;
 435
 436 fail_unreserve:
 437         if (!resv)
 438                 ww_mutex_unlock(&bo->tbo.resv->lock);
 439         amdgpu_bo_unref(&bo);
 440         return r;
 441 }
 442
 443 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 444                                    unsigned long size, int byte_align,
 445                                    struct amdgpu_bo *bo)
 446 {
 447         struct ttm_placement placement = {0};
 448         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 449         int r;
 450
 451         if (bo->shadow)
 452                 return 0;
 453
 454         memset(&placements, 0, sizeof(placements));
 455         amdgpu_ttm_placement_init(adev, &placement, placements,
 456                                   AMDGPU_GEM_DOMAIN_GTT,
 457                                   AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 458                                   AMDGPU_GEM_CREATE_SHADOW);
 459
 460         r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
 461                                         AMDGPU_GEM_DOMAIN_GTT,
 462                                         AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 463                                         AMDGPU_GEM_CREATE_SHADOW,
 464                                         NULL, &placement,
 465                                         bo->tbo.resv,
 466                                         0,
 467                                         &bo->shadow);
 468         if (!r) {
 469                 bo->shadow->parent = amdgpu_bo_ref(bo);
 470                 mutex_lock(&adev->shadow_list_lock);
 471                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 472                 mutex_unlock(&adev->shadow_list_lock);
 473         }
 474
 475         return r;
 476 }
 477
 478 /* init_value will only take effect when flags contains
 479  * AMDGPU_GEM_CREATE_VRAM_CLEARED.
 480  */
 481 int amdgpu_bo_create(struct amdgpu_device *adev,
 482                      unsigned long size, int byte_align,
 483                      bool kernel, u32 domain, u64 flags,
 484                      struct sg_table *sg,
 485                      struct reservation_object *resv,
 486                      uint64_t init_value,
 487                      struct amdgpu_bo **bo_ptr)
 488 {
 489         struct ttm_placement placement = {0};
 490         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 491         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 492         int r;
 493
 494         memset(&placements, 0, sizeof(placements));
 495         amdgpu_ttm_placement_init(adev, &placement, placements,
 496                                   domain, parent_flags);
 497
 498         r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, domain,
 499                                         parent_flags, sg, &placement, resv,
 500                                         init_value, bo_ptr);
 501         if (r)
 502                 return r;
 503
 504         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 505                 if (!resv)
 506                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 507                                                         NULL));
 508
 509                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 510
 511                 if (!resv)
 512                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 513
 514                 if (r)
 515                         amdgpu_bo_unref(bo_ptr);
 516         }
 517
 518         return r;
 519 }
 520
 521 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 522                                struct amdgpu_ring *ring,
 523                                struct amdgpu_bo *bo,
 524                                struct reservation_object *resv,
 525                                struct dma_fence **fence,
 526                                bool direct)
 527
 528 {
 529         struct amdgpu_bo *shadow = bo->shadow;
 530         uint64_t bo_addr, shadow_addr;
 531         int r;
 532
 533         if (!shadow)
 534                 return -EINVAL;
 535
 536         bo_addr = amdgpu_bo_gpu_offset(bo);
 537         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 538
 539         r = reservation_object_reserve_shared(bo->tbo.resv);
 540         if (r)
 541                 goto err;
 542
 543         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 544                                amdgpu_bo_size(bo), resv, fence,
 545                                direct, false);
 546         if (!r)
 547                 amdgpu_bo_fence(bo, *fence, true);
 548
 549 err:
 550         return r;
 551 }
 552
 553 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 554 {
 555         uint32_t domain;
 556         int r;
 557
 558         if (bo->pin_count)
 559                 return 0;
 560
 561         domain = bo->preferred_domains;
 562
 563 retry:
 564         amdgpu_ttm_placement_from_domain(bo, domain);
 565         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 566         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 567                 domain = bo->allowed_domains;
 568                 goto retry;
 569         }
 570
 571         return r;
 572 }
 573
 574 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 575                                   struct amdgpu_ring *ring,
 576                                   struct amdgpu_bo *bo,
 577                                   struct reservation_object *resv,
 578                                   struct dma_fence **fence,
 579                                   bool direct)
 580
 581 {
 582         struct amdgpu_bo *shadow = bo->shadow;
 583         uint64_t bo_addr, shadow_addr;
 584         int r;
 585
 586         if (!shadow)
 587                 return -EINVAL;
 588
 589         bo_addr = amdgpu_bo_gpu_offset(bo);
 590         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 591
 592         r = reservation_object_reserve_shared(bo->tbo.resv);
 593         if (r)
 594                 goto err;
 595
 596         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 597                                amdgpu_bo_size(bo), resv, fence,
 598                                direct, false);
 599         if (!r)
 600                 amdgpu_bo_fence(bo, *fence, true);
 601
 602 err:
 603         return r;
 604 }
 605
 606 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 607 {
 608         void *kptr;
 609         long r;
 610
 611         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 612                 return -EPERM;
 613
 614         kptr = amdgpu_bo_kptr(bo);
 615         if (kptr) {
 616                 if (ptr)
 617                         *ptr = kptr;
 618                 return 0;
 619         }
 620
 621         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 622                                                 MAX_SCHEDULE_TIMEOUT);
 623         if (r < 0)
 624                 return r;
 625
 626         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 627         if (r)
 628                 return r;
 629
 630         if (ptr)
 631                 *ptr = amdgpu_bo_kptr(bo);
 632
 633         return 0;
 634 }
 635
 636 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 637 {
 638         bool is_iomem;
 639
 640         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 641 }
 642
 643 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 644 {
 645         if (bo->kmap.bo)
 646                 ttm_bo_kunmap(&bo->kmap);
 647 }
 648
 649 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 650 {
 651         if (bo == NULL)
 652                 return NULL;
 653
 654         ttm_bo_reference(&bo->tbo);
 655         return bo;
 656 }
 657
 658 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 659 {
 660         struct ttm_buffer_object *tbo;
 661
 662         if ((*bo) == NULL)
 663                 return;
 664
 665         tbo = &((*bo)->tbo);
 666         ttm_bo_unref(&tbo);
 667         if (tbo == NULL)
 668                 *bo = NULL;
 669 }
 670
 671 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 672                              u64 min_offset, u64 max_offset,
 673                              u64 *gpu_addr)
 674 {
 675         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 676         int r, i;
 677         unsigned fpfn, lpfn;
 678
 679         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 680                 return -EPERM;
 681
 682         if (WARN_ON_ONCE(min_offset > max_offset))
 683                 return -EINVAL;
 684
 685         /* Check domain to be pinned to against preferred domains */
 686         if (bo->preferred_domains & domain)
 687                 domain = bo->preferred_domains & domain;
 688
 689         /* A shared bo cannot be migrated to VRAM */
 690         if (bo->prime_shared_count) {
 691                 if (domain & AMDGPU_GEM_DOMAIN_GTT)
 692                         domain = AMDGPU_GEM_DOMAIN_GTT;
 693                 else
 694                         return -EINVAL;
 695         }
 696
 697         if (bo->pin_count) {
 698                 uint32_t mem_type = bo->tbo.mem.mem_type;
 699
 700                 if (domain != amdgpu_mem_type_to_domain(mem_type))
 701                         return -EINVAL;
 702
 703                 bo->pin_count++;
 704                 if (gpu_addr)
 705                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 706
 707                 if (max_offset != 0) {
 708                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 709                         WARN_ON_ONCE(max_offset <
 710                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 711                 }
 712
 713                 return 0;
 714         }
 715
 716         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 717         amdgpu_ttm_placement_from_domain(bo, domain);
 718         for (i = 0; i < bo->placement.num_placement; i++) {
 719                 /* force to pin into visible video ram */
 720                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 721                     !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
 722                     (!max_offset || max_offset >
 723                      adev->mc.visible_vram_size)) {
 724                         if (WARN_ON_ONCE(min_offset >
 725                                          adev->mc.visible_vram_size))
 726                                 return -EINVAL;
 727                         fpfn = min_offset >> PAGE_SHIFT;
 728                         lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 729                 } else {
 730                         fpfn = min_offset >> PAGE_SHIFT;
 731                         lpfn = max_offset >> PAGE_SHIFT;
 732                 }
 733                 if (fpfn > bo->placements[i].fpfn)
 734                         bo->placements[i].fpfn = fpfn;
 735                 if (!bo->placements[i].lpfn ||
 736                     (lpfn && lpfn < bo->placements[i].lpfn))
 737                         bo->placements[i].lpfn = lpfn;
 738                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 739         }
 740
 741         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 742         if (unlikely(r)) {
 743                 dev_err(adev->dev, "%p pin failed\n", bo);
 744                 goto error;
 745         }
 746
 747         bo->pin_count = 1;
 748         if (gpu_addr != NULL) {
 749                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
 750                 if (unlikely(r)) {
 751                         dev_err(adev->dev, "%p bind failed\n", bo);
 752                         goto error;
 753                 }
 754                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 755         }
 756         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 757                 adev->vram_pin_size += amdgpu_bo_size(bo);
 758                 adev->invisible_pin_size += amdgpu_vram_mgr_bo_invisible_size(bo);
 759         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 760                 adev->gart_pin_size += amdgpu_bo_size(bo);
 761         }
 762
 763 error:
 764         return r;
 765 }
 766
 767 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 768 {
 769         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 770 }
 771
 772 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 773 {
 774         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 775         int r, i;
 776
 777         if (!bo->pin_count) {
 778                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 779                 return 0;
 780         }
 781         bo->pin_count--;
 782         if (bo->pin_count)
 783                 return 0;
 784         for (i = 0; i < bo->placement.num_placement; i++) {
 785                 bo->placements[i].lpfn = 0;
 786                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 787         }
 788         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 789         if (unlikely(r)) {
 790                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 791                 goto error;
 792         }
 793
 794         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 795                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 796                 adev->invisible_pin_size -= amdgpu_vram_mgr_bo_invisible_size(bo);
 797         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 798                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 799         }
 800
 801 error:
 802         return r;
 803 }
 804
 805 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 806 {
 807         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 808         if (0 && (adev->flags & AMD_IS_APU)) {
 809                 /* Useless to evict on IGP chips */
 810                 return 0;
 811         }
 812         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 813 }
 814
 815 static const char *amdgpu_vram_names[] = {
 816         "UNKNOWN",
 817         "GDDR1",
 818         "DDR2",
 819         "GDDR3",
 820         "GDDR4",
 821         "GDDR5",
 822         "HBM",
 823         "DDR3"
 824 };
 825
 826 int amdgpu_bo_init(struct amdgpu_device *adev)
 827 {
 828         /* reserve PAT memory space to WC for VRAM */
 829         arch_io_reserve_memtype_wc(adev->mc.aper_base,
 830                                    adev->mc.aper_size);
 831
 832         /* Add an MTRR for the VRAM */
 833         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 834                                               adev->mc.aper_size);
 835         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 836                 adev->mc.mc_vram_size >> 20,
 837                 (unsigned long long)adev->mc.aper_size >> 20);
 838         DRM_INFO("RAM width %dbits %s\n",
 839                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 840         return amdgpu_ttm_init(adev);
 841 }
 842
 843 void amdgpu_bo_fini(struct amdgpu_device *adev)
 844 {
 845         amdgpu_ttm_fini(adev);
 846         arch_phys_wc_del(adev->mc.vram_mtrr);
 847         arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size);
 848 }
 849
 850 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 851                              struct vm_area_struct *vma)
 852 {
 853         return ttm_fbdev_mmap(vma, &bo->tbo);
 854 }
 855
 856 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 857 {
 858         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 859
 860         if (adev->family <= AMDGPU_FAMILY_CZ &&
 861             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 862                 return -EINVAL;
 863
 864         bo->tiling_flags = tiling_flags;
 865         return 0;
 866 }
 867
 868 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 869 {
 870         lockdep_assert_held(&bo->tbo.resv->lock.base);
 871
 872         if (tiling_flags)
 873                 *tiling_flags = bo->tiling_flags;
 874 }
 875
 876 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 877                             uint32_t metadata_size, uint64_t flags)
 878 {
 879         void *buffer;
 880
 881         if (!metadata_size) {
 882                 if (bo->metadata_size) {
 883                         kfree(bo->metadata);
 884                         bo->metadata = NULL;
 885                         bo->metadata_size = 0;
 886                 }
 887                 return 0;
 888         }
 889
 890         if (metadata == NULL)
 891                 return -EINVAL;
 892
 893         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 894         if (buffer == NULL)
 895                 return -ENOMEM;
 896
 897         kfree(bo->metadata);
 898         bo->metadata_flags = flags;
 899         bo->metadata = buffer;
 900         bo->metadata_size = metadata_size;
 901
 902         return 0;
 903 }
 904
 905 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 906                            size_t buffer_size, uint32_t *metadata_size,
 907                            uint64_t *flags)
 908 {
 909         if (!buffer && !metadata_size)
 910                 return -EINVAL;
 911
 912         if (buffer) {
 913                 if (buffer_size < bo->metadata_size)
 914                         return -EINVAL;
 915
 916                 if (bo->metadata_size)
 917                         memcpy(buffer, bo->metadata, bo->metadata_size);
 918         }
 919
 920         if (metadata_size)
 921                 *metadata_size = bo->metadata_size;
 922         if (flags)
 923                 *flags = bo->metadata_flags;
 924
 925         return 0;
 926 }
 927
 928 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 929                            bool evict,
 930                            struct ttm_mem_reg *new_mem)
 931 {
 932         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 933         struct amdgpu_bo *abo;
 934         struct ttm_mem_reg *old_mem = &bo->mem;
 935
 936         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 937                 return;
 938
 939         abo = container_of(bo, struct amdgpu_bo, tbo);
 940         amdgpu_vm_bo_invalidate(adev, abo);
 941
 942         amdgpu_bo_kunmap(abo);
 943
 944         /* remember the eviction */
 945         if (evict)
 946                 atomic64_inc(&adev->num_evictions);
 947
 948         /* update statistics */
 949         if (!new_mem)
 950                 return;
 951
 952         /* move_notify is called before move happens */
 953         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 954 }
 955
 956 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 957 {
 958         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 959         struct amdgpu_bo *abo;
 960         unsigned long offset, size;
 961         int r;
 962
 963         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 964                 return 0;
 965
 966         abo = container_of(bo, struct amdgpu_bo, tbo);
 967
 968         /* Remember that this BO was accessed by the CPU */
 969         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 970
 971         if (bo->mem.mem_type != TTM_PL_VRAM)
 972                 return 0;
 973
 974         size = bo->mem.num_pages << PAGE_SHIFT;
 975         offset = bo->mem.start << PAGE_SHIFT;
 976         if ((offset + size) <= adev->mc.visible_vram_size)
 977                 return 0;
 978
 979         /* Can't move a pinned BO to visible VRAM */
 980         if (abo->pin_count > 0)
 981                 return -EINVAL;
 982
 983         /* hurrah the memory is not visible ! */
 984         atomic64_inc(&adev->num_vram_cpu_page_faults);
 985         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 986                                          AMDGPU_GEM_DOMAIN_GTT);
 987
 988         /* Avoid costly evictions; only set GTT as a busy placement */
 989         abo->placement.num_busy_placement = 1;
 990         abo->placement.busy_placement = &abo->placements[1];
 991
 992         r = ttm_bo_validate(bo, &abo->placement, false, false);
 993         if (unlikely(r != 0))
 994                 return r;
 995
 996         offset = bo->mem.start << PAGE_SHIFT;
 997         /* this should never happen */
 998         if (bo->mem.mem_type == TTM_PL_VRAM &&
 999             (offset + size) > adev->mc.visible_vram_size)
1000                 return -EINVAL;
1001
1002         return 0;
1003 }
1004
1005 /**
1006  * amdgpu_bo_fence - add fence to buffer object
1007  *
1008  * @bo: buffer object in question
1009  * @fence: fence to add
1010  * @shared: true if fence should be added shared
1011  *
1012  */
1013 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1014                      bool shared)
1015 {
1016         struct reservation_object *resv = bo->tbo.resv;
1017
1018         if (shared)
1019                 reservation_object_add_shared_fence(resv, fence);
1020         else
1021                 reservation_object_add_excl_fence(resv, fence);
1022 }
1023
1024 /**
1025  * amdgpu_bo_gpu_offset - return GPU offset of bo
1026  * @bo: amdgpu object for which we query the offset
1027  *
1028  * Returns current GPU offset of the object.
1029  *
1030  * Note: object should either be pinned or reserved when calling this
1031  * function, it might be useful to add check for this for debugging.
1032  */
1033 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1034 {
1035         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1036         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1037                      !amdgpu_ttm_is_bound(bo->tbo.ttm));
1038         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1039                      !bo->pin_count);
1040         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1041         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1042                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1043
1044         return bo->tbo.offset;
1045 }