2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <drm/drm_fb_helper.h>
39 #include <drm/drm_plane_helper.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 #include <linux/hrtimer.h>
43 #include "amdgpu_irq.h"
47 struct amdgpu_encoder;
51 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
52 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
53 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
54 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
56 #define AMDGPU_MAX_HPD_PINS 6
57 #define AMDGPU_MAX_CRTCS 6
58 #define AMDGPU_MAX_AFMT_BLOCKS 9
60 enum amdgpu_rmx_type {
67 enum amdgpu_underscan_type {
73 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
74 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
84 AMDGPU_HPD_NONE = 0xff,
87 enum amdgpu_crtc_irq {
88 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
89 AMDGPU_CRTC_IRQ_VBLANK2,
90 AMDGPU_CRTC_IRQ_VBLANK3,
91 AMDGPU_CRTC_IRQ_VBLANK4,
92 AMDGPU_CRTC_IRQ_VBLANK5,
93 AMDGPU_CRTC_IRQ_VBLANK6,
94 AMDGPU_CRTC_IRQ_VLINE1,
95 AMDGPU_CRTC_IRQ_VLINE2,
96 AMDGPU_CRTC_IRQ_VLINE3,
97 AMDGPU_CRTC_IRQ_VLINE4,
98 AMDGPU_CRTC_IRQ_VLINE5,
99 AMDGPU_CRTC_IRQ_VLINE6,
100 AMDGPU_CRTC_IRQ_LAST,
101 AMDGPU_CRTC_IRQ_NONE = 0xff
104 enum amdgpu_pageflip_irq {
105 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
106 AMDGPU_PAGEFLIP_IRQ_D2,
107 AMDGPU_PAGEFLIP_IRQ_D3,
108 AMDGPU_PAGEFLIP_IRQ_D4,
109 AMDGPU_PAGEFLIP_IRQ_D5,
110 AMDGPU_PAGEFLIP_IRQ_D6,
111 AMDGPU_PAGEFLIP_IRQ_LAST,
112 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
115 enum amdgpu_flip_status {
118 AMDGPU_FLIP_SUBMITTED
121 #define AMDGPU_MAX_I2C_BUS 16
123 /* amdgpu gpio-based i2c
124 * 1. "mask" reg and bits
125 * grabs the gpio pins for software use
127 * 2. "a" reg and bits
130 * 3. "en" reg and bits
131 * sets the pin direction
133 * 4. "y" reg and bits
137 struct amdgpu_i2c_bus_rec {
139 /* id used by atom */
141 /* id used by atom */
142 enum amdgpu_hpd_id hpd;
143 /* can be used with hw i2c engine */
145 /* uses multi-media i2c engine */
148 uint32_t mask_clk_reg;
149 uint32_t mask_data_reg;
153 uint32_t en_data_reg;
156 uint32_t mask_clk_mask;
157 uint32_t mask_data_mask;
159 uint32_t a_data_mask;
160 uint32_t en_clk_mask;
161 uint32_t en_data_mask;
163 uint32_t y_data_mask;
166 #define AMDGPU_MAX_BIOS_CONNECTOR 16
169 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
170 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
171 #define AMDGPU_PLL_USE_REF_DIV (1 << 2)
172 #define AMDGPU_PLL_LEGACY (1 << 3)
173 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
174 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
175 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
176 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
177 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
178 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
179 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
180 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
181 #define AMDGPU_PLL_USE_POST_DIV (1 << 12)
182 #define AMDGPU_PLL_IS_LCD (1 << 13)
183 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
186 /* reference frequency */
187 uint32_t reference_freq;
190 uint32_t reference_div;
193 /* pll in/out limits */
196 uint32_t pll_out_min;
197 uint32_t pll_out_max;
198 uint32_t lcd_pll_out_min;
199 uint32_t lcd_pll_out_max;
203 uint32_t min_ref_div;
204 uint32_t max_ref_div;
205 uint32_t min_post_div;
206 uint32_t max_post_div;
207 uint32_t min_feedback_div;
208 uint32_t max_feedback_div;
209 uint32_t min_frac_feedback_div;
210 uint32_t max_frac_feedback_div;
212 /* flags for the current clock */
219 struct amdgpu_i2c_chan {
220 struct i2c_adapter adapter;
221 struct drm_device *dev;
222 struct i2c_algo_bit_data bit;
223 struct amdgpu_i2c_bus_rec rec;
224 struct drm_dp_aux aux;
234 bool last_buffer_filled_status;
236 struct amdgpu_audio_pin *pin;
242 struct amdgpu_audio_pin {
253 struct amdgpu_audio {
255 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
259 struct amdgpu_mode_mc_save {
260 u32 vga_render_control;
262 bool crtc_enabled[AMDGPU_MAX_CRTCS];
265 struct amdgpu_display_funcs {
267 void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
268 /* display watermarks */
269 void (*bandwidth_update)(struct amdgpu_device *adev);
270 /* get frame count */
271 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
272 /* wait for vblank */
273 void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
275 bool (*is_display_hung)(struct amdgpu_device *adev);
276 /* set backlight level */
277 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
279 /* get backlight level */
280 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
282 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
283 void (*hpd_set_polarity)(struct amdgpu_device *adev,
284 enum amdgpu_hpd_id hpd);
285 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
287 void (*page_flip)(struct amdgpu_device *adev,
288 int crtc_id, u64 crtc_base, bool async);
289 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
290 u32 *vbl, u32 *position);
291 /* display topology setup */
292 void (*add_encoder)(struct amdgpu_device *adev,
293 uint32_t encoder_enum,
294 uint32_t supported_device,
296 void (*add_connector)(struct amdgpu_device *adev,
297 uint32_t connector_id,
298 uint32_t supported_device,
300 struct amdgpu_i2c_bus_rec *i2c_bus,
301 uint16_t connector_object_id,
302 struct amdgpu_hpd *hpd,
303 struct amdgpu_router *router);
304 void (*stop_mc_access)(struct amdgpu_device *adev,
305 struct amdgpu_mode_mc_save *save);
306 void (*resume_mc_access)(struct amdgpu_device *adev,
307 struct amdgpu_mode_mc_save *save);
310 struct amdgpu_mode_info {
311 struct atom_context *atom_context;
312 struct card_info *atom_card_info;
313 bool mode_config_initialized;
314 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
315 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
316 /* DVI-I properties */
317 struct drm_property *coherent_mode_property;
318 /* DAC enable load detect */
319 struct drm_property *load_detect_property;
321 struct drm_property *underscan_property;
322 struct drm_property *underscan_hborder_property;
323 struct drm_property *underscan_vborder_property;
325 struct drm_property *audio_property;
327 struct drm_property *dither_property;
328 /* hardcoded DFP edid from BIOS */
329 struct edid *bios_hardcoded_edid;
330 int bios_hardcoded_edid_size;
332 /* pointer to fbdev info structure */
333 struct amdgpu_fbdev *rfbdev;
336 /* pointer to backlight encoder */
337 struct amdgpu_encoder *bl_encoder;
338 struct amdgpu_audio audio; /* audio stuff */
339 int num_crtc; /* number of crtcs */
340 int num_hpd; /* number of hpd pins */
341 int num_dig; /* number of dig blocks */
343 const struct amdgpu_display_funcs *funcs;
344 struct hrtimer vblank_timer;
345 enum amdgpu_interrupt_state vsync_timer_enabled;
348 #define AMDGPU_MAX_BL_LEVEL 0xFF
350 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
352 struct amdgpu_backlight_privdata {
353 struct amdgpu_encoder *encoder;
359 struct amdgpu_atom_ss {
361 uint16_t percentage_divider;
373 struct drm_crtc base;
375 u16 lut_r[256], lut_g[256], lut_b[256];
378 uint32_t crtc_offset;
379 struct drm_gem_object *cursor_bo;
380 uint64_t cursor_addr;
387 int max_cursor_width;
388 int max_cursor_height;
389 enum amdgpu_rmx_type rmx_type;
394 struct drm_display_mode native_mode;
397 struct amdgpu_flip_work *pflip_works;
398 enum amdgpu_flip_status pflip_status;
399 int deferred_flip_completion;
401 struct amdgpu_atom_ss ss;
405 u32 pll_reference_div;
408 struct drm_encoder *encoder;
409 struct drm_connector *connector;
414 u32 lb_vblank_lead_lines;
415 struct drm_display_mode hw_mode;
418 struct amdgpu_encoder_atom_dig {
422 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
425 uint16_t panel_pwr_delay;
428 struct drm_display_mode native_mode;
429 struct backlight_device *bl_dev;
431 uint8_t backlight_level;
433 struct amdgpu_afmt *afmt;
436 struct amdgpu_encoder {
437 struct drm_encoder base;
438 uint32_t encoder_enum;
441 uint32_t active_device;
443 uint32_t pixel_clock;
444 enum amdgpu_rmx_type rmx_type;
445 enum amdgpu_underscan_type underscan_type;
446 uint32_t underscan_hborder;
447 uint32_t underscan_vborder;
448 struct drm_display_mode native_mode;
450 int audio_polling_active;
455 struct amdgpu_connector_atom_dig {
457 u8 dpcd[DP_RECEIVER_CAP_SIZE];
464 struct amdgpu_gpio_rec {
473 enum amdgpu_hpd_id hpd;
475 struct amdgpu_gpio_rec gpio;
478 struct amdgpu_router {
480 struct amdgpu_i2c_bus_rec i2c_info;
485 u8 ddc_mux_control_pin;
490 u8 cd_mux_control_pin;
494 enum amdgpu_connector_audio {
495 AMDGPU_AUDIO_DISABLE = 0,
496 AMDGPU_AUDIO_ENABLE = 1,
497 AMDGPU_AUDIO_AUTO = 2
500 enum amdgpu_connector_dither {
501 AMDGPU_FMT_DITHER_DISABLE = 0,
502 AMDGPU_FMT_DITHER_ENABLE = 1,
505 struct amdgpu_connector {
506 struct drm_connector base;
507 uint32_t connector_id;
509 struct amdgpu_i2c_chan *ddc_bus;
510 /* some systems have an hdmi and vga port with a shared ddc line */
513 /* we need to mind the EDID between detect
514 and get modes due to analog/digital/tvencoder */
517 bool dac_load_detect;
518 bool detected_by_load; /* if the connection status was determined by load */
519 uint16_t connector_object_id;
520 struct amdgpu_hpd hpd;
521 struct amdgpu_router router;
522 struct amdgpu_i2c_chan *router_bus;
523 enum amdgpu_connector_audio audio;
524 enum amdgpu_connector_dither dither;
525 unsigned pixelclock_for_modeset;
528 struct amdgpu_framebuffer {
529 struct drm_framebuffer base;
530 struct drm_gem_object *obj;
533 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
534 ((em) == ATOM_ENCODER_MODE_DP_MST))
536 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
537 #define USE_REAL_VBLANKSTART (1 << 30)
538 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
540 void amdgpu_link_encoder_connector(struct drm_device *dev);
542 struct drm_connector *
543 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
544 struct drm_connector *
545 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
546 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
549 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
550 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
552 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
554 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
556 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
557 unsigned int flags, int *vpos, int *hpos,
558 ktime_t *stime, ktime_t *etime,
559 const struct drm_display_mode *mode);
561 int amdgpu_framebuffer_init(struct drm_device *dev,
562 struct amdgpu_framebuffer *rfb,
563 const struct drm_mode_fb_cmd2 *mode_cmd,
564 struct drm_gem_object *obj);
566 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
568 void amdgpu_enc_destroy(struct drm_encoder *encoder);
569 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
570 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
571 const struct drm_display_mode *mode,
572 struct drm_display_mode *adjusted_mode);
573 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
574 struct drm_display_mode *adjusted_mode);
575 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
578 int amdgpu_fbdev_init(struct amdgpu_device *adev);
579 void amdgpu_fbdev_fini(struct amdgpu_device *adev);
580 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
581 int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
582 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
583 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
585 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
588 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
590 /* amdgpu_display.c */
591 void amdgpu_print_display_setup(struct drm_device *dev);
592 int amdgpu_modeset_create_props(struct amdgpu_device *adev);
593 int amdgpu_crtc_set_config(struct drm_mode_set *set);
594 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
595 struct drm_framebuffer *fb,
596 struct drm_pending_vblank_event *event,
597 uint32_t page_flip_flags, uint32_t target);
598 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;