2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
34 #include <linux/vga_switcheroo.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
37 #include "amdgpu_amdkfd.h"
39 #if defined(CONFIG_VGA_SWITCHEROO)
40 bool amdgpu_has_atpx(void);
42 static inline bool amdgpu_has_atpx(void) { return false; }
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
48 * @dev: drm dev pointer
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
53 int amdgpu_driver_unload_kms(struct drm_device *dev)
55 struct amdgpu_device *adev = dev->dev_private;
60 if (adev->rmmio == NULL)
63 if (amdgpu_device_is_px(dev)) {
64 pm_runtime_get_sync(dev->dev);
65 pm_runtime_forbid(dev->dev);
68 amdgpu_amdkfd_device_fini(adev);
70 amdgpu_acpi_fini(adev);
72 amdgpu_device_fini(adev);
76 dev->dev_private = NULL;
81 * amdgpu_driver_load_kms - Main load function for KMS.
83 * @dev: drm dev pointer
84 * @flags: device flags
86 * This is the main load function for KMS (all asics).
87 * Returns 0 on success, error on failure.
89 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
91 struct amdgpu_device *adev;
94 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
98 dev->dev_private = (void *)adev;
100 if ((amdgpu_runtime_pm != 0) &&
102 (amdgpu_is_atpx_hybrid() ||
103 amdgpu_has_atpx_dgpu_power_cntl()) &&
104 ((flags & AMD_IS_APU) == 0))
107 /* amdgpu_device_init should report only fatal error
108 * like memory allocation failure or iomapping failure,
109 * or memory manager initialization failure, it must
110 * properly initialize the GPU MC controller and permit
113 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
115 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
119 /* Call ACPI methods: require modeset init
120 * but failure is not fatal
123 acpi_status = amdgpu_acpi_init(adev);
125 dev_dbg(&dev->pdev->dev,
126 "Error during ACPI methods call\n");
129 amdgpu_amdkfd_load_interface(adev);
130 amdgpu_amdkfd_device_probe(adev);
131 amdgpu_amdkfd_device_init(adev);
133 if (amdgpu_device_is_px(dev)) {
134 pm_runtime_use_autosuspend(dev->dev);
135 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
136 pm_runtime_set_active(dev->dev);
137 pm_runtime_allow(dev->dev);
138 pm_runtime_mark_last_busy(dev->dev);
139 pm_runtime_put_autosuspend(dev->dev);
144 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
145 if (adev->rmmio && amdgpu_device_is_px(dev))
146 pm_runtime_put_noidle(dev->dev);
147 amdgpu_driver_unload_kms(dev);
153 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
154 struct drm_amdgpu_query_fw *query_fw,
155 struct amdgpu_device *adev)
157 switch (query_fw->fw_type) {
158 case AMDGPU_INFO_FW_VCE:
159 fw_info->ver = adev->vce.fw_version;
160 fw_info->feature = adev->vce.fb_version;
162 case AMDGPU_INFO_FW_UVD:
163 fw_info->ver = adev->uvd.fw_version;
164 fw_info->feature = 0;
166 case AMDGPU_INFO_FW_GMC:
167 fw_info->ver = adev->mc.fw_version;
168 fw_info->feature = 0;
170 case AMDGPU_INFO_FW_GFX_ME:
171 fw_info->ver = adev->gfx.me_fw_version;
172 fw_info->feature = adev->gfx.me_feature_version;
174 case AMDGPU_INFO_FW_GFX_PFP:
175 fw_info->ver = adev->gfx.pfp_fw_version;
176 fw_info->feature = adev->gfx.pfp_feature_version;
178 case AMDGPU_INFO_FW_GFX_CE:
179 fw_info->ver = adev->gfx.ce_fw_version;
180 fw_info->feature = adev->gfx.ce_feature_version;
182 case AMDGPU_INFO_FW_GFX_RLC:
183 fw_info->ver = adev->gfx.rlc_fw_version;
184 fw_info->feature = adev->gfx.rlc_feature_version;
186 case AMDGPU_INFO_FW_GFX_MEC:
187 if (query_fw->index == 0) {
188 fw_info->ver = adev->gfx.mec_fw_version;
189 fw_info->feature = adev->gfx.mec_feature_version;
190 } else if (query_fw->index == 1) {
191 fw_info->ver = adev->gfx.mec2_fw_version;
192 fw_info->feature = adev->gfx.mec2_feature_version;
196 case AMDGPU_INFO_FW_SMC:
197 fw_info->ver = adev->pm.fw_version;
198 fw_info->feature = 0;
200 case AMDGPU_INFO_FW_SDMA:
201 if (query_fw->index >= adev->sdma.num_instances)
203 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
204 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
213 * Userspace get information ioctl
216 * amdgpu_info_ioctl - answer a device specific request.
218 * @adev: amdgpu device pointer
219 * @data: request object
222 * This function is used to pass device specific parameters to the userspace
223 * drivers. Examples include: pci device id, pipeline parms, tiling params,
225 * Returns 0 on success, -EINVAL on failure.
227 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
229 struct amdgpu_device *adev = dev->dev_private;
230 struct drm_amdgpu_info *info = data;
231 struct amdgpu_mode_info *minfo = &adev->mode_info;
232 void __user *out = (void __user *)(long)info->return_pointer;
233 uint32_t size = info->return_size;
234 struct drm_crtc *crtc;
239 if (!info->return_size || !info->return_pointer)
242 switch (info->query) {
243 case AMDGPU_INFO_ACCEL_WORKING:
244 ui32 = adev->accel_working;
245 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
246 case AMDGPU_INFO_CRTC_FROM_ID:
247 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
248 crtc = (struct drm_crtc *)minfo->crtcs[i];
249 if (crtc && crtc->base.id == info->mode_crtc.id) {
250 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
251 ui32 = amdgpu_crtc->crtc_id;
257 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
260 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
261 case AMDGPU_INFO_HW_IP_INFO: {
262 struct drm_amdgpu_info_hw_ip ip = {};
263 enum amd_ip_block_type type;
264 uint32_t ring_mask = 0;
265 uint32_t ib_start_alignment = 0;
266 uint32_t ib_size_alignment = 0;
268 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
271 switch (info->query_hw_ip.type) {
272 case AMDGPU_HW_IP_GFX:
273 type = AMD_IP_BLOCK_TYPE_GFX;
274 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
275 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
276 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
277 ib_size_alignment = 8;
279 case AMDGPU_HW_IP_COMPUTE:
280 type = AMD_IP_BLOCK_TYPE_GFX;
281 for (i = 0; i < adev->gfx.num_compute_rings; i++)
282 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
283 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
284 ib_size_alignment = 8;
286 case AMDGPU_HW_IP_DMA:
287 type = AMD_IP_BLOCK_TYPE_SDMA;
288 for (i = 0; i < adev->sdma.num_instances; i++)
289 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
290 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
291 ib_size_alignment = 1;
293 case AMDGPU_HW_IP_UVD:
294 type = AMD_IP_BLOCK_TYPE_UVD;
295 ring_mask = adev->uvd.ring.ready ? 1 : 0;
296 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
297 ib_size_alignment = 16;
299 case AMDGPU_HW_IP_VCE:
300 type = AMD_IP_BLOCK_TYPE_VCE;
301 for (i = 0; i < adev->vce.num_rings; i++)
302 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
303 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
304 ib_size_alignment = 1;
310 for (i = 0; i < adev->num_ip_blocks; i++) {
311 if (adev->ip_blocks[i].type == type &&
312 adev->ip_block_status[i].valid) {
313 ip.hw_ip_version_major = adev->ip_blocks[i].major;
314 ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
315 ip.capabilities_flags = 0;
316 ip.available_rings = ring_mask;
317 ip.ib_start_alignment = ib_start_alignment;
318 ip.ib_size_alignment = ib_size_alignment;
322 return copy_to_user(out, &ip,
323 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
325 case AMDGPU_INFO_HW_IP_COUNT: {
326 enum amd_ip_block_type type;
329 switch (info->query_hw_ip.type) {
330 case AMDGPU_HW_IP_GFX:
331 type = AMD_IP_BLOCK_TYPE_GFX;
333 case AMDGPU_HW_IP_COMPUTE:
334 type = AMD_IP_BLOCK_TYPE_GFX;
336 case AMDGPU_HW_IP_DMA:
337 type = AMD_IP_BLOCK_TYPE_SDMA;
339 case AMDGPU_HW_IP_UVD:
340 type = AMD_IP_BLOCK_TYPE_UVD;
342 case AMDGPU_HW_IP_VCE:
343 type = AMD_IP_BLOCK_TYPE_VCE;
349 for (i = 0; i < adev->num_ip_blocks; i++)
350 if (adev->ip_blocks[i].type == type &&
351 adev->ip_block_status[i].valid &&
352 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
355 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
357 case AMDGPU_INFO_TIMESTAMP:
358 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
359 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
360 case AMDGPU_INFO_FW_VERSION: {
361 struct drm_amdgpu_info_firmware fw_info;
364 /* We only support one instance of each IP block right now. */
365 if (info->query_fw.ip_instance != 0)
368 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
372 return copy_to_user(out, &fw_info,
373 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
375 case AMDGPU_INFO_NUM_BYTES_MOVED:
376 ui64 = atomic64_read(&adev->num_bytes_moved);
377 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
378 case AMDGPU_INFO_NUM_EVICTIONS:
379 ui64 = atomic64_read(&adev->num_evictions);
380 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
381 case AMDGPU_INFO_VRAM_USAGE:
382 ui64 = atomic64_read(&adev->vram_usage);
383 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
384 case AMDGPU_INFO_VIS_VRAM_USAGE:
385 ui64 = atomic64_read(&adev->vram_vis_usage);
386 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
387 case AMDGPU_INFO_GTT_USAGE:
388 ui64 = atomic64_read(&adev->gtt_usage);
389 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
390 case AMDGPU_INFO_GDS_CONFIG: {
391 struct drm_amdgpu_info_gds gds_info;
393 memset(&gds_info, 0, sizeof(gds_info));
394 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
395 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
396 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
397 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
398 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
399 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
400 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
401 return copy_to_user(out, &gds_info,
402 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
404 case AMDGPU_INFO_VRAM_GTT: {
405 struct drm_amdgpu_info_vram_gtt vram_gtt;
407 vram_gtt.vram_size = adev->mc.real_vram_size;
408 vram_gtt.vram_size -= adev->vram_pin_size;
409 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
410 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
411 vram_gtt.gtt_size = adev->mc.gtt_size;
412 vram_gtt.gtt_size -= adev->gart_pin_size;
413 return copy_to_user(out, &vram_gtt,
414 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
416 case AMDGPU_INFO_READ_MMR_REG: {
417 unsigned n, alloc_size;
419 unsigned se_num = (info->read_mmr_reg.instance >>
420 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
421 AMDGPU_INFO_MMR_SE_INDEX_MASK;
422 unsigned sh_num = (info->read_mmr_reg.instance >>
423 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
424 AMDGPU_INFO_MMR_SH_INDEX_MASK;
426 /* set full masks if the userspace set all bits
427 * in the bitfields */
428 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
430 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
433 if (info->read_mmr_reg.count > 128)
436 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
439 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
441 for (i = 0; i < info->read_mmr_reg.count; i++)
442 if (amdgpu_asic_read_register(adev, se_num, sh_num,
443 info->read_mmr_reg.dword_offset + i,
445 DRM_DEBUG_KMS("unallowed offset %#x\n",
446 info->read_mmr_reg.dword_offset + i);
450 n = copy_to_user(out, regs, min(size, alloc_size));
452 return n ? -EFAULT : 0;
454 case AMDGPU_INFO_DEV_INFO: {
455 struct drm_amdgpu_info_device dev_info;
457 memset(&dev_info, 0, sizeof(dev_info));
458 dev_info.device_id = dev->pdev->device;
459 dev_info.chip_rev = adev->rev_id;
460 dev_info.external_rev = adev->external_rev_id;
461 dev_info.pci_rev = dev->pdev->revision;
462 dev_info.family = adev->family;
463 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
464 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
465 /* return all clocks in KHz */
466 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
467 if (adev->pm.dpm_enabled) {
468 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
469 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
471 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
472 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
474 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
475 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
476 adev->gfx.config.max_shader_engines;
477 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
479 dev_info.ids_flags = 0;
480 if (adev->flags & AMD_IS_APU)
481 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
482 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
483 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
484 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
485 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
486 AMDGPU_GPU_PAGE_SIZE;
487 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
489 dev_info.cu_active_number = adev->gfx.cu_info.number;
490 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
491 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
492 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
493 sizeof(adev->gfx.cu_info.bitmap));
494 dev_info.vram_type = adev->mc.vram_type;
495 dev_info.vram_bit_width = adev->mc.vram_width;
496 dev_info.vce_harvest_config = adev->vce.harvest_config;
498 return copy_to_user(out, &dev_info,
499 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
502 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
510 * Outdated mess for old drm with Xorg being in charge (void function now).
513 * amdgpu_driver_lastclose_kms - drm callback for last close
515 * @dev: drm dev pointer
517 * Switch vga_switcheroo state after last close (all asics).
519 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
521 struct amdgpu_device *adev = dev->dev_private;
523 amdgpu_fbdev_restore_mode(adev);
524 vga_switcheroo_process_delayed_switch();
528 * amdgpu_driver_open_kms - drm callback for open
530 * @dev: drm dev pointer
531 * @file_priv: drm file
533 * On device open, init vm on cayman+ (all asics).
534 * Returns 0 on success, error on failure.
536 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
538 struct amdgpu_device *adev = dev->dev_private;
539 struct amdgpu_fpriv *fpriv;
542 file_priv->driver_priv = NULL;
544 r = pm_runtime_get_sync(dev->dev);
548 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
549 if (unlikely(!fpriv)) {
554 r = amdgpu_vm_init(adev, &fpriv->vm);
560 mutex_init(&fpriv->bo_list_lock);
561 idr_init(&fpriv->bo_list_handles);
563 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
565 file_priv->driver_priv = fpriv;
568 pm_runtime_mark_last_busy(dev->dev);
570 pm_runtime_put_autosuspend(dev->dev);
576 * amdgpu_driver_postclose_kms - drm callback for post close
578 * @dev: drm dev pointer
579 * @file_priv: drm file
581 * On device post close, tear down vm on cayman+ (all asics).
583 void amdgpu_driver_postclose_kms(struct drm_device *dev,
584 struct drm_file *file_priv)
586 struct amdgpu_device *adev = dev->dev_private;
587 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
588 struct amdgpu_bo_list *list;
594 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
596 amdgpu_uvd_free_handles(adev, file_priv);
597 amdgpu_vce_free_handles(adev, file_priv);
599 amdgpu_vm_fini(adev, &fpriv->vm);
601 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
602 amdgpu_bo_list_free(list);
604 idr_destroy(&fpriv->bo_list_handles);
605 mutex_destroy(&fpriv->bo_list_lock);
608 file_priv->driver_priv = NULL;
610 pm_runtime_mark_last_busy(dev->dev);
611 pm_runtime_put_autosuspend(dev->dev);
615 * amdgpu_driver_preclose_kms - drm callback for pre close
617 * @dev: drm dev pointer
618 * @file_priv: drm file
620 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
623 void amdgpu_driver_preclose_kms(struct drm_device *dev,
624 struct drm_file *file_priv)
626 pm_runtime_get_sync(dev->dev);
630 * VBlank related functions.
633 * amdgpu_get_vblank_counter_kms - get frame count
635 * @dev: drm dev pointer
636 * @pipe: crtc to get the frame count from
638 * Gets the frame count on the requested crtc (all asics).
639 * Returns frame count on success, -EINVAL on failure.
641 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
643 struct amdgpu_device *adev = dev->dev_private;
644 int vpos, hpos, stat;
647 if (pipe >= adev->mode_info.num_crtc) {
648 DRM_ERROR("Invalid crtc %u\n", pipe);
652 /* The hw increments its frame counter at start of vsync, not at start
653 * of vblank, as is required by DRM core vblank counter handling.
654 * Cook the hw count here to make it appear to the caller as if it
655 * incremented at start of vblank. We measure distance to start of
656 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
657 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
658 * result by 1 to give the proper appearance to caller.
660 if (adev->mode_info.crtcs[pipe]) {
661 /* Repeat readout if needed to provide stable result if
662 * we cross start of vsync during the queries.
665 count = amdgpu_display_vblank_get_counter(adev, pipe);
666 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
667 * distance to start of vblank, instead of regular
668 * vertical scanout pos.
670 stat = amdgpu_get_crtc_scanoutpos(
671 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
672 &vpos, &hpos, NULL, NULL,
673 &adev->mode_info.crtcs[pipe]->base.hwmode);
674 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
676 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
677 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
678 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
680 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
683 /* Bump counter if we are at >= leading edge of vblank,
684 * but before vsync where vpos would turn negative and
685 * the hw counter really increments.
691 /* Fallback to use value as is. */
692 count = amdgpu_display_vblank_get_counter(adev, pipe);
693 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
700 * amdgpu_enable_vblank_kms - enable vblank interrupt
702 * @dev: drm dev pointer
703 * @pipe: crtc to enable vblank interrupt for
705 * Enable the interrupt on the requested crtc (all asics).
706 * Returns 0 on success, -EINVAL on failure.
708 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
710 struct amdgpu_device *adev = dev->dev_private;
711 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
713 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
717 * amdgpu_disable_vblank_kms - disable vblank interrupt
719 * @dev: drm dev pointer
720 * @pipe: crtc to disable vblank interrupt for
722 * Disable the interrupt on the requested crtc (all asics).
724 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
726 struct amdgpu_device *adev = dev->dev_private;
727 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
729 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
733 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
735 * @dev: drm dev pointer
736 * @crtc: crtc to get the timestamp for
737 * @max_error: max error
738 * @vblank_time: time value
739 * @flags: flags passed to the driver
741 * Gets the timestamp on the requested crtc based on the
742 * scanout position. (all asics).
743 * Returns postive status flags on success, negative error on failure.
745 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
747 struct timeval *vblank_time,
750 struct drm_crtc *crtc;
751 struct amdgpu_device *adev = dev->dev_private;
753 if (pipe >= dev->num_crtcs) {
754 DRM_ERROR("Invalid crtc %u\n", pipe);
758 /* Get associated drm_crtc: */
759 crtc = &adev->mode_info.crtcs[pipe]->base;
761 /* This can occur on driver load if some component fails to
762 * initialize completely and driver is unloaded */
763 DRM_ERROR("Uninitialized crtc %d\n", pipe);
767 /* Helper routine in DRM core does all the work: */
768 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
773 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
774 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
775 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
776 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
778 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
779 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
780 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
781 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
782 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
783 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
784 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
785 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
786 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
788 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
793 #if defined(CONFIG_DEBUG_FS)
795 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
797 struct drm_info_node *node = (struct drm_info_node *) m->private;
798 struct drm_device *dev = node->minor->dev;
799 struct amdgpu_device *adev = dev->dev_private;
800 struct drm_amdgpu_info_firmware fw_info;
801 struct drm_amdgpu_query_fw query_fw;
805 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
806 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
809 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
810 fw_info.feature, fw_info.ver);
813 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
814 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
817 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
818 fw_info.feature, fw_info.ver);
821 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
822 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
825 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
826 fw_info.feature, fw_info.ver);
829 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
830 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
833 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
834 fw_info.feature, fw_info.ver);
837 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
838 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
841 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
842 fw_info.feature, fw_info.ver);
845 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
846 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
849 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
850 fw_info.feature, fw_info.ver);
853 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
854 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
857 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
858 fw_info.feature, fw_info.ver);
861 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
863 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
866 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
867 fw_info.feature, fw_info.ver);
870 if (adev->asic_type == CHIP_KAVERI ||
871 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
873 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
876 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
877 fw_info.feature, fw_info.ver);
881 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
882 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
885 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
886 fw_info.feature, fw_info.ver);
889 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
890 for (i = 0; i < adev->sdma.num_instances; i++) {
892 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
895 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
896 i, fw_info.feature, fw_info.ver);
902 static const struct drm_info_list amdgpu_firmware_info_list[] = {
903 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
907 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
909 #if defined(CONFIG_DEBUG_FS)
910 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
911 ARRAY_SIZE(amdgpu_firmware_info_list));