drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28
  29 /* 0.5 second timeout */
  30 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(500)
  31
  32 /*
  33  * GPU scratch registers helpers function.
  34  */
  35 /**
  36  * amdgpu_gfx_scratch_get - Allocate a scratch register
  37  *
  38  * @adev: amdgpu_device pointer
  39  * @reg: scratch register mmio offset
  40  *
  41  * Allocate a CP scratch register for use by the driver (all asics).
  42  * Returns 0 on success or -EINVAL on failure.
  43  */
  44 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
  45 {
  46         int i;
  47
  48         i = ffs(adev->gfx.scratch.free_mask);
  49         if (i != 0 && i <= adev->gfx.scratch.num_reg) {
  50                 i--;
  51                 adev->gfx.scratch.free_mask &= ~(1u << i);
  52                 *reg = adev->gfx.scratch.reg_base + i;
  53                 return 0;
  54         }
  55         return -EINVAL;
  56 }
  57
  58 /**
  59  * amdgpu_gfx_scratch_free - Free a scratch register
  60  *
  61  * @adev: amdgpu_device pointer
  62  * @reg: scratch register mmio offset
  63  *
  64  * Free a CP scratch register allocated for use by the driver (all asics)
  65  */
  66 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
  67 {
  68         adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
  69 }
  70
  71 /**
  72  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
  73  *
  74  * @mask: array in which the per-shader array disable masks will be stored
  75  * @max_se: number of SEs
  76  * @max_sh: number of SHs
  77  *
  78  * The bitmask of CUs to be disabled in the shader array determined by se and
  79  * sh is stored in mask[se * max_sh + sh].
  80  */
  81 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
  82 {
  83         unsigned se, sh, cu;
  84         const char *p;
  85
  86         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
  87
  88         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
  89                 return;
  90
  91         p = amdgpu_disable_cu;
  92         for (;;) {
  93                 char *next;
  94                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
  95                 if (ret < 3) {
  96                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
  97                         return;
  98                 }
  99
 100                 if (se < max_se && sh < max_sh && cu < 16) {
 101                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 102                         mask[se * max_sh + sh] |= 1u << cu;
 103                 } else {
 104                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 105                                   se, sh, cu);
 106                 }
 107
 108                 next = strchr(p, ',');
 109                 if (!next)
 110                         break;
 111                 p = next + 1;
 112         }
 113 }
 114
 115 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
 116 {
 117         if (amdgpu_compute_multipipe != -1) {
 118                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 119                          amdgpu_compute_multipipe);
 120                 return amdgpu_compute_multipipe == 1;
 121         }
 122
 123         /* FIXME: spreading the queues across pipes causes perf regressions
 124          * on POLARIS11 compute workloads */
 125         if (adev->asic_type == CHIP_POLARIS11)
 126                 return false;
 127
 128         return adev->gfx.mec.num_mec > 1;
 129 }
 130
 131 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 132 {
 133         int i, queue, pipe, mec;
 134         bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
 135
 136         /* policy for amdgpu compute queue ownership */
 137         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 138                 queue = i % adev->gfx.mec.num_queue_per_pipe;
 139                 pipe = (i / adev->gfx.mec.num_queue_per_pipe)
 140                         % adev->gfx.mec.num_pipe_per_mec;
 141                 mec = (i / adev->gfx.mec.num_queue_per_pipe)
 142                         / adev->gfx.mec.num_pipe_per_mec;
 143
 144                 /* we've run out of HW */
 145                 if (mec >= adev->gfx.mec.num_mec)
 146                         break;
 147
 148                 if (multipipe_policy) {
 149                         /* policy: amdgpu owns the first two queues of the first MEC */
 150                         if (mec == 0 && queue < 2)
 151                                 set_bit(i, adev->gfx.mec.queue_bitmap);
 152                 } else {
 153                         /* policy: amdgpu owns all queues in the first pipe */
 154                         if (mec == 0 && pipe == 0)
 155                                 set_bit(i, adev->gfx.mec.queue_bitmap);
 156                 }
 157         }
 158
 159         /* update the number of active compute rings */
 160         adev->gfx.num_compute_rings =
 161                 bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 162
 163         /* If you hit this case and edited the policy, you probably just
 164          * need to increase AMDGPU_MAX_COMPUTE_RINGS */
 165         if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS))
 166                 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
 167 }
 168
 169 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 170                                   struct amdgpu_ring *ring)
 171 {
 172         int queue_bit;
 173         int mec, pipe, queue;
 174
 175         queue_bit = adev->gfx.mec.num_mec
 176                     * adev->gfx.mec.num_pipe_per_mec
 177                     * adev->gfx.mec.num_queue_per_pipe;
 178
 179         while (--queue_bit >= 0) {
 180                 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
 181                         continue;
 182
 183                 amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
 184
 185                 /*
 186                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 187                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 188                  * only can be issued on queue 0.
 189                  */
 190                 if ((mec == 1 && pipe > 1) || queue != 0)
 191                         continue;
 192
 193                 ring->me = mec + 1;
 194                 ring->pipe = pipe;
 195                 ring->queue = queue;
 196
 197                 return 0;
 198         }
 199
 200         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 201         return -EINVAL;
 202 }
 203
 204 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 205                              struct amdgpu_ring *ring,
 206                              struct amdgpu_irq_src *irq)
 207 {
 208         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 209         int r = 0;
 210
 211         spin_lock_init(&kiq->ring_lock);
 212
 213         r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs);
 214         if (r)
 215                 return r;
 216
 217         ring->adev = NULL;
 218         ring->ring_obj = NULL;
 219         ring->use_doorbell = true;
 220         ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
 221
 222         r = amdgpu_gfx_kiq_acquire(adev, ring);
 223         if (r)
 224                 return r;
 225
 226         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 227         sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 228         r = amdgpu_ring_init(adev, ring, 1024,
 229                              irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
 230         if (r)
 231                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 232
 233         return r;
 234 }
 235
 236 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
 237                               struct amdgpu_irq_src *irq)
 238 {
 239         amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
 240         amdgpu_ring_fini(ring);
 241 }
 242
 243 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
 244 {
 245         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 246
 247         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 248 }
 249
 250 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 251                         unsigned hpd_size)
 252 {
 253         int r;
 254         u32 *hpd;
 255         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 256
 257         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 258                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 259                                     &kiq->eop_gpu_addr, (void **)&hpd);
 260         if (r) {
 261                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 262                 return r;
 263         }
 264
 265         memset(hpd, 0, hpd_size);
 266
 267         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 268         if (unlikely(r != 0))
 269                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 270         amdgpu_bo_kunmap(kiq->eop_obj);
 271         amdgpu_bo_unreserve(kiq->eop_obj);
 272
 273         return 0;
 274 }
 275
 276 /* create MQD for each compute queue */
 277 int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
 278                                    unsigned mqd_size)
 279 {
 280         struct amdgpu_ring *ring = NULL;
 281         int r, i;
 282
 283         /* create MQD for KIQ */
 284         ring = &adev->gfx.kiq.ring;
 285         if (!ring->mqd_obj) {
 286                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 287                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 288                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 289                  * KIQ MQD no matter SRIOV or Bare-metal
 290                  */
 291                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 292                                             AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
 293                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 294                 if (r) {
 295                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 296                         return r;
 297                 }
 298
 299                 /* prepare MQD backup */
 300                 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
 301                 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
 302                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 303         }
 304
 305         /* create MQD for each KCQ */
 306         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 307                 ring = &adev->gfx.compute_ring[i];
 308                 if (!ring->mqd_obj) {
 309                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 310                                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 311                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 312                         if (r) {
 313                                 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 314                                 return r;
 315                         }
 316
 317                         /* prepare MQD backup */
 318                         adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 319                         if (!adev->gfx.mec.mqd_backup[i])
 320                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 321                 }
 322         }
 323
 324         return 0;
 325 }
 326
 327 void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev)
 328 {
 329         struct amdgpu_ring *ring = NULL;
 330         int i;
 331
 332         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 333                 ring = &adev->gfx.compute_ring[i];
 334                 kfree(adev->gfx.mec.mqd_backup[i]);
 335                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 336                                       &ring->mqd_gpu_addr,
 337                                       &ring->mqd_ptr);
 338         }
 339
 340         ring = &adev->gfx.kiq.ring;
 341         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
 342         amdgpu_bo_free_kernel(&ring->mqd_obj,
 343                               &ring->mqd_gpu_addr,
 344                               &ring->mqd_ptr);
 345 }
 346
 347 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 348  *
 349  * @adev: amdgpu_device pointer
 350  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 351  *
 352  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 353  * 2. other client can send request to disable gfx off feature, the request should be honored.
 354  * 3. other client can cancel their request of disable gfx off feature
 355  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 356  */
 357
 358 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 359 {
 360         if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
 361                 return;
 362
 363         if (!adev->powerplay.pp_funcs->set_powergating_by_smu)
 364                 return;
 365
 366
 367         mutex_lock(&adev->gfx.gfx_off_mutex);
 368
 369         if (!enable)
 370                 adev->gfx.gfx_off_req_count++;
 371         else if (adev->gfx.gfx_off_req_count > 0)
 372                 adev->gfx.gfx_off_req_count--;
 373
 374         if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
 375                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
 376         } else if (!enable && adev->gfx.gfx_off_state) {
 377                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false))
 378                         adev->gfx.gfx_off_state = false;
 379         }
 380
 381         mutex_unlock(&adev->gfx.gfx_off_mutex);
 382 }