2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_display.h"
35 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
37 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
40 amdgpu_mn_unregister(robj);
41 amdgpu_bo_unref(&robj);
45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
46 int alignment, u32 initial_domain,
47 u64 flags, enum ttm_bo_type type,
48 struct reservation_object *resv,
49 struct drm_gem_object **obj)
52 struct amdgpu_bo_param bp;
55 memset(&bp, 0, sizeof(bp));
57 /* At least align on page size */
58 if (alignment < PAGE_SIZE) {
59 alignment = PAGE_SIZE;
63 bp.byte_align = alignment;
66 bp.preferred_domain = initial_domain;
69 bp.domain = initial_domain;
70 r = amdgpu_bo_create(adev, &bp, &bo);
72 if (r != -ERESTARTSYS) {
73 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
74 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
78 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
79 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
82 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
83 size, initial_domain, alignment, r);
92 void amdgpu_gem_force_release(struct amdgpu_device *adev)
94 struct drm_device *ddev = adev->ddev;
95 struct drm_file *file;
97 mutex_lock(&ddev->filelist_mutex);
99 list_for_each_entry(file, &ddev->filelist, lhead) {
100 struct drm_gem_object *gobj;
103 WARN_ONCE(1, "Still active user space clients!\n");
104 spin_lock(&file->table_lock);
105 idr_for_each_entry(&file->object_idr, gobj, handle) {
106 WARN_ONCE(1, "And also active allocations!\n");
107 drm_gem_object_put_unlocked(gobj);
109 idr_destroy(&file->object_idr);
110 spin_unlock(&file->table_lock);
113 mutex_unlock(&ddev->filelist_mutex);
117 * Call from drm_gem_handle_create which appear in both new and open ioctl
120 int amdgpu_gem_object_open(struct drm_gem_object *obj,
121 struct drm_file *file_priv)
123 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
124 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
125 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
126 struct amdgpu_vm *vm = &fpriv->vm;
127 struct amdgpu_bo_va *bo_va;
128 struct mm_struct *mm;
131 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
132 if (mm && mm != current->mm)
135 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
136 abo->tbo.resv != vm->root.base.bo->tbo.resv)
139 r = amdgpu_bo_reserve(abo, false);
143 bo_va = amdgpu_vm_bo_find(vm, abo);
145 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
149 amdgpu_bo_unreserve(abo);
153 void amdgpu_gem_object_close(struct drm_gem_object *obj,
154 struct drm_file *file_priv)
156 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
157 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
158 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
159 struct amdgpu_vm *vm = &fpriv->vm;
161 struct amdgpu_bo_list_entry vm_pd;
162 struct list_head list, duplicates;
163 struct ttm_validate_buffer tv;
164 struct ww_acquire_ctx ticket;
165 struct amdgpu_bo_va *bo_va;
168 INIT_LIST_HEAD(&list);
169 INIT_LIST_HEAD(&duplicates);
173 list_add(&tv.head, &list);
175 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
177 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
179 dev_err(adev->dev, "leaking bo va because "
180 "we fail to reserve bo (%d)\n", r);
183 bo_va = amdgpu_vm_bo_find(vm, bo);
184 if (bo_va && --bo_va->ref_count == 0) {
185 amdgpu_vm_bo_rmv(adev, bo_va);
187 if (amdgpu_vm_ready(vm)) {
188 struct dma_fence *fence = NULL;
190 r = amdgpu_vm_clear_freed(adev, vm, &fence);
192 dev_err(adev->dev, "failed to clear page "
193 "tables on GEM object close (%d)\n", r);
197 amdgpu_bo_fence(bo, fence, true);
198 dma_fence_put(fence);
202 ttm_eu_backoff_reservation(&ticket, &list);
208 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
209 struct drm_file *filp)
211 struct amdgpu_device *adev = dev->dev_private;
212 struct amdgpu_fpriv *fpriv = filp->driver_priv;
213 struct amdgpu_vm *vm = &fpriv->vm;
214 union drm_amdgpu_gem_create *args = data;
215 uint64_t flags = args->in.domain_flags;
216 uint64_t size = args->in.bo_size;
217 struct reservation_object *resv = NULL;
218 struct drm_gem_object *gobj;
222 /* reject invalid gem flags */
223 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
224 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
225 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
226 AMDGPU_GEM_CREATE_VRAM_CLEARED |
227 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
228 AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
232 /* reject invalid gem domains */
233 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
236 /* create a gem object to contain this object in */
237 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
238 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
239 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
240 /* if gds bo is created from user space, it must be
243 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
246 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
247 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
248 size = size << AMDGPU_GDS_SHIFT;
249 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
250 size = size << AMDGPU_GWS_SHIFT;
251 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
252 size = size << AMDGPU_OA_SHIFT;
256 size = roundup(size, PAGE_SIZE);
258 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
259 r = amdgpu_bo_reserve(vm->root.base.bo, false);
263 resv = vm->root.base.bo->tbo.resv;
266 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
267 (u32)(0xffffffff & args->in.domains),
268 flags, ttm_bo_type_device, resv, &gobj);
269 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
271 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
273 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
275 amdgpu_bo_unreserve(vm->root.base.bo);
280 r = drm_gem_handle_create(filp, gobj, &handle);
281 /* drop reference from allocate - handle holds it now */
282 drm_gem_object_put_unlocked(gobj);
286 memset(args, 0, sizeof(*args));
287 args->out.handle = handle;
291 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
292 struct drm_file *filp)
294 struct ttm_operation_ctx ctx = { true, false };
295 struct amdgpu_device *adev = dev->dev_private;
296 struct drm_amdgpu_gem_userptr *args = data;
297 struct drm_gem_object *gobj;
298 struct amdgpu_bo *bo;
302 if (offset_in_page(args->addr | args->size))
305 /* reject unknown flag values */
306 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
307 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
308 AMDGPU_GEM_USERPTR_REGISTER))
311 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
312 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
314 /* if we want to write to it we must install a MMU notifier */
318 /* create a gem object to contain this object in */
319 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
320 0, ttm_bo_type_device, NULL, &gobj);
324 bo = gem_to_amdgpu_bo(gobj);
325 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
326 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
327 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
331 r = amdgpu_mn_register(bo, args->addr);
335 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
336 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
341 r = amdgpu_bo_reserve(bo, true);
345 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
346 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
347 amdgpu_bo_unreserve(bo);
352 r = drm_gem_handle_create(filp, gobj, &handle);
353 /* drop reference from allocate - handle holds it now */
354 drm_gem_object_put_unlocked(gobj);
358 args->handle = handle;
362 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
365 drm_gem_object_put_unlocked(gobj);
370 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
371 struct drm_device *dev,
372 uint32_t handle, uint64_t *offset_p)
374 struct drm_gem_object *gobj;
375 struct amdgpu_bo *robj;
377 gobj = drm_gem_object_lookup(filp, handle);
381 robj = gem_to_amdgpu_bo(gobj);
382 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
383 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
384 drm_gem_object_put_unlocked(gobj);
387 *offset_p = amdgpu_bo_mmap_offset(robj);
388 drm_gem_object_put_unlocked(gobj);
392 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
393 struct drm_file *filp)
395 union drm_amdgpu_gem_mmap *args = data;
396 uint32_t handle = args->in.handle;
397 memset(args, 0, sizeof(*args));
398 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
402 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
404 * @timeout_ns: timeout in ns
406 * Calculate the timeout in jiffies from an absolute timeout in ns.
408 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
410 unsigned long timeout_jiffies;
413 /* clamp timeout if it's to large */
414 if (((int64_t)timeout_ns) < 0)
415 return MAX_SCHEDULE_TIMEOUT;
417 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
418 if (ktime_to_ns(timeout) < 0)
421 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
422 /* clamp timeout to avoid unsigned-> signed overflow */
423 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
424 return MAX_SCHEDULE_TIMEOUT - 1;
426 return timeout_jiffies;
429 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
430 struct drm_file *filp)
432 union drm_amdgpu_gem_wait_idle *args = data;
433 struct drm_gem_object *gobj;
434 struct amdgpu_bo *robj;
435 uint32_t handle = args->in.handle;
436 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
440 gobj = drm_gem_object_lookup(filp, handle);
444 robj = gem_to_amdgpu_bo(gobj);
445 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
448 /* ret == 0 means not signaled,
449 * ret > 0 means signaled
450 * ret < 0 means interrupted before timeout
453 memset(args, 0, sizeof(*args));
454 args->out.status = (ret == 0);
458 drm_gem_object_put_unlocked(gobj);
462 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
463 struct drm_file *filp)
465 struct drm_amdgpu_gem_metadata *args = data;
466 struct drm_gem_object *gobj;
467 struct amdgpu_bo *robj;
470 DRM_DEBUG("%d \n", args->handle);
471 gobj = drm_gem_object_lookup(filp, args->handle);
474 robj = gem_to_amdgpu_bo(gobj);
476 r = amdgpu_bo_reserve(robj, false);
477 if (unlikely(r != 0))
480 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
481 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
482 r = amdgpu_bo_get_metadata(robj, args->data.data,
483 sizeof(args->data.data),
484 &args->data.data_size_bytes,
486 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
487 if (args->data.data_size_bytes > sizeof(args->data.data)) {
491 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
493 r = amdgpu_bo_set_metadata(robj, args->data.data,
494 args->data.data_size_bytes,
499 amdgpu_bo_unreserve(robj);
501 drm_gem_object_put_unlocked(gobj);
506 * amdgpu_gem_va_update_vm -update the bo_va in its VM
508 * @adev: amdgpu_device pointer
510 * @bo_va: bo_va to update
511 * @operation: map, unmap or clear
513 * Update the bo_va directly after setting its address. Errors are not
514 * vital here, so they are not reported back to userspace.
516 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
517 struct amdgpu_vm *vm,
518 struct amdgpu_bo_va *bo_va,
523 if (!amdgpu_vm_ready(vm))
526 r = amdgpu_vm_clear_freed(adev, vm, NULL);
530 if (operation == AMDGPU_VA_OP_MAP ||
531 operation == AMDGPU_VA_OP_REPLACE) {
532 r = amdgpu_vm_bo_update(adev, bo_va, false);
537 r = amdgpu_vm_update_directories(adev, vm);
540 if (r && r != -ERESTARTSYS)
541 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
544 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
545 struct drm_file *filp)
547 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
548 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
549 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
550 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
553 struct drm_amdgpu_gem_va *args = data;
554 struct drm_gem_object *gobj;
555 struct amdgpu_device *adev = dev->dev_private;
556 struct amdgpu_fpriv *fpriv = filp->driver_priv;
557 struct amdgpu_bo *abo;
558 struct amdgpu_bo_va *bo_va;
559 struct amdgpu_bo_list_entry vm_pd;
560 struct ttm_validate_buffer tv;
561 struct ww_acquire_ctx ticket;
562 struct list_head list, duplicates;
567 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
568 dev_dbg(&dev->pdev->dev,
569 "va_address 0x%LX is in reserved area 0x%LX\n",
570 args->va_address, AMDGPU_VA_RESERVED_SIZE);
574 if (args->va_address >= AMDGPU_VA_HOLE_START &&
575 args->va_address < AMDGPU_VA_HOLE_END) {
576 dev_dbg(&dev->pdev->dev,
577 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
578 args->va_address, AMDGPU_VA_HOLE_START,
583 args->va_address &= AMDGPU_VA_HOLE_MASK;
585 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
586 vm_size -= AMDGPU_VA_RESERVED_SIZE;
587 if (args->va_address + args->map_size > vm_size) {
588 dev_dbg(&dev->pdev->dev,
589 "va_address 0x%llx is in top reserved area 0x%llx\n",
590 args->va_address + args->map_size, vm_size);
594 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
595 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
600 switch (args->operation) {
601 case AMDGPU_VA_OP_MAP:
602 case AMDGPU_VA_OP_UNMAP:
603 case AMDGPU_VA_OP_CLEAR:
604 case AMDGPU_VA_OP_REPLACE:
607 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
612 INIT_LIST_HEAD(&list);
613 INIT_LIST_HEAD(&duplicates);
614 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
615 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
616 gobj = drm_gem_object_lookup(filp, args->handle);
619 abo = gem_to_amdgpu_bo(gobj);
621 tv.shared = !!(abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID);
622 list_add(&tv.head, &list);
628 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
630 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
635 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
640 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
641 bo_va = fpriv->prt_va;
646 switch (args->operation) {
647 case AMDGPU_VA_OP_MAP:
648 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
653 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
654 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
655 args->offset_in_bo, args->map_size,
658 case AMDGPU_VA_OP_UNMAP:
659 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
662 case AMDGPU_VA_OP_CLEAR:
663 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
667 case AMDGPU_VA_OP_REPLACE:
668 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
673 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
674 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
675 args->offset_in_bo, args->map_size,
681 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
682 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
686 ttm_eu_backoff_reservation(&ticket, &list);
689 drm_gem_object_put_unlocked(gobj);
693 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
694 struct drm_file *filp)
696 struct amdgpu_device *adev = dev->dev_private;
697 struct drm_amdgpu_gem_op *args = data;
698 struct drm_gem_object *gobj;
699 struct amdgpu_bo *robj;
702 gobj = drm_gem_object_lookup(filp, args->handle);
706 robj = gem_to_amdgpu_bo(gobj);
708 r = amdgpu_bo_reserve(robj, false);
713 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
714 struct drm_amdgpu_gem_create_in info;
715 void __user *out = u64_to_user_ptr(args->value);
717 info.bo_size = robj->gem_base.size;
718 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
719 info.domains = robj->preferred_domains;
720 info.domain_flags = robj->flags;
721 amdgpu_bo_unreserve(robj);
722 if (copy_to_user(out, &info, sizeof(info)))
726 case AMDGPU_GEM_OP_SET_PLACEMENT:
727 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
729 amdgpu_bo_unreserve(robj);
732 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
734 amdgpu_bo_unreserve(robj);
737 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
738 AMDGPU_GEM_DOMAIN_GTT |
739 AMDGPU_GEM_DOMAIN_CPU);
740 robj->allowed_domains = robj->preferred_domains;
741 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
742 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
744 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
745 amdgpu_vm_bo_invalidate(adev, robj, true);
747 amdgpu_bo_unreserve(robj);
750 amdgpu_bo_unreserve(robj);
755 drm_gem_object_put_unlocked(gobj);
759 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
760 struct drm_device *dev,
761 struct drm_mode_create_dumb *args)
763 struct amdgpu_device *adev = dev->dev_private;
764 struct drm_gem_object *gobj;
769 args->pitch = amdgpu_align_pitch(adev, args->width,
770 DIV_ROUND_UP(args->bpp, 8), 0);
771 args->size = (u64)args->pitch * args->height;
772 args->size = ALIGN(args->size, PAGE_SIZE);
773 domain = amdgpu_bo_get_preferred_pin_domain(adev,
774 amdgpu_display_supported_domains(adev));
775 r = amdgpu_gem_object_create(adev, args->size, 0, domain,
776 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
777 ttm_bo_type_device, NULL, &gobj);
781 r = drm_gem_handle_create(file_priv, gobj, &handle);
782 /* drop reference from allocate - handle holds it now */
783 drm_gem_object_put_unlocked(gobj);
787 args->handle = handle;
791 #if defined(CONFIG_DEBUG_FS)
793 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \
794 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
795 seq_printf((m), " " #flag); \
798 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
800 struct drm_gem_object *gobj = ptr;
801 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
802 struct seq_file *m = data;
804 struct dma_buf_attachment *attachment;
805 struct dma_buf *dma_buf;
807 const char *placement;
810 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
812 case AMDGPU_GEM_DOMAIN_VRAM:
815 case AMDGPU_GEM_DOMAIN_GTT:
818 case AMDGPU_GEM_DOMAIN_CPU:
823 seq_printf(m, "\t0x%08x: %12ld byte %s",
824 id, amdgpu_bo_size(bo), placement);
826 pin_count = READ_ONCE(bo->pin_count);
828 seq_printf(m, " pin count %d", pin_count);
830 dma_buf = READ_ONCE(bo->gem_base.dma_buf);
831 attachment = READ_ONCE(bo->gem_base.import_attach);
834 seq_printf(m, " imported from %p", dma_buf);
836 seq_printf(m, " exported as %p", dma_buf);
838 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
839 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
840 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
841 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
842 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
843 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
844 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
845 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
852 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
854 struct drm_info_node *node = (struct drm_info_node *)m->private;
855 struct drm_device *dev = node->minor->dev;
856 struct drm_file *file;
859 r = mutex_lock_interruptible(&dev->filelist_mutex);
863 list_for_each_entry(file, &dev->filelist, lhead) {
864 struct task_struct *task;
867 * Although we have a valid reference on file->pid, that does
868 * not guarantee that the task_struct who called get_pid() is
869 * still alive (e.g. get_pid(current) => fork() => exit()).
870 * Therefore, we need to protect this ->comm access using RCU.
873 task = pid_task(file->pid, PIDTYPE_PID);
874 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
875 task ? task->comm : "<unknown>");
878 spin_lock(&file->table_lock);
879 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
880 spin_unlock(&file->table_lock);
883 mutex_unlock(&dev->filelist_mutex);
887 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
888 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
892 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
894 #if defined(CONFIG_DEBUG_FS)
895 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);